SD53-6R8-R [ADI]
1.2 A, 20 V, 700 kHz/1.4 MHz, Nonsynchronous Step-Down Regulator; 1.2 A ， 20 V ， 700千赫/ 1.4 MHz的非同步降压型稳压器
| 型号： | SD53-6R8-R |
| 厂家： | 
ADI |
| 描述： | 1.2 A, 20 V, 700 kHz/1.4 MHz, Nonsynchronous Step-Down Regulator |
| 文件： | 总28页 (文件大小：692K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1.2 A, 20 V, 700 kHz/1.4 MHz,
Nonsynchronous Step-Down Regulator
ADP2300/ADP2301
TYPICAL APPLICATIONS CIRCUIT
FEATURES
1.2 A maximum load current
BST
3.0V TO 20V
VIN
EN
2ꢀ output accuracy over temperature range
Wide input voltage range: 3.0 V to 20 V
700 kHz (ADP2300) or 1.4 MHz (ADP2301)
switching frequency options
V
OUT
ADP2300/
ADP2301
SW
FB
ON
High efficiency up to 91ꢀ
GND
OFF
Current-mode control architecture
Output voltage from 0.8 V to 0.85 × VIN
Automatic PFM/PWM mode switching
Precision enable pin with hysteresis
Integrated high-side MOSFET
Integrated bootstrap diode
Internal compensation and soft start
Minimum external components
Figure 1.
100
95
90
85
80
75
70
65
fSW = 1.4MHz
fSW = 700kHz
Undervoltage lockout (UVLO)
Overcurrent protection (OCP) and thermal shutdown (TSD)
ADIsimPower™ online design tool
Available in ultrasmall, 6-lead TSOT package
APPLICATIONS
LDO replacement for digital load applications
Intermediate power rail conversion
Communications and networking
Industrial and instrumentation
Healthcare and medical
V
V
= 12V
OUT
IN
= 5.0V
60
0
0.2
0.4
0.6
(A)
0.8
1.0
1.2
I
OUT
Figure 2. Efficiency vs. Output Current
Consumer
GENERAL DESCRIPTION
The ADP2300/ADP2301 are compact, constant-frequency,
current-mode, step-down dc-to-dc regulators with integrated
power MOSFET. The ADP2300/ADP2301 devices run from
input voltages of 3.0 V to 20 V, making them suitable for a wide
range of applications. A precise, low voltage internal reference
makes these devices ideal for generating a regulated output
voltage as low as 0.8 V, with 2% accuracy, for up to 1.2 A load
current.
total solution size. Current-mode control provides fast and stable
line and load transient performance. The ADP2300/ADP2301
devices include internal soft start to prevent inrush current at
power-up. Other key safety features include short-circuit protec-
tion, thermal shutdown (TSD), and input undervoltage lockout
(UVLO). The precision enable pin threshold voltage allows the
ADP2300/ADP2301 to be easily sequenced from other input/
output supplies. It can also be used as a programmable UVLO
input by using a resistive divider.
There are two frequency options: the ADP2300 runs at 700 kHz,
and the ADP2301 runs at 1.4 MHz. These options allow users to
make decisions based on the trade-off between efficiency and
The ADP2300/ADP2301 are available in a 6-lead TSOT package
and are rated for the −40°C to +125°C junction temperature range.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2010 Analog Devices, Inc. All rights reserved.
ADP2300/ADP2301
TABLE OF CONTENTS
Thermal Shutdown .................................................................... 15
Control Loop............................................................................... 15
Applications Information.............................................................. 16
Programming the Output Voltage ........................................... 16
Voltage Conversion Limitations............................................... 16
Low Input Voltage Considerations .......................................... 17
Programming the Precision Enable......................................... 17
Inductor....................................................................................... 18
Catch Diode ................................................................................ 19
Input Capacitor........................................................................... 19
Output Capacitor........................................................................ 19
Thermal Considerations............................................................ 20
Design Example.............................................................................. 21
Switching Frequency Selection................................................. 21
Catch Diode Selection ............................................................... 21
Inductor Selection...................................................................... 21
Output Capacitor Selection....................................................... 21
Resistive Voltage Divider Selection.......................................... 22
Circuit Board Layout Recommendations ................................... 23
Typical Application Circuits ......................................................... 24
Outline Dimensions....................................................................... 26
Ordering Guide .......................................................................... 26
Features .............................................................................................. 1
Applications....................................................................................... 1
Typical Applications Circuit............................................................ 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 6
Functional Block Diagram ............................................................ 13
Theory of Operation ...................................................................... 14
Basic Operation .......................................................................... 14
PWM Mode................................................................................. 14
Power Saving Mode.................................................................... 14
Bootstrap Circuitry .................................................................... 14
Precision Enable ......................................................................... 14
Integrated Soft Start ................................................................... 14
Current Limit .............................................................................. 14
Short-Circuit Protection............................................................ 15
Undervoltage Lockout (UVLO) ............................................... 15
REVISION HISTORY
2/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
ADP2300/ADP2301
SPECIFICATIONS
VIN = 3.3 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 1.
Parameter
Symbol Test Conditions
Min
Typ
Max
Unit
VIN
Voltage Range
Supply Current
Shutdown Current
VIN
IVIN
ISHDN
3
20
800
35
V
No switching, VIN = 12 V
VEN = 0 V, VIN = 12 V
VIN rising
640
18
2.80
2.40
μA
μA
V
Undervoltage Lockout Threshold UVLO
2.95
VIN falling
2.15
V
FB
Regulation Voltage
Bias Current
VFB
IFB
TJ = 0°C to +125°C
TJ = −40°C to +125°C
0.788
0.784
0.800
0.800
0.01
0.812
0.816
0.1
V
V
μA
SW
On Resistance1
Peak Current Limit2
Minimum On Time
Minimum Off Time
VBST − VSW = 5 V, ISW = 150 mA
VBST − VSW = 5 V, VIN = 12 V
440
1.9
100
145
70
700
2.5
135
190
120
0.9
mΩ
A
ns
ns
ns
1.5
ADP2300
ADP2301
ADP2300
ADP2301
ADP2300
ADP2301
OSCILLATOR FREQUENCY
SOFT START TIME
0.5
1.0
0.7
1.4
MHz
MHz
μs
1.75
1460
730
μs
EN
Input Threshold
Input Hysteresis
Pull-Down Current
BOOTSTRAP VOLTAGE
THERMAL SHUTDOWN
Threshold
VEN
1.13
1.2
100
1.2
5.0
1.27
V
mV
μA
V
VBOOT
No switching, VIN = 12 V
140
15
°C
°C
Hysteresis
1 Pin-to-pin measurements.
2 Guaranteed by design.
Rev. 0 | Page 3 of 28
ADP2300/ADP2301
ABSOLUTE MAXIMUM RATINGS
Table 2.
THERMAL RESISTANCE
Parameter
VIN, EN
SW
BST to SW
BST
Rating
−0.3 V to +28 V
−1.0 V to +28 V
−0.6 V to +6 V
−0.3 V to +28 V
−0.3 V to +3.3 V
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance1
Package Type
θJA
θJC
Unit
FB
6-Lead TSOT
186.02
66.34
°C/W
Operating Junction Temperature Range −40°C to +125°C
Storage Temperature Range
Soldering Conditions
−65°C to +150°C
JEDEC J-STD-020
1 θJA and θJC are measured using natural convection on a JEDEC 4-layer board.
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all voltages are
referenced to GND.
Rev. 0 | Page 4 of 28
ADP2300/ADP2301
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
6
5
4
1
2
3
BST
GND
FB
SW
VIN
EN
ADP2300/
ADP2301
TOP VIEW
(Not to Scale)
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
BST
Boost Supply for the High-Side MOSFET Driver. A 0.1 μF capacitor is connected between the SW and BST pins
to form a floating supply to drive the gate of the MOSFET switch above the VIN supply voltage.
2
3
GND
FB
Ground. Connect this pin to the ground plane.
Feedback Voltage Sense Input. Connect this pin to a resistive divider from VOUT. Set the voltage to 0.8 V for a
desired VOUT
.
4
EN
Output Enable. Pull this pin high to enable the output. Pull this pin low to disable the output. This pin can
also be used as a programmable UVLO input. This pin has a 1.2 μA pull-down current to GND.
5
6
VIN
SW
Power Input. Connect to the input power source with a ceramic bypass capacitor to GND directly from this pin.
Switch Node Output. Connect an inductor to VOUT and a catch diode to GND from this pin.
Rev. 0 | Page 5 of 28
ADP2300/ADP2301
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 3.3 V, TA = 25°C, VEN = VIN, unless otherwise noted.
100
90
80
70
60
50
40
100
INDUCTOR: LPS6225-103MLC
DIODE: B230A
90
80
70
60
V
V
V
V
V
= 5.0V
= 3.3V
= 2.5V
= 1.8V
= 1.2V
OUT
OUT
OUT
OUT
OUT
V
V
V
V
= 12V
= 9V
= 5.0V
= 3.3V
OUT
OUT
OUT
OUT
50
40
INDUCTOR: LPS6225-472MLC
DIODE: B230A
0
0.2
0.4
0.6
(A)
0.8
1.0
1.2
0
0.2
0.4
0.6
(A)
0.8
1.0
1.2
I
I
OUT
OUT
Figure 7. Efficiency Curve, VIN = 12 V, fSW = 700 kHz
Figure 4. Efficiency Curve, VIN = 18 V, fSW = 1.4 MHz
100
90
80
70
60
50
40
100
90
80
70
60
50
40
INDUCTOR: LPS6225-472MLC
DIODE: B230A
V
V
V
V
= 12V
= 9V
= 5.0V
= 3.3V
OUT
OUT
OUT
OUT
V
V
V
= 2.5V
OUT
OUT
OUT
= 1.8V
= 1.2V
INDUCTOR: LPS6225-103MLC
DIODE: B230A
0
0.2
0.4
0.6
(A)
0.8
1.0
1.2
0
0.2
0.4
0.6
(A)
0.8
1.0
1.2
I
I
OUT
OUT
Figure 8. Efficiency Curve, VIN = 5.0 V, fSW = 1.4 MHz
Figure 5. Efficiency Curve, VIN = 18 V, fSW = 700 kHz
100
90
80
70
60
50
40
100
90
80
70
60
50
40
INDUCTOR: LPS6225-103MLC
DIODE: B230A
V
V
V
= 5.0V
V
V
V
= 2.5V
OUT
OUT
OUT
OUT
OUT
OUT
INDUCTOR: LPS6225-472MLC
DIODE: B230A
= 3.3V
= 2.5V
= 1.8V
= 1.2V
0
0.2
0.4
0.6
(A)
0.8
1.0
1.2
0
0.2
0.4
0.6
(A)
0.8
1.0
1.2
I
I
OUT
OUT
Figure 6. Efficiency Curve, VIN = 12 V, fSW = 1.4 MHz
Figure 9. Efficiency Curve, VIN = 5.0 V, fSW = 700 kHz
Rev. 0 | Page 6 of 28
ADP2300/ADP2301
100
90
80
70
60
50
40
0.20
0.15
fSW = 1.4MHz
fSW = 700kHz
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
V
V
V
= 1.8V
= 1.2V
= 0.8V
OUT
OUT
OUT
INDUCTOR: LPS6225-472MLC
DIODE: B230A
5
8
11
14
17
20
0
0.2
0.4
0.6
(A)
0.8
1.0
1.2
V
(V)
I
IN
OUT
Figure 10. Efficiency Curve, VIN = 3.3 V with External 5.0 V Bootstrap Bias
Voltage, fSW = 1.4 MHz
Figure 13. Line Regulation, VOUT = 3.3 V, IOUT = 500 mA
1600
1400
1200
1000
800
100
V
V
V
= 1.8V
= 1.2V
= 0.8V
fSW = 1.4MHz
fSW = 700kHz
OUT
OUT
OUT
90
80
70
60
50
40
600
INDUCTOR: LPS6225-103MLC
DIODE: B230A
400
–50
0
0.2
0.4
0.6
(A)
0.8
1.0
1.2
–20
10
40
70
100
130
I
TEMPERATURE (°C)
OUT
Figure 11. Efficiency Curve, VIN = 3.3 V with External 5.0 V Bootstrap Bias
Voltage, fSW = 700 kHz
Figure 14. Frequency vs. Temperature
1600
1400
1200
1000
800
0.20
fSW = 1.4MHz
fSW = 700kHz
F
F
= 1.4MHz
= 700kHz
SW
SW
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
600
400
0
0.2
0.4
0.6
(A)
0.8
1.0
1.2
2
5
8
11
(V)
14
17
20
I
V
OUT
IN
Figure 12. Load Regulation, VOUT = 3.3 V, VIN = 12 V
Figure 15. Frequency vs. VIN
Rev. 0 | Page 7 of 28
ADP2300/ADP2301
40
35
30
25
20
15
10
5
160
140
120
100
80
fSW = 1.4MHz
fSW = 700kHz
60
40
T
T
T
= −40°C
= +25°C
= +125°C
20
J
J
J
0
0
–50
2
5
8
11
(V)
14
17
20
–20
10
40
70
100
130
V
TEMPERATURE (°C)
IN
Figure 16. Shutdown Current vs. VIN
Figure 19. Minimum Off Time vs. Temperature
0.804
0.802
0.800
0.798
0.796
0.794
0.792
2.5
2.0
1.5
1.0
0.5
0
–50
–20
10
40
70
100
130
2
5
8
11
(V)
14
17
20
TEMPERATURE (°C)
V
IN
Figure 17. 0.8 V Feedback Voltage vs. Temperature
Figure 20. Current-Limit Threshold vs. VIN, VBST − VSW = 5.0 V
110
105
100
95
2.5
2.0
1.5
1.0
0.5
0
90
85
80
–50
–20
10
40
70
100
130
–50
–20
10
40
70
100
130
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 18. Minimum On Time vs. Temperature
Figure 21. Current-Limit Threshold vs. Temperature
Rev. 0 | Page 8 of 28
ADP2300/ADP2301
700
660
620
580
540
500
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
RISING
FALLING
T
T
T
= −40°C
= +25°C
= +125°C
J
J
J
2
5
8
11
(V)
14
17
20
–50
–20
10
40
70
100
130
V
TEMPERATURE (°C)
IN
Figure 22. Quiescent Current vs. VIN
Figure 25. UVLO Threshold vs. Temperature
900
800
700
600
500
400
300
200
100
0
V
OUT
1
IL
SW
4
2
V
= 5V
= 4V
= 3V
GS
GS
GS
V
V
B
B
W
CH1 5mV
CH2 5V
M400ns
A CH2
7.4V
W
–50
–20
10
40
70
100
130
B
CH4 500mA Ω
W
TEMPERATURE (°C)
Figure 26. Steady State at Heavy Load, fSW = 1.4 MHz, IOUT = 1 A
Figure 23. MOSFET RDS(ON) vs. Temperature (Pin-to-Pin Measurements)
1.30
RISING
FALLING
1.25
1.20
1.15
1.10
1.05
1.00
V
OUT
1
4
IL
SW
2
B
B
CH1 20mV
CH2 5V
M10µs
A CH2
8V
W
W
–50
–20
10
40
70
100
130
CH4 200mA Ω B
W
TEMPERATURE (°C)
Figure 27. Steady State at Light Load, fSW = 1.4 MHz, IOUT = 40 mA
Figure 24. Enable Threshold vs. Temperature
Rev. 0 | Page 9 of 28
ADP2300/ADP2301
V
V
OUT
OUT
IL
1
I
OUT
1
4
EN
4
2
SW
SW
3
2
B
B
B
B
CH1 1V
CH3 10V
CH2 10V
M100µs
A CH3
8V
W
W
W
CH1 50mV
W CH2 10V
CH4 500mA Ω B
M100µs A CH4
630mA
W
CH4 500mA Ω B
B
W
W
Figure 28. Soft Start with 1 A Resistance Load, fSW = 1.4 MHz
Figure 31. ADP2301 Load Transient, 0.2 A to 1.0 A, VOUT = 3.3 V, VIN = 12 V
(fSW = 1.4 MHz, L = 4.7 μH, COUT = 22 μF)
V
OUT
V
I
OUT
1
1
4
OUT
IL
EN
4
2
SW
SW
3
2
B
B
B
B
B
CH1 1V
CH3 10V
CH2 10V
M100µs
A CH3
8V
CH1 200mV
W CH2 10V
CH4 500mA Ω B
M100µs A CH4
630mA
W
W
W
W
CH4 500mA Ω B
W
W
Figure 32. ADP2300 Load Transient, 0.2 A to 1.0 A, VOUT = 5.0 V, VIN = 12 V
(fSW = 700 kHz, L = 10 μH, COUT = 22 μF)
Figure 29. Soft Start with No Load, fSW = 1.4 MHz
V
I
OUT
OUT
V
OUT
1
1
I
OUT
SW
4
2
SW
4
2
B
B
B
B
CH1 100mV
CH2 10V
M100µs A CH4
630mA
CH1 100mV
W CH2 10V
CH4 500mA Ω B
M100µs A CH4
580mA
W
W
W
W
CH4 500mA Ω B
W
Figure 30. ADP2301 Load Transient, 0.2 A to 1.0 A, VOUT = 5.0 V, VIN = 12 V
(fSW = 1.4 MHz, L = 4.7 μH, COUT = 10 μF)
Figure 33. ADP2300 Load Transient, 0.2 A to 1.0 A, VOUT = 3.3 V, VIN = 12 V
(fSW = 700 kHz, L = 10 μH, COUT = 22 μF)
Rev. 0 | Page 10 of 28
ADP2300/ADP2301
100
80
200
160
120
80
V
OUT
60
1
40
20
40
0
0
–20
–40
–60
–80
–100
–40
–80
–120
–160
–200
V
IN
SW
3
2
CROSS FREQUENCY: 127kHz
PHASE MARGIN: 53°
B
B
W
1
2
CH1 5mV
CH3 5V
CH2 10V
M1ms
A CH3
11.4V
W
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 34. ADP2301 Line Transient,
7 V to 15 V, VOUT = 3.3 V, IOUT = 1.2 A, fSW = 1.4 MHz
Figure 37. ADP2301 Bode Plot, VOUT = 5.0 V, VIN = 12 V
(fSW = 1.4 MHz, L = 4.7 μH, COUT = 10 μF)
100
80
200
160
120
80
V
OUT
60
40
20
40
1
0
0
–20
–40
–60
–80
–100
–40
–80
–120
–160
–200
IL
SW
4
2
CROSS FREQUENCY: 80kHz
PHASE MARGIN: 68°
B
B
B
CH1 1V
CH2 10V
CH4 1A Ω
M10µs
A CH1
2.56V
1
2
W
W
W
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 35. ADP2301 Short-Circuit Entry, VOUT = 3.3 V
(fSW = 1.4 MHz)
Figure 38. ADP2301 Bode Plot, VOUT = 3.3 V, VIN = 12 V
(fSW = 1.4 MHz, L = 4.7 μH, COUT = 22 μF)
100
80
200
160
120
80
60
1
40
20
40
V
OUT
0
0
–20
–40
–60
–80
–100
–40
–80
–120
–160
–200
IL
4
2
SW
CROSS FREQUENCY: 27kHz
PHASE MARGIN: 76°
B
B
B
1
2
CH1 1V
CH2 10V
CH4 1A Ω
M100µs
A CH1
1.2V
W
W
W
1k
10k
100k
FREQUENCY (Hz)
1M
Figure 36. ADP2301 Short-Circuit Recovery, VOUT = 3.3 V
(fSW = 1.4 MHz)
Figure 39. ADP2300 Bode Plot, VOUT = 5.0 V, VIN = 12 V
(fSW = 700 kHz, L = 10 μH, COUT = 22 μF)
Rev. 0 | Page 11 of 28
ADP2300/ADP2301
100
200
160
120
80
80
60
40
20
40
0
0
–20
–40
–60
–40
–80
–120
–160
–200
–80
CROSS FREQUENCY: 47kHz
PHASE MARGIN: 77°
–100
1
2
1k
10k
100k
FREQUENCY (Hz)
1M
Figure 40. ADP2300 Bode Plot, VOUT = 3.3 V, VIN = 12 V
(fSW = 700 kHz, L = 10 μH, COUT = 22 μF)
Rev. 0 | Page 12 of 28
ADP2300/ADP2301
FUNCTIONAL BLOCK DIAGRAM
V
IN
VIN
5
THERMAL
SHUTDOWN
SHUTDOWN
LOGIC
UVLO
SHUTDOWN IC
1.20V
OCP
4
EN
ON
250mV/A
BST
BOOT
REGULATOR
1
1.2µA
0.90V
0.5V
OFF
OVP
R
S
Q
V
OUT
V
= 1.1V
SW
BIAS
6
RAMP
GENERATOR
CLK
GENERATOR
0.8V
FREQUENCY FOLDBACK
V
FB
(fSW, ½ fSW, ¼ fSW)
FB
3
GND
220kΩ
90pF
2
0.7pF
ADP2300/ADP2301
Figure 41. ADP2300/ADP2301 Functional Block Diagram
Rev. 0 | Page 13 of 28
ADP2300/ADP2301
THEORY OF OPERATION
The ADP2300/ADP2301 are nonsynchronous, step-down
dc-to-dc regulators, each with an integrated high-side power
MOSFET. A high switching frequency and ultrasmall, 6-lead
TSOT package allow small step-down dc-to-dc regulator
solutions.
Since the pulse-skip mode comparator monitors the internal
compensation node, which represents the peak inductor current
information, the average pulse-skip load current threshold depends
on the input voltage (VIN), the output voltage (VOUT), the inductor,
and the output capacitor.
The ADP2300/ADP2301 can operate with an input voltage from
3.0 V to 20 V while regulating an output voltage down to 0.8 V.
Because the output voltage occasionally dips below regulation
and then recovers, the output voltage ripple in the power saving
mode is larger than the ripple in the PWM mode of operation.
The ADP2300/ADP2301 are available in two fixed-frequency
options: 700 kHz (ADP2300) and 1.4 MHz (ADP2301).
BOOTSTRAP CIRCUITRY
The ADP2300/ADP2301 each have an integrated boot regulator,
which requires that a 0.1 μF ceramic capacitor (X5R or X7R) be
placed between the BST and SW pins to provide the gate drive
voltage for the high-side MOSFET. There must be at least a 1.2 V
difference between the BST and SW pins to turn on the high-side
MOSFET. This voltage should not exceed 5.5 V in case the BST
pin is supplied with an external voltage source through a diode.
BASIC OPERATION
The ADP2300/ADP2301 use the fixed-frequency, peak current-
mode PWM control architecture at medium to high loads, but
shift to a pulse-skip mode control scheme at light loads to reduce
the switching power losses and improve efficiency. When the
devices operate in fixed-frequency PWM mode, output regulation
is achieved by controlling the duty cycle of the integrated MOSFET.
When the devices operate in pulse-skip mode at light loads, the
output voltage is controlled in a hysteretic manner with higher
output ripple. In this mode of operation, the regulator periodically
stops switching for a few cycles, thus keeping the conversion
losses minimal to improve efficiency.
The ADP2300/ADP2301 generate a typical 5.0 V bootstrap voltage
for a gate drive circuit by differentially sensing and regulating the
voltage between the BST and SW pins. A diode integrated on the
chip blocks the reverse voltage between the VIN and BST pins
when the MOSFET switch is turned on.
PWM MODE
PRECISION ENABLE
In PWM mode, the ADP2300/ADP2301 operate at a fixed
frequency, set by an internal oscillator. At the start of each
oscillator cycle, the MOSFET switch is turned on, sending a
positive voltage across the inductor. The inductor current
increases until the current-sense signal crosses the peak
inductor current threshold that turns off the MOSFET switch;
this threshold is set by the error amplifier output. During the
MOSFET off time, the inductor current declines through the
external diode until the next oscillator clock pulse starts a new
cycle. The ADP2300/ADP2301 regulate the output voltage by
adjusting the peak inductor current threshold.
The ADP2300/ADP2301 feature a precision enable circuit that
has a 1.2 V reference voltage with 100 mV hysteresis. When the
voltage at the EN pin is greater than 1.2 V, the part is enabled. If the
EN voltage falls below 1.1 V, the chip is disabled. The precision
enable threshold voltage allows the ADP2300/ADP2301 to be
easily sequenced from other input/output supplies. It can also be
used as programmable UVLO input by using a resistive divider.
An internal 1.2 μA pull-down current prevents errors if the EN pin
is floating.
INTEGRATED SOFT START
The ADP2300/ADP2301 include internal soft start circuitry
that ramps the output voltage in a controlled manner during
startup, thereby limiting the inrush current. The soft start time is
typically fixed at 1460 μs for the ADP2300 and at 730 μs for the
ADP2301.
POWER SAVING MODE
To achieve higher efficiency, the ADP2300/ADP2301 smoothly
transition to the pulse-skip mode when the output load decreases
below the pulse-skip current threshold. When the output voltage
dips below regulation, the ADP2300/ADP2301 enter PWM mode
for a few oscillator cycles until the voltage increases to within
regulation. During the idle time between bursts, the MOSFET
switch is turned off, and the output capacitor supplies all the
output current.
CURRENT LIMIT
The ADP2300/ADP2301 include current-limit protection circuitry
to limit the amount of positive current flowing through the high-
side MOSFET switch. The positive current limit on the power
switch limits the amount of current that can flow from the input
to the output.
Rev. 0 | Page 14 of 28
ADP2300/ADP2301
SHORT-CIRCUIT PROTECTION
UNDERVOLTAGE LOCKOUT (UVLO)
The ADP2300/ADP2301 include frequency foldback to prevent
output current runaway when there is a hard short on the output.
The switching frequency is reduced when the voltage at the FB pin
drops below a certain value, which allows more time for the
inductor current to decline, but increases the ripple current while
regulating the peak current. This results in a reduction in average
output current and prevents output current runaway. The corre-
lation between the switching frequency and the FB pin voltage
is shown in Table 5.
The ADP2300/ADP2301 have fixed, internally set undervoltage
lockout circuitry. If the input voltage drops below 2.4 V, the
ADP2300/ADP2301 shut down and the MOSFET switch turns
off. After the voltage rises again above 2.8 V, the soft start
period is initiated, and the part is enabled.
THERMAL SHUTDOWN
If the ADP2300/ADP2301 junction temperature rises above 140°C,
the thermal shutdown circuit disables the chip. Extreme junction
temperature can be the result of high current operation, poor
circuit board design, or high ambient temperature. A 15°C
hysteresis is included so that when thermal shutdown occurs,
the ADP2300/ADP2301 do not return to operation until the on-
chip temperature drops below 125°C. After the devices recover
from thermal shutdown, a soft start is initiated.
Table 5. Correlation Between the Switching Frequency
and the FB Pin Voltage
FB Pin Voltage
Switching Frequency
VFB ≥ 0.6 V
fSW
0.6 V > VFB > 0.2 V
½ fSW
VFB ≤ 0.2 V
¼ fSW
CONTROL LOOP
The ADP2300/ADP2301 are internally compensated to minimize
external component count and cost. In addition, the built-in
slope compensation helps to prevent subharmonic oscillations
when the ADP2300/ADP2301 operate at a duty cycle greater
than or close to 50%.
When a hard short (VFB ≤ 0.2 V) is removed, a soft start cycle
is initiated to regulate the output back to its level during normal
operation, which helps to limit the inrush current and prevent
possible overshoot on the output voltage.
Rev. 0 | Page 15 of 28
ADP2300/ADP2301
APPLICATIONS INFORMATION
PROGRAMMING THE OUTPUT VOLTAGE
VOLTAGE CONVERSION LIMITATIONS
There are both lower and upper output voltage limitations for a
given input voltage due to the minimum on time, the minimum
off time, and the bootstrap dropout voltage.
The output voltage of the ADP2300/ADP2301 is externally set by
a resistive voltage divider from the output voltage to the FB pin,
as shown in Figure 42. Suggested resistor values for the typical
output voltage setting are listed in Table 6. The equation for the
output voltage setting is
The lower limit of the output voltage is constrained by the finite,
controllable minimum on time, which can be as high as 135 ns for
the worst case. By considering the variation of both the switching
frequency and the input voltage, the equation for the lower limit
of the output voltage is
⎛
⎞
⎟
⎟
⎠
RFB1
RFB2
⎜
VOUT = 0.800 V× 1+
⎜
⎝
where:
VOUT is the output voltage.
RFB1 is the feedback resistor from VOUT to FB.
VOUT(min) = t MIN-ON × fSW(max) ×(VIN(max) +VD ) −VD
where:
V
f
t
IN(max) is the maximum input voltage.
SW(max) is the maximum switching frequency for the worst case.
MIN-ON is the minimum controllable on time.
RFB2 is the feedback resistor from FB to GND.
VD is the diode forward drop.
The upper limit of the output voltage is constrained by the mini-
mum controllable off time, which can be as high as 120 ns in
the ADP2301 for the worst case. By considering the variation of
both the switching frequency and the input voltage, the equation
for the upper limit of the output voltage is
ADP2300/
ADP2301
V
OUT
R
FB1
FB
R
FB2
VOUT(max) = (1 − tMIN-OFF × fSW(max) )×(VIN(min) +VD )−VD
Figure 42. Programming the Output Voltage Using a Resistive Voltage Divider
where:
Table 6. Suggested Values for Resistive Voltage Divider
V
f
IN(min) is the minimum input voltage.
SW(max) is the maximum switching frequency for the worst case.
VD is the diode forward drop.
MIN-OFF is the minimum controllable off time.
VOUT (V)
RFB1 (kΩ), 1ꢀ
RFB2 (kΩ), 1ꢀ
1.2
1.8
2.5
3.3
4.99
12.7
21.5
31.6
52.3
10
10.2
10.2
10.2
10
t
In addition, the bootstrap circuit limits the minimum input
voltage for the desired output due to internal dropout voltage.
To attain stable operation at light loads and ensure proper startup
for the prebias condition, the ADP2300/ADP2301 require the
voltage difference between the input voltage and the regulated
output voltage (or between the input voltage and the prebias
voltage) to be greater than 2.1 V for the worst case. If the voltage
difference is smaller, the bootstrap circuit relies on some minimum
load current to charge the boost capacitor for startup. Figure 43
shows the typical required minimum input voltage vs. load current
for the 3.3 V output voltage.
5.0
Rev. 0 | Page 16 of 28
ADP2300/ADP2301
5.5
5.3
5.1
4.9
4.7
4.5
4.3
4.1
3.9
3.7
3.5
PROGRAMMING THE PRECISION ENABLE
FOR STARTUP
Generally, the EN pin can be easily tied to the VIN pin so that the
device automatically starts up when the input power is applied.
However, the precision enable feature allows the ADP2300/
ADP2301 to be used as a programmable UVLO by connecting
a resistive voltage divider to VIN, as shown in Figure 46. This
configuration prevents the start-up problems that can occur
when VIN ramps up slowly in soft start with a relatively high
load current.
FOR RUNNING
V
IN
VIN
V
f
= 3.3V
OUT
= 1.4MHz
SW
ADP2300/
ADP2301
R
EN1
EN2
1
10
100
1k
LOAD CURRENT (mA)
EN
Figure 43. Minimum Input Voltage vs. Load Current
R
Based on three conversion limitations (the minimum on time,
the minimum off time, and the bootstrap dropout
voltage), Figure 44 shows the voltage conversion limitations.
22
Figure 46. Precision Enable Used as a Programmable UVLO
The precision enable feature also allows the ADP2300/ADP2301 to
be sequenced precisely by using a resistive voltage divider with
another dc-to-dc output supply, as shown in Figure 47.
17
12
7
ADP2300/
ADP2301
R
EN1
OTHER DC-TO-DC
OUTPUT
EN
R
EN2
Figure 47. Precision Enable Used as a Sequencing Control
from Another DC-to-DC Output
MAXIMUM INPUT FOR ADP2300
MAXIMUM INPUT FOR ADP2301
With a 1.2 μA pull-down current on the EN pin, the equation for
the start-up voltage in Figure 46 and Figure 47 is
MINIMUM INPUT FOR ADP2300/ADP2301
2
0
2
4
6
8
10
12
14
16
V
(V)
OUT
1.2 V
⎛
⎜
⎜
⎝
⎞
⎟
⎠
⎟
VSTARTUP
=
+1.2 ꢀA ×REN1 +1.2 V
Figure 44. Voltage Conversion Limitations
REN 2
LOW INPUT VOLTAGE CONSIDERATIONS
where:
STARTUP is the start-up voltage to enable the chip.
For low input voltage between 3 V and 5 V, the internal boot
regulator cannot provide enough 5.0 V bootstrap voltage due to
the internal dropout voltage. As a result, the increased MOSFET
V
R
EN1 is the resistor from the dc source to EN.
R
EN2 is the resistor from EN to GND.
RDS(ON) reduces the available load current. To prevent this, add
an external small-signal Schottky diode from a 5.0 V external
bootstrap bias voltage. Because the absolute maximum rating
between the BST and SW pins is 6.0 V, the bias voltage should
be less than 5.5 V. Figure 45 shows the application diagram for
the external bootstrap circuit.
SCHOTTKY DIODE
3V ~ 5V
BST
VIN
5V BIAS
VOLTAGE
ADP2300/
ADP2301
SW
EN
FB
GND
ON
OFF
Figure 45. External Bootstrap Circuit for Low Input Voltage Application
Rev. 0 | Page 17 of 28
ADP2300/ADP2301
The inductor peak current is calculated using the following
equation:
INDUCTOR
The high switching frequency of the ADP2300/ADP2301 allows
the use of small inductors. For best performance, use inductor
values between 2 ꢀH and 10 ꢀH for ADP2301, and use inductor
values between 2 ꢀH and 22 ꢀH for ADP2300.
ΔIRIPPLE
IPEAK = ILOAD(max)
+
2
The minimum current rating of the inductor must be greater
than the inductor peak current. For ferrite core inductors with a
quick saturation characteristic, the inductor saturation current
rating should be higher than the switch current-limit threshold
to prevent the inductor from reaching its saturation point. Be
sure to validate the worst-case condition, in which there is a
shorted output, over the intended temperature range.
The peak-to-peak inductor current ripple is calculated using the
following equation:
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
(VIN −VOUT
L× fsw
)
VOUT +VD
VIN +VD
ΔIRIPPLE
=
×
where:
SW is the switching frequency.
f
Inductor conduction losses are caused by the flow of current
through the inductor, which is associated with the internal dc
resistance (DCR). Larger sized inductors have smaller DCR and,
therefore, may reduce inductor conduction losses. However,
inductor core losses are also related to the core material and the
ac flux swing, which are affected by the peak-to-peak induc-
tor ripple current. Because the ADP2300/ADP2301 are high
switching frequency regulators, shielded ferrite core materials
are recommended for their low core losses and low EMI. Some
recommended inductors are shown in Table 7.
L is the inductor value.
VD is the diode forward drop.
VIN is the input voltage.
V
OUT is the output voltage.
Inductors of smaller values are usually smaller in size and less
expensive, but increase the ripple current and the output voltage
ripple. As a guideline, the inductor peak-to-peak current ripple
should typically be set to 30% of the maximum load current for
optimal transient response and efficiency. Therefore, the inductor
value is calculated using the following equation:
(
VIN −VOUT
0.3× ILOAD(max) × fsw
)
⎛VOUT +VD
⎞
⎟
⎟
⎠
⎜
⎜
L =
×
VIN +VD
⎝
where ILOAD(max) is the maximum load current.
Table 7. Recommended Inductors
Dimensions
Vendor
Value (μH)
Part No.
DCR (mΩ)
65
95
105
43
64
61
84
93
ISAT (A)
3.1
2.7
L × W × H (mm)
6.0 × 6.0 × 2.4
6.0 × 6.0 × 2.4
6.0 × 6.0 × 2.4
6.2 × 6.2 × 3.0
5.8 × 5.8 × 1.8
6.2 × 6.2 × 3.0
5.8 × 5.8 × 1.8
6.2 × 6.2 × 3.0
5.2 × 5.2 × 3.0
5.2 × 5.2 × 3.0
7.6 × 7.6 × 3.5
7.6 × 7.6 × 4.0
7.6 × 7.6 × 4.0
7.6 × 7.6 × 4.0
5.0 × 5.0 × 4.5
5.0 × 5.0 × 4.5
5.0 × 5.0 × 4.5
Coilcraft
4.7
6.8
10
LPS6225-472MLC
LPS6225-682MLC
LPS6225-103MLC
CDRH5D28RHPNP-4R7N
CDRH5D16NP-4R7N
CDRH5D28RHPNP-6R8N
CDRH5D16NP-6R8N
CDRH5D28RHPNP-100M
SD53-4R7-R
2.1
Sumida
4.7
4.7
6.8
6.8
10
3.7
2.15
3.1
1.8
2.45
2.1
1.85
2.47
2.6
2.3
1.8
Cooper Bussmann 4.7
39
59
65
6.8
10
SD53-6R8-R
DR73-100-R
Toko
TDK
4.7
6.8
10
B1077AS-4R7N
B1077AS-6R8N
B1077AS-100M
34
40
58
4.7
6.8
10
VLC5045T-4R7M
VLC5045T-6R8M
VLC5045T-100M
34
46
66
3.3
2.7
2.1
Rev. 0 | Page 18 of 28
ADP2300/ADP2301
CATCH DIODE
OUTPUT CAPACITOR
The catch diode conducts the inductor current during the off
time of the internal MOSFET. The average current of the diode
in normal operation is, therefore, dependent on the duty cycle
of the regulator as well as the output load current.
The output capacitor selection affects both the output voltage ripple
and the loop dynamics of the regulator. The ADP2300/ADP2301
are designed to operate with small ceramic capacitors that have low
equivalent series resistance (ESR) and equivalent series inductance
(ESL) and are, therefore, easily able to meet stringent output voltage
ripple specifications.
⎛
⎜
⎝
⎞
⎟
⎟
⎠
VOUT +VD
VIN +VD
⎜
IDIODE(AVG) = 1−
× ILOAD(max)
When the regulator operates in forced continuous conduction
mode, the overall output voltage ripple is the sum of the voltage
spike caused by the output capacitor ESR plus the voltage ripple
caused by charging and discharging the output capacitor.
where VD is the diode forward drop.
The only reason to select a diode with a higher current rating than
necessary in normal operation is for the worst-case condition, in
which there is a shorted output. In this case, the diode current
increases up to the typical peak current-limit threshold. Be sure to
consult the diode data sheet to ensure that the diode can operate
well within the thermal and electrical limits.
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
1
ΔVRIPPLE = ΔIRIPPLE
×
+ ESR
COUT
8× fsw ×COUT
Capacitors with lower ESR are preferable to guarantee low
output voltage ripple, as shown in the following equation:
The reverse breakdown voltage rating of the diode must be higher
than the highest input voltage and allow an appropriate margin
for the ringing that may be present on the SW node. A Schottky
diode is recommended for best efficiency because it has a low
forward voltage drop and fast switching speed. Table 8 provides
a list of recommended Schottky diodes.
ΔVRIPPLE
ΔIRIPPLE
ESRC
≤
OUT
Ceramic capacitors are manufactured with a variety of dielectrics,
each with different behavior over temperature and applied voltage.
X5R or X7R dielectrics are recommended for best performance,
due to their low ESR and small temperature coefficients. Y5V
and Z5U dielectrics are not recommended because of their poor
temperature and dc bias characteristics.
Table 8. Recommended Schottky Diodes
VRRM
(V)
IAVG
(A)
Vendor
Part No.
MBRS230LT3
MBRS240LT3
B230A
ON Semiconductor
30
40
30
40
30
40
2
2
2
2
2
2
In general, most applications using the ADP2301 (1.4 MHz
switching frequency) require a minimum output capacitor value
of 10 μF, whereas most applications using the ADP2300 (700 kHz
switching frequency) require a minimum output capacitor value
of 20 μF. Some recommended output capacitors for VOUT ≤ 5.0 V
are listed in Table 9.
Diodes Inc.
Vishay
B240A
SL23
SS24
Table 9. Recommended Capacitors for VOUT ≤ 5.0 V
INPUT CAPACITOR
Dimensions
The input capacitor must be able to support the maximum input
operating voltage and the maximum rms input current. The
maximum rms input current flowing through the input
capacitor is ILOAD(max)/2. Select an input capacitor capable of
withstanding the rms input current for an application’s maxi-
mum load current using the following equation:
Vendor Value
Part No.
L × W × H (mm)
3.2 × 1.6 × 1.15
3.2 × 1.6 × 1.6
3.2 × 1.6 × 1.6
3.2 × 1.6 × 0.85
Murata
10 μF, 6.3 V GRM31MR60J106KE19
22 μF, 6.3 V GRM31CR60J226KE19
10 μF, 6.3 V C3216X5R0J106K
22 μF, 6.3 V C3216X5R0J226M
TDK
IIN(RMS) = ILOAD(max) × D×(1− D)
where D is the duty cycle and is equal to
VOUT +VD
VIN +VD
D =
The recommended input capacitor is ceramic with X5R or X7R
dielectrics due to its low ESR and small temperature coefficients.
A capacitance of 10 μF should be adequate for most applications.
To minimize supply noise, place the input capacitor as close to
the VIN pin of the ADP2300/ADP2301 as possible.
Rev. 0 | Page 19 of 28
ADP2300/ADP2301
The rise in temperature of the package is directly proportional
to the power dissipation in the package. The proportionality
constant for this relationship is the thermal resistance from the
junction of the die to the ambient temperature, as shown in the
following equation:
THERMAL CONSIDERATIONS
The ADP2300/ADP2301 store the value of the inductor current
only during the on time of the internal MOSFET. Therefore, a small
amount of power is dissipated inside the ADP2300/ADP2301
package, which reduces thermal constraints.
TR = θJA × PD
However, when the application is operating under maximum
load with high ambient temperature and high duty cycle, the
heat dissipated within the package may cause the junction
temperature of the die to exceed the maximum junction
temperature of 125°C. If the junction temperature exceeds
140°C, the regulator goes into thermal shutdown and recovers
when the junction temperature drops below 125°C.
where:
TR is the rise in temperature of the package.
θJA is the thermal resistance from the junction of the die to the
ambient temperature of the package.
PD is the power dissipation in the package.
The junction temperature of the die is the sum of the ambient
temperature of the environment and the temperature rise of the
package due to power dissipation, as indicated in the following
equation:
TJ = TA + TR
where:
TJ is the junction temperature.
TA is the ambient temperature.
TR is the rise in temperature of the package due to power
dissipation.
Rev. 0 | Page 20 of 28
ADP2300/ADP2301
DESIGN EXAMPLE
This section provides the procedures to select the external com-
ponents, based on the example specifications listed in Table 10.
The schematic for this design example is shown in Figure 48.
INDUCTOR SELECTION
Select the inductor by using the following equation:
VIN −VOUT
0.3× ILOAD(max) × fsw
)
⎛VOUT +VD
⎞
⎟
⎟
⎠
⎜
⎜
L =
×
Table 10. Step-Down DC-to-DC Regulator Requirements
VIN +VD
⎝
Additional
Parameter
Specification
Requirements
where:
OUT = 3.3 V.
VIN = 12 V.
LOAD(max) = 1.2 A.
VD = 0.4 V.
SW = 1.4 MHz.
Input Voltage, VIN
Output Voltage, VOUT 3.3 V, 1.2 A, 1ꢀ VOUT
ripple at CCM mode
Programmable
UVLO Voltage
12.0 V 10ꢀ
None
None
V
I
VIN start-up voltage
approximately 7.8 V
None
f
This results in L = 5.15 μH. The closest standard value is 4.7 μH;
therefore, ΔIRIPPLE = 0.394 A.
SWITCHING FREQUENCY SELECTION
Select the switching frequency—700 kHz (ADP2300) or 1.4 MHz
(ADP2301)—using the conversion limitation curve shown
in Figure 44 to assess the conversion limitations (the minimum on
time, the minimum off time, and the bootstrap dropout voltage).
The inductor peak current is calculated using the following
equation:
ΔIRIPPLE
IPEAK = ILOAD(max)
+
2
For example, in Figure 44 VIN = 12 V 10% is within the conver-
sion limitation for both the 700 kHz and 1.4 MHz switching
frequencies for an output voltage of 3.3 V, but choosing the 1.4 MHz
switching frequency provides the smallest sized solution. If higher
efficiency is required, choose the 700 kHz option; however, the
PCB footprint area of the regulator will be larger because of the
bigger inductor and output capacitors.
where:
LOAD(max) = 1.2 A.
ΔIRIPPLE = 0.394 A.
I
Therefore, the calculated peak current for the inductor is 1.397 A.
However, to protect the inductor from reaching its saturation
point in the current-limit condition, the inductor should be rated
for at least a 2.0 A saturation current for reliable operation.
CATCH DIODE SELECTION
OUTPUT CAPACITOR SELECTION
Select the catch diode. A Schottky diode is recommended for best
efficiency because it has a low forward voltage drop and faster
switching speed. The average current of the catch diode in
normal operation, with a typical Schottky diode forward
voltage, can be calculated using the following equation:
Select the output capacitor based on the output voltage ripple
requirement, according to the following equation:
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
1
ΔVRIPPLE = ΔIRIPPLE
×
+ ESRC
OUT
8× fsw ×COUT
⎛
⎜
⎝
⎞
⎟
⎟
⎠
VOUT +VD
VIN +VD
⎜
IDIODE(AVG) = 1−
× ILOAD(max)
where:
ΔIRIPPLE = 0.394 A.
SW = 1.4 MHz.
ΔVRIPPLE = 33 mV.
where:
OUT = 3.3 V.
VIN = 12 V.
LOAD(max) = 1.2 A.
VD = 0.4 V.
Therefore, IDIODE(AVG) = 0.85 A.
f
V
If the ESR of the ceramic capacitor is 3 mΩ, then COUT = 1.2 μF.
I
Because the output capacitor is one of the two external components
that control the loop stability, most applications using the ADP2301
(1.4 MHz switching frequency) require a minimum 10 μF capaci-
tance to ensure stability. According to the recommended external
components in Table 11, choose 22 μF with a 6.3 V voltage rating
for this example.
However, for the worst-case condition, in which there is a shorted
output, the diode current would be increased to 2 A typical, deter-
mined by the peak switch current limit (see Table 1). In this case,
selecting a B230A, 2.0 A/30 V surface-mount Schottky diode
would result in more reliable operation.
Rev. 0 | Page 21 of 28
ADP2300/ADP2301
The resistive voltage divider for the programmable VIN start-up
voltage is
RESISTIVE VOLTAGE DIVIDER SELECTION
To select the appropriate resistive voltage divider, first calculate the
output feedback resistive voltage divider, and then calculate the
resistive voltage divider for the programmable VIN start-up voltage.
1.2 V
⎛
⎜
⎜
⎝
⎞
⎟
⎠
⎟
VSTARTUP
=
+1.2 ꢀA ×REN1 +1.2 V
REN 2
The output feedback resistive voltage divider is
If VSTARTUP = 7.8 V, choose REN2 = 10.2 kΩ, and then calculate
⎛
⎜
⎝
⎞
⎟
⎟
⎠
RFB1
RFB2
REN1, which in this case is 56 kΩ.
⎜
VOUT = 0.800 V× 1+
For the 3.3 V output voltage, choose RFB1 = 31.6 kΩ and RFB2
= 10.2 kΩ as the feedback resistive voltage divider, according to
the recommended values in Table 11.
BST
SW
V
= 12V
IN
C3
VIN
0.1µF
C1
10µF
25V
L1
6.3V
4.7µH
2.0A
V
= 3.3V
OUT
1.2A
ADP2301
(1.4MHz)
C2
22µF
6.3V
D1
B230A
R3
56kΩ
1%
R1
31.6kΩ
1%
EN
FB
R4
R2
10.2kΩ
1%
10.2kΩ
GND
1%
Figure 48. Schematic for the Design Example
Table 11. Recommended External Components for Typical Applications at 1.2 A Output Load
Part Number
VIN (V)
18
18
12
12
12
12
12
9
VOUT (V)
3.3
5.0
1.2
1.8
2.5
3.3
5.0
3.3
5.0
1.8
2.5
3.3
5.0
2.5
3.3
5.0
3.3
5.0
1.8
2.5
IOUT (A)
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
L (μH)
COUT (μF)
RFB1 (kΩ), 1ꢀ
RFB2 (kΩ), 1ꢀ
10.2
10
ADP2300 (700 kHz)
10
15
6.8
6.8
10
10
10
10
10
4.7
4.7
4.7
6.8
4.7
4.7
4.7
4.7
4.7
2.2
2.2
22
22
2 × 22
2 × 22
22
22
22
22
22
31.6
52.3
4.99
12.7
21.5
31.6
52.3
31.6
10
10.2
10.2
10.2
10
10.2
10
10.2
10.2
10.2
10
10.2
10.2
10
9
5
5
52.3
12.7
21.5
2 × 22
22
ADP2301 (1.4 MHz)
18
18
12
12
12
9
9
5
5
22
10
22
22
10
22
10
2 × 22
22
31.6
52.3
21.5
31.6
52.3
31.6
52.3
12.7
10.2
10
10.2
10.2
21.5
Rev. 0 | Page 22 of 28
ADP2300/ADP2301
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Good circuit board layout is essential to obtain the best
performance from the ADP2300/ADP2301. Poor layout can
affect the regulation and stability, as well as the electromagnetic
interface (EMI) and electromagnetic compatibility (EMC)
performance. A PCB layout example is shown in Figure 50.
Refer to the following guidelines for a good PCB layout:
•
Minimize the length of the FB trace connecting the top of the
feedback resistive voltage divider to the output. In addition,
keep these traces away from the high current traces and the
switch node to avoid noise pickup.
BST
VIN
•
Place the input capacitor, inductor, catch diode, output
capacitor, and bootstrap capacitor close to the IC using
short traces.
Ensure that the high current loop traces are as short and wide
as possible. The high current path is shown in Figure 49.
Maximize the size of ground metal on the component side
to improve thermal dissipation.
Use a ground plane with several vias connecting to the
component side ground to further reduce noise inter-
ference on sensitive circuit nodes.
ADP2300/
SW
ADP2301
EN
FB
•
•
•
GND
Figure 49. Typical Application Circuit with High Current Traces Shown in Blue
INDUC TOR
C3
L1
CATCH DIODE
D1
BST CAP
C1
C2
ADP2300/ADP2301
INPUT CAP
Figure 50. Recommended PCB Layout for the ADP2300/ADP2301
Rev. 0 | Page 23 of 28
ADP2300/ADP2301
TYPICAL APPLICATION CIRCUITS
BST
SW
V
= 12V
IN
VIN
C4
C1
10µF
25V
0.1µF
6.3V
L1
6.8µH
2.0A
V
= 1.2V
OUT
1.2A
ADP2300
(700kHz)
C2
22µF
6.3V
C3
22µF
6.3V
D1
B230A
R3
100kΩ
R1
5%
4.99kΩ
1%
EN
FB
R2
10kΩ
1%
ON
GND
OFF
Figure 51. ADP2300—700 kHz Typical Application, VIN = 12 V, VOUT = 1.2 V/1.2 A with External Enabling
BST
V
= 12V
IN
VIN
C4
C1
10µF
25V
0.1µF
6.3V
L1
6.8µH
2.0A
V
= 1.8V
OUT
1.2A
ADP2300
(700kHz)
SW
FB
C2
22µF
6.3V
C3
22µF
6.3V
D1
B230A
R3
100kΩ
R1
5%
12.7kΩ
1%
EN
R2
10.2kΩ
1%
ON
GND
OFF
Figure 52. ADP2300—700 kHz Typical Application, VIN = 12 V, VOUT = 1.8 V/1.2 A with External Enabling
BST
V
= 12V
C1
IN
VIN
C3
0.1µF
6.3V
L1
10µH
2.0A
10µF
25V
V
= 2.5V
OUT
1.2A
ADP2300
(700kHz)
SW
FB
C2
22µF
6.3V
D1
B230A
R3
100kΩ
R1
5%
21.5kΩ
1%
EN
R2
10.2kΩ
1%
ON
GND
OFF
Figure 53. ADP2300—700 kHz Typical Application, VIN = 12 V, VOUT = 2.5 V/1.2 A with External Enabling
Rev. 0 | Page 24 of 28
ADP2300/ADP2301
BST
SW
V
= 12V
IN
C3
VIN
0.1µF
6.3V
C1
10µF
25V
L1
4.7µH
2.0V
V
= 3.3V
OUT
1.2A
ADP2301
(1.4MHz)
C2
22µF
6.3V
D1
B230A
R3
56kΩ
1%
R1
31.6kΩ
1%
FB
EN
R4
R2
10.2kΩ
1%
10.2kΩ
GND
1%
Figure 54. ADP2301—1.4 MHz Typical Application, VIN = 12 V, VOUT = 3.3 V/1.2 A
(with Programmable 7.8 V Start-Up Input Voltage)
BST
V
= 12V
IN
VIN
C3
C1
10µF
25V
0.1µF
L1
6.3V 4.7µH
2.0A
V
= 5V
OUT
ADP2301
(1.4MHz)
1.2A
SW
FB
C2
10µF
6.3V
D1
B230A
R3
100kΩ
R1
5%
52.3kΩ
1%
EN
R2
10kΩ
1%
ON
GND
OFF
Figure 55. ADP2301—1.4 MHz Typical Application, VIN = 12 V, VOUT = 5.0 V/1.2 A with External Enabling
BST
V
= 18V
C1
IN
VIN
C3
0.1µF
6.3V
L1
6.8µH
2.0A
10µF
25V
V
= 5.0V
OUT
1.2A
ADP2301
(1.4MHz)
SW
FB
C2
10µF
6.3V
D1
B230A
R3
100kΩ
R1
5%
52.3kΩ
1%
EN
R2
10.2kΩ
1%
ON
GND
OFF
Figure 56. ADP2301—1.4 MHz Typical Application, VIN = 18 V, VOUT = 5.0 V/1.2 A with External Enabling
BST
V
= 9V
IN
VIN
C3
0.1µF
6.3V
C1
L1
4.7µH
2.0A
10µF
25V
V
= 3.3V
1.2A
OUT
ADP2301
(1.4MHz)
SW
FB
C2
22µF
6.3V
D1
B230A
R3
100kΩ
R1
5%
31.6kΩ
1%
EN
R2
10.2kΩ
1%
ON
GND
OFF
Figure 57. ADP2301—1.4 MHz Typical Application, VIN = 9 V, VOUT = 3.3 V/1.2 A with External Enabling
BST
V
= 5V
IN
VIN
C4
0.1µF
6.3V
C1
L1
2.2µH
2.0A
10µF
25V
V
= 1.8V
1.2A
OUT
ADP2301
(1.4MHz)
SW
FB
C2
22µF
6.3V
C3
22µF
6.3V
D1
B230A
R3
100kΩ
R1
5%
12.7kΩ
1%
EN
R2
10.2kΩ
1%
ON
GND
OFF
Figure 58. ADP2301—1.4 MHz Typical Application, VIN = 5 V, VOUT = 1.8 V/1.2 A with External Enabling
Rev. 0 | Page 25 of 28
ADP2300/ADP2301
OUTLINE DIMENSIONS
2.90 BSC
6
1
5
2
4
3
2.80 BSC
1.60 BSC
PIN 1
INDICATOR
0.95 BSC
1.90
BSC
*
0.90
0.87
0.84
0.20
0.08
*
1.00 MAX
8°
4°
0°
0.10 MAX
SEATING
PLANE
0.60
0.45
0.30
0.50
0.30
*
COMPLIANT TO JEDEC STANDARDS MO-193-AA WITH
THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
Figure 59. 6-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-6)
Dimensions shown in millimeters
ORDERING GUIDE
Switching
Frequency Temperature Range Package Description
Package
Option
Model1
Branding
ADP2300AUJZ-R7
ADP2300-EVALZ
ADP2301AUJZ-R7
ADP2301-EVALZ
700 kHz
−40°C to +85°C
6-Lead Thin Small Outline Transistor Package [TSOT]
Evaluation Board
6-Lead Thin Small Outline Transistor Package [TSOT]
Evaluation Board
UJ-6
L87
1.4 MHz
−40°C to +85°C
UJ-6
L86
1 Z = RoHS Compliant Part.
Rev. 0 | Page 26 of 28
ADP2300/ADP2301
NOTES
Rev. 0 | Page 27 of 28
ADP2300/ADP2301
NOTES
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08342-0-2/10(0)
Rev. 0 | Page 28 of 28
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