SMD/QML-H [ADI]
IC DUAL 3-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68, GULLWING, CERAMIC, LCC-68, Analog to Digital Converter;
| 型号： | SMD/QML-H |
| 厂家： | 
ADI |
| 描述： | IC DUAL 3-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68, GULLWING, CERAMIC, LCC-68, Analog to Digital Converter 转换器 |
| 文件： | 总5页 (文件大小：51K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual Channel, 14-Bit, 10 MSPS A/D Converter
with Analog Input Signal Conditioning
a
PRELIMINARY TECHNICAL DATA
AD10410
For current information contact (336) 605-4385
amplifier. The AD9240s have on-chip track-and- hold cirucutry
and utilize an innovative multipass architecture to achieve 14-bit,
10MSPS performance. The AD10410 uses innovative high-
density circuit design and laser-trimmed thin-film resistor
networks to achieve exceptional matching and performance
while still maintaining excellent isolation, and providing for
significant board area savings.
PERFORMANCE FEATURES
Dual, 10 MSPS minimum sample rate
- Channel-channel matching, +/- .1% gain error
- Channel-channel isolation, >80dB
- DC-Coupled Signal conditioning included
Selectable Bipolar Input Voltage Range
(+/- 0.5V, +/- 1.0V, +/- 2.0V)
Gain flatness up to Nyquist: < 0.2dB
85dB Spurious-Free Dynamic Range
Straight binary output format
The AD10410 operates with +/- 5.0V for the Analog signal
conditioning with a separate +5.0V/3.3V supply for the digital
output phase. Each channel is completely independent allowing
operation with independent Encode and Analog Inputs. The
AD10410 also offers the user a choice of Analog Input Signal
ranges to further minimize additional external signal
3.3 / 5V CMOS-Compatible Output Levels
.75W Per Channel
conditioning, while still remaining general-purpose.
Industrial and Military Grade
The AD10410 is packaged in a 68-lead Ceramic Gull Wing
Package, footprint compatible with the earlier generation
AD10242 (12-bit, 40 MSPS) and AD10265 (12-bit, 65MSPS).
Manufacturing is done on Analog Devices, Inc. Mil-38534
Qualified Manufacturers Line (QML) and components are
available up to Class-H (-55 to 125C).
APPLICATIONS
Phased Array Receivers
Communications Receivers
FLIR Processing
Secure Communications
GPS Anti-Jamming Receivers
Multichannel, Multimode Receivers
PRODUCT HIGHLIGHTS
PRODUCT DESCRIPTION
1. Guaranteed sample rate of 10 MSPS.
2. Input amplitude options, user configurable.
3. Input signal conditioning included; both channels
matched for gain.
The AD10410 is a full channel ADC solution with on-module
signal conditioning for improved dynamic performance and
fully matched channel-to-channel performance. The module
includes two wide dynamic range AD9240 ADCs. Each
AD9240 has a dc-coupled amplifier front end including a low
distortion, high bandwidth amplifier, providing a high input
4. Fully tested/characterized performance for full channel.
5. Footprint compatible family; 68-pin LCC.
impedance and gain, and driving a single to differential
FUNCTIONAL BLOCK DIAGRAM
Rev. Pr A
This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most
recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission.
TARGET SPECIFICATIONS
AD10410
Electrical Characteristics (AVCC=5V; AVEE=-5V; DVCC=+3.3V applies to each ADC unless otherwise noted
Mil
AD10410BZ/QML-H
Parameter
Temp
Test
Level
Sub-
Group
Min
Typ
Max
Units
Bits
RESOLUTION
14
DC ACCURACY
No Missing Codes
Offset Error
Full
+25°C
Full
Full
+25°C
Full
VI
I
VI
V
I
1,2,3
1
2.3
Guaranteed
±2.2
%FS
%FS
%
%FS
%FS
%
±2.2
±0.1
±0.5
±0.8
Offset Error Channel Match
Gain Error1
1
2,3
VI
V
Gain Error Channel Match
Full
±0.1
ANALOG INPUT (AIN)
Input Voltage Range
AIN1
AIN2
AIN3
Full
Full
Full
I
I
I
1,2,3
1,2,3
1,2,3
±0.5
±1.0
±2
V
V
V
Input Resistance
AIN1
AIN2
AIN3
Full
Full
Full
+25°C
Full
IV
IV
IV
IV
V
12
12
12
12
99
198
396
0
100
200
400
4.0
30
101
202
404
7.0
W
W
W
pF
MHz
Input Capacitance2
Analog Input Bandwidth3
ENCODE INPUT4,5
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN) = (AVCC)
Low Level Input Current (VIN) = (0 V)
Input Capacitance
Full
Full
Full
Full
I
I
I
I
1,2,3
1,2,3
1,3,3
1,2,3
+3.5
+1.0
±10
±10
5
V
V
mA
mA
pF
SWITCHING PERFORMANCE
Maximum Conversion Rate6
Minimum Conversion Rate6
Aperture Delay (tA)
Aperture Delay Matching
Aperture Uncertainty (Jitter)
ENCODE Pulse With High
ENCODE Pulse With Low
Full
Full
VI
V
V
V
V
IV
IV
IV
4,5,6
12
10
MSPS
MSPS
MSPS
ns
ps rms
ns
+25°C
+25°C
+25°C
+25°C
+25°C
Full
TBD
TBD
0.3
12
12
12
ns
ns
Output Delay (tOD
)
TBD
SNR
Analog Input @ 1MHz
+25°C
V
II
4
73
73
dB
dB
Analog Input @ 5MHz
Full
5,6
SINAD8
Analog Input @ 1MHz
+25°C
V
II
4
70
70
dB
dB
Analog Input @ 5MHz
Full
5,6
Rev. Pr A
This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most
recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission.
TARGET SPECIFICATIONS
AD10410
Electrical Characteristics (AVCC=5V; AVEE=-5V; DVCC=+3.3V applies to each ADC unless otherwise noted)
Mil
Sub-
AD10410BZ/QML-H
Typ
Parameter
Temp
Test
Min
Max
Units
Level
Group
SPURIOUS-FREE DYNAMIC RANGE9
Analog Input @ 1MHz
+25°C
V
II
4
85
85
dBFS
dBFS
Analog Input @ 5MHz
Full
5,6
Two-tone IMD Rejection10
FI, F2@ -7 dBFS
Full
II
IV
V
4,5,6
12
-80
dBFS
dB
CHANNEL-TO-CHANNEL ISOLATION11
TRANSIENT RESPONSE
+25°C
+25°C
80dB
TBD
nS
LINEARITY
Differential Non-Linearity
(Encode = 20MHz)
Intergal Nonlinearity
(Encode = 20MHz)
+25°C
Full
+25°C
Full
IV
IV
V
12
12
TBD
TBD
TBD
TBD
LSB
LSB
LSB
LSB
V
OVERVOLTAGE RECOVERY TIME12
VIN = 2.0 x FS
VIN = 4.0 x FS
Full
Full
IV
IV
12
12
TBD
TBD
nS
nS
DIGITAL OUTPUTS
High Level Output Voltage (IOH) = 50mA)
Low Level Output Voltage (IOH) = 0.5mA)
High Level Output Voltage (IOL) = 1.6mA)
Low Level Output Voltage (IOL) = 50mA)
Output Capacitance
Full
Full
Full
Full
I
I
I
I
1,2,3
1,2,3
1,3,3
1,2,3
+4.5
+2.4
+0.4
+0.1
5
V
V
V
V
pF
POWER SUPPLY
AVCC Supply Voltage
I (AVCC) Current
Full
Full
Full
VI
V
VI
4.75
3.0
+5.0
TBD
-5.0
5.25
5.25
V
mA
V
AVEE Supply Voltage
I (AVEE) Current
DVCC Supply Voltage
I (DVCC) Current
Full
Full
Full
V
VI
V
TBD
3.3V
TBD
mA
V
mA
ICC (Total) Supply Current
Power Dissipation (Total)
Power Supply Rjection Ratio (PSRR)
Full
Full
Full
I
I
I
1,2,3
1,2,3
7,8
TBD
1.5
mA
W
0.02
0.2
%FSR/%Vs
Pass Band Ripple to 10MHz
IV
12
dB
Rev. Pr A
This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most
recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission.
TARGET SPECIFICATIONS
AD10410
Electrical Characteristics (AVCC=5V; AVEE=-5V; DVCC=+3.3V applies to each ADC unless otherwise noted)
NOTES
1.
2.
3.
Gain tests are performed on Ain2 input voltage range.
Input Capacitance spec. combines AD8037 die capacitance + Ceramic package capacitance.
Full Power Bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis is reduced by
3dB.
4.
5.
All AC specifications tested by driving single ended ENCODE .
ENCODE driven by single-ended source; ENCODE bypassed to ground through .1 mF capacitor.; see "Encoding the AD10410" for
details.
6.
7.
Minimum and Maximum conversion rates allow for variation in Encode Duty Cycle of 50% ±5%.
Analog Input signal power at -1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first 5 harmonics removed).
Encode = 19MSPS.
8.
9.
Analog Input signal power at -1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics.
Encode = 10MSPS.
Analog Input signal power swept from -1 dBFS to -60 dBFS; SFDR is ratio of converter fullscale to worst spur.
10. Both input tones at -7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst 3rd order intermod
product. f1=2.5MHz ± 100kHz, 50kHz £ f1-f2 £ 300kHz.
11. Channel to Channel Isolation tested with A channel grounded and a Fullscale signal applied to B channel.
12. Input driven to 2x and 4x Ain1 range for > 4 clock cycles. Output recovers inband in specified time with Encode = 10MSPS.
13. Outputs are sourcing TBD mA.
14. Outputs are sinking TBD mA.
All specifications guaranteed within 100mS of initial power up regardless of sequencing.
TEST LEVEL
I
100% Production Tested
II 100% Production Tested at +25°C, and sample tested at specified temperatures. AC testing done on sample basis
III Sample Tested only
IV Parameter is guaranteed by design and characterization testing
V
Parameter is a typical value only
VI 100% production tested at temperature at 25°C: sample tested at temperature extremes
Rev. Pr A
This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most
recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission.
AD10410
PIN FUNCTION DESCRIPTIONS
Function
Pin No.
Name
SHIELD
AGNDA
VREF_A
AINA1
1
Internal Ground Shield between channels
2,5,9-11
3
6
A Channel Analog Ground. A and B grounds should be connected as close to the device as possible
A Channel Internal Voltage Reference
Analog Input for A side ADC (nominally ± 0.5V)
7
AINA2
Analog Input for A side ADC (nominally ± 1.0V)
8
AINA3
Analog Input for A side ADC (nominally ± 2.0V)
4
12
13
RANGEA
CML-A
AVEE
Analog Negative Supply Voltage (nominally -5.0V)
Analog Positive Supply Voltage (nominally +5.0V)
A Channel Digital Ground
14
26,27
15-25, 31-33
28
AVCC
DGNDA
D0A-D13A
NC
Digital Outputs for ADC A. D0 (LSB)
29
30
43,44
34-42,45-49
53-54,58-61,65,68
50
ENCODEA
DVCC
DGNDB
D0B-D13B
AGNDB
DVCC
Data conversion initiated on rising edge of ENCODE input
Digital Positive Supply Voltage (nominally +5.0V / + 3.3V)
B Channel Digital Ground
Digital Outputs for ADC B. D0 (LSB)
B Channal Analog Ground. A and B grounds should be connected as close to the device as possible
Digital Positive Supply Voltage (nominally +5.0V / + 3.3V)
51
52
55
57
56
62
63
64
66
67
ENCODEB
NC
VREF-B
CML-B
RANGEB
AINB1
AINB2
AINB3
AVCC
AVEE
Data conversion initiated on rising edge of ENCODE input
B Channel Internal Voltage Reference
Analog Input for B side ADC (nominally ± 0.5V)
Analog Input for B side ADC (nominally ± 1.0V)
Analog Input for B side ADC (nominally ± 2.0V)
Analog PositiveSupply Voltage (nominally +5.0V )
Analog Negative Supply Voltage (nominally -5.0V)
PIN CONFIGURATION
68-Lead Leaded Ceramic Chip Carrier
68
67 6 6
6 5 6 4
6 3 6 2
61
9
8
7
6
5
4
3
2
1
A G N D B
A G ND B
60
59
10
1 1
A G N D A
A G N D A
PIN
1
58
57
1 2
A G N D B
C M L-B
C M L -A
A V
EE
1 3
14
1 5
A V
C C
56 R A NG E B
V R EF _B
5 5
54
53
5 2
D0A (LS B A )
D1 A
A G ND B
A G ND B
N C
1 6
17
A D 1 04 1 0
D2A
D3 A 1 8
Top V ie w
(Not to Scale)
51
50
49
E N C O D E B
D4 A
D5 A
19
20
D V
C C
D1 3B (M S B B )
21
2 2
23
D6A
D7 A
D8 A
48 D1 2B
D1 1 B
47
46
45
44
D1 0 B
D9 B
2 4
25
26
D9 A
D1 0A
D G N D A
D G N D B
29
30 31 32
33
2 7
28
3 4
35
3 6
3 7 38
39 40
41 42
4 3
PLANNED GRADES
Model
Temperature Range
Package Description
AD10410BZ
SMD/QML-H
AD10410/PCB
-40°C to 85°C (Case)
-55°C to 125°C (Case)
68-pin Leaded Ceramic Chip Carrier
68-pin Leaded Ceramic Chip Carrier
Evaluation Board with AD10410BZ
Rev. Pr A
This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most
recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission.
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