SMP18FS [ADI]
Octal Sample-and-Hold with Multiplexed Input; 八通道采样和保持与多路复用输入
| 型号： | SMP18FS |
| 厂家： | 
ADI |
| 描述： | Octal Sample-and-Hold with Multiplexed Input |
| 文件： | 总8页 (文件大小：271K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Octal Sample-and-Hold
with Multiplexed Input
a
SMP18
FEATURES
FUNCTIONAL BLOCK DIAGRAM
High Speed Version of SMP08
Internal Hold Capacitors
Low Droop Rate
TTL/CMOS Compatible Logic Inputs
Single or Dual Supply Operation
Break-Before-Make Channel Addressing
Compatible With CD4051 Pinout
Low Cost
(LSB)
A
(MSB)
C
INPUT
3
B
INH
6
11
10
9
8
DGND
1 OF 8 DECODER
16
13
V
DD
SW
CH OUT
0
APPLICATIONS
14
SW
CH OUT
1
Multiple Path Timing Deskew for A.T.E.
Memory Programmers
SW
15 CH OUT
2
Mass Flow/Process Control Systems
Multichannel Data Acquisition Systems
Robotics and Control Systems
Medical and Analytical Instrumentation
Event Analysis
SW
12 CH OUT
3
CH OUT
4
SW
1
5
2
4
Stage Lighting Control
CH OUT
5
SW
GENERAL DESCRIPTION
CH OUT
6
SW
The SMP18 is a monolithic octal sample-and-hold; it has eight
internal buffer amplifiers, input multiplexer, and internal hold
capacitors. It is manufactured in an advanced oxide isolated
CMOS technology to obtain high accuracy, low droop rate, and
fast acquisition time. The SMP18 has a typical linearity error of
only 0.01% and can accurately acquire a 10-bit input signal to
±1/2 LSB in less than 2.5 microseconds. The SMP18’s output
swing includes the negative supply in both single and dual sup-
ply operation.
SW
CH OUT
7
HOLD CAPS
(INTERNAL)
V
7
SS
SMP18
The SMP18 was specifically designed for systems that use a
calibration cycle to adjust a multiple of system parameters. The
low cost and high level of integration make the SMP18 ideal for
calibration requirements that have previously required an ASIC,
or high cost multiple D/A converters.
The SMP18 offers significant cost and size reduction over
discrete designs. It is available in a 16-pin plastic DIP, a
narrow body SO-16 surface-mount SOIC package or the thin
TSSOP-16 package. The SMP18 is a higher speed direct
replacement for the SMP08.
The SMP18 is also ideally suited for a wide variety of sample-
and-hold applications including amplifier offset or VCA gain ad-
justments. One or more SMP18s can be used with single or
multiple DACs to provide multiple set points within a system.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1996
SMP18–SPECIFICATIONS
(@ VDD = +5 V, VSS = –5 V, DGND = 0 V, RL = No Load, TA = –40؇C to +85؇C for SMP18F,
unless otherwise noted)
ELECTRICAL CHARACTERISTICS
P
arameter
Symbol
Conditions
Min
Typ
Max
Units
Linearity Error
Buffer Offset Voltage
–3 V ≤ VIN ≤ +3 V
TA = +25°C, VIN = 0 V
–40°C ≤ TA ≤ +85°C, VIN = 0 V
VIN = 0 V, TA = +25°C to +85°C
0.01
2.5
3.5
4
%
VOS
VHS
10
20
6
8
40
mV
mV
mV
mV
mV/s
mA
mA
V
Hold Step
V
IN = 0 V, TA = –40°C
Droop Rate
∆VCH/∆t
ISOURCE
ISINK
TA = +25°C, VIN = 0 V
2
Output Source Current
Output Sink Current
Output Voltage Range
VIN = 0 V1
1.2
0.5
–3.0
VIN = 0 V1
RL = 20 kΩ
+3.0
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
VINH
VINL
IIN
2.4
V
V
µA
0.8
1
VIN = 2.4 V
0.5
DYNAMIC PERFORMANCE2
Acquisition Time3
tAQ
tH
tCH
tDCS
tIR
TA = +25°C, –3 V to +3 V to 0.1%
To ±1 mV of Final Value
3.5
1
90
45
90
6
µs
µs
ns
ns
Hold Mode Settling Time
Channel Select Time
Channel Deselect Time
Inhibit Recovery Time
Slew Rate
Capacitive Load Stability
Analog Crosstalk
ns
SR
V/µs
pF
dB
<30% Overshoot
–3 V to +3 V Step
500
–72
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio
Supply Current
PSRR
IDD
V
SS = ±5 V to ±6 V
60
75
5.5
dB
mA
TA = +25°C
7.5
–40°C ≤ TA ≤ +85°C
7.5
9.5
mA
(@ VDD = +12 V, VSS = 0 V, DGND = 0 V, RL = No Load, TA = –40؇C to +85؇C for SMP18F,
unless otherwise noted)
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ
Max
Limits
Linearity Error
Buffer Offset Voltage
60 mV ≤ VIN ≤ 10 V
TA = +25°C, VIN = 6 V
–40°C ≤ TA ≤ +85°C, VIN = 6 V
VIN = 6 V, TA = +25°C to +85°C
0.01
2.5
3.5
4
%
VOS
VHS
10
20
6
8
40
mV
mV
mV
mV
mV/s
mA
mA
V
Hold Step
V
IN = 6 V, TA = –40°C
Droop Rate
∆VCH/∆t
ISOURCE
ISINK
TA = +25°C, VIN = 6 V
2
Output Source Current
Output Sink Current
Output Voltage Range
VIN = 6 V1
1.2
0.5
0.06
0.06
VIN = 6 V1
R
L = 20 kΩ
10.0
9.5
RL = 10 kΩ
V
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
VINH
VINL
IIN
2.4
V
V
µA
0.8
1
VIN = 2.4 V
0.5
DYNAMIC PERFORMANCE2
Acquisition Time3
tAQ
tH
tCH
tDCS
tIR
TA = +25°C, 0 to 10 V to 0.1%
To ±1 mV of Final Value
2.5
1
90
45
90
7
3.25
µs
µs
ns
ns
Hold Mode Settling Time
Channel Select Time
Channel Deselect Time
Inhibit Recovery Time
Slew Rate4
ns
SR
V/µs
pF
dB
Capacitive Load Stability
Analog Crosstalk
<30% Overshoot
0 V to 10 V Step
500
–72
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio
Supply Current
PSRR
IDD
10.8 V ≤ VDD ≤ 13.2 V
TA = +25°C
60
75
6.0
dB
mA
8.0
–40°C ≤ TA ≤ +85°C
8.0
10.0
mA
NOTES
1Outputs are capable of sinking and sourcing over 10 mA but offset is guaranteed at specified load levels.
2All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
3This parameter is guaranteed without test.
4Slew rate is measured in the sample mode with a 0 to 10 V step from 20% to 80%.
Specifications subject to change without notice.
–2–
REV. C
SMP18
ABSOLUTE MAXIMUM RATINGS
PIN CONNECTIONS
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, 17 V
V
V
DD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, 17 V
LOGIC to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD
CH OUT
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
4
DD
CH OUT
6
CH OUT
2
VIN to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD
VOUT to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD
Analog Output Current . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
(Not short-circuit protected)
INPUT
CH OUT
1
SMP18
CH OUT
7
CH OUT
0
TOP VIEW
(Not to Scale)
CH OUT
5
CH OUT
3
Operating Temperature Range
INH
A CONTROL
FP, FS . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300°C
V
10 B CONTROL
SS
DGND
9
C CONTROL
Package Type
JA*
Units
JC
16-Pin Plastic DIP (P)
16-Pin SOIC (S)
16-Lead TSSOP (RU)
76
92
180
33
27
35
°C/W
°C/W
°C/W
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Model
NOTES
*θJA is specified for worst case mounting conditions, i.e., θJA is specified for device
in socket for plastic DIP packages; θJA is specified for device soldered to printed
circuit board for SOIC and TSSOP packages.
SMP18FP
SMP18FRU
SMP18FS
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Plastic DIP
TSSOP-16
SO-16
N-16
RU-16
R-16A
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the SMP18 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. C
–3–
SMP18–Typical Performance Characteristics
100
5
130
110
V
V
= +12V
= 0V
V
V
V
= +12V
= 0V
DD
DD
SS
IN
SS
3
T
= +85°C
= +6V
A
10
NO LOAD
R
= 10kΩ
L
90
70
50
30
10
1
0
0.1
–1
–3
–5
V
V
= +12V
= 0V
DD
SS
T
= +25°C
A
NO LOAD
0.01
–40 –20
0
20
40
60
80
100
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
TEMPERATURE –
°C
INPUT VOLTAGE – Volts
INPUT VOLTAGE – Volts
Droop Rate vs. Temperature
Droop Rate vs. Input Voltage
Droop Rate vs. Input Voltage
1
0
30
V
V
= +12V
= 0V
V
V
= +12V
= 0V
DD
V
V
V
= +12V
= 0V
DD
DD
SS
IN
0
–1
–2
–3
–4
–5
–6
–7
SS
SS
–1
–2
–3
–4
–5
–6
25
20
15
10
5
T
= +25°C
= 6V
T
= +25°C
A
A
NO LOAD
NO LOAD
NO LOAD
+SR
–SR
0
10
–55 –35 –15
5
25 45 65 85 105 125
0
1
2
3
4
5
6
7
8
9
10
11
12
13
V
14
– Volts
15
16
17 18
INPUT VOLTAGE – Volts
TEMPERATURE – °C
DD
Hold Step vs. Input Voltage
Hold Step vs. Temperature
Slew Rate vs. VDD
4
20
4
2
V
V
= +12V
= 0V
V
V
= +12V
V
V
= +12V
DD
DD
DD
= 0V
15
10
= 0V
SS
SS
SS
2
0
T
= +85°C
T
= +25°C
T = –40°C
A
A
A
R
=
∞
L
0
–2
R
=
∞
L
5
R
= 20kΩ
L
–2
–4
–6
–8
–10
R
=
∞
L
R
= 20kΩ
0
L
–4
R
= 10kΩ
R
= 20kΩ
L
L
–5
R
= 10kΩ
L
–6
R
= 10kΩ
–10
–15
–20
L
–8
–10
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
INPUT VOLTAGE – Volts
INPUT VOLTAGE – Volts
INPUT VOLTAGE – Volts
Offset Voltage vs. Input Voltage
Offset Voltage vs. Input Voltage
Offset Voltage vs. Input Voltage
–4–
REV. C
Typical Performance Characteristics–SMP18
0
–1
–2
–3
–4
–5
–6
–7
–8
14
12
90
V
= 0V
V
V
V
= +12V
= 0V
SS
NO LOAD
V
V
V
= +12V
= 0V
DD
SS
IN
DD
SS
IN
80
70
60
50
40
30
20
10
0
+PSRR
= +6V
= +5V
T
= +25°C
R
= 10kΩ
A
L
10
8
+85°C
NO LOAD
–PSRR
+25°C
6
4
–40°C
2
4
6
8
10
DD
12
14
16
18
–55 –35 –15
5
25 45 65 85 105 125
10
100
1k
10k
100k
1M
V
– Volts
TEMPERATURE –
°C
FREQUENCY – Hz
Offset Voltage vs. Temperature
Supply Current vs. VDD
Sample Mode Power Supply Rejection
90
45
2
1
35
30
V
V
= +6V
= –6V
DD
V
V
= +12V
DD
SS
= 0V
SS
T
= +25°C
A
T
= +25°C
A
NO LOAD
0
0
–1
–2
–3
–4
–5
NO LOAD
25
–45
20
15
10
5
PHASE
–90
–135
–180
GAIN
–225
10M
0
10
100
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY – Hz
FREQUENCY – Hz
Gain, Phase Shift vs. Frequency
Output Impedance vs. Frequency
15
60
50
V
V
= +6V
= –6V
DD
SS
T
= +25°C
12
9
A
+PSRR
40
NO LOAD
V
V
= +12V
= 0V
DD
30
20
SS
T
= +25°C
A
6
NO LOAD
HOLD CAPACITORS
REFERENCED TO V
10
SS
3
0
–PSRR
0
10k
–10
10
100k
1M
10M
100
1k
10k
100k
1M
FREQUENCY – Hz
FREQUENCY – Hz
Maximum Output Voltage vs.
Frequency
Hold Mode Power Supply Rejection
REV. C
–5–
SMP18
V
CC
+15V
R4
1kΩ
R3
2kΩ
D1
C1
10µF
+
C2
1µF
R1
10Ω
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SMP18
R2
R2
R2
R2
R2
R2
R2
R2
10kΩ 10kΩ 10kΩ 10kΩ
10kΩ 10kΩ 10kΩ 10kΩ
Burn-in Circuit
POWER SUPPLY SEQUENCING
APPLICATIONS INFORMATION
VDD should be applied to the SMP18 before the logic input sig-
nals. The SMP18 has been designed to be immune to latchup,
but standard precautions should still be taken.
The SMP18, a multiplexed octal S/H, minimizes board space
in systems requiring cycled calibration or an array of control
voltages. When used in conjunction with a low cost 16-bit D/A,
the SMP18 can easily be integrated into microprocessor based
systems. Since the SMP18 features break-before-make switching
and an internal decoder, no external logic is required. The
SMP18 has an internally regulated TTL supply so that
TTL/CMOS compatibility is maintained over the full supply
range. See Figure 1 for channel decode address information.
OUTPUT BUFFERS (Pins 1, 2, 4, 5, 12, 13, 14, 15)
The buffer offset specification is 10 mV; this is less than 1/2
LSB of an 8-bit DAC with 10 V full scale. The hold step (mag-
nitude of step caused in the output voltage when switching from
sample-to-hold mode, also referred to as the pedestal error or
sample-to-hold offset) is about 4 mV with little variation over
the full output voltage range. The droop rate of a held channel
is 2 mV/s typical and 40 mV/s maximum.
POWER SUPPLIES
The SMP18 is capable of operating with either single or dual
supplies over a voltage range of 7 to 15 volts. Based on the sup-
ply voltages chosen, VDD and VSS establish the output voltage
range, which is:
The buffers are designed to drive loads connected to ground.
The outputs can source more than 20 mA over the full voltage
range but have limited current sinking capability near VSS. In
split supply operation, symmetrical output swings can be ob-
tained by restricting the output range to 2 V from either supply.
(VSS + 0.06 V) ≤ VOUT ≤ (VDD – 2 V)
Note that several specifications, including acquisition time, off-
set and output voltage compliance, will degrade for supply volt-
ages of less than 7 V.
On-chip SMP18 buffers eliminate potential stability problems
associated with external buffers; outputs are stable with capaci-
tive loads up to 500 pF. However, since the SMP18’s buffer
outputs are not short circuit protected, care should be taken to
avoid shorting any output to the supplies or ground.
If split supplies are used, the negative supply should be bypassed
with a 0.1 µF capacitor in parallel with a 10 µF to ground. The
internal hold capacitors are connected to this supply pin, and
any noise will appear at the outputs.
SIGNAL INPUT (Pin 3)
In single supply applications, it is extremely important that the
The signal input should be driven from a low impedance voltage
source such as the output of an op amp. The op amp should
have a high slew rate and fast settling time if the SMP18’s ac-
quisition time characteristics are to be maintained. As with all
CMOS devices, all input voltages should be kept within range of
the supply rails (VSS ≤ VIN ≤ VDD) to avoid the possibility of
latchup. If single supply operation is desired, op amps such as
the OP183 or AD820 that have input and output voltage com-
pliances including ground, can be used to drive the inputs. Split
supplies, such as ±7.5 V, can be used with the SMP18.
V
SS (negative supply) pin is connected to a clean ground. The
hold capacitors are internally tied to the VSS (negative) rail. Any
ground noise or disturbance will directly couple to the output of
the sample-and-hold degrading the signal-to-noise performance.
The analog and digital ground traces on the circuit board should
be physically separated to reduce digital switching noise from
entering the analog circuitry.
–6–
REV. C
SMP18
APPLICATION TIPS
TYPICAL APPLICATIONS
All unused digital inputs should be connected to logic LOW.
For analog inputs that may become temporarily disconnected, a
resistor to VDD, VSS or analog ground should be used with a
value ranging from 200 kΩ to 1 MΩ.
An 8-Channel Multiplexed D/A Converter
Figure 1 illustrates a typical demultiplexing function of the
SMP18. It is used to sample-and-hold eight different output
voltages corresponding to eight different digital codes from a
D/A converter. The SMP18’s droop rate of 40 mV/s requires a
refresh once every 250 ms before the voltage drifts beyond
1/2 LSB accuracy (1 LSB of an 8-bit DAC is equivalent to
19.5 mV out of a full-scale voltage of 5 V). For a 10-bit DAC
the refresh rate must be less than 60 ms, and for a 12-bit
system, 15 ms. This implementation is very cost effective com-
pared to using multiple DACs as the number of output channels
increases.
Do not apply signals to the SMP18 with power off unless the in-
put current is limited to less than 10 mA.
+12V
SMP18
13
CH
CH
CH
0
1
2
3
4
5
6
7
REF02
+12V
+5V
V
SS
4
17
14
15
DIGITAL
INPUTS
V
A
V
DD
REF
V
OA
DAC8228
3
3
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
V
Z
1
CS
WR
GND
15
16
5
WR
CHANNEL DECODING
12 CH
ADDRESS
BUS
A
B
C
PIN 9 PIN 10 PIN 11 PIN 6
11
10
9
C
B
A
INH
CH
PIN
ADDRESS
DECODE
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
X
0
0
0
0
0
0
0
0
1
0
13
14
15
12
1
1
5
2
4
CH
CH
CH
CH
1
2
3
4
5
5
DGND
INH
6
7
2
8
6
4
NONE
–
16
7
+12V
0.1µF
Figure 1. 8-Channel Multiplexed D/A Converter
REV. C
–7–
SMP18
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Pin Plastic DIP
(N-16)
0.840 (21.33)
0.745 (18.93)
16
1
9
0.280 (7.11)
0.240 (6.10)
8
0.325 (8.25)
0.300 (7.62)
0.195 (4.95)
0.115 (2.93)
0.060 (1.52)
0.015 (0.38)
PIN 1
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
SEATING
PLANE
16-Pin (Narrow Body)
(SO-16)
0.3937 (10.00)
0.3859 (9.80)
16
9
0.1574 (4.00)
0.2550 (6.20)
1
8
0.1497 (5.80)
0.2284 (5.80)
0.0688 (1.75)
0.0196 (0.50)
PIN 1
x 45°
0.0098 (0.25)
0.0040 (0.10)
0.0532 (1.35)
0.0099 (0.25)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0500 (1.27)
0.0160 (0.41)
0.0099 (0.25)
0.0075 (0.19)
16-Lead TSSOP
(RU-16)
0.201 (5.10)
0.193 (4.90)
16
9
1
8
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0433
(1.10)
MAX
0.028 (0.70)
0.020 (0.50)
8°
0°
0.0118 (0.30)
0.0075 (0.19)
0.0256
(0.65)
BSC
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
–8–
REV. C
相关型号：
©2020 ICPDF网 联系我们和版权申明