SMPZ08FPZ [ADI]
IC 8 CHANNEL, SAMPLE AND HOLD AMPLIFIER, 3.6 us ACQUISITION TIME, PDIP16, PLASTIC, DIP-16, Sample and Hold Circuit;
| 型号： | SMPZ08FPZ |
| 厂家： | 
ADI |
| 描述： | IC 8 CHANNEL, SAMPLE AND HOLD AMPLIFIER, 3.6 us ACQUISITION TIME, PDIP16, PLASTIC, DIP-16, Sample and Hold Circuit 放大器 光电二极管 |
| 文件： | 总8页 (文件大小：475K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SMP08–SPECIFICATIONS
(@ VDD = +5 V, VSS = –5 V, DGND = 0 V, RL = No Load, TA = –40؇C to +85؇C for SMP08F,
ELECTRICAL CHARACTERISTICS unless otherwise noted)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Linearity Error
Buffer Offset Voltage
–3 V ≤ VIN ≤ +3 V
TA = +25°C, VIN = 0 V
–40°C ≤ TA ≤ +85°C, VIN = 0 V
VIN = 0 V, TA = +25°C to +85°C
0.01
2.5
3.5
2.5
%
VOS
VHS
10
20
4
5
20
mV
mV
mV
mV
mV/s
mA
mA
V
Hold Step
V
IN = 0 V, TA = –40°C
Droop Rate
∆VCH/∆t
ISOURCE
ISINK
TA = +25°C, VIN = 0 V
2
Output Source Current
Output Sink Current
Output Voltage Range
VIN = 0 V1
1.2
0.5
–3.0
VIN = 0 V1
RL = 20 kΩ
+3.0
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
VINH
VINL
IIN
2.4
V
V
µA
0.8
1
VIN = 2.4 V
0.5
DYNAMIC PERFORMANCE2
Acquisition Time3
tAQ
tH
tCH
tDCS
tIR
TA = +25°C, –3 V to +3 V to 0.1%
To ±1 mV of Final Value
3.6
1
90
45
90
3
7
µs
µs
ns
ns
Hold Mode Settling Time
Channel Select Time
Channel Deselect Time
Inhibit Recovery Time
Slew Rate
Capacitive Load Stability
Analog Crosstalk
ns
SR
V/µs
pF
dB
<30% Overshoot
–3 V to +3 V Step
500
–72
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio
Supply Current
PSRR
IDD
VS = ±5 V to ±6 V
TA = +25°C
–40°C ≤ TA ≤ +85°C
60
75
4
5
dB
mA
mA
7.5
9.5
(@ VDD = +12 V, VSS = 0 V, DGND = 0 V, RL = No Load, TA = –40؇C to +85؇C for SMP08F,
unless otherwise noted)
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Linearity Error
Buffer Offset Voltage
60 mV ≤ VIN ≤ 10 V
TA = +25°C, VIN = 6 V
–40°C ≤ TA ≤ +85°C, VIN = 6 V
VIN = 6 V, TA = +25°C to +85°C
0.01
2.5
3.5
2.5
%
VOS
VHS
10
20
4
5
20
mV
mV
mV
mV
mV/s
mA
mA
V
Hold Step
V
IN = 6 V, TA = –40°C
Droop Rate
∆VCH/∆t
ISOURCE
ISINK
TA = +25°C, VIN = 6 V
2
Output Source Current
Output Sink Current
Output Voltage Range
VIN = 6 V1
1.2
0.5
0.06
0.06
VIN = 6 V1
RL = 20 kΩ
RL = 10 kΩ
10.0
9.5
V
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
VINH
VINL
IIN
2.4
V
V
µA
0.8
1
VIN = 2.4 V
0.5
DYNAMIC PERFORMANCE2
Acquisition Time3
tAQ
TA = +25°C, 0 V to 10 V to 0.1%
–40°C ≤ TA ≤ +85°C
To ±1 mV of Final Value
3.5
3.75
1
90
45
90
4
500
–72
4.25
6.00
µs
µs
µs
ns
ns
ns
V/µs
pF
dB
Hold Mode Settling Time
Channel Select Time
Channel Deselect Time
Inhibit Recovery Time
Slew Rate
Capacitive Load Stability
Analog Crosstalk
tH
tCH
tDCS
tIR
SR
RL = 20 kΩ4
<30% Overshoot
0 V to 10 V Step
3
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio
Supply Current
PSRR
IDD
10.8 V ≤ VDD ≤ 13.2 V
TA = +25°C
60
75
6.0
dB
mA
8.0
–40°C ≤ TA ≤ +85°C
8.0
10.0
mA
NOTES
1Outputs are capable of sinking and sourcing over 20 mA but offset is guaranteed at specified load levels.
2All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
3This parameter is guaranteed without test.
4Slew rate is measured in the sample mode with 0 V to 10 V step from 20% to 80%.
Specifications subject to change without notice.
–2–
REV. D
SMP08
ABSOLUTE MAXIMUM RATINGS
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, 17 V
ORDERING GUIDE
Temperature Package
Package
Option
V
V
DD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, 17 V
LOGIC to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD
Model
Range
Description
VIN to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD
VOUT to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD
Analog Output Current . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
(Not Short-Circuit Protected)
SMP08FP
SMP08FS
–40°C to +85°C
–40°C to +85°C
Plastic DIP
SO-16
N-16
R-16A
PIN CONNECTIONS
Operating Temperature Range
FP, FS . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300°C
CH OUT
4
V
16
1
2
3
4
5
6
7
8
DD
CH OUT
6
CH OUT
15
14
13
12
11
2
INPUT
CH OUT
1
SMP08
CH OUT
7
CH OUT
0
Package Type
JA*
JC
Units
TOP VIEW
(Not to Scale)
CH OUT
5
CH OUT
3
16-Pin Plastic DIP (P)
16-Pin SOIC (S)
76
92
33
27
°C/W
°C/W
INH
A CONTROL
V
10 B CONTROL
SS
DGND
9
C CONTROL
*θJA is specified for worst case mounting conditions, i.e., θJA is specified for device
in socket for plastic DIP package; θJA is specified for device soldered to printed
circuit board for SO package.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the SMP08 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. D
–3–
SMP08–Typical Performance Characteristics
1800
1600
1000
3
V
V
= +12V
= 0V
DD
V
V
V
= +12V
= 0V
DD
SS
IN
SS
2
T
= +125°C
= +5V
A
100
R
= 10kΩ
NO LOAD
L
1400
1200
1000
800
1
10
1
0
–1
–2
–3
V
V
T
= +12V
= 0V
DD
SS
= +25°C
A
NO LOAD
600
0.1
–55 –35 –15
5
25 45 65 85 105 125
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
INPUT VOLTAGE – Volts
TEMPERATURE –
°C
INPUT VOLTAGE – Volts
Figure 3. Droop Rate vs. InputVoltage
Figure 1. Droop Rate vs. Temperature
Figure 2. Droop Rate vs. Input Voltage
7
2
2
V
T
= 0V
V
V
= +12V
= 0V
V
V
V
= +12V
= 0V
SS
= +25
DD
DD
SS
IN
°
C
A
SS
1
0
1
0
NO LOAD
= +5V
T
= +25°C
A
6
5
4
3
NO LOAD
NO LOAD
–SR
–1
–2
–3
–4
–1
–2
–3
–4
+SR
10
11
12
13
V
14
– Volts
15
16
17 18
–55 –35 –15
5
25
45
65
85
0
1
2
3
4
5
6
7
8
9
10
INPUT VOLTAGE – Volts
TEMPERATURE – °C
DD
Figure 4. Hold Step vs. Input Voltage
Figure 5. Hold Step vs. Temperature
Figure 6. Slew Rate vs. VDD
4
20
4
V
V
= +12V
= 0V
V
V
= +12V
V
V
= +12V
= 0V
DD
DD
DD
= 0V
15
10
SS
SS
SS
2
0
2
0
T
= +85°C
T
= –40°C
T
= +25°C
A
A
A
NO LOAD
R
=
NO LOAD
NO LOAD
∞
L
R
=
∞
L
5
R
= 20kΩ
L
–2
–4
–6
–8
–10
–2
–4
–6
–8
–10
R
=
∞
L
0
R
= 10kΩ
L
R
= 20kΩ
L
–5
R
= 10kΩ
L
R
= 10kΩ
–10
–15
–20
L
R
= 20kΩ
L
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
INPUT VOLTAGE – Volts
INPUT VOLTAGE – Volts
INPUT VOLTAGE – Volts
Figure 7. Offset Voltage vs. Input
Voltage
Figure 8. Offset Voltage vs. Input
Voltage
Figure 9. Offset Voltage vs. Input
Voltage
–4–
REV. D
Typical Performance Characteristics–SMP08
0
–1
–2
–3
–4
–5
–6
–7
–8
90
14
12
V
V
V
= +12V
= 0V
V
= 0V
V
V
V
= +12V
= 0V
DD
SS
IN
SS
NO LOAD
DD
SS
IN
80
70
60
50
40
30
20
10
0
+PSRR
= +6V
= +5V
T
= +25°C
R
= 10kΩ
A
L
10
8
NO LOAD
–PSRR
+85°C
+25°C
6
4
–40°C
2
–55 –35 –15
5
25 45 65 85 105 125
10
100
1k
10k
100k
1M
4
6
8
10
DD
12
14
16
18
FREQUENCY – Hz
TEMPERATURE –
°C
V
– Volts
Figure 12. Sample Mode Power
Supply Rejection
Figure 10. Offset Voltage vs.
Temperature
Figure 11. Supply Current vs. VDD
90
2
1
35
V
V
= +12V
DD
V
V
= +12V
DD
= 0V
SS
= 0V
45
0
SS
30
25
20
15
10
5
T
= +25°C
A
T
= +25°C
A
NO LOAD
NO LOAD
0
–1
–2
–3
–45
PHASE
–90
–135
GAIN
100k
–180
–225
–4
–5
0
10
100
1k
10k
1M
10M
100
1k
10k
100k
1M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 13. Gain, Phase Shift vs.
Frequency
Figure 14. Output Impedance vs.
Frequency
15
60
50
V
V
= +6V
= –6V
DD
SS
T
= +25°C
12
9
A
+PSRR
40
NO LOAD
V
V
= +12V
= 0V
DD
30
20
SS
T
= +25°C
A
NO LOAD
6
HOLD CAPACITORS
REFERENCED TO V
10
SS
3
0
–PSRR
0
10k
–10
10
100k
1M
10M
100
1k
10k
100k
1M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 15. Maximum Output Voltage
vs. Frequency
Figure 16. Hold Mode Power Supply
Rejection
–5–
REV. D
SMP08
V
CC
+15V
R3
R4
D1
6.5kΩ
1kΩ
C1
10µF
+
C2
1µF
R1
10Ω
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SMP08
R2
10kΩ
R2
10kΩ
R2
10kΩ
R2
10kΩ
R2
10kΩ
R2
10kΩ
R2
10kΩ
R2
10kΩ
Figure 17. Burn-In Circuit
OUTPUT BUFFERS (Pins 1, 2, 4, 5, 12, 13, 14, 15)
The buffer offset specification is 10 mV; this is less than 1/2 LSB
of an 8-bit DAC with 10 V full scale. The hold step (magni-
tude of step caused in the output voltage when switching from
sample-to-hold mode, also referred to as the pedestal error or
sample-to-hold offset), is about 2.5 mV with little variation
over the full output voltage range, TA = +25°C to +85°C. The
droop rate of a held channel is 2 mV/s typical and 20 mV/s
maximum.
APPLICATIONS INFORMATION
The SMP08, a multiplexed octal S/H, minimizes board space in
systems requiring cycled calibration or an array of control volt-
ages. When used in conjunction with a low cost 16-bit D/A, the
SMP08 can easily be integrated into microprocessor based sys-
tems. Since the SMP08 features break-before-make switching
and an internal decoder, no external logic is required. The
SMP08 has an internally regulated TTL supply so that TTL/
CMOS compatibility is maintained over the full supply range.
See Figure 18 for channel decode address information.
The buffers are designed to drive loads connected to ground.
The outputs can source more than 20 mA, over the full voltage
range, but have limited current sinking capability near VSS. In
split supply operation, symmetrical output swings can be ob-
tained by restricting the output range to 2 V from either supply.
POWER SUPPLIES
The SMP08 is capable of operating with either single or dual
supplies, over a voltage range of 7 volts to 15 volts. Based on the
supply voltages chosen, VDD and VSS establish the input and
output voltage range, which is:
On-chip SMP08 buffers eliminate potential stability problems
associated with external buffers; outputs are stable with ca-
pacitive loads up to 500 pF. However, since the SMP08’s
buffer outputs are not short-circuit protected, care should be
taken to avoid shorting any output to the supplies or ground.
(VSS +0.06 V) ≤ VOUT/IN ≤ (VDD –2 V)
Note that several specifications, including acquisition time, off-
set and output voltage compliance, will degrade for supply volt-
ages of less than 7 V.
SIGNAL INPUT (Pin 3)
If split supplies are used, the negative supply should be bypassed
with a 0.1 µF capacitor in parallel with a 10 µF to ground. The
internal hold capacitors are connected to this supply pin and any
noise will appear at the outputs.
The signal input should be driven from a low impedance volt-
age source such as the output of an op amp. The op amp
should have a high slew rate and fast settling time if the
SMP08’s acquisition time characteristics are to be maintained.
As with all CMOS devices, all input voltages should be kept
within range of the supply rails (VSS < VIN < VDD) to avoid the
possibility of latchup. If single supply operation is desired, op
amps such as the OP183 or AD820 that have input and output
voltage compliances including ground, can be used to drive the
inputs. Split supplies, such as ±7.5 V, can be used with the
SMP08.
In single supply applications, it is extremely important that the
V
SS (negative supply) pin is connected to a clean ground. The
hold capacitors are internally tied to the VSS (negative) rail. Any
ground noise or disturbance will directly couple to the output of
the sample-and-hold, degrading the signal-to-noise perfor-
mance. The analog and digital ground traces on the circuit
board should be physically separated to reduce digital switching
noise from entering the analog circuitry.
APPLICATION TIPS
POWER SUPPLY SEQUENCING
All unused digital inputs should be connected to logic LOW
and unused analog inputs connected to analog ground. For
connector-driven analog inputs that may become temporarily
disconnected, a resistor to VDD, VSS or analog ground should
be used with a value ranging from 200 kΩ to 1 MΩ.
VDD should be applied to the SMP08 before the logic input sig-
nals. The SMP08 has been designed to be immune to latchup,
but standard precautions should still be taken.
REV. D
–6–
SMP08
+12V
SMP08
13
14
15
CH
CH
CH
0
1
2
3
4
5
6
7
REF02
+12V
17
+5V
4
V
SS
DIGITAL
INPUTS
V
A
V
REF
DD
V
OA
DAC8228
3
3
V
SS
V
Z
1
CS
WR
GND
15
16
5
V
SS
WR
CHANNEL DECODING
12 CH
ADDRESS
BUS
A
B
C
PIN 9 PIN 10 PIN 11 PIN 6
11
10
9
C
B
A
INH
CH
PIN
ADDRESS
DECODE
V
SS
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
X
0
0
0
0
0
0
0
0
1
0
13
14
15
12
1
1
5
2
4
CH
CH
CH
CH
1
2
3
V
SS
4
5
5
DGND
INH
6
7
2
8
6
4
V
SS
NONE
–
V
SS
V
SS
16
7
+12V
0.1µF
Figure 18. 8-Channel Multiplexed D/A Converter
Do not apply signals to the SMP08 with power off unless the
input current is limited to less than 10 mA.
1/2 LSB accuracy (1 LSB of an 8-bit DAC is equivalent to
19.5 mV out of a full-scale voltage of 5 V). For a 10-bit DAC
the refresh rate must be less than 120 ms, and, for a 12-bit
system, 31 ms. This implementation is very cost effective com-
pared to using multiple DACs as the number of output channels
increases.
TYPICAL APPLICATIONS
AN 8-CHANNEL MULTIPLEXED D/A CONVERTER
Figure 18 illustrates a typical demultiplexing function of the
SMP08. It is used to sample-and-hold eight different output
voltages corresponding to eight different digital codes from a
D/A converter. The SMP08’s droop rate of 20 mV/s requires a
refresh once every 500 ms, before the voltage drifts beyond
REV. D
–7–
SMP08
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Plastic DIP
(N-16)
0.840 (21.33)
0.745 (18.93)
16
1
9
0.280 (7.11)
0.240 (6.10)
8
0.325 (8.25)
0.300 (7.62)
0.195 (4.95)
0.115 (2.93)
0.060 (1.52)
0.015 (0.38)
PIN 1
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
SEATING
PLANE
16-Lead SOIC (Narrow Body)
(SO-16)
0.3937 (10.00)
0.3859 (9.80)
16
1
9
8
0.1574 (4.00)
0.1497 (5.80)
0.2550 (6.20)
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
0.0196 (0.50)
PIN 1
x 45°
0.0098 (0.25)
0.0040 (0.10)
0.0099 (0.25)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0500 (1.27)
0.0160 (0.41)
0.0099 (0.25)
0.0075 (0.19)
REV. D
–8–
相关型号：
SMPZ18FPZ
IC 8 CHANNEL, SAMPLE AND HOLD AMPLIFIER, 3.5 us ACQUISITION TIME, PDIP16, PLASTIC, DIP-16, Sample and Hold Circuit
ADI
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