SSM2164SZ [ADI]
Low Cost Quad Voltage Controlled Amplifier;
| 型号： | SSM2164SZ |
| 厂家： | 
ADI |
| 描述： | Low Cost Quad Voltage Controlled Amplifier 光电二极管 商用集成电路 |
| 文件： | 总12页 (文件大小：329K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Cost Quad
Voltage Controlled Amplifier
a
SSM2164
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Four High Performance VCAs in a Single Package
0.02% THD
No External Trimming
120 dB Gain Range
0.07 dB Gain Matching (Unity Gain)
Class A or AB Operation
V
I
C
VCA1
VCA2
VCA3
VCA4
I
I
I
IN
IOUT
IOUT
IOUT
APPLICATIONS
Remote, Automatic, or Computer Volume Controls
Automotive Volume/Balance/Faders
Audio Mixers
Compressor/Limiters/Compandors
Noise Reduction Systems
Automatic Gain Controls
Voltage Controlled Filters
Spatial Sound Processors
Effects Processors
V
C
I
IN
V
C
GENERAL DESCRIPTION
The SSM2164 contains four independent voltage controlled
amplifiers (VCAs) in a single package. High performance
(100 dB dynamic range, 0.02% THD) is provided at a very low
cost-per-VCA, resulting in excellent value for cost sensitive gain
control applications. Each VCA offers current input and output
for maximum design flexibility, and a ground referenced
–33 mV/dB control port.
I
IN
V
C
I
I
IN
IOUT
All channels are closely matched to within 0.07 dB at unity gain,
and 0.24 dB at 40 dB of attenuation. A 120 dB gain range is
possible.
POWER SUPPLY
AND BIASING CIRCUITRY
A single resistor tailors operation between full Class A and AB
modes. The pinout allows upgrading of SSM2024 designs with
minimal additional circuitry.
The SSM2164 will operate over a wide supply voltage range of
±4 V to ±18 V. Available in 16-pin P-DIP and SOIC packages,
the device is guaranteed for operation over the extended
industrial temperature range of –40°C to +85°C.
V+
GND
V–
MODE
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
SSM2164–SPECIFICATIONS
(V = ±15 V, A = 0 dB, 0 dBu = 0.775 V rms, V = 0 dBu, R = ROUT = 30 kΩ, f = 1 kHz,
ELECTRICAL SPECIFICATIONS
S
V
IN
IN
–40°C < TA < +85°C using Typical Application Circuit (Class AB), unless otherwise noted. Typical specifications apply at TA = +25°C.)
SSM2164
Parameter
Conditions
Min
Typ
Max
Units
AUDIO SIGNAL PATH
Noise
Headroom
V
IN = GND, 20 kHz Bandwidth
–94
22
dBu
dBu
Clip Point = 1% THD+N
2nd and 3rd Harmonics Only
AV = 0 dB, Class A
Total Harmonic Distortion
0.02
0.15
0.16
0.3
.1
%
%
%
%
AV = ±20 dB, Class A1
AV = 0 dB, Class AB
AV = ±20 dB, Class AB1
Channel Separation
Unity Gain Bandwidth
Slew Rate
Input Bias Current
Output Offset Current
Output Compliance
–110
500
0.7
±10
±50
±0.1
dB
kHz
mA/µs
nA
nA
V
CF = 10 pF
CF = 10 pF
V
IN = 0
CONTROL PORT
Input Impedance
5
kΩ
Gain Constant
Gain Constant Temperature Coefficient
Control Feedthrough
(Note 2)
–33
–3300
1.5
0.07
0.24
–100
+20
mV/dB
ppm/°C
mV
dB
dB
0 dB to –40 dB Gain Range3
AV = 0 dB
AV = –40 dB
8.5
Gain Matching, Channel-to-Channel
Maximum Attenuation
Maximum Gain
dB
dB
POWER SUPPLIES
Supply Voltage Range
Supply Current
±4
±18
8
V
mA
dB
Class AB
60 Hz
6
90
Power Supply Rejection Ratio
NOTES
1–10 dBu input @ 20 dB gain; +10 dBu input @ –20 dB gain.
2After 60 seconds operation.
3+25°C to +85°C.
Specifications subject to change without notice.
TYPICAL APPLICATION AND TEST CIRCUIT
100pF
V
C
14
15
V
C4
30kΩ
I
13 IOUT
I
IN
VCA4
30kΩ
1/2
V
OUT4
V
OP275
IN4
500Ω
560pF
POWER SUPPLY
AND BIASING CIRCUITRY
9
8
16
1
V–
GND V+
MODE
0.1µF 0.1µF
R
(7.5kΩ CLASS A)
B
(OPEN CLASS AB)
–15V
+15V
Figure 1. RIN = ROUT = 30 kΩ, CF = 100 pF. Optional RB = 7.5 kΩ, Biases Gain Core to Class A Opera-
tion. For Class AB, Omit RB.
–2–
REV. 0
SSM2164
ABSOLUTE MAXIMUM RATINGS
ORDERING GUIDE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Input, Output, Control Voltages . . . . . . . . . . . . . . . . V– to V+
Output Short Circuit Duration to GND . . . . . . . . . Indefinite
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C
Temperature
Range
Package
Description
Package
Options
Model
SSM2164P
SSM2164S
–40°C to +85°C
–40°C to +85°C
Plastic DIP
Narrow SOIC R-16A
N-16
Package Type
θJA*
θJC
Units
PIN CONFIGURATION
16-Lead Epoxy DIP and SOIC
16-Pin Plastic DIP (P Suffix)
16-Pin SOIC (S Suffix)
76
92
33
27
°C/W
°C/W
*θJA is specified for the worst case conditions; i.e., θJA is specified for device in socket
for P-DIP packages, θJA is specified for device soldered in circuit board for SOIC
package.
MODE
1
2
3
4
5
6
7
8
16 V+
I
15
14
13
12
11
10
9
I
IN4
IN1
V
V
C4
C1
SSM2164
TOP VIEW
(Not to Scale)
I
I
I
OUT1
OUT4
OUT3
I
OUT2
V
V
C3
C2
I
I
IN3
IN2
GND
V–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the SSM2164 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
SSM2164
Typical Performance Characteristics
210
200
1.0
CLASS A
190
180
170
160
150
140
130
120
110
100
90
V
T
= ±15V
= +25°C
S
V
= ±15V
S
A
LPF = 80kHz
1200 CHANNELS
A
= + 20dB
= – 20dB
V
0.1
A
V
80
70
60
50
40
30
A
= 0dB
V
20
10
0
0.01
20
100
20k
1k
FREQUENCY – Hz
10k
0.00 0.05 0.10 0.15
0.20 0.25
THD – %
0.30
0.35 0.40
0.45
Figure 2. THD+N vs. Frequency, Class A
Figure 5. THD Distribution, Class AB
1.0
1.0
V
A
±15V
= 0dB
S
CLASS AB
= ±15V
LPF = 80kHz
V
V
S
LPF = 22kHz
A
= –20dB
V
A
= +20dB
V
CLASS AB
A
= 0dB
V
0.1
0.1
CLASS A
0.01
0.01
20
100
20k
20
100
20k
1k
FREQUENCY – Hz
10k
1k
AMPLITUDE – V
10k
RMS
Figure 3. THD+N vs. Frequency Class, AB
Figure 6. THD+N vs. Amplitude
0.10
300
280
260
240
220
200
180
160
140
120
100
80
V
= ±15V
= +25°C
LPF = 80kHz
S
T
A
0.08
0.06
0.04
0.02
0
1200 CHANNELS
60
40
20
0
0
±4
±8
±12
±16
±20
0.005 0.010 0.015 0.020 0.025 0.030 0.035 0.040 0.045 0.050
SUPPLY – Volts
THD – %
Figure 4. THD Distribution, Class A
Figure 7. THD+N vs. Supply Voltage, Class A
–4–
REV. 0
SSM2164
1000
100
10
V
T
= ±15V
= +25°C
S
A
V
V
A
= ±15V
= 0dBu
= 0dB
S
0.030
0.025
0.020
IN
V
0.015
0.010
1k
10k
100k
1M
–40
–20
0
20
40
60
80
R
– Ω
BIAS
TEMPERATURE – °C
Figure 8. THD vs. Temperature, Class A
Figure 11. Voltage Noise Density vs. RBIAS
1.0
V
T
= ±15V
= +25°C
S
A
V
V
A
= ±15V
= 0dBu
= 0dB
S
0.30
0.25
0.20
IN
V
0.1
0.15
0.10
0.01
–40
–20
0
20
40
60
80
1k
10k
100k
1M
R
– Ω
BIAS
TEMPERATURE – °C
Figure 9. THD vs. Temperature, Class AB
Figure 12. THD vs. RBIAS
500
400
10
5
V
= ±15V
S
V
T
= ±15V
= +25°C
S
A
R
T
= R = 30kΩ
IN
F
= +25°C
A
0
300
200
100
0
–5
–10
–15
–20
1k
10k
100k
1M
1
10
100
1k
10k
100k
R
– Ω
BIAS
FREQUENCY – Hz
Figure 10. Voltage Noise Density vs. Frequency, Class AB
Figure 13. Control Feedthrough vs. RBIAS
REV. 0
–5–
SSM2164
Typical Performance Characteristics
10M
1M
15
PHASE
V
T
= ±15V
= +25°C
S
A
10
5
180
90
0
V
= ±15V
= +25°C
= 0dB
S
T
A
A
C
V
F
= 10pF
GAIN
0
–5
–10
–15
100k
10k
–90
–180
1k
10k
100k
FREQUENCY – Hz
1M
10M
1
10
100
1000
I TO V FEEDBACK CAPACITOR – pF
Figure 14. Gain/Phase vs. Frequency
Figure 17. –3 dB Bandwidth vs. I-to-V Feedback Capacitor
0.1
30
C
= 10pF
F
±SLEW RATE
V
T
= ±15V
= +25°C
25
20
15
S
A
0
C
= 100pF
F
–0.1
OP275 OUTPUT
AMPLIFIER
V
= ±15V
= +25°C
= 0dB
S
T
A
–0.2
–0.3
–0.4
A
V
10
5
0
10
100
1k
FREQUENCY – Hz
10k
100k
1
10
100
I TO V FEEDBACK CAPACITOR – pF
Figure 15. Gain Flatness vs. Frequency
Figure 18. Slew Rate vs. I-to-V Feedback Capacitor
40
20
20
V
T
C
= ±15V
= +25°C
= 10pF
S
V
T
= ±15V
= +25°C
= 0V
S
A
A
= +20dB
V
A
F
0
V
IN
R
= R = 30kΩ
F
IN
A
= 0dB
V
0
–20
–40
–60
–20
A
= –20dB
V
–40
–60
–80
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 16. Bandwidth vs. Gain
Figure 19. Control Feedthrough vs. Frequency
–6–
REV. 0
SSM2164
APPLICATIONS INFORMATION
Circuit Description
0
The SSM2164 is a quad Voltage Controlled Amplifier (VCA)
with 120 dB of gain control range. Each VCA is a current-in,
current-out device with a separate –33 mV/dB voltage input
control port. The class of operation (either Class A or Class
AB) is set by a single external resistor allowing optimization of
the distortion versus noise tradeoff for a particular application.
The four independent VCAs in a single 16-pin package make
the SSM2164 ideal for applications where multiple volume
control elements are needed.
V
T
= ±15V
= +25°C
S
A
–20
–40
–60
+PSRR
–PSRR
–80
V+
–100
10
100
1k
10k
100K
1M
FREQUENCY – Hz
Figure 20. PSRR vs. Frequency
Q5
Q6
Q7
Q8
I
IN
25
20
V
T
= ±15V
= +25°C
S
I
OUT
A
4.5kΩ
500Ω
MODE
Q1 Q2
Q3 Q4
450Ω
V
C
+ISY
15
10
–ISY
5
0
V–
1k
10k
100k
1M
R
– Ω
BIAS
Figure 23. Simplified Schematic (One Channel)
Figure 21. Supply Current vs. RBIAS
The simplified schematic in Figure 23 shows the basic structure
of one of the four VCAs in the device. The gain core is com-
prised of the matched differential pairs Q1-Q4 and the current
mirrors of Q5, Q6 and Q7, Q8. The current input pin, IIN, is
connected to the collectors of Q1 and Q7, and the difference in
current between these two transistors is equivalent to IIN. For
example, if 100 µA is flowing into the input, Q1’s collector
current will be 100 µA higher than Q7’s collector current.
–45
–40
CLASS A AND
CLASS AB
V
= ±15V
S
–35
–30
Varying the control voltage VC, steers the signal current from
one side of each differential pair to the other, resulting in either
gain or attenuation. For example, a positive voltage on VC
steers more current through Q1 and Q4 and decreases the
current in Q2 and Q3. The current output pin, IOUT, is con-
nected to the collector of Q3 and the current mirror (Q6) from
Q2. With less current flowing through these two transistors, less
current is available at the output. Thus, a positive VC attenuates
the input and a negative VC amplifies the input. The VCA has
unity gain for a control voltage of 0.0 V where the signal current
is divided equally between the gain core differential pairs.
–25
–20
–50
–25
0
25
50
75
100
TEMPERATURE – °C
Figure 22. Gain Constant vs. Temperature
The MODE pin allows the setting of the quiescent current in
the gain core of the VCA to trade off the SSM2164’s THD and
noise performance to an optimal level for a particular applica-
tion. Higher current through the core results in lower distortion
REV. 0
–7–
SSM2164
a low cutoff frequency. The main exception to this is in
dynamic processing applications, where faster attack or decay
times may be needed.
but higher noise, and the opposite is true for less current. The
increased noise is due to higher current noise in the gain core
transistors as their operating current is increased. THD has the
opposite relationship to collector current. The lower distortion
is due to the decrease in the gain core transistors’ emitter
impedance as their operating current increases.
+5V
100pF
3
2
V
I
C
100k
This classical tradeoff between THD and noise in VCAs is
usually expressed as the choice of using a VCA in either Class A
or Class AB mode. Class AB operation refers to running a VCA
with less current in the gain core, resulting in lower noise but
higher distortion. More current in the core corresponds to
Class A performance with its lower THD but higher noise.
Figures 11 and 12 show the THD and noise performance of the
SSM2164 as the bias current is adjusted. Notice the two
characteristics have an inverse characteristic.
1µF
30k
30k
I
I
I
I
IOUT
IOUT
IOUT
IN
4
VCA1
VCA2
VCA3
1/4
OP482
V
V
V
V
V
OUT1
IN1
500
560pF
+5V
+5V
+5V
100pF
V
6
7
C
100k
1µF
30k
30k
5
I
IN
1/4
OP482
V
V
V
OUT2
OUT3
OUT4
IN2
The quiescent current in the core is set by adding a single
resistor from the positive supply to the MODE pin. As the
simplified schematic shows, the potential at the MODE pin is
one diode drop above the ground pin. Thus, the formula for the
MODE current is:
500
560pF
100pF
V
C
11
10
100k
1µF
30k
30k
I
12
IN
1/4
OP482
(V +)− 0.6V
IN3
IMODE
=
500
RB
560pF
100pF
V
I
14
15
C
With ±15 V supplies, an RB of 7.5k gives Class A biasing with a
current of 1.9 mA. Leaving the MODE pin open sets the
SSM2164 in Class AB with 30 µA of current in the gain core.
100k
1µF
30k
30k
13 IOUT
IN
VCA4
1/4
OP482
Basic VCA Configuration
IN4
500
Figure 24 shows the basic application circuit for the SSM2164.
Each of the four channels is configured identically. A 30 kΩ
resistor converts the input voltage to an input current for the
VCA. Additionally, a 500 Ω resistor in series with a 560 pF
capacitor must be added from each input to ground to ensure
stable operation. The output current pin should be maintained
at a virtual ground using an external amplifier. In this case the
OP482 quad JFET input amplifier is used. Its high slew rate,
wide bandwidth, and low power make it an excellent choice for
the current-to-voltage converter stage. A 30 kΩ feedback
resistor is chosen to match the input resistor, giving unity gain
for a 0.0 V control voltage. The 100 pF capacitors ensure
stability and reduce high frequency noise. They can be
increased to reduce the low pass cutoff frequency for further
noise reduction.
560pF
POWER SUPPLY
AND BIASING CIRCUITRY
9
8
16
1
V–
GND V+
MODE
0.1µF 0.1µF
R
(7.5kΩ CLASS A)
(OPEN CLASSAB)
B
–15V
+15V
Figure 24. Basic Quad VCA Configuration
Low Cost, Four-Channel Mixer
The four VCAs in a single package can be configured to create a
simple four-channel mixer as shown in Figure 25. The inputs
and control ports are configured the same as for the basic VCA,
but the outputs are summed into a single output amplifier. The
OP176 is an excellent amplifier for audio applications because
of its low noise and distortion and high output current drive.
The amount of signal from each input to the common output
can be independently controlled using up to 20 dB of gain or as
much as 100 dB of attenuation. Additional SSM2164s could be
added to increase the number of mixer channels by simply
summing their outputs into the same output amplifier. Another
possible configuration is to use a dual amplifier such as the
OP275 to create a stereo, two channel mixer with a single
SSM2164.
For this example, the control voltage is developed using a
100 kΩ potentiometer connected between +5 V and ground.
This configuration results in attenuation only. To produce both
gain and attenuation, the potentiometer should be connected
between a positive and negative voltage. The control input has
an impedance of 5 kΩ. Because of this, any resistance in series
with VC will attenuate the control signal. If precise control of
the gain and attenuation is required, a buffered control voltage
should be used.
Notice that a capacitor is connected from the control input to
ground. Because the control port is connected directly to the
gain core transistors, any noise on the VC pin will increase the
output noise of the VCA. Filtering the control voltage ensures
that a minimal amount of noise is introduced into the VCA,
allowing its full performance to be realized. In general, the
largest possible capacitor value should be used to set the filter at
–8–
REV. 0
SSM2164
If additional SSM2164s are added, the 100 pF capacitor may
need to be increased to ensure stability of the output amplifier.
Most op amps are sensitive to capacitance on their inverting
inputs. The capacitance forms a pole with the feedback resistor,
which reduces the high frequency phase margin. As more
SSM2164’s are added to the mixer circuit, their output capaci-
tance and the parasitic trace capacitance add, increasing the
overall input capacitance. Increasing the feedback capacitor will
maintain the stability of the output amplifier.
V
C
30k
500
I
I
I
I
IOUT
IOUT
IOUT
IOUT
VCA1
VCA2
VCA3
VCA4
I
IN
560pF
V
C
100pF
30k
30kΩ
500
I
IN
Digital Control of the SSM2164
560pF
OP176
V
OUT
One option for controlling the gain and attenuation of the
SSM2164 is to use a voltage output digital-to-analog converter
such as the DAC8426 (Figure 26), whose 0 V to +10 V output
controls the SSM2164’s attenuation from 0 dB to –100 dB. Its
simple 8-bit parallel interface can easily be connected to a
microcontroller or microprocessor in any digitally controlled
system. The voltage output configuration of the DAC8426
provides a low impedance drive to the SSM2164 so the attenua-
tion can be controlled accurately. The 8-bit resolution of the
DAC and its full-scale voltage of +10 V gives an output of
3.9 mV/bit. Since the SSM2164 has a –33 mV/dB gain con-
stant, the overall control law is 0.12 dB/bit or approximately
8 bits/dB. The input and output configuration for the
SSM2164 is the same as for the basic VCA circuit shown
earlier. The 4-to-1 mixer configuration could also be used.
V
C
30k
500
I
IN
560pF
V
C
30k
500
I
IN
560pF
FROM ADDITIONAL SSM2164s
FOR > 4 CHANNELS
POWER SUPPLY
AND BIASING CIRCUITRY
V+
GND
V–
MODE
Figure 25. Four-Channel Mixer (4 to 1)
V
+15V
C
V
DD
V
OUT +10V
REF
I
IN
I
I
I
I
IOUT
IOUT
IOUT
IOUT
4
18
VCA1
VCA2
VCA3
VCA4
10V
REFERENCE
DAC8426
V
I
C
2
V
V
OUTA
LATCH A
LATCH B
LATCH C
LATCH D
DAC A
DAC B
DAC C
DAC D
IN
1
OUTB
7
MSB
V
C
DATA BUS
14
LSB
20
19
V
V
OUTC
OUTD
I
IN
V
C
15
16
17
WR
A1
A0
LOGIC
CONTROL
3
5
6
I
IN
AGND
DGND
V
SS
POWER SUPPLY
AND BIASING CIRCUITRY
V+
V– MODE
GND
+15V
–15V
Figure 26. Digital Control of VCA Gain
REV. 0
–9–
SSM2164
Single Supply Operation
Upgrading SSM2024 Sockets
The SSM2164 can easily be operated from a single power
supply as low as +8 V or as high as +36 V. The key to using a
single supply is to reference all ground connections to a voltage
midway between the supply and ground as shown in Figure 27.
The OP176 is used to create a pseudo-ground reference for the
SSM2164. Both the OP482 and OP176 are single supply
amplifiers and can easily operate over the same voltage range as
the SSM2164 with little or no change in performance.
The SSM2164 is intended to replace the SSM2024, an earlier
generation quad VCA. The improvements in the SSM2164
have resulted in a part that is not a drop-in replacement to the
SSM2024, but upgrading applications with the SSM2024 is a
simple task. The changes are shown in Figure 28. Both parts
have identical pinouts with one small exception. The MODE
input (Pin 1) does not exist on the SSM2024. It has fixed
internal biasing, whereas flexibility was designed into the
SSM2164. A MODE set resistor should be added for Class A
operation, but if the SSM2164 is going to be operated in Class
AB, no external resistor is needed.
V+ = +8V
(1.8kΩ FOR
CLASS A)
(OPEN FOR
CLASS B)
R
B
10kΩ
100pF
V
C1
V+
16
V+
30kΩ
V+
NC
1
3
16
1
10kΩ
10µF
30kΩ
MODE
GND
10kΩ
2
4
V
IN
V
IN1
SSM2024
1/4
OP482
V
V
OUT1
OUT
500Ω
560pF
8
200Ω
V–
8
9
9
V+
V+
V–
V
C
V+
2
(0dB GAIN AT V
=
)
C
V+/2
10kΩ
V+
OP176
V
C1
3
R
10kΩ
10µF
B
16
TO ADDITIONAL
OP482 AMPLIFIERS
30kΩ
1
30kΩ
2
4
V
IN1
SSM2164
V
OUT1
8
500Ω
560pF
9
Figure 27. Single Supply Operation of the SSM2164
(One Channel Shown)
V–
The reference voltage is set by the resistor divider from the
positive supply. Two 10 kΩ resistors create a voltage equal to
the positive supply divided by 2. The 10 µF capacitor filters the
supply voltage, providing a low noise reference to the circuit.
This reference voltage is then connected to the GND pin of the
SSM2164 and the noninverting inputs of all the output amplifi-
ers. It is important to buffer the resistor divider with the OP176
to ensure a low impedance pseudo-ground connection for the
SSM2164.
Figure 28. Upgrading SSM2024 Sockets with SSM2164
Since both parts are current output devices, the output configu-
ration is nearly identical, except that the 10 kΩ resistors should
be increased to 30 kΩ to operate the SSM2164 in its optimum
range. The 10 kΩ input resistor for the SSM2024 should also
be increased to 30 kΩ to match the output resistor. Addition-
ally, the 200 Ω resistor should be replaced by a 500 Ω resistor in
series with 560 pF for the SSM2164 circuit.
The input can either be referenced to this same mid-supply
voltage or ac coupled as is done in this case. If the entire system
is single supply, then the input voltage will most likely already
be referenced to the midpoint; if this is the case, the 10 µF
input capacitor can be eliminated. Unity gain is set when VC
equals the voltage on the GND pin. Thus, the control voltage
should also be referenced to the same midsupply voltage.
One last change is the control port configuration. The
SSM2024’s control input is actually a current input. Thus, a
resistor was needed to change the control voltage to a current.
This resistor should be removed for the SSM2164 to provide a
direct voltage input. In addition, the SSM2024 has a log/log
control relationship in contrast to the SSM2164’s linear/log gain
constant. The linear input is actually much easier to control,
but the difference may necessitate adjusting a SSM2024 based
circuit’s control voltage gain curve. By making these relatively
simple changes, the superior performance of the SSM2164 can
easily be realized.
The value of the MODE setting resistor may also change
depending on the total supply voltage. Because the GND pin is
at a pseudo-ground potential, the equation to set the MODE
current now becomes:
(V +)−VGND − 0.6V
IMODE
=
RB
The value of 1.8 kΩ results in Class A biasing for the case of
using a +8 V supply.
–10–
REV. 0
SSM2164
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Pin Plastic DIP (N-16)
16
1
9
0.280 (7.11)
0.240 (6.10)
PIN 1
8
0.325 (8.25)
0.300 (7.62)
0.840 (21.33)
0.745 (18.93)
0.060 (1.52)
0.015 (0.38)
0.195 (4.95)
0.115 (2.93)
0.210
(5.33)
MAX
0.130
(3.30)
MIN
0.015 (0.381)
0.008 (0.204)
0.160 (4.06)
0.115 (2.93)
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
16-Pin Narrow SOIC (R-16A)
16
9
0.1574 (4.00)
0.1497 (3.80)
PIN 1
0.2440 (6.20)
0.2284 (5.80)
8
1
0.3937 (10.00)
0.3859 (9.80)
0.0196 (0.50)
x 45°
0.0099 (0.25)
0.0688 (1.75)
0.0532 (1.35)
8°
0°
0.0098 (0.25)
0.0040 (0.10)
0.0500 (1.27)
0.0160 (0.41)
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0099 (0.25)
0.0075 (0.19)
REV. 0
–11–
–12–
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