SSM2604CPZ-REEL [ADI]
Low Power Audio Codec; 低功耗音频编解码器
| 型号： | SSM2604CPZ-REEL |
| 厂家： | 
ADI |
| 描述： | Low Power Audio Codec |
| 文件： | 总28页 (文件大小：493K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Power Audio Codec
SSM2604
FEATURES
GENERAL DESCRIPTION
Stereo, 24-bit analog-to-digital and digital-to-analog converters
DAC SNR: 100 dB (A-weighted), THD: −80 dB at 48 kHz, 3.3 V
ADC SNR: 90 dB (A-weighted), THD: −80 dB at 48 kHz, 3.3 V
Stereo line inputs
The SSM2604 is a low power, high quality stereo audio codec
for portable digital audio applications with one set of stereo
programmable gain amplifier (PGA) line inputs. It features two
24-bit analog-to-digital converter (ADC) channels and two
24-bit digital-to-analog (DAC) converter channels.
Low power
7 mW stereo playback (1.8 V/1.5 V supplies)
14 mW record and playback (1.8 V/1.5 V supplies)
Low supply voltages
Analog: 1.8 V to 3.6 V
Digital: 1.5 V to 3.6 V
256/384 oversampling rate in normal mode;
250/272 oversampling rate in USB mode
Audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz,
22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz,
and 96 kHz
The SSM2604 can operate as a master or a slave. It supports
various master clock frequencies, including 12 MHz or 24 MHz
for USB devices; standard 256 fS or 384 fS based rates, such as
12.288 MHz and 24.576 MHz; and many common audio sam-
pling rates, such as 96 kHz, 88.2 kHz, 48 kHz, 44.1 kHz, 32 kHz,
24 kHz, 22.05 kHz, 16 kHz, 12 kHz, 11.025 kHz, and 8 kHz.
The SSM2604 can operate at power supplies as low as 1.8 V for
the analog circuitry and as low as 1.5 V for the digital circuitry.
The maximum voltage supply is 3.6 V for all supplies.
20-lead, 4 mm × 4 mm LFCSP (QFN) package
The SSM2604 is specified over the industrial temperature range
of −40°C to +85°C. It is available in a 20-lead, 4 mm × 4 mm
lead frame chip scale package (LFCSP).
APPLICATIONS
Mobile phones
MP3 players
Portable gaming
Portable electronics
Educational toys
FUNCTIONAL BLOCK DIAGRAM
AVDD VMID AGND
DVDD DGND
SSM2604
BYPASS
–34.5dB TO +33dB,
1.5dB STEP
ADC
DAC
RLINEIN
LLINEIN
ROUT
DIGITAL
PROCESSOR
ADC
DAC
LOUT
–34.5dB TO +33dB,
1.5dB STEP
BYPASS
CLK
DIGITAL AUDIO INTERFACE
CONTROL INTERFACE
MCLK/ XTO CLKOUT
XTI
PBDAT RECDAT BCLK PBLRC RECLRC SDIN
SCLK
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
SSM2604
TABLE OF CONTENTS
Features .............................................................................................. 1
ADC High-Pass and DAC De-Emphasis Filters .................... 11
Analog Interface ......................................................................... 12
Digital Audio Interface.............................................................. 12
Software Control Interface........................................................ 15
Typical Application Circuits ......................................................... 16
Register Map ................................................................................... 17
Register Map Details ...................................................................... 18
Left-Channel ADC Input Volume, Address 0x00.................. 18
Right-Channel ADC Input Volume, Address 0x01 ............... 19
Analog Audio Path, Address 0x04 ........................................... 20
Digital Audio Path, Address 0x05............................................ 20
Power Management, Address 0x06.......................................... 21
Digital Audio I/F, Address 0x07 ............................................... 22
Sampling Rate, Address 0x08.................................................... 22
Active, Address 0x09.................................................................. 25
Software Reset, Address 0x0F................................................... 25
Outline Dimensions....................................................................... 26
Ordering Guide .......................................................................... 26
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Digital Filter Characteristics ....................................................... 4
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Converter Filter Response........................................................... 9
Digital De-Emphasis.................................................................. 10
Theory of Operation ...................................................................... 11
Digital Core................................................................................. 11
ADC and DAC............................................................................ 11
REVISION HISTORY
7/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
SSM2604
SPECIFICATIONS
TA = 25°C, AVDD = DVDD = 3.3 V, 1 kHz signal, fS = 48 kHz, PGA gain = 0 dB, 24-bit audio data, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Conditions
RECOMMENDED OPERATING CONDITIONS
Analog Voltage Supply (AVDD)
Digital Power Supply
Ground (AGND, DGND)
POWER CONSUMPTION
Power-Up
1.8
1.5
3.3
3.3
0
3.6
3.6
V
V
V
Stereo Record (1.5 V and 1.8 V)
Stereo Record (3.3 V)
Stereo Playback (1.5 V and 1.8 V)
Stereo Playback (3.3 V)
Power-Down
7
22
7
22
56
mW
mW
mW
mW
μW
LINE INPUT
Input Signal Level (0 dB)
Input Impedance
1 × AVDD/3.3
200
10
480
10
V rms
kΩ
kΩ
kΩ
pF
PGA gain = 0 dB
PGA gain = +33 dB
PGA gain = −34.5 dB
Input Capacitance
Signal-to-Noise Ratio (A-Weighted)
70
90
84
−80
−75
80
0
1.5
−80
dB
dB
dB
dB
dB
dB
dB
dB
PGA gain = 0 dB, AVDD = 3.3 V
PGA gain = 0 dB, AVDD = 1.8 V
−1 dBFS input, AVDD = 3.3 V
−1 dBFS input, AVDD = 1.8 V
Total Harmonic Distortion (THD)
Channel Separation
Programmable Gain
Gain Step
Mute Attenuation
LINE OUTPUT
−34.5
+33.5
DAC
−1 dBFS input DAC + line output
Full-Scale Output
Signal-to-Noise Ratio (A-Weighted)
1 × AVDD/3.3
100
94
−80
−75
50
V rms
dB
dB
dB
dB
85
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
THD + N
−75
Power Supply Rejection Ratio
Channel Separation
dB
dB
80
LINE INPUT TO LINE OUTPUT
Full-Scale Output Voltage
Signal-to-Noise Ratio (A-Weighted)
1 × AVDD/3.3
92
V rms
dB
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
86
dB
dB
dB
dB
Total Harmonic Distortion
Power Supply Rejection
−80
−80
50
Rev. 0 | Page 3 of 28
SSM2604
DIGITAL FILTER CHARACTERISTICS
Table 2.
Parameter
ADC FILTER
Pass Band
Min
Typ
Max
Unit
Conditions
0
0.445 fS
0.04
Hz
Hz
dB
Hz
dB
Hz
Hz
Hz
0.04 dB
−6 dB
0.5 fS
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
High-Pass Filter Corner Frequency
0.555 fS
−61
f > 0.567 fS
−3 dB
−0.5 dB
−0.1 dB
3.7
10.4
21.6
DAC FILTER
Pass Band
0
0.445 fS
0.04
Hz
Hz
dB
Hz
dB
0.04 dB
−6 dB
0.5 fS
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
CORE CLOCK TOLERANCE
Frequency Range
Jitter Tolerance
0.555 fS
−61
f > 0.565 fS
8.0
13.8
MHz
ps
50
Rev. 0 | Page 4 of 28
SSM2604
TIMING CHARACTERISTICS
Table 3. I2C Timing
Limit
tMAX
Parameter
tMIN
600
600
600
1.3
0
Unit
ns
ns
ns
ꢀs
Description
tSCS
tSCH
tPH
tPL
fSCLK
tDS
Start condition setup time
Start condition hold time
SCLK pulse width high
SCLK pulse width low
SCLK frequency
526
kHz
ns
100
Data setup time
tDH
tRT
tFT
900
300
300
ns
ns
ns
ns
Data hold time
SDIN and SCLK rise time
SDIN and SCLK fall time
Stop condition setup time
tHCS
600
tSCH
tHCS
tSCS
SDIN
tDS
tPH
tDH
tPL
tRT
SCLK
tFT
Figure 2. I2C Timing
Table 4. Digital Audio Interface Slave Mode Timing
Limit
Parameter
tDS
tDH
tLRSU
tLRH
tMIN
10
10
10
10
tMAX
Unit
ns
ns
ns
ns
Description
PBDAT setup time from BCLK rising edge
PBDAT hold time from BCLK rising edge
RECLRC/PBLRC setup time to BCLK rising edge
RECLRC/PBLRC hold time to BCLK rising edge
tDD
30
ns
RECDAT propagation delay from BCLK falling edge (external load of 70 pF)
tBCH
tBCL
tBCY
25
25
50
ns
ns
ns
BCLK pulse width high
BCLK pulse width low
BCLK cycle time
tBCH tBCL
tBCY
BCLK
PBLRC/
RECLRC
tDS tLRH tLRSU
PBDAT
tDH
tDD
RECDAT
Figure 3. Digital Audio Interface Slave Mode Timing
Rev. 0 | Page 5 of 28
SSM2604
Table 5. Digital Audio Interface Master Mode Timing
Limit
Parameter
tDST
tDHT
tDL
tDDA
tBCLKR
tBCLKF
tBCLKDS
tMIN
30
10
tMAX
Unit
ns
ns
ns
ns
Description
PBDAT setup time to BCLK rising edge
PBDAT hold time to BCLK rising edge
RECLRC/PBLRC propagation delay from BCLK falling edge
RECDAT propagation delay from BCLK falling edge
BCLK rising time (10 pF load)
10
10
10
10
45:55:00
ns
ns
BCLK falling time (10 pF load)
BCLK duty cycle (normal and USB mode)
55:45:00
BCLK
tDL
PBLRC/
RECLRC
tDST tDHT
PBDAT
tDDA
RECDAT
Figure 4. Digital Audio Interface Master Mode Timing
Table 6. System Clock Timing
Limit
Parameter
tXTIY
tMCLKDS
tXTIH
tXTIL
tCOP
tMIN
72
40:60
32
32
20
tMAX
Unit
Description
ns
MCLK/XTI system clock cycle time
MCLK/XTI duty cycle
MCLK/XTI system clock pulse width high
MCLK/XTI system clock pulse width low
CLKOUT propagation delay from MCLK/XTI falling edge
CLKODIV2 propagation delay from MCLK/XTI falling edge
60:40:00
ns
ns
ns
ns
tCOPDIV2
20
tXTIH
tCOP
MCLK/XTI
tXTIL
tXTIY
CLKOUT
CLKODIV2
t
COPDIV2
Figure 5. System (MCLK) Clock Timing
Rev. 0 | Page 6 of 28
SSM2604
ABSOLUTE MAXIMUM RATINGS
At 25°C, unless otherwise noted.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 7.
Parameter
Rating
Supply Voltage
Input Voltage
3.6 V
VDD
VDD
−65°C to +150°C
−40°C to +85°C
−65°C to +165°C
300°C
Table 8. Thermal Resistance
Package Type
θJA
θJC
Unit
Common-Mode Input Voltage
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 60 sec)
20-Lead, 4 mm × 4 mm LFCSP
28
32
°C/W
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 7 of 28
SSM2604
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
MCLK/XTI 1
XTO 2
DGND 3
DVDD 4
CLKOUT 5
15 VMID
14 AGND
13 AVDD
12 ROUT
11 LOUT
SSM2604
TOP VIEW
(Not to Scale)
NOTES
1. NC = NO CONNECT.
2. FOR PROPER CONNECTION OF THE EXPOSED PAD,
CONNECT TO PCB GROUND LAYER
Figure 6. Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
Mnemonic
MCLK/XTI
XTO
DGND
DVDD
CLKOUT
BCLK
PBDAT
PBLRC
RECDAT
RECLRC
LOUT
Type
Description
1
2
3
4
5
6
7
8
Digital Input
Digital Output
Digital Ground
Digital Supply
Digital Output
Master Clock Input/Crystal Input.
Crystal Output.
Digital Ground.
Digital Core and I/O Buffer Supply.
Buffered Clock Output.
Digital Audio Bit Clock.
DAC Digital Audio Data Input, Playback Function.
DAC Sampling Rate Clock, Playback Function (from Left and Right Channels).
ADC Digital Audio Data Output, Record Function.
ADC Sampling Rate Clock, Record Function (from Left and Right Channels).
Line Output for Left Channel.
Line Output for Right Channel.
Analog Supply.
Analog Ground.
Midrail Voltage Decoupling Input.
Line Input for Right Channel.
Line Input for Left Channel.
2-Wire Control Interface Data Input/Output.
2-Wire Control Interface Clock Input.
No Connection
Digital Input/Output
Digital Input
Digital Input/Output
Digital Output
Digital Input/Output
Analog Output
Analog Output
Analog Supply
Analog Ground
Analog Output
Analog Input
9
10
11
12
13
14
15
16
17
18
19
20
ROUT
AVDD
AGND
VMID
RLINEIN
LLINEIN
SDIN
Analog Input
Digital Input/Output
Digital Input
SCLK
NC
NC
GND Pad
Thermal Pad/Exposed Pad
Center Thermal Pad. Connect to PCB ground layer.
Rev. 0 | Page 8 of 28
SSM2604
TYPICAL PERFORMANCE CHARACTERISTICS
CONVERTER FILTER RESPONSE
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
FREQUENCY (fS
)
FREQUENCY (fS
)
Figure 7. ADC Digital Filter Frequency Response
Figure 9. DAC Digital Filter Frequency Response
0.05
0.04
0.03
0.02
0.01
0
0.05
0.04
0.03
0.02
0.01
0
−0.01
−0.02
−0.03
−0.04
−0.05
−0.01
−0.02
−0.03
−0.04
−0.05
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
FREQUENCY (fS
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
FREQUENCY (fS
)
)
Figure 8. ADC Digital Filter Ripple
Figure 10. DAC Digital Filter Ripple
Rev. 0 | Page 9 of 28
SSM2604
DIGITAL DE-EMPHASIS
0
0.4
0.3
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
0.2
0.1
0
−0.1
−0.2
−0.3
−0.4
0
4
8
12
16
0
4
8
12
16
20
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 14. De-Emphasis Error, Audio Sampling Rate = 44.1 kHz
Figure 11. De-Emphasis Frequency Response, Audio Sampling Rate = 32 kHz
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
0.4
0.3
0.2
0.1
0
−0.1
−0.2
−0.3
−0.4
0
4
8
12
16
20
24
0
4
8
12
16
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 15. De-Emphasis Frequency Response, Audio Sampling Rate = 48 kHz
Figure 12. De-Emphasis Error, Audio Sampling Rate = 32 kHz
0.4
0.3
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
0.2
0.1
0
−0.1
−0.2
−0.3
−0.4
0
4
8
12
16
20
24
0
4
8
12
16
20
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 16. De-Emphasis Error, Audio Sampling Rate = 48 kHz
Figure 13. De-Emphasis Frequency Response, Audio Sampling Rate = 44.1 kHz
Rev. 0 | Page 10 of 28
SSM2604
THEORY OF OPERATION
The ADC accepts analog audio input from the stereo line
inputs. The digital data from the ADC output, once converted,
is processed using the ADC filters.
DIGITAL CORE
Inside the SSM2604 digital core is a central clock source, called
the master clock (MCLK), that produces a reference clock for
all internal audio data processing and synchronization. When
using an external clock source to drive the MCLK pin, great
care should be taken to select a clock source with less than 50 ps
of jitter. Without careful generation of the MCLK signal, the
digital audio quality likely suffers.
Complementary to the ADC channels, the SSM2604 contains a
pair of oversampling Σ-Δ DACs that convert the digital audio
data from the internal DAC filters into an analog audio signal.
The DAC output can also be muted by setting the DACMU bit
(Register R5, Bit D3) in the control register.
To enable the SSM2604 to generate the central reference clock
in a system, connect a crystal oscillator between the MCLK/XTI
input pin and the XTO output pin.
ADC HIGH-PASS AND DAC DE-EMPHASIS FILTERS
The ADC and DAC employ separate digital filters that perform
24-bit signal processing. The digital filters are used for both
record and playback modes and are optimized for each individ-
ual sampling rate used.
To allow an external device to generate the central reference
clock, apply the external clock signal directly through the MCLK/
XTI input pin. In this configuration, the oscillator circuit of the
SSM2604 can be powered down by using the OSC bit (Register
R6, Bit D5) to reduce power consumption.
For recording mode operations, the unprocessed data from the
ADC enters the ADC filters and is converted to the appropriate
sampling frequency, and then is output to the digital audio
interface.
To accommodate applications with very high frequency master
clocks, the internal core reference clock of the SSM2604 can be
set to either MCLK or MCLK divided by 2. This is enabled by
adjusting the setting of the CLKDIV2 bit (Register R8, Bit D6).
Complementary to this feature, the CLKOUT pin can also drive
external clock sources with either the core clock signal or the
core clock divided by 2 by enabling the CLKODIV2 bit
(Register R8, Bit D7).
For playback mode operations, the DAC filters convert the digital
audio interface data to oversampled data, using a sampling rate
selected by the user. The oversampled data is processed by the
DAC and then is sent to the analog output mixer by enabling
the DACSEL (Register R4, Bit D4).
Users have the option of setting up the device so that any dc
offset in the input source signal is automatically detected and
removed. To accomplish this, enable the digital high-pass filter
(see Table 2 for characteristics) contained in the ADC digital
filters by using the ADCHPF bit (Register R5, Bit D0).
ADC AND DAC
The SSM2604 contains a pair of oversampling Σ-Δ ADCs.
The maximum ADC full-scale input level is 1.0 V rms when
AVDD = 3.3 V. If the input signal to the ADC exceeds this
level, data overloading occurs and causes audible distortion.
In addition, users can implement digital de-emphasis by using
the DEEMPH bits (Register R5, Bit D1 and Bit D2).
Rev. 0 | Page 11 of 28
SSM2604
ANALOG INTERFACE
Signal Chain
BYPASS
DACSEL
LINE
INPUT
The SSM2604 includes stereo single-ended line inputs to the
on-board ADC. In addition, the line inputs can be routed and
mixed directly to the output terminals via the BYPASS bit
(Register R4, Bit D3). The SSM2604 also includes line outputs
from the on-board DAC.
DAC
OUTPUT
LINE OUTPUT
AVDD
Stereo Line Inputs
The SSM2604 contains a set of single-ended stereo line inputs
(RLINEIN and LLINEIN) that are internally biased to VMID
by way of a voltage divider between AVDD and AGND. The
line input signal can be connected to the internal ADC and, if
desired, routed directly to the outputs via the bypass path by
using the BYPASS bit (Register R4, Bit D3).
VMID
AGND
Figure 18. Output Signal Chain
LINEIN
The maximum output level of the line outputs is 1.0 V rms
when AVDD and HPVDD = 3.3 V. To suppress audible pops
and clicks, the line outputs are held at the VMID dc voltage
level when the device is set to standby mode.
AVDD
–
+
ADC
The stereo line outputs of the SSM2604, the LOUT and
ROUT pins, are able to drive a load impedance of 10 kΩ and
50 pF. The line output signal levels are not adjustable at the
output mixer, having a fixed gain of 0 dB.
OR
BYPASS
VMID
AGND
DIGITAL AUDIO INTERFACE
Figure 17. Line Input to ADC
The digital audio input can support the following four
digital audio communication protocols: right-justified mode,
left-justified mode, I2S mode, and digital signal processor
(DSP) mode.
The line input volume can be adjusted from −34.5 dB to +33 dB
in steps of +1.5 dB by setting the LINVOL (Register R0, Bit D0
to Bit D5) and RINVOL (Register R1, Bit D0 to Bit D5) bits.
Volume control, by default, is independently adjustable on
both right and left line inputs. However, the LRINBOTH or
RLINBOTH bit, if selected, simultaneously loads both sets of
volume control with the same value. The user can also set the
LINMUTE (Register R0, Bit D7) and RINMUTE (Register R1,
Bit D7) bits to mute the line input signal to the ADC.
The mode selection is performed by writing to the FORMAT
bits of the digital audio interface register (Register R7, Bit D1
and Bit D0). All modes are MSB first and operate with data of
16 to 32 bits.
Recording Mode
On the RECDAT output pin, the digital audio interface can
send digital audio data for recording mode operation. The
digital audio interface outputs the processed internal ADC
digital filter data onto the RECDAT output. The digital audio
data stream on RECDAT comprises left- and right-channel
audio data that is time domain multiplexed.
Note that when sourcing audio data from line inputs, the maxi-
mum full-scale input of the ADC is 1.0 V rms when AVDD = 3.3 V.
Do not source any input voltage larger than full scale to avoid
overloading the ADC, which causes distortion of sound and
deterioration of audio quality. For best sound quality in line
inputs, gain should be carefully configured so that the ADC
receives a signal equal to its full scale. This maximizes the
signal-to-noise ratio for best total audio quality.
The RECLRC is the digital audio frame clock signal that
separates left- and right-channel data on the RECDAT lines.
Bypass Path to Output
The BCLK signal acts as the digital audio clock. Depending on
if the SSM2604 is in master or slave mode, the BCLK signal is
either an input or an output signal. During a recording opera-
tion, RECDAT and RECLRC must be synchronous to the BCLK
signal to avoid data corruption.
The line inputs can be routed and mixed directly to the output
terminals via the BYPASS (Register R4, Bit D3) software control
register selection. The analog input signal is routed directly to
the output terminals and is not digitally converted. The bypass
signal at the output mixer is the same level as the output of the
PGA associated with each line input.
Playback Mode
On the PBDAT input pin, the digital audio interface can receive
digital audio data for playback mode operation. The digital audio
data stream on PBDAT comprises left- and right-channel audio
data that is time domain multiplexed. The PBLRC is the digital
Line Outputs
The DAC outputs and the line inputs (the bypass path) are
summed at an output mixer.
Rev. 0 | Page 12 of 28
SSM2604
audio frame clock signal that separates left- and right-channel
data on the PBDAT lines.
SSM2604 to support the common universal serial bus (USB)
clock rate of 12 MHz, or to support 24 MHz if the CLKDIV2
control register bit is activated. The user must set the appropriate
sampling rate in the SR control bits (Register R8, Bit D2 to Bit D5).
See Table 25 and Table 26 for guidelines.
The BCLK signal acts as the digital audio clock. Depending on
if the SSM2604 is in master or slave mode, the BCLK signal is
either an input or an output signal. During a playback opera-
tion, PBDAT and PBLRC must be synchronous to the BCLK
signal to avoid data corruption.
Note that the sampling rate is generated as a fixed divider from
the MCLK signal. Because all audio processing references the
core MCLK signal, corruption of this signal, in turn, corrupts
the outgoing audio quality of the SSM2604. The BCLK/RECLRC/
RECDAT or BCLK/PBLRC/PBDAT signals must be synchronized
with MCLK in the digital audio interface circuit. MCLK must
be faster or equal to the BCLK frequency to guarantee that no
data is lost during data synchronization.
Digital Audio Data Sampling Rate
To accommodate a wide variety of commonly used DAC and
ADC sampling rates, the SSM2604 allows for two modes of
operation, normal and USB, selected by the USB bit (Register R8,
Bit D0).
In normal mode, the SSM2604 supports digital audio sampling
rates from 8 kHz to 96 kHz. Normal mode supports 256 fS and
384 fS based clocks. To select the desired sampling rate, the user
must set the appropriate sampling rate register in the SR control
bits (Register R8, Bit D2 to Bit D5) and match this selection to
the core clock frequency that is pulsed on the MCLK pin.
See Table 25 and Table 26 for guidelines.
The BCLK frequency should be greater than
Sampling Rate × Word Length × 2
Ensuring that the BCLK frequency is greater than this value
guarantees that all valid data bits are captured by the digital
audio interface circuitry. For example, if a 32 kHz digital
audio sampling rate with a 32-bit word length is desired,
BCLK ≥ 2.048 MHz.
In USB mode, the SSM2604 supports digital audio sampling
rates from 8 kHz to 96 kHz. USB mode is enabled on the
1/fS
LEFT CHANNEL
RIGHT CHANNEL
RECLRC/
PBLRC
BCLK
RECDAT/
PBDAT
1
2
3
4
N
X
X
1
2
3
N
X
X
X = DON’T CARE.
Figure 19. Left-Justified Audio Input Mode
1/fS
LEFT CHANNEL
RIGHT CHANNEL
RECLRC/
PBLRC
BCLK
RECDAT/
PBDAT
X
X
N
4
3
2
1
X
X
N
4
3
2
1
X = DON’T CARE.
Figure 20. Right-Justified Audio Input Mode
Rev. 0 | Page 13 of 28
SSM2604
1/fS
LEFT CHANNEL
RIGHT CHANNEL
RECLRC/
PBLRC
BCLK
RECDAT/
PBDAT
X
1
2
3
4
N
X
N
X
X
1
2
3
X = DON’T CARE.
Figure 21. I2S Audio Input Mode
1/fS
LEFT CHANNEL
RIGHT CHANNEL
RECLRC/
PBLRC
BCLK
1
2
3
N
1
2
3
N
X
X
X
RECDAT/
PBDAT
X = DON’T CARE.
Figure 22. DSP/Pulse Code Modulation (PCM) Mode Audio Input Submode 1 (SM1) [Bit LRP = 0]
1/fS
LEFT CHANNEL
RIGHT CHANNEL
RECLRC/
PBLRC
BCLK
X
1
2
3
N
1
2
3
N
X
X
RECDAT/
PBDAT
X = DON’T CARE.
Figure 23. DSP/PCM Mode Audio Input Submode 2 (SM2) [Bit LRP = 1]
Rev. 0 | Page 14 of 28
SSM2604
address, and Bit D8 to Bit D0 are register data for the associated
register map.
SOFTWARE CONTROL INTERFACE
The software control interface provides access to the user-
selectable control registers and can operate with a 2-wire (I2C®)
interface.
SDIN generates the serial control data-word; SCLK clocks the
serial data,
The device address for the SSM2604 is 0011010.
Within each control register is a control data-word consisting
of 16 bits, MSB first. Bit D15 to Bit D9 are the register map
SDIN
SCLK
S
P
8
9
8
9
8
9
1 TO 7
START ADDR
1 TO 7
1 TO 7
DATA
R/W
ACK
SUBADDRESS
ACK
ACK
STOP
Figure 24. 2-Wire I2C Generalized Clocking Diagram
WRITE
S
S
A7 ... A1 A0 A(S) D15 ... D9 D8 A(S) D7 ... D0 A(S)
0
P
SEQUENCE
DEVICE
ADDRESS
REGISTER
ADDRESS
REGISTER
DATA
READ
SEQUENCE
A7 ... A1 A0 A(S)
0
D15 ... D9
0
A(S)
S
A7 ... A1 A0 A(S)
1
D7 ... D0 A(M)
...
0
D8 A(M)
0
P
DEVICE
ADDRESS
REGISTER
ADDRESS
DEVICE
ADDRESS
REGISTER
DATA
(SLAVE DRIVE)
S/P = START/STOP BIT.
2
A0 = I C R/W BIT.
A(S) = ACKNOWLEDGE BY SLAVE.
A(M) = ACKNOWLEDGE BY MASTER.
A(M) = ACKNOWLEDGE BY MASTER (INVERSION).
Figure 25. I2C Write and Read Sequences
Rev. 0 | Page 15 of 28
SSM2604
TYPICAL APPLICATION CIRCUITS
AVDD VMID AGND
DVDD DGND
SSM2604
REF
PWROFF
BYPASS
ADC
ADC
DAC
DAC
RLINEIN
ROUT
LOUT
DIGITAL
PROCESSOR
ADC
DAC
LLINEIN
LINE
BYPASS
OSC
CLKOUT
CLK GEN
OSC
DIGITAL AUDIO INTERFACE
CONTROL INTERFACE
MCLK/XTI
XTO
CLKOUT
PBDAT RECDAT BCLK PBLRC RECLRC SDIN
SCLK
Figure 26. Power Management Functional Location Diagram (Control Register R6, Bit D0 to Bit D7)
+3.3V_VA
L1
B1
FB
+3,3V_VD
47uH,15mA
C1
10uF
+
+
C4
10uF
C2
0.1uF
C3
0.1uF
R1
5.6K
U1
L-LINE INPUT
C5
R2
J1
BNC
10M
NC
NC
C6
C13
1uF
R7
1uF
C7
220PF
100
17
16
12
1
LLINEIN
RLINEIN
ROUT
LOUT
J2
BNC
11
1
R3
5.6K
R8
100
10M
NC
C14
1uF
1uF
R-LINE INPUT
SSM2604
R6
47K
R5
47K
I2S[0..4]
R4
NC
C8
220PF
DACLRC
DACDAT
ADCDAT
ADCLRC
BCLK
8
7
9
10
6
PBLRC
PBDAT
RECDAT
RECLRC
BCLK
5
CLKOUT
VMID
20
18
19
15
I2C[0..1]
NC
SDIN
SCLK
SDIN
SCLK
C12
4.7uF
+
C11
0.1uF
1
2
MCLK/XTI
XTO
Y1
12.288MHz
C9
22pF
C10
22pF
CONNECTION UNDER CHIP
Figure 27. Typical Application Circuit
Rev. 0 | Page 16 of 28
SSM2604
REGISTER MAP
Table 10. Register Map
Reg. Address Name
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
R0
0x00
Left-Channel
ADC Input
Volume
LRINBOTH LINMUTE
0
LINVOL [5:0]
010010111
R1
0x01
Right-Channel RLINBOTH RINMUTE
0
RINVOL [5:0]
010010111
ADC Input
Volume
R2
R3
0x02
0x03
Reserved
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
000000000
000000000
R4
R5
R6
R7
R8
0x04
0x05
0x06
0x07
0x08
Analog Audio
Path
0
0
0
0
0
0
0
0
0
DACSEL BYPASS
0
0
0
000001000
Digital Audio
Path
0
0
0
HPOR
1
DACMU
DAC
DEEMPH
[1:0]
ADCHPF 000001000
Power
Management
PWROFF
BCLKINV
CLKOUT OSC
MS
ADC
1
LINEIN
010011111
000001010
000000000
Digital Audio
I/F
LRSWAP LRP
WL [1:0]
FORMAT [1:0]
Sampling
Rate
CLKODIV2 CLKDIV2
SR [3:0]
BOSR USB
ACTIVE
R9
0x09
0x0F
Active
0
0
0
0
0
0
0
000000000
000000000
R15
Software
Reset
RESET [8:0]
Rev. 0 | Page 17 of 28
SSM2604
REGISTER MAP DETAILS
LEFT-CHANNEL ADC INPUT VOLUME, ADDRESS 0x00
Table 11. Left-Channel ADC Input Volume Register Bit Map
D8
D7
D6
D5
D4
D3
D2
D1
D0
LRINBOTH
LINMUTE
0
LINVOL [5:0]
Table 12. Descriptions of Left-Channel ADC Input Volume Register Bits
Bit Name
Description
Settings
LRINBOTH
Left-to-right line input ADC data load control
0 = disable simultaneous loading of left-channel ADC data to right-
channel register (default)
1 = enable simultaneous loading of left-channel ADC data to right-
channel register
LINMUTE
Left-channel input mute
0 = disable mute
1 = enable mute on data path to ADC (default)
00 0000 = −34.5 dB
… 1.5 dB step up
LINVOL [5:0]
Left-channel PGA volume control
01 0111 = 0 dB (default)
… 1.5 dB step up
01 1111 = 12 dB
10 0000 = 13.5 dB
10 0001 = 15 dB
10 0010 = 16.5 dB
10 0011 = 18 dB
10 0100 = 19.5 dB
10 0101 = 21 dB
10 0110 = 22.5 dB
10 0111 = 24 dB
10 1000 = 25.5 dB
10 1001 = 27 dB
10 1010 = 28.5 dB
10 1011 = 30 dB
10 1100 = 31.5 dB
10 1101 = 33 dB
11 1111 to 10 1101 = 33 dB
Rev. 0 | Page 18 of 28
SSM2604
RIGHT-CHANNEL ADC INPUT VOLUME, ADDRESS 0x01
Table 13. Right-Channel ADC Input Volume Register Bit Map
D8
D7
D6
D5
D4
D3
D2
D1
D0
RLINBOTH
RINMUTE
0
RINVOL [5:0]
Table 14. Descriptions of Right-Channel ADC Input Volume Register Bits
Bit Name
Description
Settings
RLINBOTH
Right-to-left line input ADC data load control 0 = disable simultaneous loading of right-channel ADC data to left-
channel register (default)
1 = enable simultaneous loading of right-channel ADC data to left-
channel register
RINMUTE
Right-channel input mute
0 = disable mute
1 = enable mute on data path to ADC (default)
00 0000 = −34.5 dB
… 1.5 dB step up
RINVOL [5:0]
Right-channel PGA volume control
01 0111 = 0 dB (default)
… 1.5 dB step up
01 1111 = 12 dB
10 0000 = 13.5 dB
10 0001 = 15 dB
10 0010 = 16.5 dB
10 0011 = 18 dB
10 0100 = 19.5 dB
10 0101 = 21 dB
10 0110 = 22.5 dB
10 0111 = 24 dB
10 1000 = 25.5 dB
10 1001 = 27 dB
10 1010 = 28.5 dB
10 1011 = 30 dB
10 1100 = 31.5 dB
10 1101 = 33 dB
11 1111 to 10 1101 = 33 dB
Rev. 0 | Page 19 of 28
SSM2604
ANALOG AUDIO PATH, ADDRESS 0x04
Table 15. Analog Audio Path Register Bit Map
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
DACSEL
BYPASS
0
0
0
Table 16. Descriptions of Analog Audio Path Register Bits
Bit Name
Description
Settings
DACSEL
DAC select. Allow DAC output to be mixed at device output
terminal.
0 = do not select DAC (default)
BYPASS
Bypass select. Allow line input signal to be mixed at device
output terminal.
0 = bypass disable
DIGITAL AUDIO PATH, ADDRESS 0x05
Table 17. Digital Audio Path Register Bit Map
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
HPOR
DACMU
DEEMPH [1:0]
ADCHPF
Table 18. Descriptions of Digital Audio Path Register Bits
Bit Name
Description
Settings
HPOR
Store dc offset when high-pass filter is disabled
DAC digital mute
0 = clear offset (default)
1 = store offset
0 = no mute (signal active)
1 = mute (default)
DACMU
DEEMPH [1:0]
De-emphasis control
00 = no de-emphasis (default)
01 = 32 kHz sampling rate
10 = 44.1 kHz sampling rate
11 = 48 kHz sampling rate
ADCHPF
ADC high-pass filter control
0 = ADC high-pass filter enable (default)
1 = ADC high-pass filter disable
Rev. 0 | Page 20 of 28
SSM2604
POWER MANAGEMENT, ADDRESS 0x06
Table 19. Power Management Register Bit Map
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
PWROFF
CLKOUT
OSC
1
DAC
ADC
1
LINEIN
Table 20. Description of Power Management Register Bits
Bit Name
Description
Settings
PWROFF
Whole chip power-down control
0 = power up
1 = power down (default)
0 = power up (default)
1 = power down
0 = power up (default)
1 = power down
CLKOUT
OSC
Clock output power-down control
Crystal power-down control
DAC power-down control
DAC
0 = power up
1 = power down (default)
0 = power up
ADC
ADC power-down control
1 = power down (default)
0 = power up
LINEIN
Line input power-down control
1 = power down (default)
Power Consumption
Table 21.
AVDD
(3.3 V)
DVDD
(3.3 V)
Mode
PWROFF
CLKOUT
OSC
DAC
ADC
LINEIN
Unit
Record and Playback
Playback Only
Oscillator Enabled
External Clock
Record Only
0
0
0
0
0
0
9.41
3.7
mA
0
0
0
1
0
1
0
0
1
1
1
1
4.45
4.56
1.9
1.9
mA
mA
Line Clock
Line Oscillator
0
0
0
0
0
1
1
1
0
0
0
0
4.31
4.33
2.0
2.0
mA
mA
Analog Bypass
(Line Input or Line Output)
External Line
Internally Generated Line
Power-Down
0
0
0
0
1
1
1
1
1
1
0
0
1.88
1.88
0.21
0.25
mA
mA
External Clock
Oscillator
1
1
1
1
1
1
1
1
1
1
1
1
0.002
0.002
0.015
0.015
mA
mA
Rev. 0 | Page 21 of 28
SSM2604
DIGITAL AUDIO I/F, ADDRESS 0x07
Table 22. Digital Audio I/F Register Bit Map
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
BCLKINV
MS
LRSWAP
LRP
WL [1:0]
FORMAT [1:0]
Table 23. Descriptions of Digital Audio I/F Register Bits
Bit Name
Description
Settings
BCLKINV
BCLK inversion control
0 = BCLK not inverted (default)
1 = BCLK inverted
MS
Master mode enable
0 = enable slave mode (default)
1 = enable master mode
LRSWAP
LRP
Swap DAC data control
0 = output left- and right-channel data as normal (default)
1 = swap left- and right-channel DAC data in audio interface
0 = normal PBLRC and RECLRC (default), or DSP Submode 1
1 = invert PBLRC and RECLRC polarity, or DSP Submode 2
00 = 16 bits
Polarity control for clocks in right-justified,
left-justified, and I2S modes
WL [1:0]
Data-word length control
01 = 20 bits
10 = 24 bits (default)
11 = 32 bits
FORMAT [1:0]
Digital audio input format control
00 = right justified
01 = left justified
10 = I2S mode (default)
11 = DSP mode
SAMPLING RATE, ADDRESS 0x08
Table 24. Sampling Rate Register Bit Map
D8
D7
D6
D5
D4
D3
SR [3:0]
D2
D1
D0
0
CLKODIV2
CLKDIV2
BOSR
USB
Table 25. Descriptions of Sampling Rate Register Bits
Bit Name
Description
Settings
CLKODIV2
CLKOUT divider select
0 = CLKOUT is core clock (default)
1 = CLKOUT is core clock divided by 2
0 = core clock is MCLK (default)
1= core clock is MCLK divided by 2
See Table 26 and Table 27
CLKDIV2
Core clock divide select
SR [3:0]
BOSR
Clock setting condition
Base oversampling rate
USB mode:
0 = support for 250 fS based clock (default)
1 = support for 272 fS based clock
Normal mode:
0 = support for 256 fS based clock (default)
1 = support for 384 fS based clock
0 = normal mode enable (default)
1 = USB mode enable
USB
USB mode select
Rev. 0 | Page 22 of 28
SSM2604
Table 26. Sampling Rate Lookup Table, USB Disabled (Normal Mode)
MCLK
(CLKDIV2 = 0)
MCLK
(CLKDIV2 = 1)
ADC Sampling Rate
(RECLRC)
DAC Sampling Rate
(PBLRC)
BCLK
USB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SR [3:0]
0011
0010
0100
0101
1110
0110
0001
0000
0111
1011
1010
1100
1101
1001
1000
1111
0011
0010
0100
0101
1110
0110
0000
0001
0111
1011
1010
1100
1101
1001
1000
1111
BOSR
0
(MS = 1)1
12.288 MHz
24.576 MHz
8 kHz (MCLK/1536)
8 kHz (MCLK/1536)
12 kHz (MCLK/1024)
16 kHz (MCLK/768)
24 kHz (MCLK/512)
32 kHz (MCLK/384)
48 kHz (MCLK/256)
48 kHz (MCLK/256)
96 kHz (MCLK/128)
8.0182 kHz (MCLK/1408)
8.0182 kHz (MCLK/1408)
11.025 kHz (MCLK/1024)
22.05 kHz (MCLK/512)
44.1 kHz (MCLK/256)
44.1 kHz (MCLK/256)
88.2 kHz (MCLK/128)
8 kHz (MCLK/2304)
8 kHz (MCLK/2304)
12 kHz (MCLK/1536)
16 kHz (MCLK/1152)
24 kHz (MCLK/768)
32 kHz (MCLK/576)
48 kHz (MCLK/384)
48 kHz (MCLK/384)
96 kHz (MCLK/192)
8.0182 kHz (MCLK/2112)
8.0182 kHz (MCLK/2112)
11.025 kHz (MCLK/1536)
22.05 kHz (MCLK/768)
44.1 kHz (MCLK/384)
44.1 kHz (MCLK/384)
88.2 kHz (MCLK/192)
8 kHz (MCLK/1536)
48 kHz (MCLK/256)
12 kHz (MCLK/1024)
16 kHz (MCLK/768)
24 kHz (MCLK/512)
32 kHz (MCLK/384)
8 kHz (MCLK/1536)
48 kHz (MCLK/256)
96 kHz (MCLK/128)
8.0182 kHz (MCLK/1408)
44.1 kHz (MCLK/256)
11.025 kHz (MCLK/1024)
22.05 kHz (MCLK/512)
8.0182 kHz (MCLK/1408)
44.1 kHz (MCLK/256)
88.2 kHz (MCLK/128)
8 kHz (MCLK/2304)
48 kHz (MCLK/384)
12 kHz (MCLK/1536)
16 kHz (MCLK/1152)
24 kHz (MCLK/768)
32 kHz (MCLK/576)
48 kHz (MCLK/384)
8 kHz (MCLK/2304)
96 kHz (MCLK/192)
8.0182 kHz (MCLK/2112)
44.1 kHz (MCLK/384)
11.025 kHz (MCLK/1536)
22.05 kHz (MCLK/768)
8.0182 kHz (MCLK/2112)
44.1 kHz (MCLK/384)
88.2 kHz (MCLK/192)
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/2
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/2
MCLK/6
MCLK/6
MCLK/6
MCLK/6
MCLK/6
MCLK/6
MCLK/6
MCLK/6
MCLK/3
MCLK/6
MCLK/6
MCLK/6
MCLK/6
MCLK/6
MCLK/6
MCLK/3
0
0
0
0
0
0
0
0
11.2896 MHz
22.5792 MHz
0
0
0
0
0
0
0
18.432 MHz
36.864 MHz
1
1
1
1
1
1
1
1
1
16.9344 MHz
33.8688 MHz
1
1
1
1
1
1
1
1 BCLK frequency is for master mode and slave right-justified mode only.
Rev. 0 | Page 23 of 28
SSM2604
Table 27. Sampling Rate Lookup Table, USB Enabled (USB Mode)
MCLK
(CLKDIV2 = 0)
MCLK
(CLKDIV2 = 1)
ADC Sampling Rate
(RECLRC)
DAC Sampling Rate
(PBLRC)
BCLK
USB
1
SR [3:0]
0011
0010
1011
1010
1100
1000
1010
1101
1110
0110
1001
1000
0001
0000
1111
0111
BOSR
(MS = 1)1
12.000 MHz
24.000 MHz
8 kHz (MCLK/1500)
8 kHz (MCLK/1500)
0
0
1
1
1
0
0
1
0
0
1
1
0
0
1
0
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
8 kHz (MCLK/1500)
48 kHz (MCLK/250)
1
8.0214 kHz (MCLK/1496)
8.0214 kHz (MCLK/1496)
11.0259 kHz (MCLK/1088)
12 kHz (MCLK/1000)
16 kHz (MCLK/750)
8.0214 kHz (MCLK/1496)
44.118 kHz (MCLK/272)
11.0259 kHz (MCLK/1088)
12 kHz (MCLK/1000)
16 kHz (MCLK/750)
1
1
1
1
1
22.0588 kHz (MCLK/544)
24 kHz (MCLK/500)
22.0588 kHz (MCLK/544)
24 kHz (MCLK/500)
1
1
32 kHz (MCLK/375)
32 kHz (MCLK/375)
1
44.118 kHz (MCLK/272)
44.118 kHz (MCLK/272)
48 kHz (MCLK/250)
8.0214 kHz (MCLK/1496)
44.118 kHz (MCLK/272)
8 kHz (MCLK/1500)
1
1
1
48 kHz (MCLK/250)
48 kHz (MCLK/250)
1
88.235 kHz (MCLK/136)
96 kHz (MCLK/125)
88.235 kHz (MCLK/136)
96 kHz (MCLK/125)
1
1
1 BCLK frequency is for master mode and slave right-justified mode only.
Rev. 0 | Page 24 of 28
SSM2604
ACTIVE, ADDRESS 0x09
Table 28. Active Register Bit Map
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
ACTIVE
Table 29. Descriptions of Active Register Bit
Bit Name
Description
Settings
ACTIVE
Digital core activation control
0 = disable digital core (default)
1 = activate digital core
SOFTWARE RESET, ADDRESS 0x0F
Table 30. Software Reset Register Bit Map
D8
D7
D6
D5
D4
D3
D2
D1
D0
RESET [8:0]
Table 31. Descriptions of Software Reset Register Bits
Bit Name
Description
Settings
0 = reset (default)
RESET [8:0]
Write all 0s to this register to set all registers to their default settings. Other data written
to this register has no effect.
Rev. 0 | Page 25 of 28
SSM2604
OUTLINE DIMENSIONS
0.60 MAX
4.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
15
16
20
1
5
0.50
BSC
2.65
2.50 SQ
2.35
PIN 1
INDICATOR
3.75
BSC SQ
EXPOSED
PAD
(BOTTOM VIEW)
10
11
6
0.50
0.40
0.30
0.25 MIN
TOP VIEW
0.80 MAX
0.65 TYP
12° MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
1.00
0.85
0.80
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SECTION OF THIS DATA SHEET.
0.30
0.23
0.18
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
Figure 28. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-20-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
SSM2604CPZ-R21
SSM2604CPZ-REEL1
SSM2604CPZ-REEL71
SSM2604-EVALZ1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
CP-20-4
CP-20-4
20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
CP-20-4
1 Z = RoHS Compliant Part.
Rev. 0 | Page 26 of 28
SSM2604
NOTES
Rev. 0 | Page 27 of 28
SSM2604
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06978-0-7/08(0)
Rev. 0 | Page 28 of 28
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