SSM3302ACPZ [ADI]
2 ×10 W Filterless Class-D; 2 × 10瓦无滤波器D类
| 型号： | SSM3302ACPZ |
| 厂家： | 
ADI |
| 描述： | 2 ×10 W Filterless Class-D |
| 文件： | 总20页 (文件大小：1111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2 ×10 W Filterless Class-D
Stereo Audio Amplifier
SSM3302
Data Sheet
load or with 82% efficiency at 10 W into 4 Ω from a 12 V supply,
and it has an SNR of >98 dB.
FEATURES
Filterless stereo Class-D amplifier with Σ-Δ modulation
2 × 10 W into 4 Ω load and 2 × 8 W into 8 Ω load at 12 V supply
with <1% total harmonic distortion plus noise (THD + N)
91% efficiency at 12 V, 8 W into 8 Ω speaker
98 dB signal-to-noise ratio (SNR)
Single-supply operation from 7 V to 18 V
Flexible gain adjustment pin from 9 dB to 24 dB
Fixed input impedance of 40 kΩ
Mono output mode pin for 1 × 20 W output power into 2 Ω
10 µA shutdown current
Short-circuit and thermal protection
Available in a 40-lead, 6 mm × 6 mm LFCSP
Pop-and-click suppression
Spread spectrum pulse density modulation (PDM) is used to
provide lower EMI radiated emissions compared with other
Class-D architectures. The SSM3302 includes an optional
modulation select pin (ultralow EMI emission mode) that
significantly reduces the radiated emissions at the Class-D
outputs, particularly above 100 MHz. The SSM3302 can pass
FCC Class-B emissions testing with an unshielded 20 inch cable
using common-mode choke-based filtering.
The fully differential input of the SSM3302 provides excellent
rejection of common-mode noise on the input. The device also
includes a highly flexible gain select pin that only requires one
series resistor to choose a gain between 9 dB and 24 dB, with no
change to the input impedance. The benefit of this is to improve
gain matching between multiple SSM3302 devices within a single
application compared with using external resistors to set gain.
User-selectable ultralow EMI emissions mode
Thermal warning indicator
Power-on reset
APPLICATIONS
The SSM3302 includes an integrated voltage regulator that
generates a 5 V rail.
Mobile computing
Flat panel televisions
Media docking stations
Portable electronics
Sound bars
The SSM3302 has a micropower shutdown mode with a typical
shutdown current of 10 µA. Shutdown is enabled by applying a
SD
logic low to the
pin. The device also includes pop-and-click
suppression circuitry that minimizes voltage glitches at the output
during turn on and turn off, reducing audible noise during
activation and deactivation.
GENERAL DESCRIPTION
The SSM3302 is a fully integrated, high efficiency, stereo Class-D
audio amplifier. The application circuit requires minimal external
components and operates from a single 7 V to 18 V supply. The
device is capable of delivering 2 × 10 W of continuous output
power into a 4 Ω load (or 2 × 8 W into 8 Ω) with <1% THD + N
from a 12 V supply. In addition, while mono mode is activated,
the user can drive a load as small as 2 Ω up to 20 W continuous
output power by stacking the stereo output terminals.
Other included features to simplify system level integration of
the SSM3302 are input low-pass filtering to suppress out-of-
band DAC noise interference to the pulse density modulator,
fixed input impedance to simplify component selection across
multiple platform production builds, and a thermal warning
indicator pin.
The SSM3302 is specified over the commercial temperature
range (−40°C to +85°C). It has built-in thermal shutdown and
output short-circuit protection. It is available in a halide-free,
40-lead, 6 mm × 6 mm lead frame chip scale package (LFCSP).
The SSM3302 features a high efficiency, low noise modulation
scheme that requires no external LC output filters. This scheme
continues to provide high efficiency even at low output power.
The SSM3302 operates with 90% efficiency at 7 W into an 8 Ω
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2012 Analog Devices, Inc. All rights reserved.
SSM3302
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Analog Supply............................................................................. 16
Gain Selection............................................................................. 16
Amplifier Protection.................................................................. 16
Pop-and-Click Suppression ...................................................... 16
EMI Noise.................................................................................... 16
Mono Mode................................................................................. 16
Output Modulation Description .............................................. 17
Layout .......................................................................................... 17
Input Capacitor Selection.......................................................... 17
Bootstrap Capacitors.................................................................. 17
Power Supply Decoupling ......................................................... 18
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 19
Applications....................................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Typical Application Circuits.......................................................... 14
Applications Information .............................................................. 16
Overview...................................................................................... 16
REVISION HISTORY
2/12—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
Data Sheet
SSM3302
FUNCTIONAL BLOCK DIAGRAM
PVDD
THERM
SSM3302
BOOTR+
40kΩ
OUTR+
INR+
GAIN
CONTROL
MODULATOR
FET
DRIVER
40kΩ
(Σ-∆)
INR–
OUTR–
BOOTR–
BIAS
SDNR
EDGE
INTERNAL
OSCILLATOR
EDGE
CONTROL
MONO
BIAS
BOOTL+
SDNL
40kΩ
OUTL+
INL+
GAIN
CONTROL
MODULATOR
FET
DRIVER
40kΩ
(Σ-∆)
INL–
OUTL–
BOOTL–
VREG
AGND
VREG
(AVDD)
REGEN
PGND
GAIN
Figure 1.
Rev. 0 | Page 3 of 20
SSM3302
Data Sheet
SPECIFICATIONS
PVDD = 12 V, TA = 25oC, RL = 8 Ω + 64 μH, EDGE = AGND, gain = 9 dB, VREG = off, unless otherwise noted.
Table 1.
Parameter
Symbol Test Conditions/Comments
PO RL = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, PVDD = 15 V
Min
Typ
Max
Unit
DEVICE CHARACTERISTICS
Output Power/Channel
121
8
2.7
151
10
3.2
201
131
4.8
241
161
5.7
292
W
W
W
W
W
W
W
W
W
W
W
W
W
RL = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, PVDD = 12 V
RL = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, PVDD = 7 V
RL = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, PVDD = 15 V
RL = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, PVDD = 12 V
RL = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, PVDD = 7 V
RL = 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, PVDD = 15 V
RL = 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, PVDD = 12 V
RL = 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, PVDD = 7 V
RL = 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, PVDD = 15 V
RL = 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, PVDD = 12 V
RL = 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, PVDD = 7 V
RL = 2 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, PVDD = 12 V
(mono mode)
RL = 2 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, PVDD = 7 V
(mono mode)
RL = 2 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, PVDD = 12 V
(mono mode)
RL = 2 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, PVDD = 7 V
(mono mode)
9.42
W
W
W
36.62
12.72
Efficiency
η
PO = 7 W, 8 Ω, PVDD = 12 V, EDGE = low (normal operation)
PO = 7 W, 8 Ω, PVDD = 12 V, EDGE = AVDD (ultralow
EMI mode)
91.5
82
%
%
Total Harmonic
Distortion + Noise
Input Common-Mode
Voltage Range
THD + N PO = 5 W into 8 Ω, f = 1 kHz, PVDD = 12 V
0.01
%
V
VCM
1.0
AVDD − 1
Common-Mode
Rejection Ratio
Channel Separation
Average Switching
Frequency
CMRR
VCM = 2.5 V 100 mV at 1 kHz, output referred
PO = 0.5 W, f = 1 kHz
43
dB
XTALK
fSW
80
300
dB
kHz
Differential Output
Offset Voltage
VOOS
Gain = 9 dB
3.0
18
mV
POWER SUPPLY
Supply Voltage Range
PVDD
Guaranteed from PSRR test
7
V
Power Supply Rejection
Ratio
PSRRDC
PVDD = 7 V to 15 V, dc input floating
70
dB
PSRRAC
ISYPVDD
VRIPPLE = 100 mV at 1 kHz, inputs are ac grounded, CIN = 0.1 μF
VIN = 0 V, load = 8 Ω + 68 μH, PVDD = 15 V, VREGEN = AVDD
(internal VREG active)
80
12.2
dB
mA
Supply Current (Stereo)
VIN = 0 V, load = 8 Ω + 68 μH, PVDD = 15 V, VREGEN = AGND
(internal VREG disabled)
VIN = 0 V, load = 8 Ω + 68 μH, PVDD = 12 V, VREGEN = AGND
(internal VREG disabled)
VIN = 0 V, load = 8 Ω + 68 μH, PVDD = 7 V, VREGEN = AGND
(internal VREG disabled)
6.2
5
mA
mA
mA
3
Rev. 0 | Page 4 of 20
Data Sheet
SSM3302
Parameter
Symbol Test Conditions/Comments
ISYAVDD
VIN = 0 V, load = 8 Ω + 68 μH, PVDD = 15 V, VREGEN = AGND
Min
Typ
Max
Unit
5.85
mA
(internal VREG disabled)
VIN = 0 V, load = 8 Ω + 68 μH, PVDD = 12 V, VREGEN = AGND
(internal VREG disabled)
VIN = 0 V, load = 8 Ω + 68 μH, PVDD = 7 V, VREGEN = AGND
(internal VREG disabled)
5.8
5.6
10
mA
mA
μA
Shutdown Current
ISD
SD = AGND
ANALOG SUPPLY
External Supply Voltage
On-Board Regulator
Regulator Current
Regulator Power Supply
Rejection
AVDD
VVREG
IVREG
Permissible range for external AVDD, VREGEN = AGND
4.5
5.5
V
V
mA
dB
5
20
70
PSRRVREG
GAIN CONTROL
Closed-Loop Voltage Gain AV
See Table 5 for gain options
9
24
dB
kΩ
Input Impedance
SHUTDOWN CONTROL
Input Voltage High
Input Voltage Low
Turn-On Time
ZIN
40
VIH
VIL
tWU
tSD
1.35
V
V
ms
μs
kΩ
0.35
SD rising edge from AGND to AVDD
SD falling edge from AVDD to AGND
SD = GND
40
Turn-Off Time
500
56
Output Impedance
ZOUT
AMPLIFIER PROTECTION
Overcurrent Threshold
IOC
6
A
Overtemperature
Warning
TWARN
120
°C
Overtemperature
Shutdown
Recovery Temperature
NOISE PERFORMANCE
Output Voltage Noise
TSD
145
85
°C
°C
TREC
en
PVDD = 12 V, f = 20 Hz to 20 kHz, inputs are ac grounded,
gain = 9 dB, A-weighted
PO = 10 W, RL = 8 Ω
100
98
μV rms
dB
Signal-to-Noise Ratio
SNR
1 Although the SSM3302 has good audio quality above 2 × 10 W into 4 Ω, continuous output power beyond 2 × 10 W into 4 Ω must be avoided due to device packaging
limitations.
2 Mono mode. Output power beyond 20 W needs special care for thermally considered printed circuit board (PCB) design.
Rev. 0 | Page 5 of 20
SSM3302
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at 25°C, unless otherwise noted.
THERMAL RESISTANCE
θJA (junction to air) is specified for the worst-case conditions,
that is, a device soldered in a circuit board for surface-mount
packages. θJA and θJC are determined according to JESD51-9 on
a 4-layer printed circuit board (PCB) with natural convection
cooling.
Table 2.
Parameter
Power Supply Voltage (PVDD)
Analog Supply Voltage (AVDD)
Input Voltage
Rating
−0.3 V to +25 V
−0.3 V to +6 V
−0.3 V to +6 V
4 kV
−65°C to +150°C
−40°C to +85°C
−65°C to +165°C
300°C
ESD Susceptibility
Table 3. Thermal Resistance
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 60 sec)
Package Type
θJA
θJC
Unit
40-Lead, 6 mm × 6 mm LFCSP
31
2.5
°C/W
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 6 of 20
Data Sheet
SSM3302
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BOOTL+
OUTL+
1
2
3
4
5
6
7
8
9
30 BOOTR+
29 OUTR+
28 OUTR+
27 OUTR–
26 OUTR–
25 BOOTR–
24 AGND
OUTL+
SSM3302
TOP VIEW
(Not to Scale)
OUTL–
OUTL–
BOOTL–
AGND
VREG/AVDD
SDNL
23 REGEN
22
SDNR
EDGE 10
21 GAIN
NOTES
1. USE MULTIPLE VIAS TO CONNECT THE EXPOSED PAD
TO THE GROUND PLANE.
2. PINS LABELED NC CAN BE ALLOWED TO FLOAT,
BUT IT IS BETTER TO CONNECT THESE PINS TO
GROUND. AVOID ROUTING HIGH SPEED SIGNALS
THROUGH THESE PINS BECAUSE NOISE COUPLING
MAY RESULT.
Figure 2. Pin Configuration (Top Side View)
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
BOOTL+
OUTL+
Description
1
Bootstrap Input/Output for Left Channel, Noninverting Output.
Noninverting Output for Left Channel.
2, 3
4, 5
OUTL−
Inverting Output for Left Channel.
6
BOOTL−
AGND
VREG/AVDD
SDNL
Bootstrap Input/Output for Left Channel, Inverting Output.
Analog Ground.
5 V Regulator Output (if REGEN = high)/AVDD Input (if REGEN = low).
Shutdown, Left Channel. Active low digital input.
Edge Control (Low Emission Mode). Active high digital input.
Noninverting Input for Left Channel.
7
8
9
10
11
12
13, 18
EDGE
INL+
INL−
NC
Inverting Input for Left Channel.
This pin is not connected internally (see Figure 2).
14, 15
16
TEST
Test Pins. Tie to AGND.
MONO
Mono Output Mode Enable.
17
THERM
INR−
Overtemperature Warning (Open Collector).
Inverting Input for Right Channel.
19
20
INR+
Noninverting Input for Right Channel.
Gain Select from 9 dB to 24 dB.
21
GAIN
22
SDNR
Shutdown, Right Channel. Active low digital input.
5 V Regulator Enable, Active High.
23
REGEN
AGND
BOOTR−
OUTR−
OUTR+
BOOTR+
24
Analog Ground.
25
Bootstrap Input/Output for Right Channel, Inverting Output.
Inverting Output for Right Channel.
26, 27
28, 29
30
Noninverting Output for Right Channel.
Bootstrap Input/Output for Right Channel, Noninverting Output.
Power Stage Ground.
31, 32, 33, 38, 39, 40 PGND
34, 35, 36, 37
PVDD
Power Stage Power Supply.
Exposed Pad
Thermal Exposed Pad. Use multiple vias to connect this pad to the ground plane.
Rev. 0 | Page 7 of 20
SSM3302
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise stated, all data at PVDD = 12 V, EDGE = low, MONO = low, REGEN = high, and GAIN = 9 dB.
100
10
1
100
R
= 8Ω + 33µH
R = 8Ω + 33µH
L
GAIN = 9dB
PVDD = 12V
L
GAIN = 9dB
EDGE = LOW
PVDD = 7V
10
PVDD = 12V
1
0.1
PVDD = 18V
EDGE = HIGH
0.1
EDGE = LOW
0.01
0.01
0.001
0.0001
0.001
0.001
0.01
0.1
1
10
100
1µ
0.01m 0.1m
1m
10m 100m
1
10
100
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 3. THD + N vs. Output Power into 8 Ω;
PVDD = 7 V, PVDD = 12 V, PVDD = 18 V
Figure 6. THD + N vs. Output Power into 8 Ω;
EDGE = High, EDGE = Low
100
10
100
10
R
= 4Ω + 15µH
R
= 4Ω + 15µH
L
L
PVDD = 7V
GAIN = 9dB
EDGE = LOW
GAIN = 9dB
PVDD = 12V
PVDD = 18V
1
0.1
1
0.1
EDGE = HIGH
EDGE = LOW
0.01
0.01
0.001
0.0001
0.001
0.001
0.01
0.1
1
10
100
1µ
0.01m 0.1m
1m
10m 100m
1
10
100
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 4. THD + N vs. Output Power into 4 Ω;
PVDD = 7 V, PVDD = 12 V, PVDD = 18 V
Figure 7. THD + N vs. Output Power into 4 Ω;
EDGE = High, EDGE = Low
100
10
100
10
R
= 2Ω + 7.5µH
R
= 2Ω + 7.5µH
L
PVDD = 7V
L
GAIN = 9dB
GAIN = 9dB
PVDD = 12V
1
1
EDGE = LOW
PVDD = 18V
0.1
0.1
EDGE = HIGH
0.01
0.001
0.0001
0.01
0.001
0.0001
1µ
0.01m 0.1m
1m
10m 100m
1
10
100
1µ
0.01m 0.1m
1m
10m 100m
1
10
100
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 5. THD + N vs. Output Power into 2 Ω;
Mono Mode; Gain = 9 dB; PVDD = 7 V, PVDD = 12 V, 1 PVDD = 8 V
Figure 8. THD + N vs. Output Power into 2 Ω;
EDGE = High, EDGE = Low
Rev. 0 | Page 8 of 20
Data Sheet
SSM3302
100
100
10
PVDD = 7V
PVDD = 12V
R = 8Ω + 33µH
L
GAIN = 9dB
R
= 8Ω + 33µH
L
GAIN = 9dB
EDGE = LOW
10
1
EDGE = LOW
P
= 2.5W
O
P = 7.5W
O
1
0.1
0.1
P
= 2.5W
O
P
= 0.25W
O
0.01
0.01
P
= 0.5W
1k
P
= 5W
O
O
0.001
0.001
10
100
10k
100k
100k
100k
10
100
1k
FREQUENCY (Hz)
10k
100k
FREQUENCY (Hz)
Figure 9. THD + N vs. Frequency;
RL = 8 Ω; PVDD = 7 V; PO = 0.25 W, PO = 0.5 W, PO = 2.5 W
Figure 12. THD + N vs. Frequency;
RL = 8 Ω; PVDD = 12 V; PO = 2.5 W, PO = 5 W, PO = 7.5 W
100
10
100
10
PVDD = 7V
PVDD = 12V
R
= 4Ω + 15µH
R = 4Ω + 15µH
L
L
GAIN = 9dB
GAIN = 9dB
EDGE = LOW
EDGE = LOW
P
= 5W
O
1
0.1
1
0.1
P
= 0.5W
O
P = 5W
O
P
= 2.5W
O
0.01
0.01
P
= 2.5W
O
P
= 10W
O
0.001
0.001
10
100
1k
FREQUENCY (Hz)
10k
10
100
1k
FREQUENCY (Hz)
10k
100k
Figure 10. THD + N vs. Frequency;
RL = 4 Ω; PVDD = 7 V; PO = 0.5 W, PO = 2.5 W, PO = 5 W
Figure 13. THD + N vs. Frequency;
RL = 4 Ω; PVDD = 12 V; PO = 2.5 W, PO = 5 W, PO = 10 W
100
10
100
10
PVDD = 7V
PVDD = 12V
R
= 2Ω + 7.5µH
R = 4Ω + 7.5µH
L
L
GAIN = 9dB
EDGE = 0V
MONO = 5V
GAIN = 9dB
EDGE = LOW
MONO = 5V
P
= 3.5W
O
1
0.1
1
0.1
P
= 0.5W
O
P = 0.5W
O
P
= 2.5W
O
0.01
0.01
P
= 2.5W
O
P
= 5W
O
0.001
0.001
10
100
1k
FREQUENCY (Hz)
10k
10
100
1k
FREQUENCY (Hz)
10k
100k
Figure 11. THD + N vs. Frequency;
RL = 2 Ω; Mono Mode; PVDD = 7 V; PO = 0.5 W, PO = 2.5 W, PO = 3.5 W
Figure 14. THD + N vs. Frequency;
RL = 2 Ω; Mono Mode; PVDD = 12 V; PO = 0.5 W, PO = 2.5 W, PO = 5 W
Rev. 0 | Page 9 of 20
SSM3302
Data Sheet
100
16
14
PVDD = 18V
= 8Ω + 33µH
GAIN = 9dB
NO LOAD
R
L
10
1
EDGE = LOW
8Ω + 33µH
12
10
8
4Ω + 15µH
0.1
6
P
= 5W
O
P
= 2.5W
O
4
0.01
2
P
= 10W
O
0
0.001
7
8
9
10
11
12
13
14
15
16
17
18
10
100
1k
FREQUENCY (Hz)
10k
100k
100k
100k
SUPPLY VOLTAGE (V)
Figure 18. Quiescent Current vs. Supply Voltage,
RL = 8 Ω + 33 μH, No Load, , RL = 4 Ω + 15 μH
Figure 15. THD + N vs. Frequency;
RL = 8 Ω; PVDD = 18 V; PO = 2.5 W, PO = 5 W, PO = 10 W
16
14
100
10
PVDD = 18V
= 4Ω + 15µH
GAIN = 9dB
EDGE = 0
NO LOAD
R
L
12
10
8
4Ω + 15µH
1
0.1
2Ω + 7.5µH
6
P
= 5W
O
P
= 10W
O
4
0.01
2
P
= 2.5W
O
0
0.001
7
8
9
10
11
12
13
14
15
16
17
18
10
100
1k
FREQUENCY (Hz)
10k
SUPPLY VOLTAGE (V)
Figure 16. THD + N vs. Frequency;
RL = 4 Ω; PVDD = 18 V; PO = 2.5 W, PO = 5 W, PO = 10 W
Figure 19. Quiescent Current vs. Supply Voltage,
Mono Mode, No Load, RL = 4 Ω + 15 μH, RL = 2 Ω + 7.5 μH
100
10
25
20
15
10
5
PVDD = 18V
= 2Ω + 7.5µH
GAIN = 9dB
EDGE = 0
MONO = 5V
R = 8Ω + 33µH
L
GAIN = 9dB
EDGE = 0
R
L
1
0.1
THD = 10%
P
= 0.5W
O
P
= 5W
O
THD + N = 1%
0.01
P
= 2.5W
O
0
0.001
7
9
11
13
15
17
10
100
1k
FREQUENCY (Hz)
10k
SUPPLY VOLTAGE (V)
Figure 20. Maximum Output Power vs. Supply Voltage;
RL = 8 Ω; THD + N = 1%, THD + N = 10%
Figure 17. THD + N vs. Frequency;
RL = 2 Ω; Mono Mode; PVDD = 18 V; PO = 0.5 W, PO = 2.5 W, PO = 5 W
Rev. 0 | Page 10 of 20
Data Sheet
SSM3302
30
800
700
600
500
400
300
200
100
0
R
= 4Ω + 15µH
L
GAIN = 9dB
EDGE = 0
25
20
15
10
5
PVDD = 7V
THD = 10%
PVDD = 12V
THD + N = 1%
PVDD = 18V
R
= 4Ω + 15µH
GAIN = 9dB
REGEN = 5V
L
0
7
8
9
10
11
12
13
14
15
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
40
30
SUPPLY VOLTAGE (V)
OUTPUT POWER (W)
Figure 21. Maximum Output Power vs. Supply Voltage;
RL = 4 Ω; THD + N = 1%, THD + N = 10%
Figure 24. Supply Current vs. Output Power into 4 Ω;
PVDD = 7 V, PVDD = 12 V, PVDD = 18 V
60
3500
3000
2500
2000
1500
1000
500
R
= 2Ω + 7.5µH
L
GAIN = 9dB
EDGE = 0
MONO
50
40
30
20
10
0
PVDD = 12V
PVDD = 7V
THD = 10%
THD = 1%
PVDD = 18V
R
= 2Ω + 7.5µH
GAIN = 9dB
REGEN = 5V
L
0
7
9
11
13
15
17
0
5
10
15
20
25
30
35
SUPPLY VOLTAGE (V)
OUTPUT POWER (W)
Figure 22. Maximum Output Power vs. Supply Voltage;
RL = 2 Ω; Mono Mode; THD + N = 1%, THD + N = 10%
Figure 25. Supply Current vs. Output Power into 2 Ω;
Mono Mode; PVDD = 7 V, PVDD = 12 V, PVDD = 18 V
800
700
600
500
400
300
200
100
0
100
90
PVDD =7V
80
PVDD = 7V
PVDD = 18V
PVDD = 12V
70
60
50
40
30
20
10
0
PVDD = 12V
PVDD = 18V
R
= 8Ω + 33µH
GAIN = 9dB
EDGE = LOW
R
= 8Ω + 33µH
L
L
GAIN = 9dB
REGEN = 5V
0
5
10
15
20
25
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 26. Efficiency vs. Output Power into 8 Ω;
PVDD = 7 V, PVDD = 12 V, PVDD = 18 V
Figure 23. Supply Current vs. Output Power into 8 Ω;
PVDD = 7 V, PVDD = 12 V, PVDD = 18 V
Rev. 0 | Page 11 of 20
SSM3302
Data Sheet
100
100
90
80
70
60
50
40
30
20
10
0
PVDD = 7V
90
80
70
60
50
40
30
20
10
0
EDGE = LOW
EDGE = HIGH
PVDD = 18V
PVDD = 12V
R
= 4Ω + 15µH
L
GAIN = 9dB
EDGE = LOW
0
0
0
5
10
15
20
25
30
40
30
0
5
10
15
20
25
30
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 27. Efficiency vs. Output Power into 4 Ω;
PVDD = 7 V, PVDD = 12 V, PVDD = 18 V
Figure 30. Efficiency vs. Output Power into 4 Ω;
PVDD = 12 V; EDGE = High, EDGE = Low
100
90
100
90
PVDD = 7V
EDGE = LOW
80
80
EDGE = HIGH
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
PVDD = 18V
PVDD = 12V
R
= 2Ω + 7.5µH
L
GAIN = 9dB
EDGE = LOW
5
10
15
20
25
30
35
0
5
10
15
20
25
30
35
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 28. Efficiency vs. Output Power into 2 Ω;
Mono Mode; PVDD = 7 V, PVDD = 12 V, PVDD = 18 V
Figure 31. Efficiency vs. Output Power into 2 Ω;
Mono Mode; PVDD = 12 V; EDGE = High, EDGE = Low
100
90
80
70
60
50
40
30
20
10
0
0
EDGE = LOW
–10
EDGE = HIGH
–20
–30
–40
–50
–60
–70
–80
5
10
15
20
25
20
200
2,000
20,000
OUTPUT POWER (W)
FREQUENCY (Hz)
Figure 29. Efficiency vs. Output Power into 8 Ω;
PVDD = 12 V; EDGE = High, EDGE = Low
Figure 32. CMRR vs. Frequency, VRIPPLE = 100 mV rms, AC-Coupled
Rev. 0 | Page 12 of 20
Data Sheet
SSM3302
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 33. PSRR vs. Frequency, VRIPPLE = 100 mV rms
Figure 35. Turn-On Response
SDNL SDNR
Pin Rising Edge and Output)
(Showing
Pin or
0
–20
–40
–60
–80
–100
–120
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 36. Turn-Off Response
SDNL SDNR
Pin Falling Edge and Output)
Figure 34. Crosstalk vs. Frequency,
PO = 0.5 W, RL = 8 Ω
(Showing
Pin or
Rev. 0 | Page 13 of 20
SSM3302
Data Sheet
TYPICAL APPLICATION CIRCUITS
PV
7V TO 18V
DD
470µF
10µF
2× 1µF
OVERTEMPERATURE
WARNING
PVDD
THERM
SSM3302
BOOTR+
0.22µF
0.1µF
0.1µF
40kΩ
40kΩ
OUTR+
INR+
INR–
RIGHT INPUT+
RIGHT INPUT–
GAIN
CONTROL
MODULATOR
FET
DRIVER
(Σ-∆)
OUTR–
BOOTR–
0.22µF
BIAS
SHUTDOWN – RIGHT
SDNR
EDGE
INTERNAL
OSCILLATOR
EDGE
CONTROL
EMISSION
CONTROL
MONO
SHUTDOWN – LEFT
BIAS
BOOTL+
SDNL
INL+
0.22µF
0.22µF
0.1µF
0.1µF
40kΩ
40kΩ
OUTL+
LEFT INPUT+
LEFT INPUT–
GAIN
CONTROL
MODULATOR
FET
DRIVER
(Σ-∆)
INL–
OUTL–
BOOTL–
VREG
AGND
VREG/
AVDD
REGEN
PGND
GAIN
R
5V
GAIN
GAIN SELECT
2.2µF
GAIN = 9dB, 12dB, 15dB, 18dB, or 24dB
REGULATOR
ENABLE
Figure 37. Stereo Mode Configuration
Rev. 0 | Page 14 of 20
Data Sheet
SSM3302
PV
7V TO 18V
DD
470µF
10µF
2× 1µF
OVERTEMPERATURE
WARNING
PVDD
THERM
SSM3302
BOOTR+
0.22µF
0.22µF
40kΩ
40kΩ
OUTR+
INR+
INR–
GAIN
CONTROL
MODULATOR
FET
DRIVER
(Σ-∆)
OUTR–
BOOTR–
BIAS
SDNR
AVDD
EDGE
INTERNAL
OSCILLATOR
EDGE
CONTROL
EMISSION
CONTROL
MONO
SHUTDOWN
BIAS
BOOTR+
SDNL
INL+
0.22µF
0.22µF
0.1µF
0.1µF
40kΩ
40kΩ
OUTR+
INPUT+
INPUT–
GAIN
CONTROL
MODULATOR
FET
DRIVER
(Σ-∆)
INL–
OUTR–
BOOTR–
VREG
AGND
VREG/
AVDD
REGEN
PGND
GAIN
R
5V
GAIN
GAIN SELECT
2.2µF
GAIN = 9dB, 12dB, 15dB, 18dB, or 24dB
REGULATOR
ENABLE
Figure 38. Mono Mode Configuration
Rev. 0 | Page 15 of 20
SSM3302
Data Sheet
APPLICATIONS INFORMATION
OVERVIEW
AMPLIFIER PROTECTION
The SSM3302 includes protection circuitry to prevent damage
in case of overcurrent and overtemperature conditions. Shorts
across the output terminals, or between either terminal and
PVDD or PGND, are also detected; in this case, the output
transistors do not switch until the fault is removed.
The SSM3302 stereo Class-D audio amplifier features a filterless
modulation scheme that greatly reduces the external component
count, conserving board space and reducing system cost. The
SSM3302 does not require an output filter; it relies on the inherent
inductance of the speaker coil and the natural filtering of the
speaker and human ear to recover the audio component of the
square wave output.
If the temperature exceeds the threshold temperature (approxi-
mately 145°C), the chip is disabled until the temperature drops
below the recovery threshold (85°C). This hysteresis prevents
rapid cycling of the output at high temperatures.
Most Class-D amplifiers use some variation of pulse-width
modulation (PWM), but the SSM3302 uses Σ-Δ modulation to
determine the switching pattern of the output devices, resulting in
several important benefits. Unlike pulse-width modulators, Σ-Δ
modulators do not produce a sharp peak with many harmonics in
the AM broadcast band. In addition, Σ-Δ modulation reduces the
amplitude of spectral components at high frequencies, reducing
EMI emission that might otherwise be radiated by speakers and
long cable traces. Due to the inherent spread spectrum nature of
Σ-Δ modulation, the need for oscillator synchronization is elim-
inated for designs incorporating multiple SSM3302 amplifiers.
Additionally, a temperature warning signal is available on the
THERM pin. If the die temperature rises above 120°C, a logic
high is output on this pin.
POP-AND-CLICK SUPPRESSION
Voltage transients at the outputs of the audio amplifiers may occur
when shutdown is activated or deactivated. Voltage transients as
small as 10 mV can be heard as an audible pop in the speaker.
Clicks and pops are defined as undesirable audible transients
generated by the amplifier system that do not come from the
system input signal.
The SSM3302 also integrates overcurrent and overtemperature
protection, as well as an overtemperature warning indicator pin.
Such transients may be generated when the amplifier system
changes its operating mode. For example, system power-up and
power-down can be sources of audible transients.
ANALOG SUPPLY
The SSM3302 includes an integrated low dropout (LDO) linear
regulator to generate a 5 V supply for the input stage. This regulator
can be enabled using the REGEN pin. This analog supply voltage is
available at the VREG/AVDD pin. Connect a 2.2 ꢀF decoupling
capacitor from this pin to the AGND pin.
The SSM3302 has a pop-and-click suppression architecture that
reduces these output transients, resulting in noiseless activation
and deactivation.
EMI NOISE
Alternatively, an external 5 V analog supply can be connected to
the AVDD pin. In this case, tie REGEN low to disable the
internal regulator.
The SSM3302 uses a proprietary modulation and spread spectrum
technology to minimize EMI emissions from the device. The
SSM3302 can pass FCC Class-B emissions testing with unshielded
20 inch cable using ferrite bead-based filtering. For applica
tions that have difficulty passing FCC Class-B emission tests, the
SSM3302 includes a modulation select pin (ultralow EMI emission
mode) that significantly reduces the radiated emissions at the
Class-D outputs, particularly above 100 MHz. Note that reducing
the supply voltage greatly reduces radiated emissions.
The internal 5 V regulator can supply up to 20 mA of current to
the VREG pin if other analog circuits use the same supply. The
regulator includes short-circuit protection, but no current
limiter or other protection is provided.
GAIN SELECTION
The preset gain of SSM3302 can be selected between 9 dB and
24 dB with one external resistor and no change to the input imped-
ance. Gain can be further adjusted to a user-defined setting by
inserting series external resistors at the inputs. A major benefit
of fixed input impedance is that there is no need to recalculate
the input corner frequency (fc) when gain is adjusted. The same
input coupling components can be used for all gain settings.
MONO MODE
The SSM3302 can also be configured to stack its stereo outputs
into a monaural amplifier configuration by enabling the mono
output mode using the MONO pin. The user can drive a load as
small as 2 Ω up to 20 W continuous output power—a particularly
useful feature for driving the subwoofer in a 2.1 audio system.
Table 5. Gain Function Descriptions
To activate this operation, pull up the MONO pin to the level of
VREG/AVDD. In mono mode, OUTL+ and OUTR+ (Pin 2/Pin 3
and Pin 28/Pin 29) provide the noninverting output, and OUTL−
and OUTR− (Pin 4/Pin 5 and Pin 26/Pin 27) provide the inverting
output. While the device is in mono mode, audio input is taken
only from the left channel set of inputs: INL+ and INL− (Pin 11
and Pin 12).
Gain Setting (dB)
GAIN Pin Configuration
Tie to AVDD
24
18
15
12
9
Tie to AVDD through 47 kΩ
Open
Tie to AGND through 47 kΩ
Tie to AGND
Rev. 0 | Page 16 of 20
Data Sheet
SSM3302
Because the mono mode uses output sense circuitry attached to
the left channel outputs, run PCB traces directly from the speaker
to the left channel outputs and then extend the PCB traces to
the right channel outputs.
and minimum inductance, ensure that track widths are at least
200 mil for every inch of length and use 1 oz. or 2 oz. copper. Use
large traces for the power supply inputs and amplifier outputs.
Proper grounding guidelines help to improve audio performance,
minimize crosstalk between channels, and prevent switching
noise from coupling into the audio signal.
OUTPUT MODULATION DESCRIPTION
The SSM3302 uses three-level, Σ-Δ output modulation. Each
output can swing from PGND to PVDD and vice versa. Ideally,
when no input signal is present, the output differential voltage is
0 V because there is no need to generate a pulse. In a real-world
situation, however, there are always noise sources present.
To maintain high output swing and high peak output power,
ensure that the PCB traces that connect the output pins to the
load and supply pins are as wide as possible to maintain the
minimum trace resistances. It is also recommended that a large
ground plane be used for minimum impedances. In addition,
good PCB layout isolates critical analog paths from sources of
high interference. High frequency circuits (analog and digital)
should be separated from low frequency circuits.
Due to this constant presence of noise, a differential pulse is
occasionally generated in response to this stimulus. A small
amount of current flows into the inductive load when the
differential pulse is generated. However, most of the time, the
output differential voltage is 0 V. This feature ensures that the
current flowing through the inductive load is small.
Properly designed multilayer PCBs can reduce EMI emission
and increase immunity to the RF field by a factor of 10 or more
compared with double-sided boards. A multilayer board allows
a complete layer to be used for the ground plane, whereas the
ground plane side of a double-sided board is often disrupted by
signal crossover.
When the user sends an input signal, an output pulse is generated
to follow the input voltage. The differential pulse density is
increased by raising the input signal level. Figure 39 depicts three-
level, Σ-Δ output modulation with and without input stimulus.
If the system has separate ground planes for small signal and
high power connections, there should be no overlap between
these planes. Stitch the power plane to the SSM3302 exposed pad
using multiple vias. Proper layout improves heat conduction
into the board, allowing operation at larger output power levels
without overtemperature issues.
OUTPUT = 0V
+5V
OUTR+/
OUTL+
0V
+5V
OUTR–/
OUTL–
0V
+5V
VOUT
0V
–5V
OUTPUT > 0V
INPUT CAPACITOR SELECTION
+5V
OUTR+/
OUTL+
Input capacitors are required if the input signal is not biased within
the recommended input dc common-mode voltage range, if
high-pass filtering is needed, or if a single-ended source is used.
If high-pass filtering is needed at the input, the input capacitor
and the input resistor of the SSM3302 form a high-pass filter
with a corner frequency determined by the following equation:
0V
+5V
OUTR–/
OUTL–
0V
+5V
VOUT
0V
OUTPUT < 0V
+5V
OUTR+/
OUTL+
0V
+5V
fC = 1/(2π × RIN × CIN)
OUTR–/
OUTL–
0V
0V
The input capacitor can significantly affect the performance of
the circuit. Failure to use input capacitors degrades the output
offset of the amplifier.
VOUT
–5V
Figure 39. Three-Level, Σ-Δ Output Modulation With and
Without Input Stimulus
BOOTSTRAP CAPACITORS
LAYOUT
The output stage of the SSM3302 uses a high-side NMOS driver,
rather than PMOS driver. To generate the gate drive voltage for
the high-side NMOS driver, a bootstrap capacitor for each output
terminal acts as a floating power supply for the switching cycle.
Using 0.22 μF ceramic capacitors with a voltage rating of 6.3 V
or greater is recommended.
As output power increases, care must be taken to lay out PCB traces
and wires properly among the amplifier, load, and power supply;
a poor layout increases voltage drops, consequently decreasing
efficiency. A good practice is to use short, wide PCB tracks to
decrease voltage drops and minimize inductance. For lowest DCR
Rev. 0 | Page 17 of 20
SSM3302
Data Sheet
For high frequency transient noises, place two separate 1 ꢀF
POWER SUPPLY DECOUPLING
capacitors as close as possible to the PVDD pins of the device.
Connect one of the 1 ꢀF capacitors between the left-side PVDD
terminals and PGND terminals, and connect the other 1 ꢀF
capacitor between the right-side PVDD terminals and PGND
terminals. Placing the decoupling capacitor as close as possible
to the SSM3302 helps to achieve the best performance.
To ensure high efficiency, low total harmonic distortion, and high
power supply rejection ratio, proper power supply decoupling
is necessary. Noise transients on the power supply lines are
short-duration voltage spikes. These spikes can contain frequency
components that extend into the hundreds of megahertz. Decouple
the power supply input with a good quality, low ESL, low ESR
bulk capacitor larger than 220 ꢀF. This capacitor bypasses low
frequency noises to the ground plane.
Rev. 0 | Page 18 of 20
Data Sheet
SSM3302
OUTLINE DIMENSIONS
6.10
6.00 SQ
5.90
0.30
0.23
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
31
30
40
1
0.50
BSC
4.45
4.30 SQ
4.25
EXPOSED
PAD
21
20
10
11
0.45
0.40
0.35
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD.
Figure 40. 40-Lead Lead Free Chip Scale Package [LFCSP_WQ]
6 mm × 6 mm Body, Very Very Thin Quad
(CP-40-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
SSM3302ACPZ
SSM3302ACPZ-RL
SSM3302ACPZ-R7
EVAL-SSM3302Z
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
40-Lead Lead Free Chip Scale Package [LFCSP_WQ]
40-Lead Lead Free Chip Scale Package [LFCSP_WQ]
40-Lead Lead Free Chip Scale Package [LFCSP_WQ]
Evaluation Board
CP-40-10
CP-40-10
CP-40-10
1 Z = RoHS Compliant Part.
Rev. 0 | Page 19 of 20
SSM3302
NOTES
Data Sheet
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10198-0-2/12(0)
Rev. 0 | Page 20 of 20
相关型号：
SSM340S3
Rectifier Diode, 1 Phase, 1 Element, 3A, 400V V(RRM), Silicon, HERMETIC SEALED, MELF-2
SENSITRON
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