SW06GS [ADI]
Quad SPST JFET Analog Switch; 四通道SPST JFET模拟开关
| 型号： | SW06GS |
| 厂家： | 
ADI |
| 描述： | Quad SPST JFET Analog Switch |
| 文件： | 总12页 (文件大小：274K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad SPST JFET
Analog Switch
a
SW06
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
Tw o Norm ally Open and Tw o Norm ally Closed SPST
Sw itches w ith Disable
V+
Sw itches Can Be Easily Configured as a Dual SPDT or
a DPDT
Highly Resistant to Static Discharge Destruction
Higher Resistance to Radiation than Analog Sw itches
Designed w ith MOS Devices
Guaranteed RON Matching: 10% m ax
Guaranteed Sw itching Speeds
TON = 500 ns m ax
12
3
S1
1
8
9
IN 1
IN 2
2
6
D1
S2
LEVEL
SHIFT
TOFF = 400 ns m ax
7
D2
S3
Guaranteed Break-Before-Make Sw itching
Low “ON” Resistance: 80 ⍀ m ax
Low RON Variation from Analog Input Voltage: 5%
Low Total Harm onic Distortion: 0.01%
Low Leakage Currents at High Tem perature
TA = +125؇C: 100 nA m ax
TA = +85؇C: 30 nA m ax
Digital Inputs TTL/ CMOS Com patible and Independent
of V+
11
IN 3
10
14
D3
S4
16
13
IN 4
DIS
15
D4
4
5
Im proved Specifications and Pin Com patible to
LF-11333/ 13333
GND
V–
Dual or Single Pow er Supply Operation
Available in Die Form
GENERAL D ESCRIP TIO N
T he SW06 is a four channel single-pole, single-throw analog
switch that employs both bipolar and ion-implanted FET
devices. T he SW06 FET switches use bipolar digital logic inputs
which are more resistant to static electricity than CMOS devices.
Ruggedness and reliability are inherent in the SW06 design and
construction technology.
Increased reliability is complemented by excellent electrical
specifications. Potential error sources are reduced by minimizing
“ON” resistance and controlling leakage currents at high tem-
peratures. T he switching FET exhibits minimal RON variation
over a 20 V analog signal range and with power supply voltage
changes. Operation from a single positive power supply voltage
is possible. With V+ = 36 V, V– = 0 V, the analog signal range
will extend from ground to +32 V.
PNP logic inputs are T T L and CMOS compatible to allow the
SW06 to upgrade existing designs. T he logic “0” and logic “1”
input currents are at microampere levels reducing loading on
CMOS and T T L logic.
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700 Fax: 617/ 326-8703
SW06–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(@ V+ = +15 V, V– = –15 V and T = +25؇C, unless otherwise noted)
A
SW06B
SW06F
SW06G
P aram eter
Sym bol
Conditions
Min Typ Max Min Typ Max Min Typ Max
Units
“ON” RESIST ANCE
RON
VS = 0 V, IS = 1 mA
VS = ±10 V, IS = 1 mA
60
65
80
80
60 100
65 100
100 150
100 150
Ω
RON MAT CH BET WEEN SWIT CHES
ANALOG VOLT AGE RANGE
RON Match VS = 0 V, IS = 100 µA1
5
10
5
20
20
%
V
VA
IS = 1 mA2
IS = 1 mA2
+10 +11
–10 –15
+10 +11
–10 –15
+10 +11
–10 –15
ANALOG CURRENT RANGE
IA
VS = ±10 V
10
15
5
7
12
5
10
10
mA
%
∆RON VS. APPLIED VOLT AGE
∆RON
–10 V ≤ VS ≤ 10 V, IS = 1.0 mA
15
10 20
20
SOURCE CURRENT IN
“OFF” CONDIT ION
IS(OFF)
VS = 10 V, VD = –10 V3
0.3 2.0
0.3 2.0
0.3 10
nA
DRAIN CURRENT IN
“OFF” CONDIT ION
ID(OFF)
VS = 10 V, VD = –10 V3
0.3 2.0
0.3 2.0
0.3 2.0
0.3 2.0
0.3 10
0.3 10
nA
nA
SOURCE CURRENT IN
“ON” CONDIT ION
IS(ON)+
ID(ON)
VS = VD = ±10 V3
LOGICAL “1” INPUT VOLT AGE
LOGICAL “0” INPUT VOLT AGE
LOGICAL “1” INPUT CURRENT
LOGICAL “0” INPUT
VINH
VINL
IINH
IINL
tON
Full T emperature Range2, 4
Full T emperature Range2, 4
VIN = 2.0 V to 15.0 V5
VIN = 0.8 V
2.0
2.0
2.0
V
0.8
5
0.8
5
0.8
10
V
µA
µA
ns
1.5 5.0
340 500
1.5 5.0
340 600
1.5 10.0
340 700
T URN-ON T IME
See Switching T ime
T est Circuit4, 6
T URN-OFF T IME
tOFF
See Switching T ime
T est Circuit4, 6
200 400
200 400
200 500
ns
BREAK-BEFORE-MAKE T IME
SOURCE CAPACIT ANCE
tON–tOFF
CS(OFF)
CD(OFF)
Note 7
50
140
7.0
5.5
15
50
140
7.0
5.5
15
50
140
7.0
5.5
15
ns
VS = 0 V3
VS = 0 V3
VS = VD = 0 V3
pF
pF
pF
DRAIN CAPACIT ANCE
CHANNEL “ON” CAPACIT ANCE
CD(ON)+
CS(ON)
“OFF” ISOLAT ION
ISO(OFF)
VS = 5 V rms, RL = 680 Ω,
58
58
58
dB
CL = 7 pF, f = 500 kHz3
CROSST ALK
CT
I+
I–
IG
VS = 5 V rms, RL = 680 Ω,
70
70
70
dB
CL = 7 pF, f = 500 kHz3
POSIT IVE SUPPLY CURRENT
NEGAT IVE SUPPLY CURRENT
GROUND CURRENT
All Channels “OFF”,
DIS = “0”3
5.0 6.0
3.0 5.0
3.0 4.0
5.0 9.0
4.0 7.0
3.0 4.0
6.0 9.0
4.0 7.0
3.0 5.0
mA
mA
mA
All Channels “OFF”,
DIS = “0”3
All Channels “ON” or
“OFF”3
–2–
REV. A
SW06
(@ V+ = +15 V, V– = –15 V, –55؇C ≤ T ≤ +125؇C for SW06BQ, –40؇C ≤ T ≤ +85؇C for
A
A
ELECTRICAL CHARACTERISTICS
SW06FQ and –40؇C ≤ T ≤ +85؇C for SW06GP/GS, unless otherwise noted)
A
SW06B
SW06F
SW06G
P aram eter
Sym bol
T A
Conditions
Min Typ Max Min Typ Max Min Typ Max
Units
°C
T EMPERAT URE RANGE
“ON” RESIST ANCE
Operating
–55
+125 –25
+85
0
70
RON
VS = 0 V, IS = 1.0 mA
VS = ±10 V, IS = 1.0 mA
75
80
110
110
75 125
80 125
75
80
175
175
Ω
∆RON MAT CH BET WEEN SWIT CHES RON Match
VS = 0 V, IS = 100 µA1
6
20
6
25
10
%
V
ANALOG VOLT AGE RANGE
VA
IS = 1.0 mA2
IS = 1.0 mA2
+10 +11
–10 –15
+10 +11
–10 –15
+10 +11
–10 –15
ANALOG CURRENT RANGE
IA
VS = ±10 V
7
12
10
5
11
12
11
15
mA
%
∆RON WIT H APPLIED VOLT AGE
∆RON
–10 V ≤ VS ≤ 10 V, IS = 1.0 mA
SOURCE CURRENT IN
“OFF” CONDIT ION
VS = 10 V, VD = –10 V
IS(OFF)
T A = Max Operating T emp3, 9
60
30
30
30
60
60
60
nA
nA
nA
DRAIN CURRENT IN
“OFF” CONDIT ION
VS = 10 V, VD = –10 V
ID(OFF)
T A = Max Operating T emp3, 9
60
LEAKAGE CURRENT IN
“ON” CONDIT ION
IS(ON)+
ID(ON)
VS = VD = ±10 V
100
T A = Max Operating T emp3, 9
LOGICAL “1” INPUT CURRENT
LOGICAL “0” INPUT CURRENT
T URN-ON T IME
IINH
IINL
tON
VIN = 2.0 V to 15.0 V5
VIN = 0.8 V
10
10
10
10
15
15
µA
µA
4
4
5
See Switching T ime
T est Circuit4, 8
440 900
500 900
1000 ns
T URN-OFF T IME
tOFF
See Switching T ime
T est Circuit4, 8
300 500
330 500
500
ns
BREAK-BEFORE-MAKE T IME
POSIT IVE SUPPLY CURRENT
tON –tOFF
I+
Note 7
70
70
50
ns
All Channels “OFF,”
DIS = “0”3
9.0
13.5
13.5
10.5
7.5
mA
NEGAT IVE SUPPLY CURRENT
GROUND CURRENT
NOT ES
I–
IG
All Channels “OFF,”
DIS = “0”3
7.5
6.0
10.5
7.5
mA
mA
All Channels “ON” or
“OFF”3
RON1 + RON 2 + RON 3 + RON 4
1VS = 0 V, IS = 100 µA. Specified as a percentage of RAVERAGE where: RAVERAGE
=
.
4
2Guaranteed by RON and leakage tests. For normal operation maximum analog signal voltages should be restricted to less than (V+) –4 V.
3Switch being tested ON or OFF as indicated, VINH = 2.0 V or VINL = 0.8 V, per logic truth table.
4Also applies to disable pin.
5Current tested at VIN = 2.0 V. T his is worst case condition.
6Sample tested.
7Switch is guaranteed by design to provide break-before-make operation.
8Guaranteed by design.
9Parameter tested only at T A = +125°C for military grade device.
Specifications subject to change without notice.
REV. A
–3–
SW06
WAFER TEST LIMITS
(@ V+ = +15 V, V– = –15 V, T = +25؇C, unless otherwise noted)
A
SW06N
Lim it
SW06G
Lim it
P aram eter
Sym bol
Conditions
Units
“ON” RESIST ANCE
RON
–10 V ≤ VA ≤ 10 V, IS ≤ 1 mA
80
100
20
Ω max
% max
% max
mA max
mA max
mA max
V min
RON MAT CH BET WEEN SWIT CHES
∆RON VS. VA
RON Match VA = 0 V, IS ≤ 100 µA
15
∆RON
I+
–10 V ≤ VA ≤ 10 V, IS ≤ 1 mA
10
20
POSIT IVE SUPPLY CURRENT
NEGAT IVE SUPPLY CURRENT
GROUND CURRENT
Note 1
6.0
5.0
4.0
±10.0
2.0
0.8
5.0
5
9.0
7.0
4.0
±10.0
2.0
0.8
5.0
5
I–
Note 1
IG
Note 1
ANALOG VOLT AGE RANGE
LOGIC “1” INPUT VOLT AGE
LOGIC “0” INPUT VOLT AGE
LOGIC “0” INPUT CURRENT
LOGIC “1” INPUT CURRENT
VA
IS = 1 mA
Note 2
VINH
VINL
IINL
IINH
IA
V min
Note 2
V max
0 V ≤ VIN ≤ 0.8 V
2.0 V ≤ VIN ≤ 15 V3
VS = ±10 mV
µA max
µA max
mA min
ANALOG CURRENT RANGE
10
7
NOT E
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
(@ V+ = +15 V, V– = –15 V, T = +25؇C, unless otherwise noted)
TYPICAL ELECTRICAL CHARACTERISTICS
A
SW06N
Typical
SW06G
Typical Units
P aram eter
Sym bol
RON
Conditions
“ON” RESIST ANCE
T URN-ON T IME
T URN-OFF T IME
–10 V ≤ VA ≤ 10 V, IS ≤ 1 mA
60
60
Ω
tON
340
200
340
200
ns
ns
tOFF
DRAIN CURRENT IN
“OFF” CONDIT ION
ID(OFF)
ISO(OFF)
CT
VS = 10 V, VD = –10 V
f = 500 kHz, RL = 680 Ω
f = 500 kHz, RL = 680 Ω
0.3
58
70
0.3
58
70
nA
dB
dB
“OFF” ISOLAT ION
CROSST ALK
NOT ES
1Power supply and ground current specified for switch “ON” or “OFF.”
2Guaranteed by RON and leakage tests.
3Current tested at VIN = 2.0 V. T his is worst case condition.
–4–
REV. A
SW06
O RD ERING GUID E
ABSO LUTE MAXIMUM RATINGS1
Operating T emperature Range
Tem perature
P ackage
P ackage
SW06BQ, BRC . . . . . . . . . . . . . . . . . . . –55°C to +125°C
SW06FQ . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
SW06GP, GS . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage T emperature Range . . . . . . . . . . . –65°C to +150°C
Lead T emperature (Soldering, 60 sec) . . . . . . . . . . . . +300°C
Maximum Junction T emperature . . . . . . . . . . . . . . . . +150°C
V+ Supply to V– Supply . . . . . . . . . . . . . . . . . . . . . . . +36 V
V+ Supply to Ground . . . . . . . . . . . . . . . . . . . . . . . . . +36 V
Logic Input Voltage . . . . . . . . . . . (–4 V or V–) to V+ Supply
Analog Input Voltage Range
Model
Range
D escription
O ption
SW06BQ
SW06BRC
SW06FQ
SW06GP
SW06GS
–55°C to +125°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Cerdip
LCC
Cerdip
Plastic DIP
SOL
Q-16
E-20A
Q-16
N-16
R-16
TRUTH TABLE
Continuous . . . . . . . . . . . . . V– Supply to V+ Supply +20 V
Maximum Current T hrough
Any Pin Including Switch . . . . . . . . . . . . . . . . . . . . . 30 mA
Switch State
Channels
1 & 2
D isable
Input
Logic
Input
Channels
3 & 4
2
P ackage Type
JA
JC
Units
0
X
0
1
OFF
OFF
ON
OFF
ON
OFF
1 or NC
1 or NC
16-Pin Hermetic DIP (Q)
16-Pin Plastic DIP (P)
20-Contact LCC (RC)
16-Pin SOL (S)
100
82
98
16
39
38
30
°C/W
°C/W
°C/W
°C/W
98
NOT ES
P IN CO NNECTIO NS
1Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
16-P in D IP (Q or P -Suffix)
16-P in SO L (S-Suffix)
2θJA is specified for worst case mounting conditions, i.e., θJA is specified for device
in socket for Cerdip, P-DIP, and LCC packages; θJA is specified for device soldered
to printed circuit board for SO package.
D ICE CH ARACTERISTICS
D ie Size 0.101 × 0.097 inch, 9797 sq. mils
(2.565 × 2.464 mm, 6320 sq. mm)
SW06BRC/883
LCC P ackage
(RC-Suffix)
REV. A
–5–
SW06–Typical Performance Characteristics
“ON” Resistance vs. Power Supply
Voltage
“ON” Resistance vs. Analog Voltage
RON vs. Tem perature
Leakage Current vs. Tem perature
Leakage Current vs. Analog Voltage
Switch Current vs. Voltage
Switch Capacitance vs. Analog
Voltage
Supply Current vs. Tem perature
Supply Current vs. Supply Voltage
–6–
REV. A
SW06
TON/TOFF Switching Response
Switching Tim e vs. Tem perature
Switching Tim e vs. Analog Voltage
Insertion Loss vs. Frequency
Crosstalk and “OFF” Isolation vs.
Frequency
Total Harm onic Distortion
Power Supply Rejection vs.
Frequency
Overvoltage Characteristics
REV. A
–7–
SW06–Typical Performance Characteristics (Operating and Single Supply)
Supply Current vs. Supply Voltage
“On” Resistance vs. Analog Voltage
Leakage Current vs. VANALOG
NO TE
T hese single-supply-operation characteristic curves are valid
when the negative power supply V– is tied to the logic ground
reference pin “GND.” T T L input compatibility is still main-
tained when “GND” is the same potential as the T T L ground.
tOFF is measured from 50% of logic input waveform to 0.9 VO.
T he analog voltage range extends from 0 V to V+ –4 V; the
switch will no longer respond to logic control when VA is within
4 volts of V+.
Switching Tim e vs. Supply Voltage
Sim plified Schem atic Diagram (Typical Switch)
–8–
REV. A
SW06
“Off” Isolation Test Circuit
Crosstalk Test Circuit
Switching Tim e Test Circuit
REV. A
–9–
SW06
Figure 1. Functional Applications of SW06
AP P LICATIO NS INFO RMATIO N
supplies are OFF. When the V+ and V– supplies are OFF, the
logic inputs present a reverse bias diode loading to active logic
inputs. Input logic thresholds are independent of V+ and V–
supplies making single V+ supply operation possible by simply
connecting GND and V– together to the logic ground supply.
T he single analog switch product configures, by appropriate pin
connections, into four switch applications. As shown in Figure
1, the SW06 connects as a QUAD SPST , a DUAL SPDT , a
DUAL DPST , or a DPDT analog switch. T his versatility in-
creases further when taking advantage of the disable input (DIS)
which turns all switches OFF when taken active low.
ANALO G VO LTAGE AND CURRENT
ANALO G VO LTAGE
Ion-implantation of the JFET analog switch achieves low ON
resistance and tight channel-to-channel matching. Combining
the low ON resistance and low leakage currents results in a
T hese switches have constant ON resistance for analog voltages
from the negative power supply (V–) to within 4 volts of the
positive power supply. T his characteristic shown in the plots re-
sults in good total harmonic distortion, especially when com-
pared to CMOS analog switches that have a 20 to 30 percent
variation in ON resistance versus analog voltage. Positive analog
input voltage should be restricted to 4 volts less than V+ assur-
ing the switch remains open circuit in the OFF state. No in-
crease in switch ON resistance occurs when operating at supply
voltages less than ±15 volts (see plot). Small signals have a 3 dB
down frequency of 70 MHz (see insertion loss versus frequency
plot).
worst case voltage error figure VERROR @ +125°C = ID(ON)
×
RSD(ON) = 100 nA × 100 Ω = 11 microvolts. T his amount of er-
ror is negligible considering dissimilar-metal thermally-induced
offsets will be in the 5 to 15 microvolt range.
LO GIC INP UTS
T he logic inputs (INX) and disable input (DIS) are referenced
to a T T L logic threshold value of two forward diode drops (1.4 V
at +25°C) above the GND terminal. T hese inputs use PNP
transistors which draw maximum current at a logic “0” level and
drops to a leakage current of a reverse biased diode as the logic
input voltage raises above 1.4 volts. Any logic input voltage
greater than 2.0 volts becomes logic “1,” less than 0.8 volts be-
comes logic “0” resulting in full T T L noise immunity not avail-
able from similar CMOS input analog switches. T he PNP
transistor inputs require such low input current that the SW06
approaches fan-ins of CMOS input devices. T hese bipolar logic
inputs exceed any CMOS input circuit in resistance to static
voltage and radiation susceptibility. No damage will occur to the
SW06 if logic high voltages are present when the SW06 power
ANALO G CURRENT
T he analog switches in the ON state are JFET s biased in their
triode region and act as switches for analog current up to the IA
specification (see plot of IDS vs VDS). Some applications require
pulsed currents exceeding the IA spec. For example, an integra-
tor reset switch discharging a shunt capacitor will produce a
peak current of IA(PEAK) = VCAP/RDS(ON). In this application, it is
best to connect the source to the most positive end of the ca-
pacitor, thereby achieving the lowest switch resistance and
–10–
REV. A
SW06
fastest reset times. T he switch can easily handle any amount of
capacitor discharge current subject only to the maximum heat
dissipation of the package and the maximum operating junction
temperature from which repetition can be established.
D ISABLE NO D E
T his T T L compatible node is similar to the logic inputs INX but
has an internal 2 µA current source pull-up. If disable is left un-
connected, it will assume the logic “1” state, then the state of
the switches is controlled only by the logic inputs INX.
SWITCH ING
Switching time tON and tOFF characteristics are plotted versus
VANALOG and temperature. In all cases, tOFF is designed faster
than tON to ensure a break-before-make interval for SPDT and
DPDT applications. T he disable input (DIS) has the same
switching times (tON and tOFF) as the logic inputs (INX).
P O WER SUP P LIES
T his product operates with power supply voltages ranging from
±12 to ±18 volts; however, the specifications only guarantee
device parameters with ±15 volt ±5% power supplies. T he
power supply sensitive parameters have plots to indicate effects
of supply voltages other than ±15 volts.
Switching transients occurring at the source and drain contacts
results from ac coupling of the switching FET s gate-to-source
and gate-to-drain coupling capacitance. T he switch turn ON
will cause a negative going spike to occur and the turn OFF will
cause a positive spike to occur. T hese spikes can be reduced by
additional capacitance loading, lower values of RL, or switching
an additional switch (with its extra contact floating) to the op-
posite state connected to the spike sensitive node.
Typical Applications
Operation from Single Positive Power Supply
4-Channel Sam ple Hold Am plifier
High Off Isolation Selector Switch (Shunt-Series Switch)
–11–
REV. A
SW06
Single Pole Double Throw Selector Switch with Break-Before-Make Interval
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
20-Term inal Leadless Chip Carrier
16-Lead Cerdip
(Q-Suffix)
Q-16
(RC-Suffix)
E-20A
0.005 (0.13) MIN
0.080 (2.03) MAX
9
0.200 (5.08)
BSC
0.075
(1.91)
REF
0.100 (2.54)
0.064 (1.63)
16
0.100 (2.54) BSC
0.015 (0.38)
0.310 (7.87)
PIN 1
0.220 (5.59)
0.095 (2.41)
19
3
MIN
20
1
8
0.075 (1.90)
18
4
0.028 (0.71)
0.358
1
0.320 (8.13)
0.290 (7.37)
0.358 (9.09)
0.011 (0.28)
0.022 (0.56)
(9.09)
MAX
SQ
0.840 (21.34) MAX
BOTTOM
VIEW
0.342 (8.69)
SQ
0.007 (0.18)
R TYP
0.075 (1.91)
REF
0.060 (1.52)
0.015 (0.38)
0.050 (1.27)
BSC
0.200
(5.08)
MAX
14
13
8
9
0.150
(3.81)
MIN
45° TYP
0.015 (0.38)
0.008 (0.20)
0.200 (5.08)
0.125 (3.18)
0.055 (1.40)
0.045 (1.14)
0.088 (2.24)
0.054 (1.37)
0.150 (3.81)
BSC
15°
0°
0.023 (0.58)
0.070 (1.78)
0.030 (0.76)
0.100
(2.54)
BSC
SEATING
PLANE
0.014 (0.36)
16-Lead P lastic D IP
(P -Suffix)
16-Lead Wide Body SO L
(S-Suffix)
N-16
R-16/SO L-16
0.840 (21.33)
0.745 (18.93)
0.4133 (10.50)
0.3977 (10.00)
16
1
9
8
16
9
0.280 (7.11)
0.240 (6.10)
0.325 (8.25)
0.195 (4.95)
0.115 (2.93)
0.060 (1.52)
0.015 (0.38)
0.300 (7.62)
PIN 1
1
8
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.1043 (2.65)
0.0291 (0.74)
PIN 1
0.160 (4.06)
0.115 (2.93)
x 45°
0.0118 (0.30)
0.0040 (0.10)
0.0926 (2.35)
0.0098 (0.25)
0.015 (0.381)
0.008 (0.204)
0.070 (1.77) SEATING
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
PLANE
0.045 (1.15)
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
0.0138 (0.35)
–12–
REV. A
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