SQF-S10M2-64G-SBC [ADVANTECH]
CFast 640 Datasheet;
| 型号： | SQF-S10M2-64G-SBC |
| 厂家： | 
Advantech Co., Ltd. |
| 描述： | CFast 640 Datasheet |
| 文件： | 总23页 (文件大小：813K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SQFlash
CFast 640
CFast 640
Datasheet
(SQF-S10x-xxx-SBx)
Specifications subject to change without notice, contact your sales representatives for the most update information.
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SQFlash
CFast 640
CONTENTS
1.Overview ............................................................................................ 4
2.Features ............................................................................................. 5
3.Specification Table............................................................................ 6
4.General Description .......................................................................... 8
5.Pin Assignment and Description................................................... 11
5.1 CFast Interface Pin Assignments .................................................................................. 11
6.Identify Device Data ........................................................................ 12
7.ATA Command Set .......................................................................... 15
8.System Power Consumption ......................................................... 21
8.1 Supply Voltage .............................................................................................................. 21
8.2 Power Consumption...................................................................................................... 21
9.Physical Dimension ........................................................................ 22
Appendix: Part Number Table ........................................................... 23
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SQFlash
CFast 640
Revision History
Rev.
Date
History
0.1
2016/10/13
1. Preliminary
0.2
0.3
0.4
0.5
2017/9/7
2018/7/30
2018/10/03
2018/11/13
1. Update PN & performance data
1. Add 3D NAND information
2. Update performance data
1. Update performance data & revised typo
1. Update TBW and power comsumption
2. Modify OP temperature information
Advantech reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or
design. Information furnished by Advantech is believed to be accurate and reliable. However, Advantech does not assure any liability
arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither
does it convey any license under its patent rights nor the rights of others.
Copyright © 1983-2018 Advantech Co., Ltd. All rights reserved.
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SQFlash
CFast 640
1. Overview
Advantech SQFlash 640 series CFast (SQF-S10 640) delivers all the advantages of flash disk technology with
the Serial ATA I/II/III interface and is fully compliant with MO-300 CFast specification. The SQF-S10 640 is
designed to operate at a maximum operating frequency of 200MHz with 30MHz external crystal. Its capacity could
provide a wide range up to 256GB. Moreover, it can reach up to 560MB/s read as well as 470MB/s write high
performance based on Toggle 2.0 MLC flash (with 32MB SDR enabled and measured by CrystalDiskMark v5.0).
The power consumption of SQF-S10 640 is much lower than traditional hard drives, making it the best embedded
solution for new platforms.
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SQFlash
CFast 640
2. Features
Standard SATA interface
–
–
Support SATA 1.5/3.0/6.0 Gbps interface
SATA Revision 3.2 compliant
Operating Voltage：3.3V
TRIM、AHCI supported
Temperature Ranges
–
Commercial Temperature
● 0℃ to 70℃ for operating1
● -40℃ to 85℃ for storage
–
Industrial Temperature
● -40℃ to 85℃ for operating
● -40℃ to 85℃ for storage
*Note: 1. Based on SMART Attribute C2h, which measured by thermal sensor
Mechanical Specification
–
Shock：1,500G / 0.5ms
–
Vibration：20G / 80~2,000Hz
Humidty
–
Humidity：5% ~ 95% under 55℃
Endurance : > 2,000,000 program/erase cycles
–
This is a test result of the whole SQFlash drive. The test is to keep writing a fixed logical block address
(LBA) and see if any bad blocks occur after 2M cycles. With wear-levelling mechanism, although the disk
was kept writing the same LBA but the physical block changes per block writing. So this test also proves
that wear-leveling is really working, or the block would be wearout after its designated life cycles.
Data Retention
–
10 years
Acquired RoHS、WHQL、CE、FCC Certificate
Acoustic：0 dB
Dimension：42.8 mm x 36.4 mm x 3.3 mm
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SQFlash
CFast 640
3. Specification Table
Performance
Sequential Performance (MB/sec)
Random Performance (IOPS @4K)
Read
TBD
Write
TBD
Read
TBD
Write
TBD
8 GB
TBD
TBD
TBD
TBD
16 GB
SLC
TBD
TBD
TBD
TBD
32 GB
TBD
TBD
TBD
TBD
64 GB
16 GB
355.86
561.72
561.53
355.83
561.47
561.30
554.55
561.15
567.97
166.55
313.61
471.83
165.92
327.99
472.86
260.29
458.49
498.67
35,943
74,856
88,885
36,957
57,479
82,841
35,010
65,402
84,850
40,026
75,655
83,322
40,056
76,938
82,765
61,265
81,994
86,060
Ultra
MLC
32 GB
64 GB
32 GB
MLC
64 GB
128 GB
64 GB
3D
NAND
(BiCS3)
128 GB
256 GB
* All performance above are tested with AHCI mode.
* Tested by CrystalDiskMark 1GB workload.
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SQFlash
CFast 640
Endurance
JEDEC defined an endurance rating TBW (TeraByte Written), following by the equation below, for indicating
the number of terabytes a SSD can be written which is a measurement of SSDs’ expected lifespan,
represents the amount of data written to the device.
TBW = [(NAND Endurance) x (SSD Capacity)] / WAF
NAND Endurance: Program / Erase cycle of a NAND flash.
o SLC: 100,000 cycles
o Ultra MLC: 30,000 cycles
o MLC: 3,000 cycles
SSD Capacity: SSD physical capacity in total of a SSD.
WAF: Write Amplification Factor (WAF), as the equation shown below, is a numerical value
representing the ratio between the amount of data that a SSD controller needs to write and the
amount of data that the host’s flash controller writes. A better WAF, which is near to 1, guarantees
better endurance and lower frequency of data written to flash memory.
WAF = (Lifetime write to flash) / (Lifetime write to host)
Endurance measurement is based on JDEC 219 workload and verified with following workload conditions,
PreCond%full = 100%
Trim commands enabled
Random data pattern.
SQFlash 640 CFast TBW
TBW
WAF
SLC
Ultra MLC
MLC
TBD
TBD
TBD
TBD
TBD
8 GB
16 GB
32 GB
64 GB
128 GB
--
--
--
5.97
3.84
2.74
2.89
80
250
701
25
70
--
--
133
SQFlash 640 CFast TBW (3D NAND (BiCS3))
TBW
WAF
3D NAND (BiCS3)
2.61
2.93
2.44
64 GB
128 GB
256 GB
74
131
315
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SQFlash
CFast 640
4. General Description
Error Correction Code (ECC)
Flash memory cells will deteriorate with use, which might generate random bit errors in the stored data. Thus,
SQFlash 640 series CFast applies the LDPC (Low Density Parity Check) of ECC algorithm, which can detect
and correct errors occur during read process, ensure data been read correctly, as well as protect data from
corruption.
Wear Leveling
NAND flash devices can only undergo a limited number of program/erase cycles, and in most cases, the
flash media are not used evenly. If some areas get updated more frequently than others, the lifetime of the
device would be reduced significantly. Thus, Wear Leveling is applied to extend the lifespan of NAND Flash
by evenly distributing write and erase cycles across the media.
SQFlash provides advanced Wear Leveling algorithm, which can efficiently spread out the flash usage
through the whole flash media area. Moreover, by implementing both dynamic and static Wear Leveling
algorithms, the life expectancy of the NAND flash is greatly improved.
Bad Block Management
Bad blocks are blocks that include one or more invalid bits, and their reliability is not guaranteed. Blocks that
are identified and marked as bad by the manufacturer are referred to as “Initial Bad Blocks”. Bad blocks that
are developed during the lifespan of the flash are named “Later Bad Blocks”. SQFlash implements an
efficient bad block management algorithm to detect the factory-produced bad blocks and manages any bad
blocks that appear with use. This practice further prevents data being stored into bad blocks and improves
the data reliability.
Power Loss Protection: Flush Manager
Power Loss Protection is a mechanism to prevent data loss during unexpected power failure. DRAM is a
volatile memory and frequently used as temporary cache or buffer between the controller and the NAND
flash to improve the SSD performance. However, one major concern of the DRAM is that it is not able to
keep data during power failure. Accordingly, SQFlash SSD applies the Flush Manager technology, only when
the data is fully committed to the NAND flash will the controller send acknowledgement (ACK) to the host.
Such implementation can prevent false-positive performance and the risk of power cycling issues.
In addition, it is critical for a controller to shorten the time the in-flight data stays in the controller internal
cache. Thus, SQFlash applies an algorithm to reduce the amount of data resides in the cache to provide a
better performance. With Flush Manager, incoming data would only have a “pit stop” in the cache and then
move to NAND flash directly. Also, the onboard DDR will be treated as an “organizer” to consolidate
incoming data into groups before written into the flash to improve write amplification.
TRIM
TRIM is a feature which helps improve the read/write performance and speed of solid-state drives (SSD).
Unlike hard disk drives (HDD), SSDs are not able to overwrite existing data, so the available space gradually
becomes smaller with each use. With the TRIM command, the operating system can inform the SSD which
blocks of data are no longer in use and can be removed permanently. Thus, the SSD will perform the erase
action, which prevents unused data from occupying blocks all the time.
SMART
SMART, an acronym for Self-Monitoring, Analysis and Reporting Technology, is an open standard that allows
a hard disk drive to automatically detect its health and report potential failures. When a failure is recorded by
SMART, users can choose to replace the drive to prevent unexpected outage or data loss. Moreover,
SMART can inform users of impending failures while there is still time to perform proactive actions, such as
copy data to another device.
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SQFlash
CFast 640
Over-Provision
Over Provisioning refers to the inclusion of extra NAND capacity in a SSD, which is not visible and cannot be
used by users. With Over Provisioning, the performance and IOPS (Input/Output Operations per Second)
are improved by providing the controller additional space to manage P/E cycles, which enhances the
reliability and endurance as well. Moreover, the write amplification of the SSD becomes lower when the
controller writes data to the flash.
Thermal Throttling
Thermal Throttling function is for protecting the drive and reducing the possibility of read / write error due to
overheat. The temperature is monitored by the thermal sensor. As the operating temperature continues to
increase to threshold temperature, the Thermal Throttling mechanism is activated. At this time, the
performance of the drive will be significantly decreased to avoid continuous heating. When the operating
temperature falls below threshold temperature, the drive can resume to normal operation.
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SQFlash
CFast 640
Block Diagram
LBA value
Density
16 GB
32 GB
64 GB
128 GB
256 GB
LBA
30,752,064
62,008,128
125,045,424
250,069,680
500,118,192
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SQFlash
CFast 640
5. Pin Assignment and Description
5.1 CFast Interface Pin Assignments
Pin # Pin Def.
Description
Mate Sequence
S1
S2
S3
S4
S5
S6
S7
GND
A+
A-
GND
B-
B+
1st
2nd
2nd
1st
Host Transmitter
Differential Signal Pair
2nd
2nd
1st
Host Receiver
Differential Signal Pair
GND
5.2 CFast Interface Pin Assignments (Power Segment)
Pin #
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
Pin Def.
CDI
GND
DEVSLP
TBD
TBD
TBD
GND
LED1
LED2
IO1
Function
Card Detect in
Mate Sequence
3rd
1st
DevSleep State Enable (optional)
2nd
2nd
2nd
2nd
1st
LED Output
LED Output
2nd
2nd
2nd
2nd
2nd
2nd
2nd
1st
Reserved Input/Output
Reserved Input/Output
Card output, connect to PGND on card
Device Power (3.3V)
Device Power (3.3V)
Device Ground
IO2
PC12 IFDet (GND)
PC13
PC14
PC15
PC16
PC17
PWR
PWR
PGND
PGND
CDO
Device Ground
Card Detect Out
1st
3rd
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SQFlash
CFast 640
6. Identify Device Data
The Identity Device Data enables Host to receive parameter information from the device. The
parameter words in the buffer have the arrangement and meanings defined in below table. All reserve
bits or words are zero
Word
ATA Identify Parameter
Value
0
1
General configuration bit-significant information
Obsolete
0040h
*1
2
Specific configuration
C837h
3
Obsolete
0010h
4-5
6
Retired
Obsolete
00000000h
003Fh
7-8
9
Reserved for assignment by the Compact Flash Association
Retired
00000000h
0000h
10-19
20-21
22
Serial number (20 ASCII characters)
Retired
Obsolete
Varies
00000000h
0000h
23-26
27-46
Firmware revision (8 ASCII characters)
Model number (xxxxxxxx)
Varies
Varies
7:0- Maximum number of sectors transferred per interrupt on
MULTIPLE commands
47
8010h
48
49
50
Trusted Computing feature set options(not support)
4000h
2F00h
4000h
000000000h
0007h
*1
Capabilities
Capabilities
Obsolete
51-52
53
54
Words 88 and 70:64 valid
Obsolete
55
56
57-58
Obsolete
Obsolete
Obsolete
0010h
003Fh
*2
Sanitize and Number of sectors transferred per interrupt on MULTIPLE
commands
59
5D10h
60-61
62
Maximum number of sector ( 28bit LBA mode)
Obsolete
*3
0000h
63
64
Multi-word DMA modes supported/selected
PIO modes supported
0407h
0003h
65
Minimum Multiword DMA transfer cycle time per word
Manufacturer’s recommended Multiword DMA transfer cycle time
Minimum PIO transfer cycle time without flow control
Minimum PIO transfer cycle time with IORDY flow control
Additional Supported (support download microcode DMA)
Reserved
0078h
66
67
68
69
0078h
0078h
0078h
0D00h
70
0000h
71-74
75
Reserved for the IDENTIFY PACKET DEVICE command
Queue depth
0000000000000000h
001Fh
76
Serial SATA capabilities
E70Eh
77
Serial ATA Additional Capabilities
0086h
78
Serial ATA features supported
014Ch
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SQFlash
CFast 640
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Serial ATA features enabled
Major Version Number
Minor Version Number
Command set supported
0040h
0FF8h
0000h
706Bh
7409h
6163h
7069h
B401h
6163h
007Fh
0001h
001Eh
0000h
FFFEh
Command set supported
Command set/feature supported extension
Command set/feature enabled
Command set/feature enabled
Command set/feature default
Ultra DMA Modes
Time required for security erase unit completion
Time required for Enhanced security erase completion
Current advanced power management value
Master Password Revision Code
Hardware reset result. For SATA devices, word 93 shall be set to the
value 0000h.
93
0000h
94
95
96
97
98-99
Obsolete
Stream Minimum Request Size
Streaming Transfer Time – DMA
Streaming Access Latency – DMA and PIO
Streaming Performance Granularity
0000h
0000h
0000h
0000h
0000h
*4
100-103 Maximum user LBA for 48 bit Address feature set
104
Streaming Transfer Time – PIO
0000h
Maximum number of 512-byte blocks per DATA SET MANAGEMENT
command
105
0008h
106
107
Physical sector size/Logical sector size
Inter-seek delay for ISO-7779 acoustic testing in microseconds
4000h
0000h
Varies
108-111 World Wide Name
112-115 Reserved
0000000000000000h
116
Reserved
0000h
00000000h
411Ch
401Ch
0h
117-118 Words per logical Sector
119
120
Supported settings
Command set/Feature Enabled/Supported
121-126 Reserved
127
128
Obsolete
Security status
0h
0021h
Varies
Varies
Varies
0h
129-140 Vendor specific
141 Vendor specific
142-159 Vendor specific
160 Reserved for CFA
161-167 Reserved for CFA
0h
168
169
Device Nominal Form Factor
DATA SET MANAGEMENT command is supported
Varies
0001h
0h
170-173 Additional Product Identifier
174-175 Reserved
0h
176-205 Current media serial number
0h
206
SCT Command Transport
0h
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SQFlash
CFast 640
207-208 Reserved
0h
4000h
0000h
0000h
0000h
0001h
0h
0h
0h
0h
209
Alignment of logical blocks within a physical block
210-211 Write-Read-Verify Sector Count Mode 3 (not support)
212-213 Write-Read-Verify Sector Count Mode 2 (not support)
214-216 Obsolete
217
218
219
220
221
222
223
Non-rotating media device
Reserved
NV Cache relate (not support)
Write read verify feature set current mode
Reserved
Transport major version number
Transport minor version number
10FFh
0000h
0h
224-229 Reserved
230-233 Extend number of user addressable sectors
0h
Minimum number of 512-byte data blocks per DOWNLOAD
MICROCODE command for mode 03h
Maximum number of 512-byte data blocks per DOWNLOAD
MICROCODE command for mode 03h
234
0001h
FFFEh
235
236-254 Reserved
0h
255
Integrity word (Checksum and Signature)
XXA5h
Capacity
(GB)
8
16
32
64
128
256
*1
(Word 1/Word 54)
3CA5h
*2
*3
*4
(Word 57 – 58)
EEC9B0h
FBFC10h
(Word 60 – 61)
(Word 100 – 103)
EEC9B0h
EEC9B0h
3FFFh
3FFFh
3FFFh
3FFFh
1DD40B0h
3BA2EB0h
7740AB0h
EE7C2B0h
FFFFFFFh
1DD40B0h
3BA2EB0h
7740AB0h
EE7C2B0h
FBFC10h
FBFC10h
FBFC10h
FBFC10h
3FFFh
1DCF32B0h
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SQFlash
CFast 640
7. ATA Command Set
[Command Set List]
Op-Code
Command Description
Op-Code
Command Description
00h
06h
NOP
91h
92h
93h
B0h
B4h
C4h
C5h
C6h
C8h
C9h
CAh
CBh
CEh
E0h
E1h
E2h
E3h
E4h
E5h
E6h
E7h
E8h
EAh
ECh
EFh
F1h
F2h
F3h
Initialize Device Parameters
Download Microcode
Download Microcode DMA
SMART
Data Set Management
Recalibrate
10h-1Fh
20h
21h
24h
25h
29h
2Fh
Read Sectors
Read Sectors without Retry
Read Sectors EXT
Read DMA EXT
Sanitize
Read Multiple
Write Multiple
Set Multiple Mode
Read DMA
Read Multiple EXT
Read Log EXT
30h
31h
34h
35h
38h
39h
3Dh
3Fh
Write Sectors
Read DMA without Retry
Write DMA
Write Sectors without Retry
Write Sectors EXT
Write DMA EXT
Write DMA without Retry
Write Multiple FUA EXT
Standby Immediate
Idle Immediate
Standby
CFA Write Sectors Without Erase
Write Multiple EXT
Write DMA FUA EXT
Write Long EXT
Idle
40h
41h
42h
44h
45h
47h
57h
60h
61h
70h-76h
77h
Read Verify Sectors
Read Verify Sectors without Retry
Read Verify Sectors EXT
Zero EXT
Read Buffer
Check Power Mode
Sleep
Flush Cache
Write Uncorrectable EXT
Read Log DMA EXT
Write Log DMA EXT
Read FPDMA Queued
Write FPDMA Queued
Seek
Write Buffer
Flush Cache EXT
Identify Device
Set Features
Security Set Password
Security Unlock
Security Erase Prepare
Set Date & Time EXT
Accessible Max Address
configuration
78h
F4h
Security Erase Unit
79h-7Fh
90h
Seek
F5h
F6h
Security Freeze Lock
Execute Device Diagnostic
Security Disable Password
Note: ND = Non-Data Command
PI = PIO Data-In Command
PO = PIO Data-Out Command
DM = DMA Command
DD = Execute Diagnostic Command
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SQFlash
CFast 640
[Command Set Descriptions]
1. CHECK POWER MODE (code: E5h);
This command allow host to determine the current power mode of the device.
2. DOWNLOAD MICROCODE (code: 92h);
This command enables the host to alter the device’s microcode. The data transferred using the
DOWNLOAD MICROCODE command is vendor specific.
All transfers shall be an integer multiple of the sector size. The size of the data transfer is determined
by the content of the LBA Low register and the Sector Count register.
This allows transfer sizes from 0 bytes to 33,553,920 bytes, in 512bytes increments.
3. EXECUTE DEVICE DIAGNOSTIC (code: 90h);
This command performs the internal diagnostic tests implemented by the module.
4. FLUSH CACHE (code: E7h);
This command used by the host to request the device to flush the write cache.
5. FLUSH CACHE EXT (code: EAh);
This command is used by the host to request the device to flush the write cache. If there is data in the
write cache, that data shall be written to the media.
6. IDENTIFY DEVICE (code: ECh);
The IDENTIFY DEVICE command enables the host to receive parameter information from the module.
7. IDLE (code: 97h or E3h);
This command allows the host to place the module in the IDLE mode and also set the Standby timer.
INTRQ may be asserted even through the module may not have fully transitioned to IDLE mode. If the
Sector Count register is non-”0”, then the Standby timer shall be enabled. The value in the Sector
Count register shall be used to determine the time programmed into the Standby timer. If the Sector
Count register is “0” then the Standby timer is disabled.
8. IDLE IMMEDIATE (code: E1h);
This command causes the module to set BSY, enter the Idle (Read) mode, clear BSY and generate an
interrupt.
9. INITIALIZE DEVICE PARAMETERS (code: 91h);
This command enables the host to set the number of sectors per track and the number of heads per
cylinder.
10. NOP (code: 00h);
If this command is issued, the module respond with command aborted.
11. READ BUFFER (code: E4h);
This command enables the host to read the current contents of the module's sector buffer.
12. READ DMA (code: C8h or C9h);
This command reads from “1” to “256” sectors as specified in the Sector Count register using the DMA
data transfer protocol. A sector count of “0” requests “256” sectors transfer. The transfer begins at the
sector specified in the Sector Number register.
13. READ DMA Ext (code: 25h);
This command allows the host to read data using the DMA data transfer protocol.
14. READ MULTIPLE (code: C4h);
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SQFlash
CFast 640
This command performs similarly to the READ SECTORS command. Interrupts are not generated on
each sector, but on the transfer of a block which contains the number of sector per block is defined by
the content of word 59 in the IDENTIFY DEVICE response.
15. READ MULTIPLE EXT (code: 29h);
This command performs similarly to the READ SECTORS command. The number of sectors per block
is defined by a successful SET MULTIPLE command. If no successful SET MULTIPLE command has
been issued, the block is defined by the device’s default value for number of sectors per block as
defined in bits (7:0) in word 47 in the IDENTIFY DEVICE information.
16. READ NATIVE MAX ADDRESS (code: F8h);
This command returns the native maximum address. The native maximum address is the highest
address accepted by the device in the factory default condition.
17. READ NATIVE MAX ADDRESS EXT (code: 27h);
This command returns the native maximum address.
18. READ SECTOR(S) (code: 20h or 21h);
This command reads from “1” to “256” sectors as specified in the Sector Count register. A sector count
of “0” requests “256” sectors transfer. The transfer begins at the sector specified in the Sector Number
register.
19. READ SECTOR(S) EXT (code: 24h);
This command reads from “1” to “65536” sectors as specified in the Sector Count register. A sector
count of “0” requests “65536” sectors transfer. The transfer begins at the sector specified in the Sector
Number register.
20. READ VERIFY SECTOR(S) (code: 40h or 41h);
This command is identical to the READ SECTORS command, except that DRQ is never set and no
data is transferred to the host.
21. READ VERIFY SECTOR(S) EXT (code: 42h);
This command is identical to the READ SECTORS command, except that DRQ is never set and no
data is transferred to the host.
22. RECALIBRATE (code: 1Xh);
This command return value is select address mode by the host request.
23. SECURITY DISABLE PASSWORD (code: F6h);
This command transfers 512 bytes of data from the host. Table defines the content of this information.
If the password selected by word 0 match the password previously saved by the device, the device
shall disable the Lock mode. This command shall not change the Master password. The Master
password shall be reactivated when a User password is set.
24. SECURITY ERASE PREPARE (code: F3h);
This command shall be issued immediately before the SECURITY ERASE UNIT command to enable
device erasing and unlocking.
25. SECURITY ERASE UNIT (code: F4h);
This command transfer 512 bytes of data from the host. Table## defines the content of this information.
If the password does not match the password previously saved by the device, the device shall reject
the command with command aborted.
The SECURITY ERASE PREPARE command shall be completed immediately prior to the SECURITY
ERASE UNIT command.
Specifications subject to change without notice, contact your sales representatives for the most update information.
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26. SECURITY FREEZE LOCK (code: F5h);
This command shall set the device to frozen mode. After command completion any other commands
that update the device Lock mode shall be command aborted. Frozen shall be disabled by power-off
or hardware reset.
If SECURITY FREEZE LOCK is issued when the drive is in frozen mode, the drive executes the
command and remains in frozen mode.
27. SECURITY SET PASSWORD (code: F1h);
This command transfer 512 bytes of data from the host. Table defines the content of this information.
The data transferred controls the function of this command. Table defines the interaction of the
identifier and security level bits.
28. SECURITY UNLOCK (code: F2h);
This command transfer 512 bytes of data from the host. Table (as Disable Password) defines the
content of this information.
If the Identifier bit is set to Master and the device is in high security level, then the password supplied
shall be compared with the stored Master password. If the device is in maximum security level then
the unlock shall be rejected.
If the identifier bit is set to user then the device shall compare the supplied password with the stored
User password.
If the password compare fails then the device shall return command aborted to the host and
decrements the unlock counter. This counter shall be initially set to five and shall be decremented for
each password mismatch when SECURITY UNLOCK is issued and the device is locked. When this
counter reaches zero then SECURITY UNLOCK and SECURITY ERASE UNIT command shall be
aborted until a power-on or hardware reset.
29. SEEK (code: 7Xh);
This command performs address range check.
30. SET MAX ADDRESS (code: F9h);
After successful command completion, all read and write access attempts to address greater than
specified by the successful SET MAX ADDRESS command shall be rejected with an IDNF error.
IDENTIFY DEVICE response words (61:60) shall reflect the maximum address set with this command.
31. SET MAX ADDRESS EXT (code: 37h);
After successful command completion, all read and write access attempts to address greater than
specified by the successful SET MAX ADDRESS command shall be rejected with an IDNF error.
IDENTIFY DEVICE response words (61:60) shall reflect the maximum address set with this command.
32. SET FEATURE (code: EFh);
This command is used by the host to establish parameters that affect the execution of certain device
features.
33. SET MULTIPLE MODE (code: C6h);
This command enables the device to perform READ and Write Multiple operations and establishes the
block count for these commands.
34. SLEEP (code: 99h or E6h);
This command causes the module to set BSY, enter the Sleep mode, clear BSY and generate an
interrupt.
35. SMART READ DATA (code: B0h with Feature register value of D0h);
This command returns the Device SMART data structure to the host.
Specifications subject to change without notice, contact your sales representatives for the most update information.
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36. SMART ENABLE/DISABLE AUTO SAVE (code: B0h with Feature register value of D2h);
This command enables and disables the optional attribute autosave feature of the device.
37. SMART EXECUTE OFF_LINE (code: B0h with Feature register value of D4h);
This command cause the device to immediately initiate the optional set of activities that collect
SMART data in an off-line mode and then save this data to the device’s non-volatile memory, or
execute a self-diagnostic test routine in either captive or off-line mode.
38. SMART READ LOG (code: B0h with Feature register value of D5h);
This command returns the specified log data to the host.
39. SMART ENABLE OPERATION (code: B0h with Feature register value of D8h);
This command enables access to all SMART capabilities within the device. Prior to receipt of this
command SMART data are neither monitored nor saved by the device.
40. SMART DISABLE OPERATION (code: B0h with Feature register value of D9h);
This command disables all SMART capabilities within the device including any and all timer and event
count functions related exclusively to this feature. After command acceptance the device shall disable
all SMART operations.
After receipt of this command by the device, all other SMART commands including SMART DISABLE
OPERATION commands, with exception of SMART ENABLE OPERATIONS, are disabled and invalid
and shall be command aborted by the device.
41. SMART RETURN STATUS (code: B0h with Feature register value of DAh);
This command causes the device to communicate the reliability status of the device to the host.
42. STANDBY (code: E2h);
This command causes the module to set BSY, enter the Standby mode, clear BSY and return the
interrupt immediately.
43. STANDBY IMMEDIATE (code: E0h);
This command causes the module to set BSY, enter the Standby mode, clear BSY and return the
interrupt immediately.
44. WRITE BUFFER (code: E8h);
This command enables the host to overwrite contents of the module’s sector buffer with any data
pattern desired.
45. WRITR DMA (code: CAh or CBh);
This command writes from “1” to “256” sectors as specified in the Sector Count register using the DMA
data transfer protocol. A sector count of “0” requests “256” sectors transfer. The transfer begins at the
sector specified in the Sector Number register.
46. WRITR DMA EXT (code: 35h);
This command writes from “1” to “65536” sectors as specified in the Sector Count register using the
DMA data transfer protocol. A sector count of “0” requests “65536” sectors transfer. The transfer
begins at the sector specified in the Sector Number register.
47. WRITE MULTIPLE (code: C5h);
This command is similar to the WRITE SECTORS command. Interrupts are not presented on each
sector, but on the transfer of a block which contains the number of sectors defined by Set Multiple
command.
48. WRITE MULTIPLE EXT (code: 39h);
This command is similar to the WRITE SECTORS command. Interrupts are not presented on each
sector, but on the transfer of a block which contains the number of sectors defined by Set Multiple
Specifications subject to change without notice, contact your sales representatives for the most update information.
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command.
49. WRITE SECTOR(S) (code: 30h);
This command writes from “1” to “256” sectors as specified in the Sector Count register. A sector count
of “0” requests “256” sectors transfer. The transfer begins at the sector specified in the Sector Number
register.
50. WRITE SECTOR(S) EXT (code: 34h);
This command writes from “1” to “65536” sectors as specified in the Sector Count register. A sector
count of “0” requests “65536” sectors transfer. The transfer begins at the sector specified in the Sector
Number register.
51. WRITE SECTOR(S) W/O ERASE (code: 38h);
This command writes from “1” to “256” sectors as specified in the Sector Count register. A sector count
of “0” requests “256” sectors transfer. The transfer begins at the sector specified in the Sector Number
register.
52. WRITE VERIFY (code: 3Ch);
This command is similar to the WRITE SECTOR(S) command, except that each sector is verified
before the command is completed.
Specifications subject to change without notice, contact your sales representatives for the most update information.
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CFast 640
8. System Power Consumption
8.1 Supply Voltage
Parameter
Rating
Operating Voltage
3.3V
8.2 Power Consumption
mA
Read
TBD
Write
TBD
Idle
Slumber
TBD
TBD
TBD
TBD
1.48
1.48
1.48
1.48
1.48
1.48
8 GB
16 GB
32 GB
64 GB
16 GB
32 GB
64 GB
32 GB
64 GB
128 GB
64 GB
128 GB
256 GB
TBD
TBD
TBD
TBD
SLC
TBD
TBD
TBD
TBD
TBD
TBD
348.48
315.15
330.30
348.48
315.15
330.30
333.33
368.18
446.97
333.33
368.18
446.97
87.88
78.79
78.79
87.88
78.79
78.79
Ultra MLC
MLC
383.31
393.94
412.12
387.31
409.09
436.36
90.00
90.00
92.00
3.03
3.03
3.49
3D NAND
(BiCS 3)
Specifications subject to change without notice, contact your sales representatives for the most update information.
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SQFlash
CFast 640
9. Physical Dimension
CFast (Unit: mm)
Specifications subject to change without notice, contact your sales representatives for the most update information.
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CFast 640
Appendix: Part Number Table
Product
Advantech PN
SQF CFast 640 16G UMLC (0~70°C)
SQF-S10U1-16G-SBC
SQF-S10U2-32G-SBC
SQF-S10U2-64G-SBC
SQF-S10U1-16G-SBE
SQF-S10U2-32G-SBE
SQF-S10U2-64G-SBE
SQF-S10M1-32G-SBC
SQF-S10M2-64G-SBC
SQF-S10M2-128G-SBC
SQF-S10M1-32G-SBE
SQF-S10M2-64G-SBE
SQF-S10M2-128G-SBE
SQF-S10V1-64G-SBC
SQF-S10V2-128G-SBC
SQF-S10V2-256G-SBC
SQF-S10V1-64G-SBE
SQF-S10V2-128G-SBE
SQF-S10V2-256G-SBE
SQF CFast 640 32G UMLC (0~70°C)
SQF CFast 640 64G UMLC (0~70°C)
SQF CFast 640 16G UMLC (-40~85°C)
SQF CFast 640 32G UMLC (-40~85°C)
SQF CFast 640 64G UMLC (-40~85°C)
SQF CFast 640 32G MLC (0~70°C)
SQF CFast 640 64G MLC (0~70°C)
SQF CFast 640 128G MLC (0~70°C)
SQF CFast 640 32G MLC (-40~85°C)
SQF CFast 640 64G MLC (-40~85°C)
SQF CFast 640 128G MLC (-40~85°C)
SQF CFast 640 64G 3D NAND (BiCS3) (0~70°C)
SQF CFast 640 128G 3D NAND (BiCS3) (0~70°C)
SQF CFast 640 256G 3D NAND (BiCS3) (0~70°C)
SQF CFast 640 64G 3D NAND (BiCS3) (-40~85°C)
SQF CFast 640 128G 3D NAND (BiCS3) (-40~85°C)
SQF CFast 640 256G 3D NAND (BiCS3) (-40~85°C)
Specifications subject to change without notice, contact your sales representatives for the most update information.
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