SQF-SM8V4-480G-SCC [ADVANTECH]
SQFlash;
| 型号： | SQF-SM8V4-480G-SCC |
| 厂家： | 
Advantech Co., Ltd. |
| 描述： | SQFlash |
| 文件： | 总27页 (文件大小：874K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SQFlash
M.2 2280 SATA SSD 840
M.2 2280 SATA SSD 840
Datasheet
(SQF-SM8x-xxx-SCx)
Specifications subject to change without notice, contact your sales representatives for the most update information.
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SQFlash
M.2 2280 SATA SSD 840
CONTENTS
1.Overview ............................................................................................ 4
2.Features ............................................................................................. 5
3.Specification Table............................................................................ 6
4.General Description .......................................................................... 8
5.Security Features ............................................................................ 11
6.Pin Assignment and Description................................................... 12
7.Identify Device Data ........................................................................ 15
8.ATA Command Set .......................................................................... 18
9.System Power Consumption ......................................................... 25
9.1 Supply Voltage .............................................................................................................. 25
9.2 Power Consumption...................................................................................................... 25
10. Physical Dimension...................................................................... 26
Appendix: Part Number Table ........................................................... 27
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SQFlash
M.2 2280 SATA SSD 840
Revision History
Rev.
0.1
0.2
Date
History
2018/5/18
2018/8/22
1. Preliminary
1. Update PN information
0.3
2019/7/15
1. Update produce information
Advantech reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or
design. Information furnished by Advantech is believed to be accurate and reliable. However, Advantech does not assure any liability
arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither
does it convey any license under its patent rights nor the rights of others.
Copyright © 1983-2019 Advantech Co., Ltd. All rights reserved.
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SQFlash
M.2 2280 SATA SSD 840
1. Overview
Advantech SQFlash 840 series M.2 2280 SATA-SSD (SQF-SM8 840) delivers all the advantages of Flash
Disk technology with the Serial ATA III (6.0Gb) interface, fully compliant with standard Next Generation Form
Factor (NGFF) M.2 2280 (B+M Key) form factor. The SATA SSD is designed to operate at a maximum operating
frequency of 300MHz with 30MHz external crystal. Its capacity could provide a wide range up to 2TB. Moreover, it
can reach up to 550MB/s read and 530MB/s write high performance based on Toshiba 64-layer 3D NAND Flash.
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SQFlash
M.2 2280 SATA SSD 840
2. Features
Standard SATA interface
–
–
Support SATA 1.5/3.0/6.0 Gbps interface
SATA Revision 3.2 compliant
Operating Voltage：3.3V
Support LDPC with RAID ECC
TRIM、AHCI、AES256 and OPAL supported
Hardware Quick Erase supported (optional)
Voltage Stabilizer supported (optional)
Temperature Ranges
–
Commercial Temperature1
● 0℃ to 70℃ for operating
● -40℃ to 85℃ for storage
–
Industrial Temperature1
● -40℃ to 85℃ for operating
● -40℃ to 85℃ for storage
Note: 1. Based on SMART Attribute C2h, which measured by thermal sensor
Mechanical Specification
–
Shock：1,500G / 0.5ms
–
Vibration：20G / 80~2,000Hz
Humidty
–
Humidity：5% ~ 95% under 55℃
Data Retention
–
10 years
Acquired RoHS、WHQL、CE、FCC Certificate
Acoustic：0 dB
Dimension：80.8 mm x 22.0 mm x 3.8 mm
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SQFlash
M.2 2280 SATA SSD 840
3. Specification Table
Performance
Sequential Performance
(MB/sec)
Random Performance (IOPS @4K)
Read
Write
Read
Write
240 GB
561.2
560.7
561.0
560.7
536.9
542.1
542.6
541.7
98,069
95,735
98,899
98,466
88,349
89,009
85,469
88,317
480 GB
960 GB
1920 GB
3D NAND
(BiCS3)
* Subject to change based on firmware migration
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SQFlash
M.2 2280 SATA SSD 840
Endurance
JEDEC defined an endurance rating TBW (TeraByte Written), following by the equation below, for indicating
the number of terabytes a SSD can be written which is a measurement of SSDs’ expected lifespan,
represents the amount of data written to the device.
TBW = [(NAND Endurance) x (SSD Capacity)] / WAF
NAND Endurance: Program / Erase cycle of a NAND flash.
o SLC: 100,000 cycles
o Ultra MLC: 30,000 cycles
o MLC: 3,000 cycles
o 3D NAND (BiCS3): 3,000 cycles
SSD Capacity: SSD physical capacity in total of a SSD.
WAF: Write Amplification Factor (WAF), as the equation shown below, is a numerical value
representing the ratio between the amount of data that a SSD controller needs to write and the
amount of data that the host’s flash controller writes. A better WAF, which is near to 1, guarantees
better endurance and lower frequency of data written to flash memory.
WAF = (Lifetime write to flash) / (Lifetime write to host)
Endurance measurement is based on New JEDEC 218/ 219 Client Workload and verified with following
workload conditions,
PreCond%full = 100%
Trim commands enabled
Random data pattern.
SQFlash 840 M.2 2280 SSD TBW
TBW
WAF
1.85
3D NAND (BiCS3)
240 GB
389
480 GB
960 GB
1920 GB
1.85
1.85
1.85
778
1556
3113
* Subject to change based on firmware migration
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SQFlash
M.2 2280 SATA SSD 840
4. General Description
Error Correction Code (ECC)
Flash memory cells will deteriorate with use, which might generate random bit errors in the stored data. Thus,
SQFlash 840 series SSD applies the LDPC with RAID ECC algorithm, which can detect and correct errors
occur during read process, ensure data been read correctly, as well as protect data from corruption.
Wear Leveling
NAND flash devices can only undergo a limited number of program/erase cycles, and in most cases, the
flash media are not used evenly. If some areas get updated more frequently than others, the lifetime of the
device would be reduced significantly. Thus, Wear Leveling is applied to extend the lifespan of NAND Flash
by evenly distributing write and erase cycles across the media.
SQFlash provides advanced Wear Leveling algorithm, which can efficiently spread out the flash usage
through the whole flash media area. Moreover, by implementing both dynamic and static Wear Leveling
algorithms, the life expectancy of the NAND flash is greatly improved.
Bad Block Management
Bad blocks are blocks that include one or more invalid bits, and their reliability is not guaranteed. Blocks that
are identified and marked as bad by the manufacturer are referred to as “Initial Bad Blocks”. Bad blocks that
are developed during the lifespan of the flash are named “Later Bad Blocks”. SQFlash implements an
efficient bad block management algorithm to detect the factory-produced bad blocks and manages any bad
blocks that appear with use. This practice further prevents data being stored into bad blocks and improves
the data reliability.
Power Loss Protection
– Flush Manager
Power Loss Protection is a mechanism to prevent data loss during unexpected power failure. DRAM is a
volatile memory and frequently used as temporary cache or buffer between the controller and the NAND
flash to improve the SSD performance. However, one major concern of the DRAM is that it is not able to
keep data during power failure. Accordingly, SQFlash SSD applies the Flush Manager technology, only when
the data is fully committed to the NAND flash will the controller send acknowledgement (ACK) to the host.
Such implementation can prevent false-positive performance and the risk of power cycling issues.
In addition, it is critical for a controller to shorten the time the in-flight data stays in the controller internal
cache. Thus, SQFlash applies an algorithm to reduce the amount of data resides in the cache to provide a
better performance. With Flush Manager, incoming data would only have a “pit stop” in the cache and then
move to NAND flash directly. Also, the onboard DDR will be treated as an “organizer” to consolidate
incoming data into groups before written into the flash to improve write amplification.
– Voltage Stabilizer
While the built-in voltage detector detects an unstable power input (< 3.135 V or > 3.465 V), the controller
will issue a power failure interrupt and force a Flush CMD first. At the same time, the whole internal power
supply will be switched to Voltage Stabilizer immediately to ensure stable power is supplied throughout the
whole drive. This ensures the Flash IC and DDR IC will not operate with unstable power which could lead to
data errors or bad data integrity.
TRIM
TRIM is a feature which helps improve the read/write performance and speed of solid-state drives (SSD).
Unlike hard disk drives (HDD), SSDs are not able to overwrite existing data, so the available space gradually
becomes smaller with each use. With the TRIM command, the operating system can inform the SSD which
blocks of data are no longer in use and can be removed permanently. Thus, the SSD will perform the erase
action, which prevents unused data from occupying blocks all the time.
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SQFlash
M.2 2280 SATA SSD 840
SMART
SMART, an acronym for Self-Monitoring, Analysis and Reporting Technology, is an open standard that allows
a hard disk drive to automatically detect its health and report potential failures. When a failure is recorded by
SMART, users can choose to replace the drive to prevent unexpected outage or data loss. Moreover,
SMART can inform users of impending failures while there is still time to perform proactive actions, such as
copy data to another device.
Over-Provision
Over Provisioning refers to the inclusion of extra NAND capacity in a SSD, which is not visible and cannot be
used by users. With Over Provisioning, the performance and IOPS (Input/Output Operations per Second)
are improved by providing the controller additional space to manage P/E cycles, which enhances the
reliability and endurance as well. Moreover, the write amplification of the SSD becomes lower when the
controller writes data to the flash.
Thermal Throttling
Thermal Throttling function is for protecting the drive and reducing the possibility of read / write error due to
overheat. The temperature is monitored by the thermal sensor. As the operating temperature continues to
increase to threshold temperature, the Thermal Throttling mechanism is activated. At this time, the
performance of the drive will be significantly decreased to avoid continuous heating. When the operating
temperature falls below threshold temperature, the drive can resume to normal operation.
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SQFlash
M.2 2280 SATA SSD 840
Block Diagram
LBA value
Density
240 GB
480 GB
960 GB
1920 GB
LBA
468,862,128
937,703,088
1,875,385,008
3,750,748,848
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SQFlash
M.2 2280 SATA SSD 840
5. Security Features
Advanced Encryption Standard (AES)
An AES 256-bit encryption key is generated in the drive's security controller before the data got stored on
the NAND flash. When the controller or firmware fails, the data that is securely stored in the encryption key
becomes inaccessible through the NAND flash.
Secure / Quick Erase (optional)
SQFlash 840 series supports standard SATA command secure erase. Also, with internal AES encryption
support, the erase process will start with resetting AES key. By doing so, existing data will be scrambled
within 10ms and cannot be recovered anymore. Moreover, erase flag is set when erase function is triggered,
which will ensure the whole erase process can be 100% completed. Even there’s power interrupt, after
power resume, erase operation will be resume right away as well.
TCG-OPAL 2.0 Compliance
TCG-OPAL compliance SED (Self-encryption Drive) supports a built-in shadow MBR to process user
authentication to SSD before booting to normal MRR area and OS. SQFlash 840 series supports such
feature with 100% TCG-OPAL compliance. Further, with SQFlash Flash Lock function, the user
authentication process in shadow MBR can be done automatically by bonding with motherboard unique ID
such as UUID in BIOS / MAC address / TPM unique code. So with Flash Lock enabled, only designated
motherboard can have access to the SSD.
Flash Vault
Flash Vault is to lock Read and Write command by SSD firmware setting and make the SSD need password
to verify and only operate with the corresponding platform. User can use Flash Vault to prevent data being
stolen by reading the SQFlash SSD with other computers and unauthorized person.
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SQFlash
M.2 2280 SATA SSD 840
6. Pin Assignment and Description
Pin #
SATA Pin
Description
Ground
CONFIG_3 = GND
1
2
3
4
5
6
7
8
9
3.3V
GND
Supply pin
Ground
3.3V
Supply pin
No Connect
No Connect
No Connect
No Connect
N/C
N/C
N/C
N/C
N/C or GND Note
No Connect or Ground
Status indicators via LED devices that will be provided by the
system Active Low. A pulled-up LED with series current
limiting resistor should allow for 9mA when On.
DAS/DSS# (O) (OD)
10
N/C
Module Key
Module Key
Module Key
Module Key
Module Key
Module Key
Module Key
Module Key
N/C
No Connect
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
No Connect
Ground
CONFIG_0 = GND
N/C
No Connect
No Connect
No Connect
No Connect
No Connect
Ground
N/C
N/C
N/C
N/C
GND
N/C
No Connect
No Connect
No Connect
No Connect
No Connect
Ground
N/C
N/C
N/C
N/C
GND
N/C
No Connect
No Connect
No Connect
N/C
N/C
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SQFlash
M.2 2280 SATA SSD 840
N/C
No Connect
37
38
Device Sleep, Input.
When driven high the host is informing the SSD to enter a
DEVSLP (I) (0/3.3V)
low power state (default NC, DEVSLP disable)
GND
N/C
Ground
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
No Connect
SATA-B+
N/C
SATA differential signals in the SATA specification
No Connect
SATA-B-
N/C
SATA differential signals in the SATA specification
No Connect
GND
N/C
Ground
No Connect
SATA-A-
N/C
SATA differential signals in the SATA specification
No Connect
SATA-A+
N/C
SATA differential signals in the SATA specification
No Connect
Ground
GND
N/C
No Connect
No Connect
No Connect
No Connect
N/C
N/C
N/C
Manufacturing Data line. Used for SSD manufacturing only.
Not used in normal operation. Pins should be left N/C in
platform Socket.
Reserved for MFG
Data
56
57
58
GND
Ground
Manufacturing Clock line. Used for SSD manufacturing only.
Not used in normal operation. Pins should be left N/C in
platform Socket
Reserved for MFG
Clock
Module Key
Module Key
Module Key
Module Key
Module Key
Module Key
Module Key
Module Key
N/C
59
60
61
62
63
64
65
66
67
No Connect
32 kHz clock supply input that is provided by PCH to reduce
power and cost for the module. (default NC)
SUSCLK (I) (0/3.3V)
68
CONFIG_1 = GND
Defines module type
Supply pin
69
70
71
72
3.3V
GND
3.3V
Ground
Supply pin
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SQFlash
M.2 2280 SATA SSD 840
GND
3.3V
Ground
Supply pin
Ground
73
74
75
CONFIG_2 = GND
NOTE: N/C for Socket 2, and GND for Socket 3.
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SQFlash
M.2 2280 SATA SSD 840
7. Identify Device Data
The Identity Device Data enables Host to receive parameter information from the device. The parameter
words in the buffer have the arrangement and meanings defined in below table. All reserve bits or words
are zero
Word
ATA Identify Parameter
Value
0 General configuration
0040h
3FFFh
C837h
0010h
0000h
003Fh
0000h
0000h
ASCII
1 Number of cylinders in the default CHS translation
2 Specific configuration
3 Number of heads in the default CHS translation
4-5 Retired
6 Number of sectors per track in the default CHS translation
7-8 Reserved for the CFA
9 Obsolete
10-19 Serial number
20 Retired
21 Retired
22 Obsolete
0000h
0000h
0000h
ASCII
23-26 Firmware revision
ASCII
27-46 Model number
47 READ/WRITE MULTIPLE commands function
48 Trusted Computing feature set options
49 Capabilities
8010h
4000h
2F00h
4000h
0000h
0007h
3FFFh
0010h
003Fh
00FBFC10h
0110h
*3
50 Capabilities
51-52 Obsolete
53 field validity
54 Number of cylinders in the current CHS translation
55 Number of heads in the current CHS translation
56 Number of sectors per track in the current CHS translation
57-58 Current capacity in sectors
59 Multiple sector setting
60-61 Total number of user addressable logical sectors for 28-bit commands
62 Obsolete
0000h
0407h
63 Multiword DMA modes
64 PIO mode supported
0003h
65 Minimum Multiword DMA transfer cycle time per word
66 Manufacturer's recommended Multiword DMA transfer cycle time
67 Minimum PIO transfer cycle time without flow control
68 Minimum PIO transfer cycle time with IORDY flow control
69 Additional Supported
0078h
0078h
0078h
0078h
5F20h
70-73 Reserved
0000h
74 Reserved
0000h
75 Queue depth
001Fh
76 Serial ATA Capabilities
E70Eh
77 Supported Serial ATA Phy speed
78 Serial ATA features supported
0006/0004/0002h
054Ch
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SQFlash
M.2 2280 SATA SSD 840
79 Serial ATA features enabled
80 Major version number
81 Minor version number
82 Commands and feature sets supported
83 Commands and feature sets supported
84 Commands and feature sets supported
85 Commands and feature sets supported or enabled
86 Commands and feature sets supported or enabled
87 Commands and feature sets supported or enabled
88 Ultra DMA modes
0040h
03F8h
0000h
746Bh
7D09h
4163h
7469h
BC09h
4163h
007Fh
89 Time required for Normal Erase mode SECURITY ERASE UNIT command
0001h
Time required for an Enhanced Erase mode SECURITY ERASE UNIT
command
90
0001h
91 Current APM level value
00FEh
FFFEh
0000h
0000h
0000h
0000h
0000h
0000h
*4
92 Master Password Identifier
93 Hardware reset result
94 Current AAM value
95 Stream Minimum Request Size
96 Streaming Transfer Time - DMA
97 Streaming Access Latency -DMA and PIO
98-99 Streaming Performance Granularity
100-103 Total Number of User Addressable Logical Sectors for 48-bit commands
104 Streaming Transfer Time - PIO
0000h
Maximum number of 512-byte blocks of LBA Range Entries per DATA
SET MANAGEMENT command
105
0008h
106 Physical sector size / logical sector size
107 Inter-seek delay for ISO 7999 standard acoustic testing
108-111 World wide name
112-115 Reserved
116 Reserved for TLC
117-118 Logical sector size
119 Commands and feature sets supported
120 Commands and feature sets supported or enabled
121-124 Reserved for expanded supported and enabled settings
125-126 Reserved for expanded supported and enabled settings
127 Obsolete
4000h
0000h
Vender Specific
0000h
0000h
0000h
401Ch
401Ch
0000h
0000h
0000h
0021h
0000h
0000h
0000h
0000h
0003h
0001h
0000h
0000h
0000h
0039h
128 Security status
129-159 Vendor specific
160 CFA power mode
161-164 Reserved for the CFA
165-167 Reserved for the CFA
168 Device Nominal Form Factor
169 DATA SET MANAGEMENT is supported
170-173 Additional Product Identifier
174-175 Reserved
176-205 Current media serial number
206 SCT Command Transport
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M.2 2280 SATA SSD 840
207-208 Reserved for CE-ATA
0000h
4000h
0000h
0000h
0000h
0000h
0001h
0000h
0000h
0000h
0000h
107Fh
0000h
0000h
0000h
0000h
209 Alignment of logical blocks within a physical block
210-211 Write-Read-Verify Sector Count Mode 3
212-213 Write-Read-Verify Sector Count Mode 2
214 NV Cache Capabilities
215-216 NV Cache Size in Logical Blocks
217 Nominal media rotation rate
218 Reserved
219 NV Cache Options
220 Current mode of the Write-Read-Verify feature set
221 Reserved
222 Transport major version number
223 Transport minor version number
224-227 Reversed for CE-ATA
228-229 Reversed for CE-ATA
230-233 Extend Number of User Addressable Sectors
Minimum number of 512-byte data blocks per DOWNLOAD
MICROCODE command for mode 03h
Maximum number of 512-byte data blocks per DOWNLOAD
MICROCODE command for mode 03h
234
0001h
FFFFh
235
236-239 Reserved
240-242 Reserved
0000h
0000h
Security feature
4000 : Self Encrypting Drive
243
4000h
244-247 Reserved
248-251 Reserved
252-254 Reserved
255 Integrity word
0000h
0000h
0000h
xxA5h
Capacity
(GB)
240
*1
(Word 1/Word 54)
3FFFh
*2
*3
*4
(Word 57 – 58)
(Word 60 – 61)
(Word 100 – 103)
FBFC10h
FFFFFFFh
1BF244B0h
480
3FFFh
FBFC10h
FFFFFFFh
37E436B0h
960
1920
3FFFh
3FFFh
FBFC10h
FBFC10h
FFFFFFFh
FFFFFFFh
6FC81AB0h
DF8FE2B0h
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SQFlash
M.2 2280 SATA SSD 840
8. ATA Command Set
[Command Set List]
Op-Code
Command Description
Op-Code
Command Description
Read FPDMA Queued
Write FPDMA Queued
Seek
00h
06h
10h
20h
21h
24h
25h
27h
29h
NOP
60h
61h
70h
90h
91h
92h
93h
B0h
B0h
Data Set Management
Recalibrate
Read Sectors
Execute Device Diagnostic
Initialize Device Parameters
Download Microcode
Download Microcode DMA
SMART
Read Sectors without Retry
Read Sectors EXT
Read DMA EXT
Read Native Max Address EXT
Read Multiple EXT
D0h
D1h
SMART READ DATA
SMART READ DATA ATTRIBUTE
THRESHOLD
2Fh
30h
31h
34h
Read Log EXT
B0h
B0h
B0h
B0h
SMART ENABLE/DISABLE ATTRIBUTE
AUTOSAVE
Write Sectors
D2h
D3h
D4h
Write Sectors without Retry
Write Sectors EXT
SMART SAVE ATTRIBUTE VALUES
SMART EXECUTE OFF-LINE
IMMEDIATE
35h
37h
39h
Write DMA EXT
B0h
B0h
B0h
B0h
B0h
D5h
D6h
D8h
D9h
DAh
SMART READ LOG
Set Native Max Address EXT
Write Multiple EXT
Write DMA FUA EXT
Write Long EXT
SMART WRITE LOG
SMART ENABLE OPERATIONS
SMART DISABLE OPERATIONS
SMART RETURN STATUS
3Dh
3Fh
SMART ENABLE/DISABLE
AUTOMATIC OFF-LINE
40h
41h
42h
45h
Read Verify Sectors
B0h
B1h
B1h
B1h
DBh
Read Verify Sectors without Retry
Read Verify Sectors EXT
Write Uncorrectable EXT
DEVICE CONFIGURATION OVERLAY
DEVICE CONFIGURATION RESTORE
C0h
C1h
DEVICE CONFIGURATION FREEZE
LOCK
47h
Read Log DMA EXT
Write Log DMA EXT
B1h
B1h
ECh
C2h
C3h
DEVICE CONFIGURATION IDENTIFY
DEVICE CONFIGURATION SET
Identify Device
57h
DEVICE CONFIGURATION IDENTIFY
DMA
B1h C4h
B1h C5h
C4h
DEVICE CONFIGURATION SET DMA EFh
Read Multiple EFh
Set Features
02h
Enable 8-bit PIO transfer mode
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SQFlash
M.2 2280 SATA SSD 840
Set transfer mode based on value in
Count field
C5h
Write Multiple
EFh
03h
Enable advanced power
management
C6h
C8h
C9h
Set Multiple Mode
Read DMA
EFh
EFh
EFh
05h
10h
Enable use of Serial ATA feature
Enable DMA Setup FIS Auto-Activate
optimization
Read DMA without Retry
10h 02h
Enable Device-initiated interface
power state (DIPM) transitions
CAh
Write DMA
EFh
10h 03h
Enable Software Settings
Preservation (SSP)
CBh
CEh
Write DMA without Retry
Write Multiple FUA EXT
EFh
EFh
10h 06h
10h 07h
Enable Device Automatic Partial to
Slumber transitions
E0h
E1h
Standby Immediate
Idle Immediate
EFh
EFh
10h 09h Enable Device Sleep
55h
66h
82h
85h
Disable read look-ahead feature
Disable reverting to power-on
defaults
E2h
E3h
E4h
Standby
Idle
EFh
EFh
EFh
Disable write cache
Disable advanced power
management
Read Buffer
E5h
E6h
Check Power Mode
Sleep
EFh
EFh
90h
Disable use of Serial ATA feature set
Disable DMA Setup FIS Auto-Activate
optimization
90h 02h
Disable Device-initiated interface
power state (DIPM) transitions
E7h
Flush Cache
EFh
90h 03h
Disable Software Settings
Preservation (SSP)
E8h
E9h
Write Buffer
EFh
EFh
90h 06h
90h 07h
Disable Device Automatic Partial to
Slumber transitions
Read Buffer DMA
EAh
EBh
Flush Cache EXT
EFh
EFh
90h 09h Disable Device Sleep
Write Buffer DMA
AAh
Enable read look-ahead feature
Enable
reverting
to
EFh
CCh
F4h
Security Erase Unit
power-on
defaults
F1h
F2h
F3h
Security Set Password
Security Unlock
F5h
F6h
F8h
Security Freeze Lock
Security Disable Password
Read Native Max Address
Security Erase Prepare
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Note: ND = Non-Data Command
PI = PIO Data-In Command
PO = PIO Data-Out Command
DM = DMA Command
DD = Execute Diagnostic Command
[Command Set Descriptions]
1. CHECK POWER MODE (code: E5h);
This command allows host to determine the current power mode of the device.
2. DOWNLOAD MICROCODE (code: 92h);
This command enables the host to alter the device’s microcode. The data transferred using the
DOWNLOAD MICROCODE command is vendor specific.
All transfers shall be an integer multiple of the sector size. The size of the data transfer is determined by
the content of the LBA Low register and the Sector Count register.
This allows transfer sizes from 0 bytes to 33,553,920 bytes, in 512bytes increments.
3. EXECUTE DEVICE DIAGNOSTIC (code: 90h);
This command performs the internal diagnostic tests implemented by the module.
4. FLUSH CACHE (code: E7h);
This command used by the host to request the device to flush the write cache.
5. FLUSH CACHE EXT (code: EAh);
This command is used by the host to request the device to flush the write cache. If there is data in the
write cache, that data shall be written to the media.
6. IDENTIFY DEVICE (code: ECh);
The IDENTIFY DEVICE command enables the host to receive parameter information from the module.
7. IDLE (code: 97h or E3h);
This command allows the host to place the module in the IDLE mode and also set the Standby timer.
INTRQ may be asserted even through the module may not have fully transitioned to IDLE mode. If the
Sector Count register is non-”0”, then the Standby timer shall be enabled. The value in the Sector Count
register shall be used to determine the time programmed into the Standby timer. If the Sector Count
register is “0” then the Standby timer is disabled.
8. IDLE IMMEDIATE (code: E1h);
This command causes the module to set BSY, enter the Idle (Read) mode, clear BSY and generate an
interrupt.
9. INITIALIZE DEVICE PARAMETERS (code: 91h);
This command enables the host to set the number of sectors per track and the number of heads per
cylinder.
10. NOP (code: 00h);
If this command is issued, the module respond with command aborted.
11. READ BUFFER (code: E4h);
This command enables the host to read the current contents of the module's sector buffer.
12. READ DMA (code: C8h or C9h);
This command reads from “1” to “256” sectors as specified in the Sector Count register using the DMA
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data transfer protocol. A sector count of “0” requests “256” sectors transfer. The transfer begins at the
sector specified in the Sector Number register.
13. READ DMA Ext (code: 25h);
This command allows the host to read data using the DMA data transfer protocol.
14. READ MULTIPLE (code: C4h);
This command performs similarly to the READ SECTORS command. Interrupts are not generated on
each sector, but on the transfer of a block which contains the number of sector per block is defined by the
content of word 59 in the IDENTIFY DEVICE response.
15. READ MULTIPLE EXT (code: 29h);
This command performs similarly to the READ SECTORS command. The number of sectors per block is
defined by a successful SET MULTIPLE command. If no successful SET MULTIPLE command has been
issued, the block is defined by the device’s default value for number of sectors per block as defined in
bits (7:0) in word 47 in the IDENTIFY DEVICE information.
16. READ NATIVE MAX ADDRESS (code: F8h);
This command returns the native maximum address. The native maximum address is the highest
address accepted by the device in the factory default condition.
17. READ NATIVE MAX ADDRESS EXT (code: 27h);
This command returns the native maximum address.
18. READ SECTOR(S) (code: 20h or 21h);
This command reads from “1” to “256” sectors as specified in the Sector Count register. A sector count of
“0” requests “256” sectors transfer. The transfer begins at the sector specified in the Sector Number
register.
19. READ SECTOR(S) EXT (code: 24h);
This command reads from “1” to “65536” sectors as specified in the Sector Count register. A sector count
of “0” requests “65536” sectors transfer. The transfer begins at the sector specified in the Sector Number
register.
20. READ VERIFY SECTOR(S) (code: 40h or 41h);
This command is identical to the READ SECTORS command, except that DRQ is never set and no data
is transferred to the host.
21. READ VERIFY SECTOR(S) EXT (code: 42h);
This command is identical to the READ SECTORS command, except that DRQ is never set and no data
is transferred to the host.
22. RECALIBRATE (code: 1Xh);
This command return value is select address mode by the host request.
23. SECURITY DISABLE PASSWORD (code: F6h);
This command transfers 512 bytes of data from the host. Table defines the content of this information. If
the password selected by word 0 match the password previously saved by the device, the device shall
disable the Lock mode. This command shall not change the Master password. The Master password
shall be reactivated when a User password is set.
24. SECURITY ERASE PREPARE (code: F3h);
This command shall be issued immediately before the SECURITY ERASE UNIT command to enable
device erasing and unlocking.
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25. SECURITY ERASE UNIT (code: F4h);
This command transfers 512 bytes of data from the host. Table## defines the content of this information.
If the password does not match the password previously saved by the device, the device shall reject the
command with command aborted.
The SECURITY ERASE PREPARE command shall be completed immediately prior to the SECURITY
ERASE UNIT command.
26. SECURITY FREEZE LOCK (code: F5h);
This command shall set the device to frozen mode. After command completion any other commands that
update the device Lock mode shall be command aborted. Frozen shall be disabled by power-off or
hardware reset.
If SECURITY FREEZE LOCK is issued when the drive is in frozen mode, the drive executes the
command and remains in frozen mode.
27. SECURITY SET PASSWORD (code: F1h);
This command transfers 512 bytes of data from the host. Table defines the content of this information.
The data transferred controls the function of this command. Table defines the interaction of the identifier
and security level bits.
28. SECURITY UNLOCK (code: F2h);
This command transfers 512 bytes of data from the host. Table (as Disable Password) defines the
content of this information.
If the Identifier bit is set to Master and the device is in high security level, then the password supplied
shall be compared with the stored Master password. If the device is in maximum security level then the
unlock shall be rejected.
If the identifier bit is set to user then the device shall compare the supplied password with the stored User
password.
If the password compare fails then the device shall return command aborted to the host and decrements
the unlock counter. This counter shall be initially set to five and shall be decremented for each password
mismatch when SECURITY UNLOCK is issued and the device is locked. When this counter reachs zero
then SECURITY UNLOCK and SECURITY ERASE UNIT command shall be aborted unitl a power-on or
a hardware reset.
29. SEEK (code: 7Xh);
This command performs address range check.
30. SET MAX ADDRESS (code: F9h);
After successful command completion, all read and write access attempts to address greater than
specified by the successful SET MAX ADDRESS command shall be rejected with an IDNF error.
IDENTIFY DEVICE response words (61:60) shall reflect the maximum address set with this command.
31. SET MAX ADDRESS EXT (code: 37h);
After successful command completion, all read and write access attempts to address greater than
specified by the successful SET MAX ADDRESS command shall be rejected with an IDNF error.
IDENTIFY DEVICE response words (61:60) shall reflect the maximum address set with this command.
32. SET FEATURE (code: EFh);
This command is used by the host to establish parameters that affect the execution of certain device
features.
33. SET MULTIPLE MODE (code: C6h);
This command enables the device to perform READ and Write Multiple operations and establishes the
block count for these commands.
34. SLEEP (code: 99h or E6h);
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This command causes the module to set BSY, enter the Sleep mode, clear BSY and generate an
interrupt.
35. SMART READ DATA (code: B0h with Feature register value of D0h);
This command returns the Device SMART data structure to the host.
36. SMART ENABLE/DISABLE AUTO SAVE (code: B0h with Feature register value of D2h);
This command enables and disables the optional attribute auto-save feature of the device.
37. SMART EXECUTE OFF_LINE (code: B0h with Feature register value of D4h);
This command causes the device to immediately initiate the optional set of activities that collect SMART
data in an off-line mode and then save this data to the device’s non-volatile memory, or execute a
self-diagnostic test routine in either captive or off-line mode.
38. SMART READ LOG (code: B0h with Feature register value of D5h);
This command returns the specified log data to the host.
39. SMART ENABLE OPERATION (code: B0h with Feature register value of D8h);
This command enables access to all SMART capabilities within the device. Prior to receipt of this
command SMART data are neither monitored nor saved by the device.
40. SMART DISABLE OPERATION (code: B0h with Feature register value of D9h);
This command disables all SMART capabilities within the device including any and all timer and event
count functions related exclusively to this feature. After command acceptance the device shall disable all
SMART operations.
After receipt of this command by the device, all other SMART commands including SMART DISABLE
OPERATION commands, with exception of SMART ENABLE OPERATIONS, are disabled and invalid
and shall be command aborted by the device.
41. SMART RETURN STATUS (code: B0h with Feature register value of DAh);
This command causes the device to communicate the reliability status of the device to the host.
42. STANDBY (code: E2h);
This command causes the module to set BSY, enter the Standby mode, clear BSY and return the
interrupt immediately.
43. STANDBY IMMEDIATE (code: E0h);
This command causes the module to set BSY, enter the Standby mode, clear BSY and return the
interrupt immediately.
44. WRITE BUFFER (code: E8h);
This command enables the host to overwrite contents of the module’s sector buffer with any data pattern
desired.
45. WRITR DMA (code: CAh or CBh);
This command writes from “1” to “256” sectors as specified in the Sector Count register using the DMA
data transfer protocol. A sector count of “0” requests “256” sectors transfer. The transfer begins at the
sector specified in the Sector Number register.
46. WRITR DMA EXT (code: 35h);
This command writes from “1” to “65536” sectors as specified in the Sector Count register using the DMA
data transfer protocol. A sector count of “0” requests “65536” sectors transfer. The transfer begins at the
sector specified in the Sector Number register.
47. WRITE MULTIPLE (code: C5h);
This command is similar to the WRITE SECTORS command. Interrupts are not presented on each sector,
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but on the transfer of a block which contains the number of sectors defined by Set Multiple command.
48. WRITE MULTIPLE EXT (code: 39h);
This command is similar to the WRITE SECTORS command. Interrupts are not presented on each sector,
but on the transfer of a block which contains the number of sectors defined by Set Multiple command.
49. WRITE SECTOR(S) (code: 30h);
This command writes from “1” to “256” sectors as specified in the Sector Count register. A sector count of
“0” requests “256” sectors transfer. The transfer begins at the sector specified in the Sector Number
register.
50. WRITE SECTOR(S) EXT (code: 34h);
This command writes from “1” to “65536” sectors as specified in the Sector Count register. A sector count
of “0” requests “65536” sectors transfer. The transfer begins at the sector specified in the Sector Number
register.
51. WRITE SECTOR(S) W/O ERASE (code: 38h);
This command writes from “1” to “256” sectors as specified in the Sector Count register. A sector count of
“0” requests “256” sectors transfer. The transfer begins at the sector specified in the Sector Number
register.
52. WRITE VERIFY (code: 3Ch);
This command is similar to the WRITE SECTOR(S) command, except that each sector is verified before
the command is completed.
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9. System Power Consumption
9.1 Supply Voltage
Parameter
Rating
Operating Voltage
3.3V
9.2 Power Consumption
(Unit: W)
240 GB
Read
3.0
Write
2.5
Idle
1.5
1.5
3D NAND
(BiCS3)
480 GB
3.0
2.5
960 GB
3.5
3.5
3.0
3.2
1.5
1.5
1920 GB
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10. Physical Dimension
M.2 2280 SATA SSD (Unit: mm)
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Appendix: Part Number Table
Product
Advantech PN
SQF M.2 2280 SATA SSD 840 (OPAL) 240G 3D NAND (0~70°C)
SQF M.2 2280 SATA SSD 840 (OPAL) 480G 3D NAND (0~70°C)
SQF M.2 2280 SATA SSD 840 (OPAL) 960G 3D NAND (0~70°C)
SQF M.2 2280 SATA SSD 840 (OPAL) 1920G 3D NAND (0~70°C)
SQF M.2 2280 SATA SSD 840 (OPAL) 240G 3D NAND (-40~85°C)
SQF M.2 2280 SATA SSD 840 (OPAL) 480G 3D NAND (-40~85°C)
SQF M.2 2280 SATA SSD 840 (OPAL) 960G 3D NAND (-40~85°C)
SQF M.2 2280 SATA SSD 840 (OPAL) 1920G 3D NAND (-40~85°C)
SQF-SM8V4-240G-SCC
SQF-SM8V4-480G-SCC
SQF-SM8V4-960G-SCC
SQF-SM8V4-1K9G-SCC
SQF-SM8V4-240G-SCE
SQF-SM8V4-480G-SCE
SQF-SM8V4-960G-SCE
SQF-SM8V4-1K9G-SCE
Specifications subject to change without notice, contact your sales representatives for the most update information.
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