AD1938XSTZ [ADI]
4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC; 4 ADC / DAC 8与PLL ， 192千赫， 24位编解码器
| 型号： | AD1938XSTZ |
| 厂家： | 
ADI |
| 描述： | 4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC |
| 文件： | 总30页 (文件大小：382K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4 ADC/8 DAC with PLL,
192 kHz, 24 Bit CODEC
Preliminary Technical Data
AD1935/AD1936/AD1937/AD1938/AD1939
Features
Applications
PLL generated (32-192kHz) or direct master clock
Low EMI design
109 dB DAC/ 107dB ADC Dynamic Range and SNR
-94dB THD+N
Automotive audio systems
Home theater systems
Set-top boxes
Digital audio effects processors
Single 3.3V Supply
Tolerance for 5V logic inputs
GENERAL DESCRIPTION
Supports 24-bits and 8 kHz - 192 kHz sample rates
Differential ADC input
The AD193X family are high performance, single-chip codecs that
provide 4 ADCs with differential input and 8 DACs with either
single-ended or differential output using ADI’s patented multibit
sigma-delta architecture. An SPI® or I2C® port is included, allowing
a microcontroller to adjust volume and many other parameters.
The AD193X family operates from 3.3V digital and analog supplies.
The AD193X is available in a 48-lead (SE output) or 64-lead
(differential output) LQFP package.
Single-ended or Differential DAC output versions
Log volume control with "auto-ramp" function
Hardware and software controllable clickless mute
Software and hardware power-down
Right justified, left justified, I2S and TDM Modes
Master and slave modes up to 16 channel in/out
48-lead LQFP or 64-lead LQFP plastic package
The AD193X is designed for low EMI. This consideration is
apparent in both the system and circuit design architectures. By
using the on-board PLL to derive master clock from L-R clock, the
AD193X eliminates the need for a separate high frequency master
clock. It can also be used with a suppressed bit clock. The D-A and
A-D converters are designed using the latest ADI continuous time
architectures to further minimize EMI. By using 3.3V supplies,
power consumption is minimized, further reducing emissions.
Functional Block Diagram
Digital Audio
Input/Output
AD193X
Serial Data Port
DAC
DAC
DAC
SDATAOUT
SDATAIN
ADC
Digital
Filter
Digital
Filter
DAC
DAC
DAC
DAC
DAC
Analog
Audio
ADC
Analog
Audio
Inputs
&
Volume
Control
CLOCKS
Outputs
ADC
ADC
Timing Management
&
Control
(Clock & PLL)
Precision
Voltage
Reference
Control Port
SPI / I2C
Control Data
Input/Output
Figure 1
Rev. PrI
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
Preliminary Technical Data
AD1935/AD1936/AD1937/AD1938/AD1939
AD193X—SPECIFICATIONS
Test Conditions, Unless Otherwise Noted.
Performance of all channels is identical (exclusive of the Inter-channel Gain Mismatch and Inter-channel Phase Deviation specifications).
Parameter
Rating
Supply Voltages (AVDD, DVDD)
Case Temperature
Master Clock
3.3 V
25°C
12.288 MHz (48 kHz fS, 256 × fS Mode)
Input Signal
1.000 kHz, 0 dBFS (Full Scale), -1 dBVrms (0.9Vrms)
Input Sample Rate
Measurement Bandwidth
Word Width
48 kHz
20 Hz to 20 kHz
24 Bits
Load Capacitance (Digital Output)
Load Current (Digital Output)
Input Voltage HI
50 pF
1 mA or 1.5kΩ to ½ DVDD supply
2.0 V
0.8 V
Input Voltage LO
Table 1
Analog Performance
Parameter
Min
Typ
Max
Unit
ADC Resolution (all ADCs)
24
Bits
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)1
No Filter (RMS)
102
105
107
–92
1.9
dB
With A-Weighted Filter (RMS)
With A-Weighted Filter (Avg)
Total Harmonic Distortion + Noise (–1 dBFS)1
Full-Scale Input Voltage (Differential)
Gain Error
dB
dB
dB
V rms
%
–5.0
–0.1
–10
+5.0
+0.1
+10
Interchannel Gain Mismatch
dB
ANALOG-TO-DIGITAL CONVERTERS
Offset Error
0
mV
ppm/°C
dB
Gain Drift
100
–110
70
Interchannel Isolation
CMRR, 100 mV RMS, 1 kHz
dB
CMRR, 100 mV RMS, 20 kHz
70
dB
Input Resistance
14
kΩ
pF
Input Capacitance
10
Input Common-Mode Bias Voltage
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)1
No Filter (RMS), Single-ended version
With A-Weighted Filter (RMS), Single-ended version
With A-Weighted Filter (Avg), Single-ended version
No Filter (RMS), Differential version
With A-Weighted Filter (RMS), Differential version
With A-Weighted Filter (Avg), Differential version
Total Harmonic Distortion + Noise (0 dBFS)1
Single-ended version
1.5
V
DIGITAL-TO-ANALOG CONVERTERS
101
104
106
104
107
109
dB
dB
dB
dB
dB
dB
–92
dB
Differential version
–94
dB
Full-Scale Output Voltage (Single-ended version)
Full-Scale Output Voltage (Differential version)
Gain Error
0.9 (2.5)
1.8 (5.0)
TBD
V rms (V pp)
V rms (V pp)
%
-6%
+6%
1 Total harmonic distortion + noise and dynamic range typical specifications are for two channels active, max/min are all channels active.
Rev. PrI | Page 2 of 30
Preliminary Technical Data
AD1935/AD1936/AD1937/AD1938/AD1939
Parameter
Min
Typ
Max
Unit
dB
Interchannel Gain Mismatch
-0.5
+0.5
Offset Error, Single-ended version
Offset Error, Differential version
Gain Drift
-15
-10
mV
mV
ppm/°C
dB
-30
30
Interchannel Isolation
100
0
Interchannel Phase Deviation
Volume Control Step
Degrees
dB
0.375
95
Volume Control Range
dB
De-emphasis Gain Error
0.6
dB
Output Resistance at Each Pin
Internal Reference Voltage, FILTR
External Reference Voltage, FILTR
Common-Mode Reference Output, CM
100
1.50
1.50
1.50
Ω
V
REFERENCE
0.90
1.80
V
V
Table 2
Crystal Oscillator
Parameter
Min
Typ
Max
Unit
Transconductance
10
mmhos
Table 3
Digital I/O
Parameter
Min
Typ
Max
Unit
V
Input Voltage HI (VIH)
2.0
Input Voltage LO (VIL)
0.8
10
10
V
Input Leakage (IIH @ VIH = 2.4 V)
Input Leakage (IIL @ VIL = 0.8 V)
High Level Output Voltage (VOH) IOH = 4 mA
Low Level Output Voltage (VOL) IOL = 4 mA
Input Capacitance
µA
µA
V
DVDD – 0.5
0.5
5
V
pF
Table 4
Power Supplies
Parameter
Min
3.0
Typ
Max
Unit
V
Voltage, DVDD
3.3
3.6
3.6
Voltage, AVDD
3.0
3.3
V
Digital Current
56
mA
mA
mA
mA
mA
mA
mW
mW
mW
mW
dB
Digital Current—Power-Down
Digital Current—Reset
Analog Current
TBD
TBD
74
Supplies
Analog Current—Power-Down
Analog Current—Reset
Operation—All Supplies
Operation—Digital Supply
Operation—Analog Supply
Power-Down—All Supplies
TBD
TBD
429
185
244
TBD
TBD
TBD
Dissipation
1 kHz 200 mV p-p Signal at Analog Supply Pins
20 kHz 200 mV p-p Signal at Analog Supply Pins
Power Supply Rejection Ratio
dB
Table 5
Rev. PrI | Page 3 of 30
Preliminary Technical Data
AD1935/AD1936/AD1937/AD1938/AD1939
Temperature Range
Parameter
Min
Typ
Max
Unit
Specifications Guaranteed
25
°C Case
°C Ambient
°C Case
°C
–40
–40
–65
+105
+125
+150
Functionality Guaranteed
Storage
Table 6
Digital Filters
Mode
Parameter
Factor
Min
Typ
21
0.015
Max
Unit
kHz
dB
Pass Band
0.4375 fS
Pass-Band Ripple
Transition Band
Stop Band
ADC
DECIMATION
FILTER
All Modes,
Typ @ 48 kHz
0.5 fS
24
27
kHz
kHz
dB
0.5625 fS
Stop-Band Attenuation
Group Delay
79
70
70
70
22.9844/ fS
0.4535 fS
479
22
µs
Pass Band
kHz
dB
Pass-Band Ripple
Transition Band
Stop Band
0.01
48 kHz Mode,
Typ @ 48 kHz
0.5 fS
24
26
kHz
kHz
dB
0.5465 fS
Stop-Band Attenuation
Group Delay
25/ fS
521
35
µs
Pass Band
0.3646 fS
kHz
dB
Pass-Band Ripple
Transition Band
Stop Band
0.05
DAC
INTERPOLATION
FILTER
96 kHz Mode,
Typ @ 96 kHz
0.5 fS
48
61
kHz
kHz
dB
0.6354 fS
Stop-Band Attenuation
Group Delay
11/ fS
115
70
µs
Pass Band
0.3646 fS
kHz
dB
Pass-Band Ripple
Transition Band
Stop Band
0.1
192 kHz Mode,
Typ @ 192 kHz
0.5 fS
96
kHz
kHz
dB
0.6354 fS
122
Stop-Band Attenuation
Group Delay
8/ fS
42
µs
Table 7
Timing Specifications
Parameter
Comments
Min
Max
Unit
tMH
MCLK High
MCLK Low
MCLK Period
PLL Mode
PLL Mode
15
15
73
6.9
15
15
36
ns
tML
ns
tMCLK
fMCLK
tMH
PLL Mode, 256 fS reference
PLL Mode, 256 fS reference
Direct 512 fS Mode
146
ns
MCLK Frequency
MCLK High
13.8
MHz
ns
MASTER CLOCK AND RESET
tML
MCLK Low
Direct 512 fS Mode
ns
tMCLK
fMCLK
tPDR
tPDRR
tCCH
tCCL
MCLK Period
MCLK Frequency
Direct 512 fS Mode
ns
Direct 512 fS Mode
27.6
MHz
ns
PD/RST
PD/RST
TBD
TBD
TBD
TBD
50
Low
Reset to Active Output
tMCLK
ns
Recovery
SPI PORT
CCLK High
CCLK Low
CCLK Period
ns
tCCP
ns
Rev. PrI | Page 4 of 30
Preliminary Technical Data
AD1935/AD1936/AD1937/AD1938/AD1939
Parameter
fCCLK
tCDS
Comments
Min
Max
Unit
MHz
ns
CCLK Frequency
CDATA Setup
CDATA Hold
20
To CCLK Rising
TBD
TBD
TBD
TBD
TBD
tCDH
From CCLK Rising
To CCLK Rising
ns
tCLS
CLATCH
CLATCH
CLATCH
ns
Setup
Hold
High
tCLH
From CCLK Falling
ns
tCLH
ns
tCOE
COUT Enable
COUT Delay
From CCLK Falling
From CCLK Falling
From CCLK Falling
From CCLK Falling
TBD
TBD
ns
tCOD
ns
tCOH
COUT Hold
TBD
ns
tCOTS
fSCL
COUT Three-State
TBD
400
ns
SCL Clock
Frequency
kHz
tSCLH
tSCLL
tSCS
SCL High
SCL Low
0.6
1.3
0.6
µS
µS
µS
Setup Time
Relevant for Repeated Start
Condition
tSCH
Hold Time
After this period the 1st clock is
generated
0.6
µS
I2C PORT
tDS
Data Setup Time
SCL Rise Time
SCL Fall Time
SDA Rise Time
SDA Fall Time
Setup Time
100
ns
ns
ns
ns
ns
µS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Start Condition
tSCR
tSCF
tSDR
tSDF
tSCS
tDBH
tDBL
fDB
300
300
300
300
Stop Condition
Slave Mode
0.6
DBCLK High
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
DBCLK Low
DBCLK Frequency
DLRCLK Setup
DLRCLK Hold
DLRCLK Skew
DSDATA Setup
DSDATA Hold
ABCLK High
tDLS
tDLH
tDLS
tDDS
tDDH
tABH
tABL
fDB
To DBCLK Rising
DAC SERIAL PORT
From DBCLK Rising
From DBCLK Falling
To DBCLK Rising
Master Mode
TBD
From DBCLK Rising
ABCLK Low
Slave Mode
ABCLK Frequency
ALRCLK Setup
ALRCLK Hold
ALRCLK Skew
ASDATA Delay
AAUXDATA Setup
AAUXDATA Hold
DAUXDATA Delay
AUXBCLK High
AUXBCLK Low
ADC SERIAL PORT
tALS
tALH
tALS
tABDD
tAXDS
tAXDH
tDXDD
tXBH
tXBL
fXB
To ABCLK Rising
From ABCLK Rising
From ABCLK Falling
From ABCLK Falling
To AUXBCLK Rising
From AUXBCLK Rising
From AUXBCLK Falling
Master Mode
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
AUXILIARY INTERFACE
AUXBCLK
Frequency
tDLS
tDLH
AUXLRCLK Setup
AUXLRCLK Hold
To AUXBCLK Rising
TBD
TBD
ns
ns
From AUXBCLK Rising
Table 8
Rev. PrI | Page 5 of 30
Preliminary Technical Data
AD1935/AD1936/AD1937/AD1938/AD1939
ABSOLUTE MAXIMUM RATINGS
Package Characteristics
Parameter
Min Typ
Max Unit
Parameter
Min
–0.3
–0.3
Max
Unit
V
50.1
°C/W
Analog (AVDD)
+3.6
θJA (Thermal Resistance
[Junction to Ambient]), 48-lead LQFP
Digital (DVDD)
+3.6
V
17
°C/W
°C/W
°C/W
θJC (Thermal Resistance
[Junction to Case]), 48-lead LQFP
Input Current (Except Supply Pins)
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
Case Temperature (Operating)
20
mA
V
–0.3
–0.3
–40
AVDD + 0.3
DVDD + 0.3
+125
47
θJA (Thermal Resistance
[Junction to Ambient]), 64-lead LQFP
V
°C
11.1
θJC (Thermal Resistance
[Junction to Case]), 64-lead LQFP
Table 9
Note: Characteristics are for a 4-layer board
Stresses above those listed under the Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating
only; functional operation of the device at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Table 10
Rev. PrI | Page 6 of 30
Preliminary Technical Data
AD1935/AD1936/AD1937/AD1938/AD1939
Figure 2. ADC Passband Filter Response, 48 kHz
Figure 3. ADC Stopband Filter Response, 48 kHz
Figure 4. DAC Passband Filter Response, 48 kHz
Figure 5. DAC Stopband Filter Response, 48 kHz
Figure 6. DAC Passband Filter Response, 96 kHz
Figure 7. DAC Stopband Filter Response, 96 kHz
Rev. PrI | Page 7 of 30
Preliminary Technical Data
AD1935/AD1936/AD1937/AD1938/AD1939
Figure 8. DAC Passband Filter Response, 192 kHz
Figure 9. DAC Stopband Filter Response, 192 kHz
Rev. PrI | Page 8 of 30
Preliminary Technical Data
AD1935/AD1936/AD1937/AD1938/AD1939
FUNCTIONAL OVERVIEW
ADCs
rate or low bandwidth may cause high frequency noise and tones to
fold down into the audio band; care should be exercised in selecting
these components.
There are four ADC channels in the AD193X configured as two
stereo pairs with differential inputs. The ADCs can operate at a
nominal sample rate of 48, 96 , or 192 kHz. The ADCs include on-
board digital anti-aliasing filters with 79 dB stop-band attenuation
and linear phase response, operating at an oversampling ratio of
128 (48 kHz, 96 kHz, and 192 kHz modes). Digital outputs are
supplied through two serial data output pins (one for each stereo
pair) and a common frame (ALRCLK) and bit (ABCLK) clock.
Alternatively, one of the TDM modes may be used to access up to
16 channels on a single TDM data line.
The voltage at the common-mode reference pin, CM can be used to
bias the external op amps that buffer the output signals (see the
Power Supply and Voltage Reference section).
Clock Signals
The on-chip Phase Locked Loop (PLL) can be selected to use as its
reference the input sample rate from either of the LRCLK pins or
256, 384, 512, or 768 times the sample rate, referenced to 48kHz
mode, from the MCLKI pin. The default at power-up is 256 × fS
from MCLKI. In 96 kHz mode, the master clock frequency will stay
at the same absolute frequency so the actual multiplication rate will
be divided by 2. In 192 kHz mode, the actual multiplication rate will
be divided by 4. For example, if the AD193X is programmed in 256
× fS mode, the frequency of the master clock input would be 256 ×
48 kHz = 12.288 MHz. If the AD193X is then switched to 96 kHz
operation (by writing to the SPI or I2C port), the frequency of the
master clock should remain at 12.288 MHz, which is now 128 × fS.
In 192kHz mode, this would be 64 × fS.
The ADCs must be driven from a differential signal source for best
performance. The input pins of the ADCs connect to internal
switched capacitors. To isolate the external driving op amp from the
“glitches” caused by the internal switched capacitors, each input pin
should be isolated by using a series-connected external 100
Ω resistor together with a 1 nF capacitor connected from each
input to ground. This capacitor must be of high quality; for
example, ceramic NPO or polypropylene film.
The differential inputs have a nominal common-mode voltage of
1.5V. The voltage at the common-mode reference pin, CM can be
used to bias external op amps to buffer the input signals (see the
Power Supply and Voltage Reference section). The inputs can also
be AC coupled and do not need an external DC bias to CM.
The internal clock for the ADCs is 256 × fS for all clock modes. The
internal clock for the DACs is 512 × fS (48 kHz mode), 256 × fS (96
kHz mode), or 128 × fS (192 kHz mode). By default, the on-board
PLL is used to generate this internal master clock from an external
clock. A direct 512 × fS ( referenced to 48 kHz mode) master clock
can be used for either the ADCs or DACs if selected in PLL and
Clock Control Register 1.
A digital high-pass filter can be switched in line with the ADCs
under serial control to remove residual dc offsets. It has a 1.4 Hz,
6 dB per octave cutoff at a 48 kHz sample rate. The cutoff
frequency will scale directly with sample frequency.
Note that it is not possible to use a direct clock for the ADCs set to
192kHz mode. It is required that the on-chip PLL be used in this
mode.
DACs
The AD193X DAC channels are arranged as four stereo pairs
giving eight analog outputs, either single-ended for minimum
external components or differential for improved noise and
distortion performance. The DACs include on-board digital
reconstruction filters with 70 dB stop-band attenuation and linear
phase response, operating at an oversampling ratio of 4 (48 kHz or
96 kHz modes) or 2 (192 kHz mode). Each channel has its own
independently programmable attenuator, adjustable in 255 0.375 dB
steps. Digital inputs are supplied through four serial data input pins
(one for each stereo pair) and a common frame (DLRCLK) and bit
(DBCLK) clock. Alternatively, one of the TDM modes may be used
to access up to 16 channels on a single TDM data line.
The PLL can be powered down in PLL and Clock Control Register
0. To ensure reliable locking when changing PLL modes or if the
reference clock may be unstable at power-on, the PLL should be
powered down and then powered back up when the reference clock
is stable.
The internal MCLK can be disabled in PLL and Clock Control
Register 0 to reduce power dissipation when the AD193X is idle.
The clock should be stable before it is enabled. Unless a stand-
alone mode is selected (see Serial Control Port), the clock is
disabled by reset and must be enabled by writing to the SPI or I2C
port for normal operation.
Each output pin has a nominal common-mode dc level of 1.5V and
swings 1.27 V for a 0 dBFS digital input signal. A single op amp
third order external low-pass filter is recommended to remove high
frequency noise present on the output pins, as well as to provide
differential-to-single-ended conversion in the case of the
To maintain the highest performance possible, it is recommended
that the clock jitter of the internal master clock signal be limited to
less than 300 ps rms TIE (time interval error). Even at these levels,
extra noise or tones may appear in the DAC outputs if the jitter
spectrum contains large spectral peaks. If the internal PLL is not
being used, it is highly recommended that an independent crystal
differential output part. Note that the use of op amps with low slew
Rev. PrI | Page 9 of 30
Preliminary Technical Data
AD1935/AD1936/AD1937/AD1938/AD1939
oscillator generate the master clock. In addition, it is especially
important that the clock signal should not be passed through an
FPGA, CPLD, or other large digital chip (such as a DSP) before
being applied to the AD193X. In most cases, this will induce clock
jitter due to the sharing of common power and ground connections
with other unrelated digital output signals. When the PLL is used,
jitter in the reference clock will be attenuated above a certain
frequency depending on the loop filter.
permits programming and reading back the internal control
registers for the ADCs, DACs, and clock system. There is also a
stand-alone mode available for operation without serial control,
configured at reset using the serial control pins. All registers are set
to default except Internal MCLK Enable is set to 1 and ADC BCLK
and LRCLK Master/Slave is set by COUT/SDA. Refer to Table 10
for details.
CLATCH/ADR1
CIN/ADR0
COUT/SDA
CCLK/SCL
ADC
Clocks:
Reset and Power-Down
Slave
Master
0
0
0
1
0
0
0
0
Reset will set all the control registers to their default settings. To
avoid pops, reset does not power down the analog outputs. After
reset is de-asserted, an initialization routine will run inside the
AD193X. This initialization lasts for approximately XX MCLKs.
Table 11. Stand-alone Mode Selection
The SPI control port of the AD1938 and AD1939 is a 4-wire serial
control port. The format is similar to the Motorola SPI format
except the input data-word is 24 bits wide. The serial bit clock and
latch may be completely asynchronous to the sample rate of the
ADCs and DACs. Figure 10 shows the format of the SPI signal. The
first byte is a global address with a read/write bit. For the AD193X
the address is 0x04, shifted left 1 bit due to the R/W bit. The
second byte is the AD193X register address and the third byte is the
data.
The power-down bits in the PLL and Clock Control 0, DAC
Control 1, and ADC Control 1 registers will power down the
respective sections. All other register settings are retained.
Serial Control Port
The AD193X has an SPI or I2C compatible control port that
tCLS
tCLH
tCCH tCCL
tCCP
CLATCH
CCLK
tCOTS
tCDH
tCDS
D9
D9
D8
CIN
D15
D14
D0
D0
tCOE
COUT
D8
tCOD
Figure 10. Format of SPI Signal
AD1936 and AD1937 which register is required to be written to.
The I2C interface of the AD1936 and AD1937 is a two wire
Another ACK is issued by the AD1936 and AD1937. Finally the
user can send another frame with the 8 data bits required to be
written to the register. A third ACK is issued by the AD1936 and
AD1937 after which the user can send a STOP condition to
complete the data transfer.
interface consisting of a clock line, SCL and a data line, SDA. SDA is
bidirectional and the AD1936 and AD1937 will drive SDA either to
acknowledge the master, ACK, or to send data during a read
operation. The SDA pin for the I2C port is an open drain collector
and requires a 1KΩ pullup resistor. A write or read access occurs
when the SDA line is pulled low while the SCL line is high
A read operation requires that the user first write to the AD1936
and AD1937 to point to the correct register and then read the data.
This is achieved by sending a START condition followed by the
device address frame, with R/W low, and then the register address
frame. Following the ACK from the AD1936 and AD1937 the user
must issue a REPEATED START condition. This is identical to a
START condition. The next frame is the device address with R/W
set high. On the next frame the AD1936 and AD1937 will output
the register data on the SDA line. A STOP condition completes the
read operation. Figure 3 and Figure 4 show examples of writing to
and reading from the DAC 1 Left Volume Register (address = 0x06)
indicated by START in the timing diagrams. SDA is only allowed to
change when SCL is low except when a START or STOP condition
occurs as shown in figures 3 and 4. The first eight bits of the access
consist of the device address and the R/W bit. The device address
consists of an internal built-in address (0x04) and two address pins,
AD1 and AD0. The two address pins allow up to four AD1936s and
AD1937s to be used in a system. Initiating a write operation to the
AD1936 and AD1937 involves sending a START condition and
then sending the device address with the R/W set low. The AD1936
and AD1937 will respond by issuing an ACK to indicate that it has
been addressed. The user then sends a second frame telling the
Rev. PrI | Page 10 of 30
Preliminary Technical Data
AD1935/AD1936/AD1937/AD1938/AD1939
SCK
0
0
0
1
SDA
0
0
0
1
AD1
AD0
0
0
0
1
R/W
0
ACK. BY
AD193X
ACK. BY
AD193X
START BY
MASTER
FRAME 2
FRAME 1
CHIP ADDRESS BYTE
REGISTER ADDRESS BYTE
SCK
(CONTINUED)
SDA
D2
D5
D4
D3
D1
D0
D7
D6
(CONTINUED)
ACK. BY
AD193X
STOP BY
MASTER
FRAME 3
DATA BYTE TO
AD193X
Figure 11. Format of I2C Write
SCL
SDA
0
0
0
1
0
0
0
1
AD1
AD0
0
0
0
1
R/W
0
ACK. BY
AD193X
START BY
MASTER
ACK. BY
AD193X
FRAME 2
REGISTER ADDRESS BYTE
FRAME 1
CHIP ADDRESS BYTE
SCL
(Continued)
SDA
0
0
0
1
AD0
0
AD1
R/W
D4
D2
D7
D5
D3
D1
D0
D6
(Continued)
ACK. BY
AD193X
ACK. BY
AD193X
REPEATED START
STOP BY
MASTER
BY MASTER
FRAME 4
FRAME 3
CHIP ADDRESS BYTE
REGISTER DATA
Figure 12. Format of I2C Read
outputs are driven from the 3.3 V DVDD supply and are
compatible with TTL and 3.3 V CMOS levels.
Power Supply and Voltage Reference
The AD193X is designed for 3.3 V supplies. Separate power supply
pins are provided for the analog and digital sections. These pins
should be bypassed with 100 nF ceramic chip capacitors, as close to
the pins as possible, to minimize noise pickup. A bulk aluminum
electrolytic capacitor of at least 22 µF should also be provided on
the same PC board as the codec. For critical applications, improved
performance will be obtained with separate supplies for the analog
and digital sections. If this is not possible, it is recommended that
the analog and digital supplies be isolated by means of a ferrite
bead in series with each supply. It is important that the analog
supply be as clean as possible.
The ADC and DAC internal voltage reference VREF is brought out
on FILTR and should be bypassed as close as possible to the chip,
with a parallel combination of 10 µF and 100 nF. Any external
current drawn should be limited to less than 50 µA.
The internal reference can be disabled in PLL and Clock Control
Register 1 and FILTR driven from an external source. This can be
used to scale the DAC output to a power amplifier's clipping level
based on its power supply voltage. The ADC input gain will also
vary by the inverse ratio. The total gain from ADC input to DAC
output will stay constant.
The AD1935 (64-pin single-ended version), and the AD1939 and
AD1937 (64-pin differential versions) include a 3.3V regulator
driver which requires only an external pass transistor and bypass
capacitors to make a 5V to 3.3V regulator. If the regulator driver is
not used, VSUPPLY, VDRIVE, and VSENSE should be connected to
DGND.
The CM pin is the internal common-mode reference. It should be
bypassed as close as possible to the chip, with a parallel
combination of 10 µF and 100 nF. This voltage may be used to bias
external op amps to the common-mode voltage of the input and
output signal pins. The output current should be limited to less
than 0.5 mA source and 2 mA sink.
All digital inputs are compatible with TTL and CMOS levels. All
Rev. PrI | Page 11 of 30
Preliminary Technical Data
AD1935/AD1936/AD1937/AD1938/AD1939
at 48 kHz, 8 channels at 96 kHz or 4 channels at 192 kHz. There is
also a dual-line TDM mode to support 8 channels at 192 kHz.
Serial Data Ports—Data Format
The eight DAC channels output or accept a common serial bit clock
and left-right framing clock to clock in the serial data. The four
ADC channels output or accept a common serial bit clock and left-
right framing clock to clock out the data. The clock signals are all
synchronous with the sample rate. In the AUX Modes, set in ADC
Control 1 and DAC Control 0, the DACs use the ADC serial bit
clock and left-right clock as the DAC clock pins are used for the
auxiliary ADC/DAC serial clocks.
The special auxiliary modes are provided to allow two external
stereo ADCs and/or two external stereo DACs to be interfaced with
the AD193X to provide up to 8 in/12 out operation or 2 AD193Xs
to be chained for up to 16 in/16 out operation. These modes
provide a glueless interface to a single SHARC serial port, allowing
the DSP to access up to 16 channels of analog I/O. In these modes
many pins are redefined, see table 10. See Figure 18 for details of
these modes.
The ADC and DAC serial data modes default to I2S. The ports can
also be programmed for left-justified, right-justified and TDM
modes. The word width is 24 bits by default and can be
The following figures show the serial mode formats.
programmed for 16 or 20 bits. The normal TDM mode can be
daisy-chained with a second AD193X and will support 16 channels
LRCLK
BCLK
LEFT CHANNEL
RIGHT CHANNEL
SDATA
MSB
LSB
MSB
LSB
LEFT JUSTIFIED MODE––16 BITS TO 24 BITS PER CHANNEL
LEFT CHANNEL
LRCLK
BCLK
RIGHT CHANNEL
LSB
MSB
LSB
MSB
SDATA
2
I
S MODE––16 BITS TO 24 BITS PER CHANNEL
RIGHT CHANNEL
LEFT CHANNEL
LRCLK
BCLK
MSB
LSB
MSB
LSB
SDATA
RIGHT JUSTIFIED MODE––SELECT NUMBER OF BITS PER CHANNEL
LRCLK
BCLK
SDATA
MSB
LSB
MSB
LSB
DSP MODE––16 BITS TO 24 BITS PER CHANNEL
1/f
S
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL
2. LRCLK NORMALLY OPERATES AT f EXCEPT FOR DSP MODE WHICH IS 2 × f
S
S
3. BCLK FREQUENCY IS NORMALLY 64 × LRCLK BUT MAY BE OPERATED IN BURST MODE
Figure 13. Stereo Serial Modes
Rev. PrI | Page 12 of 30
Preliminary Technical Data
AD1935/AD1936/AD1937/AD1938/AD1939
tDBH
tDBP
DBCLK
tDBL
tDLS
tDLH
DLRCLK
tDDS
DSDATA
LEFT-JUSTIFIED
MODE
MSB
tDDH
MSB-1
tDDS
MSB
tDDH
DSDATA
2
I S-JUSTIFIED
MODE
tDDS
LSB
tDDH
tDDS
MSB
tDDH
DSDATA
RIGHT-JUSTIFIED
MODE
Figure 14. DAC Serial Timing
tABH
tABP
ABCLK
tABL
tALS
tALH
ALRCLK
tABDD
ASDATA
LEFT-JUSTIFIED
MODE
MSB
MSB-1
tABDD
ASDATA
2
I S-JUSTIFIED
MSB
MODE
tABDD
ASDATA
RIGHT-JUSTIFIED
MODE
LSB
MSB
Figure 15. ADC Serial Timing
Rev. PrI | Page 13 of 30
Preliminary Technical Data
AD1935/AD1936/AD1937/AD1938/AD1939
LRCLK
256 BCLKs
BCLK
32 BCLKs
SLOT 1 SLOT 2 SLOT 3 SLOT 4
LEFT 1 RIGHT 1 LEFT 2 RIGHT 2
SLOT 6 SLOT 7 SLOT 8
SLOT 5
DATA
LRCLK
BCLK
DATA
MSB
MSB–1
MSB–2
Figure 16. ADC TDM (8-channel I2Smode )
LRCLK
BCLK
DATA
256 BCLKs
32 BCLKs
SLOT 1 SLOT 2 SLOT 3 SLOT 4
SLOT 6 SLOT 7 SLOT 8
SLOT 5
LEFT 1 RIGHT 1 LEFT 2 RIGHT 2 LEFT 3 RIGHT 3 LEFT 4 RIGHT 4
LRCLK
BCLK
DATA
MSB
MSB–1
MSB–2
Figure 17. DAC TDM (8-channel I2S mode)
FSTDM
BCLK
TDM
MSB TDM
MSB TDM
1ST
8TH
ASDATA1
CH
CH
TDM (OUT)
ADC R2
ADC R1
DAC R1
AUX ADC R1
AUX ADC L2
ADC L1
ADC L2
DAC L2
AUX ADC L1
AUX ADC R2
MSB TDM
ASDATA
32
MSB TDM
1ST
8TH
DSDATA1
TDM (IN)
CH
CH
DAC L3
DAC L1
32
DAC R2
DAC R3
DAC L4
RIGHT
DAC R4
DSDATA1
AUX LRCLK
LEFT
(FROM AUX ADC 1)
AUX BCLK
(FROM AUX ADC 1)
AUX DATA IN 1
2
2
I S - MSB LEFT
I S - MSB RIGHT
(FROM AUX ADC 1)
AUX DATA IN 2
2
2
I S - MSB LEFT
I S - MSB RIGHT
(FROM AUX ADC 2)
AUX BCLK FREQUENCY IS 64 × FRAME-RATE; TDM BCLK FREQUENCY IS 256 × FRAME-RATE.
Figure 18. AUX 256 Mode Timing (Note that the Clocks Are Not to Scale)
Rev. PrI | Page 14 of 30
Preliminary Technical Data
AD1935/AD1936/AD1937/AD1938/AD1939
Pin Function Changes in TDM and AUX Modes
Pin Name
ASDATA1
ASDATA2
DSDATA1
DSDATA2
DSDATA3
DSDATA4
ALRCLK
Stereo Modes
ADC1 Data Out
ADC2 Data Out
DAC1 Data In
TDM Modes
AUX Modes
ADC TDM Data Out
TDM Data Out
ADC TDM Data In
AUX Data Out 1 (to Ext. DAC 1)
TDM Data In
DAC TDM Data In
DAC2 Data In
DAC TDM Data Out
AUX Data In 1 (from Ext. ADC 1)
AUX Data In 2 (from Ext. ADC 2)
AUX Data Out 2 (to Ext. DAC 2)
TDM Frame Sync In/Out
TDM BCLK In/Out
DAC3 Data In
DAC TDM Data In 2 (dual-line mode)
DAC TDM Data Out 2 (dual-line mode)
ADC TDM Frame Sync In/Out
ADC TDM BCLK In/Out
DAC4 Data In
ADC LRCLK In/Out
ADC BCLK In/Out
DAC LRCLK In/Out
DAC BCLK In/Out
ABCLK
DLRCLK
DAC TDM Frame Sync In/Out
DAC TDM BCLK In/Out
AUX LRCLK In/Out
DBCLK
AUX BCLK In/Out
Table 12
30MHz
SHARC IS RUNNING IN SLAVE MODE
(INTERRUPT-DRIVEN)
SHARC
12.288MHz
LRCLK
LRCLK
BCLK
DATA
MCLK
BCLK
AUX
AUX
ASDATA1 ALRCLK ABCLK DSDATA1
DAC 1
DATA
ADC 1
MCLK
DBCLK
DLRCLK
AD193X
LRCLK
BCLK
DAC 2
DATA
MCLK
LRCLK
BCLK
DATA
MCLK
TDM MASTER
AUX MASTER
ASDATA2
DSDATA4
DSDATA2
AUX
AUX
ADC 2
DSDATA3
MCLK
Figure 19. Example of AUX Mode Connection to SHARC (AD193X as TDM Master/AUX Master shown)
Rev. PrI | Page 15 of 30
Preliminary Technical Data
AD1935/AD1936/AD1937/AD1938/AD1939
PIN FUNCTION DESCRIPTIONS
48-Lead LQFP Plastic Package – AD1936, AD1938
Pin No.
1
In/Out Mnemonic
Description
I
AGND
Analog Ground.
2
I
MCLKI/XI
MCLK/XO
AGND
Master Clock Input/ Crystal Oscillator Input.
Master Clock Output/ Crystal Oscillator Output.
Analog Ground.
3
I
4
I
5
I
AVDD
Analog Power Supply. Connect to analog 3.3 V supply.
DAC 3 Left Output.
6
O
OL3
7
O
OR3
DAC 3 Right Output.
8
O
OL4
DAC 4 Left Output.
9
O
OR4
DAC 4 Right Output.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
I
Power-Down Reset (Active Low).
DAC Input 4 (Input to DAC 4 L and R).
Digital Ground.
PD/RST
DSDATA4
DGND
I
I
I
DVDD
Digital Power Supply. Connect to digital 3.3 V supply.
DAC Input 3 (Input to DAC 3 L and R).
DAC Input 2 (Input to DAC 2 L and R).
DAC Input 1 (Input to DAC 1 L and R).
Bit Clock for DACs.
I
DSDATA3
DSDATA2
DSDATA1
DBCLK
DLRCLK
ASDATA2
ASDATA1
ABCLK
ALRCLK
CIN/ADR0
COUT/SDA
DGND
I
I
I/O
I/O
LR Clock for DACs.
O
ADC Serial Data Output 2 (ADC 2 L and R).
ADC Serial Data Output 1 (ADC 1 L and R).
Bit Clock for ADCs.
O
I/O
I/O
O
I
LR Clock for ADCs.
Control Data Input (SPI)/Address 0 (I2C).
Control Data Output (SPI)/Serial Data (I2C).
Digital Ground.
Control Clock Input (SPI)/Serial Clock (I2C).
Latch Input for Control Data (SPI)/Address 1 (I2C).
DAC 1 Left Output.
I
I
CCLK/SCL
CLATCH/ADR1
OL1
I
O
O
O
O
I
OR1
DAC 1 Right Output.
OL2
DAC 2 Left Output.
OR2
DAC 2 Right Output.
AGND
Analog Ground.
I
AVDD
Analog Power Supply. Connect to analog 3.3 V supply.
Analog Ground.
I
AGND
O
I
FILTR
Voltage Reference Filter Capacitor Connection. Bypass with 10 µF||100 nF to AGND.
Analog Ground.
AGND
I
AVDD
Analog Power Supply. Connect to analog 3.3 V supply.
Common Mode Reference Filter Capacitor Connection. Bypass with 10 µF||100 nF to AGND.
ADC1 Left Positive Input.
O
I
CM
ADC1LP
ADC1LN
ADC1RP
ADC1RN
ADC2LP
ADC2LN
ADC2RP
ADC2RN
LF
I
ADC1 Left Negative Input.
I
ADC1 Right Positive Input.
I
ADC1 Right Negative Input.
I
ADC2 Left Positive Input.
I
ADC2 Left Negative Input.
I
ADC2 Right Positive Input.
I
ADC2 Right Negative Input.
O
I
PLL Loop Filter, Return to AVDD.
AVDD
Analog Power Supply. Connect to analog 3.3 V supply.
Table 13. Pin Function Description—48-Lead LQFP( AD1936, AD1938)
Rev. PrI | Page 16 of 30
Preliminary Technical Data
AD1935/AD1936/AD1937/AD1938/AD1939
64-Lead LQFP Plastic Package – AD1937, AD1939
Pin No.
1
In/Out Mnemonic
Description
I
AGND
Analog Ground.
2
I
MCLKI/XI
MCLK/XO
AGND
Master Clock Input/ Crystal Oscillator Input.
Master Clock Output/ Crystal Oscillator Output.
Analog Ground.
3
I
4
I
5
I
AVDD
Analog Power Supply. Connect to analog 3.3 V supply.
DAC 3 Left Positive Output.
6
O
O
O
O
O
O
O
O
I
OL3P
7
OL3N
DAC 3 Left Negative Output.
8
OR3P
DAC 3 Right Positive Output.
9
OR3N
DAC 3 Right Negative Output.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
OL4P
DAC 4 Left Positive Output.
OL4N
DAC 4 Left Negative Output.
OR4P
DAC 4 Right Positive Output.
OR4N
DAC 4 Right Negative Output.
Power-Down Reset (Active Low).
DAC Input 4 (Input to DAC 4 L and R).
Digital Ground.
PD/RST
DSDATA4
DGND
I
I
I
DVDD
Digital Power Supply. Connect to digital 3.3 V supply.
DAC Input 3 (Input to DAC 3 L and R).
DAC Input 2 (Input to DAC 2 L and R).
DAC Input 1 (Input to DAC 1 L and R).
Bit Clock for DACs.
I
DSDATA3
DSDATA2
DSDATA1
DBCLK
DLRCLK
VSUPPLY
VSENSE
VDRIVE
ASDATA2
ASDATA1
ABCLK
ALRCLK
CIN/ADR0
COUT/SDA
DVDD
I
I
I/O
I/O
LR Clock for DACs.
+5V Input to Regulator, Emitter of Pass Transistor
+3.3V Output of Regulator, Collector of Pass Transistor
Drive for Base of Pass Transistor
ADC Serial Data Output 2 (ADC 2 L and R).
ADC Serial Data Output 1 (ADC 1 L and R).
Bit Clock for ADCs.
O
O
I/O
I/O
I
LR Clock for ADCs.
Control Data Input (SPI)/Address 0 (I2C).
Control Data Output (SPI)/Serial Data (I2C).
Digital Power Supply. Connect to digital 3.3 V supply.
Digital Ground.
Control Clock Input (SPI)/Serial Clock (I2C).
Latch Input for Control Data (SPI)/Address 1 (I2C).
DAC 1 Left Positive Output.
I/O
I
I
DGND
I
CCLK/SCL
CLATCH/ADR1
OL1P
I
O
O
O
O
O
O
O
O
I
OL1N
DAC 1 Left Negative Output.
OR1P
DAC 1 Right Positive Output.
OR1N
DAC 1 Right Negative Output.
OL2P
DAC 2 Left Positive Output.
OL2N
DAC 2 Left Negative Output.
OR2P
DAC 2 Right Positive Output.
OR2N
DAC 2 Right Negative Output.
AGND
Analog Ground.
I
AVDD
Analog Power Supply. Connect to analog 3.3 V supply.
Analog Ground.
I
AGND
O
I
FILTR
Voltage Reference Filter Capacitor Connection. Bypass with 10 µF||100 nF to AGND.
Analog Ground.
AGND
No Connect.
No Connect.
I
AVDD
Analog Power Supply. Connect to analog 3.3 V supply.
Rev. PrI | Page 17 of 30
Preliminary Technical Data
AD1935/AD1936/AD1937/AD1938/AD1939
Pin No.
52
In/Out Mnemonic
Description
O
I
CM
Common Mode Reference Filter Capacitor Connection. Bypass with 10 µF||100 nF to AGND.
ADC1 Left Positive Input.
53
ADC1LP
ADC1LN
ADC1RP
ADC1RN
ADC2LP
ADC2LN
ADC2RP
ADC2RN
LF
54
I
ADC1 Left Negative Input.
55
I
ADC1 Right Positive Input.
56
I
ADC1 Right Negative Input.
57
I
ADC2 Left Positive Input.
58
I
ADC2 Left Negative Input.
59
I
ADC2 Right Positive Input.
60
I
ADC2 Right Negative Input.
61
O
I
PLL Loop Filter, Return to AVDD.
Analog Power Supply. Connect to analog 3.3 V supply.
No Connect.
62
AVDD
63
64
No Connect.
Table 14. Pin Function Description—64-Lead LQFP (AD1937, AD1939)
64-Lead LQFP Plastic Package – AD1935
Pin No.
1
In/Out Mnemonic
Description
I
AGND
Analog Ground.
2
I
MCLKI/XI
MCLK/XO
AGND
Master Clock Input/ Crystal Oscillator Input.
Master Clock Output/ Crystal Oscillator Output.
Analog Ground.
3
I
4
I
5
I
AVDD
Analog Power Supply. Connect to analog 3.3 V supply.
DAC 3 Left Output.
6
O
O
O
O
O
O
O
O
I
OL3
7
No Connect.
8
OR3
OL4
OR4
DAC 3 Right Output.
9
No Connect.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
DAC 4 Left Output.
No Connect.
DAC 4 Right Output.
No Connect.
Power-Down Reset (Active Low).
DAC Input 4 (Input to DAC 4 L and R).
Digital Ground.
PD/RST
DSDATA4
DGND
I
I
I
DVDD
Digital Power Supply. Connect to digital 3.3 V supply.
DAC Input 3 (Input to DAC 3 L and R).
DAC Input 2 (Input to DAC 2 L and R).
DAC Input 1 (Input to DAC 1 L and R).
Bit Clock for DACs.
I
DSDATA3
DSDATA2
DSDATA1
DBCLK
I
I
I/O
I/O
DLRCLK
VSUPPLY
VSENSE
VDRIVE
ASDATA2
ASDATA1
ABCLK
LR Clock for DACs.
+5V Input to Regulator, Emitter of Pass Transistor
+3.3V Output of Regulator, Collector of Pass Transistor
Drive for Base of Pass Transistor
ADC Serial Data Output 2 (ADC 2 L and R).
ADC Serial Data Output 1 (ADC 1 L and R).
Bit Clock for ADCs.
O
O
I/O
I/O
ALRCLK
CIN
LR Clock for ADCs.
I
Control Data Input (SPI)
I/O
COUT
Control Data Output (SPI)
I
I
I
I
DVDD
Digital Power Supply. Connect to digital 3.3 V supply.
Digital Ground.
DGND
CCLK
Control Clock Input (SPI)
Latch Input for Control Data (SPI)
Rev. PrI | Page 18 of 30
CLATCH
Preliminary Technical Data
AD1935/AD1936/AD1937/AD1938/AD1939
Pin No.
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
In/Out Mnemonic
Description
O
O
O
O
O
O
O
O
I
OL1
OR1
OL2
OR2
DAC 1 Left Output.
No Connect.
DAC 1 Right Output.
No Connect.
DAC 2 Left Output.
No Connect.
DAC 2 Right Output.
No Connect.
AGND
AVDD
AGND
FILTR
Analog Ground.
I
Analog Power Supply. Connect to analog 3.3 V supply.
I
Analog Ground.
O
I
Voltage Reference Filter Capacitor Connection. Bypass with 10 µF||100 nF to AGND.
AGND
Analog Ground.
No Connect.
No Connect.
I
AVDD
Analog Power Supply. Connect to analog 3.3 V supply.
Common Mode Reference Filter Capacitor Connection. Bypass with 10 µF||100 nF to AGND.
ADC1 Left Positive Input.
O
I
CM
ADC1LP
ADC1LN
ADC1RP
ADC1RN
ADC2LP
ADC2LN
ADC2RP
ADC2RN
LF
I
ADC1 Left Negative Input.
I
ADC1 Right Positive Input.
I
ADC1 Right Negative Input.
I
ADC2 Left Positive Input.
I
ADC2 Left Negative Input.
I
ADC2 Right Positive Input.
I
ADC2 Right Negative Input.
O
I
PLL Loop Filter, Return to AVDD.
Analog Power Supply. Connect to analog 3.3 V supply.
No Connect.
AVDD
No Connect.
Table 15. Pin Function Description—64-Lead LQFP (AD1935)
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
1
2
AGND
MCLKI/XI
MCLKO/XO
AGND
AVDD
OL3
OR3
OL4
OR4
PD/RST
36
35
34
33
AGND
FILTR
AGND
AVDD
3
4
AD193X
5
32 AGND
TOP VIEW
6
31
OR2
30 OL2
29
(Not to Scale)
7
Single-ended
8
OR1
28 OL1
27
Output
9
10
11
CLATCH/ADR1
26 CCLK/SCL
25
Preliminary
DSDATA4
DGND 12
DGND
13 14 15 16 17 18 19 20 21 22 23 24
Figure 20. Single-ended Output 48-Lead LQFP (AD1936, AD1938)
Rev. PrI | Page 19 of 30
Preliminary Technical Data
AD1935/AD1936/AD1937/AD1938/AD1939
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AGND
48
47
46
45
44
1
2
3
4
5
6
7
8
9
AGND
MCLKI/XI
MCLKO/XO
AGND
FILTR
AGND
AVDD
AGND
43 OR2N
42 OR2P
41 OL2N
OL2P
39 OR1N
OR1P
OL1N
OL1P
AVDD
OL3P
OL3N
OR3P
AD193X
TOP VIEW
(Not to Scale)
OR3N
40
Differential
OL4P 10
11
Output
38
37
36
35
34
33
OL4N
OR4P 12
OR4N 13
Preliminary
14
PD/RST
DSDATA4
DGND
CLATCH/ADR1
CCLK/SCL
DGND
15
16
17 18 19 20 21 22 23 24 25 26 27 28
29 30 31 32
Figure 21. Differential Output 64-Lead LQFP (AD1937, AD1939)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AGND
48
47
46
45
44
1
2
3
4
5
6
7
8
9
AGND
MCLKI/XI
MCLKO/XO
AGND
AVDD
OL3
FILTR
AGND
AVDD
AGND
43 NC
42 OR2
41 NC
OL2
39 NC
OR1
NC
AD193X
NC
OR3
NC
TOP VIEW
(Not to Scale)
40
Single-ended
OL4 10
11
Output
38
37
36
35
34
33
NC
OR4 12
NC 13
14
Preliminary
OL1
CLATCH
CCLK
DGND
PD/RST
DSDATA4
DGND
15
16
17 18 19 20 21 22 23 24 25 26 27 28
29 30 31 32
Figure 22. Single-ended Output Output 64-Lead LQFP (AD1935)
Rev. PrI | Page 20 of 30
Preliminary Technical Data
APPLICATION CIRCUITS
AD1935/AD1936/AD1937/AD1938/AD1939
Figure 23. Typical ADC Input Filter Circuit
Figure 24. Typical DAC Output Filter Circuit (Single-ended, Non-inverting)
Figure 25. Typical DAC Output Filter Circuit (Single-ended, Inverting)
Figure 26. Typical DAC Output Filter Circuit (Differential)
Rev. PrI | Page 21 of 30
Preliminary Technical Data
AD1935/AD1936/AD1937/AD1938/AD1939
Figure 27. Recommended Loop Filters for LRCLK or MCLK PLL reference.
Figure 28. Recommended 3.3V Regulator Circuit (64-lead versions)
Rev. PrI | Page 22 of 30
Preliminary Technical Data
AD1935/AD1936/AD1937/AD1938/AD1939
REGISTER DEFINITIONS
Register format
Global Address
R/W Register Address
16 15:8
Data
Bit
23:17
7:0
Table 16
Note 1: The format is the same for I2C and SPI.
Note 2: Global address for the AD193X series is 0x04, shifted left 1 bit due to the R/W bit.
Note 3: In I2C, ADR0 and ADR1 are ORed into bits 17 and 18 to provide multiple chip addressing.
Note 4: All registers are reset to 0, except for the DAC volume registers which are set to full volume.
Register addresses and functions
Address
Function
0
PLL and Clock Control 0
PLL and Clock Control 1
DAC Control 0
1
2
DAC Control 1
3
DAC Control 2
4
DAC Individual Channel Mutes
DAC 1L Vol Control
DAC 1R Vol Control
DAC 2L Vol Control
DAC 2R Vol Control
DAC 3L Vol Control
DAC 3R Vol Control
DAC 4L Vol Control
DAC 4R Vol Control
ADC Control 0
5
6
7
8
9
10
11
12
13
14
15
16
ADC Control 1
ADC Control 2
Table 17
Rev. PrI | Page 23 of 30
Preliminary Technical Data
AD1935/AD1936/AD1937/AD1938/AD1939
PLL AND CLOCK CONTROL REGISTERS
PLL and Clock control 0
Bit
Value
0
1
Function
Description
0
Normal operation
Power down
PLL power down
2:1
4:3
6:5
7
00
01
10
11
00
01
10
11
00
01
10
11
0
INPUT 256 (x 44.1 or 48kHz)
INPUT 384 (x 44.1 or 48kHz)
INPUT 512 (x 44.1 or 48kHz)
INPUT 768 (x 44.1 or 48kHz)
XTAL Oscillator Enabled
256xfs VCO Output
512xfs VCO Output
Off
MCLK pin functionality (PLL active)
MCLK_O pin
MCLK
DLRCLK
ALRCLK
Reserved
PLL input
Disable: ADC and DAC Idle
Enable: ADC and DAC Active
Internal MCLK Enable
1
Table 18
PLL and Clock control 1
Bit
Value
Function
PLL Clock
MCLK
Description
0
0
1
DAC Clock Source Select
1
0
1
PLL Clock
MCLK
ADC Clock Source Select
2
0
1
Enabled
Disabled
Not Locked
Locked
On-chip Voltage Reference
PLL Lock Indicator (Read Only)
3
0
1
7:4
0000
Reserved
Table 19
Rev. PrI | Page 24 of 30
Preliminary Technical Data
DAC CONTROL REGISTERS
DAC control 0
AD1935/AD1936/AD1937/AD1938/AD1939
Bit
Value
0
Function
Description
0
Normal
Power Down
1
Power down
2:1
5:3
00
01
10
11
32/44.1/48 kHz
64/88.2/96 kHz
128/176.4/192 kHz
Reserved
Sample Rate
000
001
010
011
100
101
110
111
00
1
0
8
12
16
Reserved
Reserved
Reserved
SDATA Delay (BCLK periods)
7:6
Stereo (Normal)
TDM (Daisy Chain)
DAC Aux mode (ADC, DAC TDM coupled)
Dual-line TDM
Serial Format
01
10
11
Table 20
DAC control 1
Bit
Value
Function
Description
0
0
1
Latch in mid cycle (normal)
Latch in at end of cycle (pipeline)
64 (2 channels)
128 (4 channels)
256 (8 channels)
512 (16 channels)
Left low
BCLK Active Edge (TDM In)
2:1
00
01
10
11
0
BCLKs Per Frame
3
4
5
6
7
LRCLK Polarity
LRCLK Master/Slave
BCLK Master/Slave
BCLK Source
1
Left high
0
1
Slave
Master
0
1
Slave
Master
0
1
DBCLK pin
Internally generated
Normal
0
BCLK Polarity
1
Inverted
Table 21
Rev. PrI | Page 25 of 30
Preliminary Technical Data
AD1935/AD1936/AD1937/AD1938/AD1939
DAC control 2
Bit
Value
0
1
Function
Unmute
Mute
Description
0
Master Mute
2:1
4:3
00
01
10
11
00
01
10
11
0
Flat
Deemphasis (32/44.1/48 kHz mode only)
Word width
48 kHz Curve
44.1 kHz Curve
32 kHz Curve
24
20
Reserved
16
5
Non-inverted
Inverted
Reserved
DAC Output Polarity
1
7:6
00
Table 22
DAC Individual Channel Mutes
Bit
Value
Function
Unmute
Mute
Description
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DAC 1 Left Mute
1
2
3
4
5
6
7
Unmute
Mute
DAC 1 Right Mute
DAC 2 Left Mute
DAC 2 Right Mute
DAC 3 Left Mute
DAC 3 Right Mute
DAC 4 Left Mute
DAC 4 Right Mute
Unmute
Mute
Unmute
Mute
Unmute
Mute
Unmute
Mute
Unmute
Mute
Unmute
Mute
Table 23
DAC Volume Controls
Bit
Value
0
1-254
255
Function
Description
7:0
No attenuation
-3/8 dB per step
Full Attenuation
DAC Volume Control
Table 24
Rev. PrI | Page 26 of 30
Preliminary Technical Data
ADC CONTROL REGISTERS
ADC control 0
AD1935/AD1936/AD1937/AD1938/AD1939
Bit
Value
Function
Normal
Power down
Off
Description
0
0
1
Power Down
1
0
1
Highpass Filter
ADC 1L mute
On
2
0
1
Unmute
Mute
3
0
1
Unmute
Mute
ADC 1R mute
4
0
1
Unmute
Mute
ADC 2L mute
5
0
1
Unmute
Mute
ADC 2R mute
7:6
00
01
10
11
32/44.1/48
64/88.2/96
128/176.4/192
Reserved
Output Sample Rate
Table 25
ADC control 1
Bit
Value
00
Function
Description
1:0
24
Word width
01
20
10
Reserved
11
16
4:2
000
001
010
011
100
101
110
111
00
1
0
8
12
16
Reserved
Reserved
Reserved
SDATA delay (BCLK periods)
6:5
7
Stereo
Serial Format
01
10
11
TDM (Daisy Chain)
ADC Aux mode (ADC, DAC TDM coupled)
Reserved
0
1
Latch in mid cycle (normal)
Latch in at end of cycle (pipeline)
BCLK Active Edge (TDM In)
Table 26.
Rev. PrI | Page 27 of 30
Preliminary Technical Data
AD1935/AD1936/AD1937/AD1938/AD1939
ADC control 2
Bit
Value
Function
Description
0
0
50/50 (allows 32/24/20/16 BCLK/channel)
LRCLK Format
1
Pulse (32 BCLK/channel)
1
0
Drive out on falling edge (DEF)
BCLK Polarity
1
Drive out on rising edge
2
0
1
Left Low
Left High
Slave
Master
64
128
256
512
LRCLK Polarity
LRCLK Master/Slave
BCLKs per frame
3
0
1
5:4
00
01
10
11
0
6
7
Slave
BCLK Master/Slave
BCLK Source
1
Master
ABCLK pin
Internally generated
0
1
Table 27
Rev. PrI | Page 28 of 30
Preliminary Technical Data
OUTLINE DIMENSIONS
AD1935/AD1936/AD1937/AD1938/AD1939
0.75
0.60
0.45
9.00
1.60
BSC SQ
MAX
37
48
36
1
PIN 1
7.00
TOP VIEW
(PINS DOWN)
BSC SQ
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
25
12
0.15
0.05
13
24
SEATING
0.08 MAX
0.27
0.22
0.17
PLANE
VIEW A
0.50
BSC
COPLANARITY
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
Figure 29. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
Figure 30. 64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64)
Dimensions shown in millimeters
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features proprietary
ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges.
Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrI | Page 29 of 30
Preliminary Technical Data
AD1935/AD1936/AD1937/AD1938/AD1939
Ordering Guide
AD193X Products
Temperature Package (ambient)
–40°C to +105°C
Package Description
Package Option
AD1935XSTZ
64-Lead LQFP, SE out, SPI control w/ reg
64-Lead LQFP, SE out, SPI control w/ reg
48-Lead LQFP, SE out, I2C control
48-Lead LQFP, SE out, I2C control
64-Lead LQFP, Diff out, I2C control
64-Lead LQFP, Diff out, I2C control
48-Lead LQFP, SE out, SPI control
48-Lead LQFP, SE out, SPI control
64-Lead LQFP, Diff out, SPI control
64-Lead LQFP, Diff out, SPI control
AD1935 Evaluation Board
ST-64
AD1935XSTZRL
AD1936XSTZ
–40°C to +105°C
ST-64 on 13” Reels
ST-48
–40°C to +105°C
AD1936XSTZRL
AD1937XSTZ
–40°C to +105°C
ST-48 on 13” Reels
ST-64
–40°C to +105°C
AD1937XSTZRL
AD1938XSTZ
–40°C to +105°C
ST-64 on 13” Reels
ST-48
–40°C to +105°C
AD1938XSTZRL
AD1939XSTZ
–40°C to +105°C
ST-48 on 13” Reels
ST-64
–40°C to +105°C
AD1939XSTZRL
EVAL-AD1935EB
EVAL-AD1936EB
EVAL-AD1937EB
EVAL-AD1938EB
EVAL-AD1939EB
–40°C to +105°C
ST-64 on 13” Reels
AD1936 Evaluation Board
AD1937 Evaluation Board
AD1938 Evaluation Board
AD1939 Evaluation Board
Note: All parts are lead-free
Table 28. Ordering Guide
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.
Printed in the U.S.A.
PR05582-0-5/05(PrI)
Rev. PrI | Page 30 of 30
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