概述
数据手册AD2S90 概述
Low Cost, Complete 12-Bit Resolver-to-Digital Converter 低成本，完整的12位分解器数字转换器
AD2S90 数据手册
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a
Resolver-to-Digital Converter
AD2S90
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Complete Monolithic Resolver-to-Digital Converter
Incremental Encoder Emulation (1024-Line)
Absolute Serial Data (12-Bit)
Differential Inputs
12-Bit Resolution
Industrial Temperature Range
20-Lead PLCC
REF
SIN
SIN ( – )
VEL
P.S.D. AND
FREQUENCY
SHAPING
SIN LO
HIGH ACCURACY
SIN COS
ANGLE
COS
MULTIPLIER
ERROR
AMPLIFIER
COS LO
DIGITAL
ANGLE
CLKOUT
DIR
U/D
NMC
A
B
HIGH
DYNAMIC
RANGE V.C.O.
UP-DOWN
COUNTER
CLK
Low Power (50 mW)
DECODE
LOGIC
NM
APPLICATIONS
CS
LATCH
Industrial Motor Control
Servo Motor Control
Industrial Gauging
SCLK
DATA
SERIAL INTERFACE
Encoder Emulation
Automotive Motion Sensing and Control
Factory Automation
Limit Switching
GENERAL DESCRIPTION
The AD2S90 operates on ±5 V dc ± 5% power supplies and is
fabricated on Analog Devices’ Linear Compatible CMOS pro-
cess (LC2MOS). LC2MOS is a mixed technology process that
combines precision bipolar circuits with low power CMOS logic
circuits.
The AD2S90 is a complete 12-bit resolution tracking resolver-
to-digital converter. No external components are required to
operate the device.
The converter accepts 2 V rms ± 10% input signals in the range
3 kHz–20 kHz on the SIN, COS and REF inputs. A Type II
servo loop is employed to track the inputs and convert the input
SIN and COS information into a digital representation of the
input angle. The bandwidth of the converter is set internally at
1 kHz within the tolerances of the device. The guaranteed maxi-
mum tracking rate is 500 rps.
PRODUCT HIGHLIGHTS
Complete Resolver-Digital Interface. The AD2S90 provides
the complete solution for digitizing resolver signals (12-bit reso-
lution) without the need for external components.
Dual Format Position Data. Incremental encoder emulation
in standard A QUAD B format with selectable North Marker
width. Absolute serial 12-bit angular binary position data
accessed via simple 3-wire interface.
Angular position output information is available in two forms,
absolute serial binary and incremental A quad B.
The absolute serial binary output is 12-bit (1 in 4096). The data
output pin is high impedance when Chip Select CS is logic HI.
This allows the connection of multiple converters onto a com-
mon bus. Absolute angular information in serial pure binary
form is accessed by CS followed by the application of an exter-
nal clock (SCLK) with a maximum rate of 2 MHz.
Single High Accuracy Grade in Low Cost Package. ±10.6 arc
minutes of angular accuracy available in a 20-lead PLCC.
Low Power. Typically 50 mW power consumption.
The encoder emulation outputs A, B and NM continuously
produce signals equivalent to a 1024 line encoder. When de-
coded this corresponds to 12 bits of resolution. Three common
north marker pulsewidths are selected via a single pin (NMC).
An analog velocity output signal provides a representation of
velocity from a rotating resolver shaft traveling in either a clock-
wise or counterclockwise direction.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
(VDD = +5 V ؎ 5%, VSS = –5 V ؎ 5%, AGND = DGND = 0 V, TA = –40؇C to +85؇C unless
AD2S90–SPECIFICATIONS otherwise noted)
Parameter
Min
Typ
Max
Units
Test Condition
SIGNAL INPUTS
Voltage Amplitude
1.8
3
2.0
2.2
V rms
Sinusoidal Waveforms, Differential
SIN to SINLO, COS to COSLO
Frequency
20
kHz
Input Bias Current
Input Impedance
Common-Mode Volts1
CMRR
100
nA
MΩ
mV peak
dB
VIN = 2 ± 10% V rms
VIN = 2 ± 10% V rms
CMV @ SINLO, COSLO w.r.t.
AGND @ 10 kHz
1.0
60
100
REFERENCE INPUT
Voltage Amplitude
Frequency
Input Bias Current
Input Impedance
Permissible Phase Shift
1.8
3
2.0
3.35
20
100
V rms
kHz
nA
kΩ
Degrees
Sinusoidal Waveform
100
–10
+10
Relative to SIN, COS Inputs
CONVERTER DYNAMICS
Bandwidth
Maximum Tracking Rate
Maximum VCO Rate (CLKOUT)
Settling Time
700
500
2.048
840
2
1000
Hz
rps
MHz
1° Step
179° Step
7
20
ms
ms
ACCURACY
Angular Accuracy2
Repeatability3
±10.6 + 1 LSB arc min
1
LSB
VELOCITY OUTPUT
Scaling
Output Voltage at 500 rps
Load Drive Capability
120
±2.78
150
±3.33
180
±4.17
±250
rps/V dc
V dc
µA
VOUT = ±2.5 V dc (typ), RL ≥ 10 kΩ
LOGIC INPUTS SCLK, CS
Input High Voltage (VINH
)
3.5
4.0
V dc
V dc
µA
VDD = +5 V dc, VSS = –5 V dc
VDD = +5 V dc, VSS = –5 V dc
Input Low Voltage (VINL
Input Current (IIN)
Input Capacitance
)
1.5
10
10
pF
LOGIC OUTPUTS DATA, A, B,4
NM, CLKOUT, DIR
VDD = +5 V dc, VSS = –5 V dc
IOH = 1 mA
IOL = 1 mA
IOL = 400 µA
Output High Voltage
Output Low Voltage
V dc
V dc
V dc
1.0
0.4
SERIAL CLOCK (SCLK)
SCLK Input Rate
2
MHz
NORTH MARKER CONTROL (NMC)
90°
180°
360°
+4.75
–0.75
–4.75
+5.0
DGND
–5.0
+5.25
+0.75
–5.25
V dc
V dc
V dc
North Marker Width Relative to
“A” Cycle
POWER SUPPLIES
VDD
VSS
IDD
ISS
+4.75
–4.75
+5.00
–5.00
+5.25
–5.25
10
V dc
V dc
mA
10
mA
NOTES
1If the tolerance on signal inputs = ±5%, then CMV = 200 mV.
21 LSB = 5.3 arc minute.
3Specified at constant temperature.
4Output load drive capability.
Specifications subject to change without notice.
–2–
REV. D
AD2S90
(VDD = +5 V ؎ 5%, VSS = –5 V ؎ 5%, AGND = DGND = 0 V, TA = –40؇C to +85؇C unless
otherwise noted)
TIMING CHARACTERISTICS1, 2
t2
t6
CSB
t3
SCLK
t4
t*
MSB
LSB
DATA
t1
t7
t5
*THE MINIMUM ACCESS TIME: USER DEPENDENT
Figure 1. Serial Interface
NOTES
1Timing data are not 100% production tested. Sample tested at +25°C only to ensure conformance to data sheet limits. Logic output timing tests carried out using
10 pF, 100 kΩ load.
2Capacitance of data pin in high impedance state = 15 pF.
Parameter
AD2S90
Units
Test Conditions/Notes
t11
t2
t3
t4
t5
t6
t7
150
600
250
250
100
600
150
ns max
ns min
ns min
ns min
ns max
ns min
ns max
CS to DATA Enable
CS to 1st SCLK Negative Edge
SCLK Low Pulse
SCLK High Pulse
SCLK Negative Edge to DATA Valid
CS High Pulsewidth
CS High to DATA High Z (Bus Relinquish)
NOTE
1SCLK can only be applied after t2 has elapsed.
COUNTER IS CLOCKED
ON THIS EDGE
A
B
CLKOUT
A, B, NM
DIR
tCLK
tABN
90؇
180؇
360؇
NM
tDIR
NUMBER OF DEGREES REFERS TO WIDTH RELATIVE TO "A" CYCLE
Figure 2. Incremental Encoder
Figure 3. DIR/CLKOUT/A, B and NM Timing
AD2S90
Parameter
Min
Max
Units
Test Conditions/Notes
tDIR
tCLK
tABN
200
400
250
ns
ns
ns
DIR to CLKOUT Positive Edge
CLKOUT Pulsewidth
CLKOUT Negative Edge to A, B and NM Transition
250
REV. D
–3–
AD2S90
RECOMMENDED OPERATING CONDITIONS
PIN DESCRIPTIONS
Power Supply Voltage (VDD – VSS) . . . . . . . . . . ±5 V dc ± 5%
Analog Input Voltage (SIN, COS & REF) . . . . .2 V rms ± 10%
Signal and Reference Harmonic Distortion . . . . . . . . . . . . 10%
Phase Shift between Signal and Reference . . . . . . . . . . . . . ±10°
Ambient Operating Temperature Range
Pin
No. Mnemonic Function
1
2
AGND
SIN
Analog ground, reference ground.
SIN channel noninverting input connect to
resolver SIN HI output. SIN to SIN LO =
2 V rms ± 10%.
Industrial (AP) . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
ABSOLUTE MAXIMUM RATINGS*
3
4
5
SIN LO
DATA
SCLK
SIN channel inverting input connect to
resolver SIN LO.
VDD to AGND . . . . . . . . . . . . . . . . . . . .–0.3 V dc to +7.0 V dc
VSS to AGND . . . . . . . . . . . . . . . . . . . .+0.3 V dc to –7.0 V dc
AGND to DGND . . . . . . . . . . . . –0.3 V dc to VDD + 0.3 V dc
Analog Inputs to AGND
REF . . . . . . . . . . . . . . . . . . VSS – 0.3 V dc to VDD + 0.3 V dc
SIN, SIN LO . . . . . . . . . . . VSS – 0.3 V dc to VDD + 0.3 V dc
COS, COS LO . . . . . . . . . . VSS – 0.3 V dc to VDD + 0.3 V dc
Analog Output to AGND
Serial interface data output. High impedance
with CS = HI. Enabled by CS = 0.
Serial interface clock. Data is clocked out on
“first” negative edge of SCLK after a LO transi-
tion on CS. 12 SCLK pulses to clock data out.
VEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to VDD
Digital Inputs to DGND, CSB,
6
CS
Chip select. Active LO. Logic LO transition
enables DATA output.
SCLK, RES . . . . . . . . . . . . . . . –0.3 V dc to VDD + 0.3 V dc
Digital Outputs to DGND, NM, A, B,
DIR, CLKOUT DATA . . . . . . –0.3 V dc to VDD + 0.3 V dc
7
8
9
A
Encoder A output.
Encoder B output.
B
Operating Temperature Range
NM
Encoder North Marker emulation output.
Pulse triggered as code passes through zero.
Three common pulsewidths available.
Industrial (AP) . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . 300°C
Power Dissipation to +75°C . . . . . . . . . . . . . . . . . . . . 300 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . . 10 mW/°C
10 DIR
Indicates direction of rotation of input.
Logic HI = increasing angular rotation.
Logic LO = decreasing angular rotation.
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
11 DGND
12 VSS
Digital power ground return.
Negative power supply, –5 V dc ± 5%.
Positive power supply, +5 V dc ± 5%.
13 VDD
14 VDD
Positive power supply, +5 V dc ± 5%. Must
be connected to Pin 13.
ORDERING GUIDE
Model
Temperature Range Accuracy
Package Option
15 NMC
North marker width control. Internally pulled
HI via 50 kΩ nominal.
AD2S90AP –40°C to +85°C
10.6 arc min P-20A
16 CLKOUT Internal VCO clock output. Indicates angular
velocity of input signals. Max nominal rate =
PIN CONFIGURATION
1.536 MHz. CLKOUT is a 300 ns positive pulse.
17 VEL
18 REF
Indicates angular velocity of input signals.
Positive voltage w.r.t. AGND indicates in-
creasing angle. FSD = 375 rps.
3
2
1
20 19
Converter reference input. Normally derived
from resolver primary excitation. REF = 2 V
rms nominal. Phase shift w.r.t. COS and SIN
= ±10° max
PIN 1
IDENTIFIER
4
5
6
7
8
18
17
16
15
14
DATA
SCLK
REF
VEL
AD2S90
TOP VIEW
(Not to Scale)
CLKOUT
NMC
CS
A
B
V
19 COS LO
20 COS
COS channel inverting input. Connect to
resolver COS LO.
DD
9
10 11 12 13
COS channel noninverting input. Connect to
resolver COS HI output. COS = 2 V rms ± 10%.
CAUTION
The AD2S90 features an input protection circuit consisting of large “distributed” diodes and
polysilicon series resistors to dissipate both high energy discharges (Human Body Model) and
fast, low energy pulses (Charges Device Model).
WARNING!
Proper ESD precautions are strongly recommended to avoid functional damage or performance
degradation. For further information on ESD precautions, refer to Analog Devices ESD
Prevention Manual.
ESD SENSITIVE DEVICE
–4–
REV. D
AD2S90
RESOLVER FORMAT SIGNALS
For more information on the operation of the converter, see
Circuit Dynamics section.
A resolver is a rotating transformer which has two stator wind-
ings and one rotor winding. The stator windings are displaced
mechanically by 90° (see Figure 4). The rotor is excited with an
ac reference. The amplitude of subsequent coupling onto the
stator windings is a function of the position of the rotor (shaft)
relative to the stator. The resolver, therefore, produces two
output voltages (S3–S1, S2–S4) modulated by the SINE and
COSINE of shaft angle. Resolver format signals refer to the
signals derived from the output of a resolver. Equation 1 illus-
trates the output form.
S2 TO S4
(COS)
S3 TO S1
(SIN)
S3–S1 = EO SIN ωt • SINθ
R2 TO R4
(REF)
S2–S4 = EO SIN ωt • COSθ
= shaft angle
SIN ωt = rotor excitation frequency
O = rotor excitation amplitude
(1)
where:
θ
E
0؇
90؇
180؇
270؇
360؇
Principle of Operation
The AD2S90 operates on a Type 2 tracking closed-loop prin-
Figure 4. Electrical and Physical Resolver Representation
ciple. The output continually tracks the position of the resolver
without the need for external convert and wait states. As the
transducer moves through a position equivalent to the least
significant bit weighting, the output is updated by one LSB.
Connecting The Converter
Refer to Figure 4. Positive power supply VDD = +5 V dc ± 5%
should be connected to Pin 13 & Pin 14 and negative power
supply VSS = –5 V dc ± 5% to Pin 12. Reversal of these power
supplies will destroy the device. S3 (SIN) and S2 (COS)
from the resolver should be connected to the SIN and COS pins
of the converter. S1 (SIN) and S4 (COS) from the resolver
should be connected to the SINLO and COSLO pins of the
converter. The maximum signal level of either the SIN or COS
resolver outputs should be 2 V rms ± 10%. The AD2S90
AGND pin is the point at which all analog signal grounds should
be star connected. The SIN LO and COS LO pins on the
AD2S90 should be connected to AGND. Separate screened
twisted cable pairs are recommended for all analog inputs SIN,
COS, and REF. The screens should terminate at the converter
AGND pin.
On the AD2S90, CLKOUT updates corresponding to one LSB
increment. If we assume that the current word state of the
up-down counter is φ, S3–S1 is multiplied by COS φ and S2–S4
is multiplied by SIN φ to give:
E
O SIN ωt • SIN θ COSφ
EO SIN ωt • COS θ SINφ
(2)
An error amplifier subtracts these signals giving:
E
O SIN θ • (SIN θ COS φ – COS θ SIN φ)
O SIN ωt • SIN (θ – φ)
or
E
(3)
where (θ – φ) = angular error
North marker width selection is controlled by Pin 15, NMC.
Application of VDD, 0 V, or VSS to NMC will select standard
90°, 180° and 360° pulsewidths. If unconnected, the NM pulse
defaults to 90°. For a more detailed description of the output
formats available see the Position Output section.
A phase sensitive detector, integrator and voltage controlled
oscillator (VCO) form a closed loop system which seeks to null
sin (θ – φ). When this is accomplished the word state of the
up/down counter, φ, equals within the rated accuracy of the
converter, the resolver shaft angle θ.
+5V
OSCILLATOR
47F
47F
10nF
10nF
0V (POWER GROUND)
–5V
18 17 16 15 14
REF
V
DD
S4
V
19
13
12
11
10
9
COS LO
DD
TWISTED PAIR
SCREENED
S2
CABLE
V
20
SS
COS
AGND
1
2
3
DGND
SIN
SIN LO
AD2S90AP
S2
R1
S4
S3
4
5
6
7
8
S3
S1
R2
RESOLVER
S1
POWER RETURN
Figure 5. Connecting the AD2S90 to a Resolver
–5–
REV. D
AD2S90
ABSOLUTE POSITION OUTPUT
The north marker pulse is generated as the absolute angular
position passes through zero. The AD2S90 supports the three
industry standard widths controlled using the NMC pin. Figure
7 details the relationship between A, B and NM. The width of
NM is defined relative to the A cycle.
SERIAL INTERFACE
Absolute angular position is represented by serial binary data
and is extracted via a three-wire interface, DATA, CS and
SCLK. The DATA output is held in a high impedance state
when CS is HI.
INCREASING ANGLE
Upon the application of a Logic LO to the CS pin, the DATA
output is enabled and the current angular information is trans-
ferred from the counters to the serial interface. Data is retrieved
by applying an external clock to the SCLK pin. The maximum
data rate of the SCLK is 2 MHz. To ensure secure data retrieval
it is important to note that SCLK should not be applied until a
minimum period of 600 ns after the application of a Logic LO
to CS. Data is then clocked out, MSB first, on successive nega-
tive edges of the SCLK; 12 clock edges are required to extract
the full 12 bits of data. Subsequent negative edges greater than
the defined resolution of the converter will clock zeros from the
data output if CS remains in a low state.
A
B
90؇
180؇
*
NM
If a resolution of less than 12 bits is required, the data access
can be terminated by releasing CS after the required number of
bits have been read.
360؇
NUMBER OF DEGREES REFERS TO WIDTH RELATIVE TO "A" CYCLE
WIDTH
LEVEL
t2
t6
SELECTABLE WITH THREE - LEVEL
CONTROL PIN "MARKER" DEFAULT
TO 90؇ USING INTERNAL PULL - UP.
*
90؇
180؇
360؇
+V
DD
0
CSB
SCLK
DATA
–V
SS
t3
Figure 7. A, B and NM Timing
Unlike incremental encoders, the AD2S90 encoder output is
not subject to error specifications such as cycle error, eccentric-
ity, pulse and state width errors, count density and phase φ.
t4
t*
MSB
LSB
The maximum speed rating, n, of an encoder is calculated from
its maximum switching frequency, fMAX, and its ppr (pulses per
revolution).
t1
t7
t5
*
THE MINIMUM ACCESS TIME: USER DEPENDENT
60× f MAX
n =
Figure 6. Serial Read Cycle
PPR
CS can be released a minimum of 100 ns after the last negative
edge. If the user is reading data continuously, CS can be reap-
plied a minimum of 250 ns after it is released (see Figure 6).
The AD2S90 A, B pulses are initiated from CLKOUT which
has a maximum frequency of 2.048 MHz. The equivalent
encoder switching frequency is:
The maximum read time is given by: (12-bits read @ 2 MHz)
Max RD Time = [600 + (12 × 500) + 600 + 100] = 7.30 µs.
1/4 × 2.048 MHz = 512 kHz (4 updates = 1 pulse)
At 12 bits the ppr = 1024, therefore the maximum speed, n, of
the AD2S90 is:
INCREMENTAL ENCODER OUTPUTS
The incremental encoder emulation outputs A, B and NM are
free running and are always valid, providing that valid resolver
format input signals are applied to the converter.
60 × 512000
n =
= 30000 rpm
1024
This compares favorably with encoder specifications where fMAX
is specified from 20 kHz (photo diodes) to 125 kHz (laser based)
depending on the light system used. A 1024 line laser-based
encoder will have a maximum speed of 7300 rpm.
The AD2S90 emulates a 1024-line encoder. Relating this to
converter resolution means one revolution produces 1024 A, B
pulses. B leads A for increasing angular rotation (i.e., clockwise
direction). The addition of the DIR output negates the need for
external A and B direction decode logic. DIR is HI for increas-
ing angular rotation.
The inclusion of A, B outputs allows the AD2S90 + resolver
solution to replace optical encoders directly without the need to
change or upgrade existing application software.
–6–
REV. D
AD2S90
VELOCITY OUTPUT
unless all parts of the system are backed up, a reset to a known
datum point needs to take place. This can be extremely hazard-
ous in many applications. The AD2S90 gets round this problem
by supplying an absolute position serial data stream upon re-
quest, thus removing the need to reset to a known datum.
The analog velocity output VEL is scaled to produce 150 rps/V
dc ± 15%. The sense is positive V dc for increasing angular
rotation. VEL can drive a maximum load combination of
10 kΩ and 30 pF. The internal velocity scaling is fixed.
HOST I/O
PORT
POSITION CONTROL
TO HOST PROCESSOR
The rotor movement of dc or ac motors used for servo control is
monitored at all times. Feedback transducers used for this pur-
pose detect either relative position in the case of an incremental
encoder or absolute position and velocity using a resolver. An
incremental encoder only measures change in position not
actual position.
COMMAND POSITION
SEQUENCER (32-BIT)
HOST
INTERFACE
POWER
AMP
+
8 – 12
DAC
DIGITAL
PID
FILTER
(16-BIT)
⌺
–
DAC
PORT
DC
MOTOR
POSITION
FEEDBACK
PROCESSOR
(32-BIT)
Closed Loop Control Systems
The primary demand for a change in position must take into
account the magnitude of that change and the associated accel-
eration and velocity characteristics of the servo system. This is
necessary to avoid “hunting” due to over- or underdamping of
the control employed.
OPTIONAL
VELOCITY
FEEDBACK
IN, A, B
INCREMENTAL POSITION
AD2S90
ABSOLUTE
POSITION
RESOLVER
A position loop needs both actual and demand position infor-
mation. Algorithms consisting of proportional, integral and
derivative control (PID) may be implemented to control the
velocity profile.
Figure 9. Practical Implementation of the AD2S90
DSP Interfacing
The AD2S90 serial output is ideally suited for interfacing to
DSP configured microprocessors. Figures 10 to 13 illustrate
how to configure the AD2S90 for serial interfacing to the DSP.
A simplified position loop is shown in Figure 8.
ADSP-2105 Interfacing
POSITION CONTROLLER
SERVO
MOTOR
SERVO
AMP
Figure 10 shows the AD2S90 interfaced to an ADSP-2105. The
on-chip serial port of the ADSP-2105 is used in alternate fram-
ing receive mode with internal framing (internally inverted) and
internal serial clock generation (externally inverted) options
selected. In this mode the ADSP-2105 provides a CS and a
serial clock to the AD2S90. The serial clock is inverted to pre-
vent timing errors as a result of both the AD2S90 and ADSP-
2105 clock data on the negative edge of SCLK. The first data
bit is void; 12 bits of significant data then follow on each con-
secutive negative edge of the clock. Data is clocked from the
AD2S90 into the data receive register of the ADSP-2105. This
is internally set to 13 bit (12 bits and one “dummy” bit) when
13 bits are received. The serial port automatically generates an
internal processor interrupt. This allows the ADSP-2105 to read
12 significant bits at once and continue processing.
POSITION
DEMAND
RE-
SOLVER
ACTUAL
POSITION
AD2S90
Figure 8. Position Loop
MOTION CONTROL PROCESSES
Advanced VLSI designs mean that silicon system blocks are now
available to achieve high performance motion control in servo
systems.
A digital position control system using the AD2S90 is shown in
Figure 9. In this system the task of determining the acceleration
and velocity characteristics is fulfilled by programming a trap-
ezoidal velocity profile via the I/O port.
The ADSP-2101, ADSP-2102, ADSP-2111 and 21msp50 can
all interface to the AD2S90 with similar interface circuitry.
As can be seen from Figure 9 encoder position feedback infor-
mation is used. This is a popular format and one which the
AD2S90 emulates thereby facilitating the replacement of encod-
ers with an AD2S90 and a resolver. However, major benefits
can be realized by adopting the resolver principle as opposed to
the incremental technique.
SCLK
ADSP-2105
SCLK
AD2S90
RFS
CS
DR
DATA
Incremental feedback based systems normally carry out a peri-
odic check between the position demanded by the controller
and the increment position count. This requires software and
hardware comparisons and battery backup in the case of power
failure. If there is a supply failure and the drive system moves,
NOTE:
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 10. ADSP-2105/AD2S90 Serial Interface
REV. D
–7–
AD2S90
TMS32020 Interfacing
Select the AD2S90 and frame the data. The S1 register is fixed
at 16 bits, therefore, to obtain the 12-significant bits the proces-
sor needs to execute four right shifts. Once the NEC7720 has
read 16 bits, an internal interrupt is generated to read the inter-
nal contents of the S1 register.
Figure 11 shows the serial interface between the AD2S90 and
the TMS32020. The interface is configured in alternate internal
framing, external clock (externally inverted) mode. Sixteen bits
of data are clocked from the AD2S90 into the data receive regis-
ter (DRR) of the TMS32020. The DRR is fixed at 16 bits. To
obtain the 12-significant bits, the processor needs to execute
three right shifts. (First bit read is void, the last three will be
zeros). When 16 bits have been received by the TMS32020, it
generates an internal interrupt to read the data from the DRR.
SCLK
SCLK
PD7720
AD2S90
SIEN
CS
S1
DATA
NOTE:
SCLK
FSR
SCLK
ADDITIONAL PINS OMITTED FOR CLARITY
TMS32020
AD2S90
CS
Figure 13. µPD7720/AD2S90 Serial Interface
DRR
DATA
EDGE TRIGGERED 4
؋
DECODING LOGIC NOTE:
In most data acquisition or control systems the A, B incremental
outputs must be decoded into absolute information, normally a
parallel word, before they can be utilized effectively.
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 11. TMS32020/AD2S90 Serial Interface
To decode the A, B outputs on the AD2S90 the user must
implement a 4× decoding architecture. The principle states that
one A, B cycle represents 4 LSB weighted increments of the
converter (see Equation 4).
DSP56000 Interface
Figure 12 shows a serial interface between the AD2S90 and the
DSP56000. The DSP in configured for normal mode synchro-
nous operation with gated clock with SCLK and SC1 as out-
puts. SC1 is applied to CS.
Up = (↑A) • B + (↓B) • A + (↓A) • B + (↑Β) • A
Down = (↑A) • B + (↑B) • A + (↓A) • B + (↓B) • A
(4)
SCLK
SC1
SCLK
DSP56000
AD2S90
CLOCKWISE ROTATION
COUNTER CLOCKWISE ROTATION
CS
CH A
CH B
SRD
DATA
NOTE:
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 12. DSP56000/AD2S90 Serial Interface
UP
DOWN
The DSP56000 assumes valid data on the first falling edge of
SCLK. SCLK is inverted to ensure that the valid data is clocked
in after one leading bit. The receive data shift register (SRD) is
set for a 13-bit word.
Figure 14. Principles of 4× Decoding
The algorithms in Equation 4 can be implemented using the
architecture shown in Figure 15. Traditionally the direction of
the shaft is decoded by determining whether A leads B. The
AD2S90 removes the need to derive direction by supplying a
direction output state which can be fed straight into the up-
down counter.
When this register has received 13 bits of data, it generates an
internal interrupt on the DSP56000 to read the 12 bits of sig-
nificant data from the register.
NEC7720 Interface
Figure 13 shows the serial interface between the NEC7720 and
the AD2S90. The NEC7720 expects data on the rising edge of
its SCLK output, and therefore unlike the previous interfaces no
inverter is required to clock data into the S1 register. There is
no need to ignore the first data bit read. SIEN is used to Chip
For further information on this topic please refer to the applica-
tion note “Circuit Applications of the AD2S90 Resolver-to-
Digital Converters.”
CHA
A
A
B
B
EDGE GENERATOR
CHB
CLOCK
PARALLEL
UP/DOWN
COUNTER
DIGITAL
OUTPUT
DIRECTION
U/D
RESET
Figure 15. 4× Decoding Incremental to Parallel Conversion
–8–
REV. D
AD2S90
REMOTE MULTIPLE SENSOR INTERFACING
The DATA output of the AD2S90 is held in a high impedance
state until CS is taken LO. This allows a user to operate the
AD2S90 in an application with more than one converter con-
nected on the same line. Figure 16 shows four resolvers inter-
faced to four AD2S90s. Excitation for the resolvers is provided
locally by an oscillator.
The AD2S90 acceleration constant is given by:
Ka = K1 × K2 3.0 ×106 sec−2
(8)
The AD2S90’s design has been optimized with a critically
damped response. The closed-loop transfer function is given by:
θOUT
θIN
1+st1
s2
K1K2 K1K2
=
s3t2
SCLK, DATA and two address lines are fed down low loss
cables suitable for communication links. The two address lines
are decoded locally into CS for the individual converters. Data
is received and transmitted using transmitters and receivers.
(9)
1+st1 +
+
The normalized gain and phase diagrams are given in Figures 18
and 19.
A0
2-4 DECODING
(74HC139)
5
0
A1
4
4
4
4
CS CS CS CS
AD2S90
1
1
2
3
4
RES1
RES2
RES3
RES4
–5
AD2S90
2
SCLK
DATA
–10
AD2S90
3
–15
–20
–25
–30
AD2S90
4
V
DD
2
V
SS
2
OSC
0V
BUFFER
–35
–40
–45
Figure 16. Remote Sensor Interfacing
CIRCUIT DYNAMICS/ERROR SOURCES
Transfer Function
1
10
100
1k
10k
FREQUENCY – Hz
The AD2S90 operates as a Type 2 tracking servo loop. An
integrator and VCO/counter perform the two integrations inher-
ent in a Type 2 loop.
Figure 18. AD2S90 Gain Plot
0
The overall system response of the AD2S90 is that of a unity
gain second order low-pass filter, with the angle of the resolver
as the input and the digital position data as the output. Figure
17 illustrates the AD2S90 system diagram.
–20
–40
–60
–80
–100
–120
–140
VEL OUT
OUT
IN
A1 (S)
A2 (S)
Figure 17. AD2S90 Transfer Function
–160
–180
The open-loop transfer function is given by:
1
10
100
1k
10k
θOUT
K1K2 (1+ st1)
FREQUENCY – Hz
=
(5)
s2
θIN
1+ st2
Figure 19. AD2S90 Phase Plot
where:
K11+st1
s 1+st2
t1 =1.0ms
t2 = 90µs
A(s)=
1
(6)
(7)
(
)
K2
s
K1 = 4.875V / LSB ×sec
K2 =614,400 LSB/(V ×sec)
A (s)=
2
REV. D
–9–
AD2S90
The small step response is given in Figure 20, and is the time
taken for the converter to settle to within 1 LSB.
SOURCES OF ERROR
Acceleration Error
A tracking converter employing a Type 2 servo loop does not
suffer any velocity lag, however, there is an additional error due
to acceleration. This additional error can be defined using the
acceleration constant Ka of the converter.
ts = 7.00 ms (maximum)
The large step response (steps >20°) applies when the error
voltage will exceed the linear range of the converter. Typically it
will take three times longer to reach the first peak for a 179°
step.
Input Acceleration
Error in Output Angle
Ka
=
(10)
In response to a velocity step [VELOUT/(dθ/dt)] the velocity
output will exhibit the same response characteristics as outlined
above.
The numerator and denominator’s units must be consistent. Ka
does not define maximum input acceleration, only the error due to
its acceleration. The maximum acceleration allowable before the
converter loses track is dependent on the angular accuracy
requirements of the system.
Angular Error × Ka = degrees/sec2
(11)
10؇
Ka can be used to predict the output position error for a given
input acceleration. The AD2S90 has a fixed Ka = 3.0 × 106
sec–2 if we apply an input accelerating at 100 revs/sec2, the error
can be calculated as follows:
Input Acceleration LSB / sec2
[
]
Error in LSBs =
0؇
Ka sec−2
[
]
100 rev/sec2 ×212 LSB/rev
0
4
8
12
16
20
[
]
= 0.14 LSBs
[
]
=
(12)
3.0×106 sec–2
Figure 20. Small Step Response
[
]
–10–
REV. D
AD2S90
AD2S90/AD2S99 TYPICAL CONFIGURATION
shields should also be terminated at the AD2S90 AGND pin.
The SYNREF output of the AD2S99 should be connected to
the REF input pin of the AD2S90 via a 0.1 µF capacitor with a
100 kΩ resistor to GND. This is to block out any dc offset in
the SYNREF signal. For more detailed information please refer
to the AD2S99 data sheet.
Figure 21 shows a typical circuit configuration for the AD2S99
Oscillator and the AD2S90 Resolver-to-Digital Converter. The
maximum level of the SIN and COS input signals to the
AD2S90 should be 2 V rms ±10%. All the analog ground sig-
nals should be star connected to the AD2S90 AGND pin. If
shielded twisted pair cables are used for the resolver signals, the
V
SS
0.1F
4.7F
2
3
1
20 19
NC = NO CONNECT
EXC
NC
4
18
EXC
SIN
5
6
17
16
AD2S99
DGND
COS
AGND
TOP VIEW
(Not to Scale)
7
8
15 NC
14 NC
SEL2 = GND
NC
SEL1 = V
SS
F
= 5kHz
OUT
9
10 11 12 13
V
DD
50k⍀
4.7F
0.1F
0.1F
100k⍀
V
V
DD
18 17 16 15 14
4.7F
4.7F
0.1F
0.1F
REF
V
19
20
1
13
COS LO
DD
COS
V
12
11
10
9
SS
SS
AGND
SIN
DGND
S2
R2
COS S4
2
AD2S90
S3
TOP VIEW
(Not to Scale)
3
SIN LO
REF
R4
SIN
S1
5
6
4
7
8
RESOLVER
Figure 21. AD2S90 and AD2S99 Example Configuration
REV. D
–11–
AD2S90
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
P-20A
20-Lead Plastic Leaded Chip Carrier (PLCC)
0.180 (4.57)
0.165 (4.19)
0.048 (1.21)
0.056 (1.42)
0.042 (1.07)
0.025 (0.63)
0.015 (0.38)
0.042 (1.07)
0.048 (1.21)
3
19
18
0.042 (1.07)
0.021 (0.53)
0.013 (0.33)
4
8
PIN 1
0.050
(1.27)
BSC
IDENTIFIER
0.330 (8.38)
0.290 (7.37)
TOP VIEW
(PINS DOWN)
0.032 (0.81)
0.026 (0.66)
14
9
13
0.020
(0.50)
R
0.040 (1.01)
0.025 (0.64)
0.356 (9.04)
SQ
0.350 (8.89)
0.110 (2.79)
0.085 (2.16)
0.395 (10.02)
SQ
0.385 (9.78)
0.020
(0.50)
R
PIN 1
IDENTIFIER
BOTTOM
VIEW
(PINS UP)
–12–
REV. D
AD2S90 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| AD2S90AP | ADI | Low Cost, Complete 12-Bit Resolver-to-Digital Converter | 获取价格 |
|
| AD2S90APZ | ADI | Low Cost, Complete 12-Bit Resolver-to-Digital Converter | 获取价格 |
|
| AD2S93 | ADI | Low Cost LVDT-to-Digital Converter | 获取价格 |
|
| AD2S93AP | ADI | Low Cost LVDT-to-Digital Converter | 获取价格 |
|
| AD2S93BP | ADI | Low Cost LVDT-to-Digital Converter | 获取价格 |
|
| AD2S99 | ADI | Programmable Oscillator | 获取价格 |
|
| AD2S99AP | ADI | Programmable Oscillator | 获取价格 |
|
| AD2S99APZ | ADI | Programmable Oscillator | 获取价格 |
|
| AD2S99BP | ADI | Programmable Oscillator | 获取价格 |
|
| AD2S99BPZ | ADI | Programmable Oscillator | 获取价格 |
|
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