AD5204BR100 [ADI]
4-/6-Channel Digital Potentiometers; 4- / 6通道数字电位器
| 型号： | AD5204BR100 |
| 厂家： | 
ADI |
| 描述： | 4-/6-Channel Digital Potentiometers |
| 文件： | 总11页 (文件大小：176K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4-/6-Channel
a
Digital Potentiometers
AD5204/AD5206
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
256 Position
Multiple Independently Programmable Channels
AD5204—4-Channel
AD5206—6-Channel
Potentiometer Replacement
10 k⍀, 50 k⍀, 100 k⍀
3-Wire SPI-Compatible Serial Data Input
+2.7 V to +5.5 V Single Supply; ؎2.7 V Dual Supply
Operation
AD5204
V
DD
CS
A1
W1
B1
CLK
D7
D0
EN
RDAC
LATCH
#1
ADDR
DEC
A2
A1
A0
DO
SDO
R
D7
Power ON Midscale Preset
SER
REG
A4
W4
B4
APPLICATIONS
D7
D0
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Programmable Voltage-to-Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
RDAC
LATCH
#4
DI
D0
SDI
SHDN
8
R
V
POWER-
ON
PRESET
SS
PR
GND
GENERAL DESCRIPTION
AD5206
V
CS
DD
The AD5204/AD5206 provides four-/six-channel, 256 position
digitally-controlled Variable Resistor (VR) devices. These de-
vices perform the same electronic adjustment function as a
potentiometer or variable resistor. Each channel of the AD5204/
AD5206 contains a fixed resistor with a wiper contact that taps
the fixed resistor value at a point determined by a digital code
loaded into the SPI-compatible serial-input register. The resis-
tance between the wiper and either endpoint of the fixed resistor
varies linearly with respect to the digital code transferred into
the VR latch. The variable resistor offers a completely program-
mable value of resistance between the A terminal and the wiper
or the B Terminal and the wiper. The fixed A-to-B terminal
resistance of 10 kΩ, 50 kΩ, or 100 kΩ has a nominal tempera-
ture coefficient of 700 ppm/°C.
A1
W1
B1
CLK
D7
EN
RDAC
LATCH
#1
ADDR
DEC
A2
A1
A0
R
D0
D7
SER
REG
A6
W6
B6
D7
D0
RDAC
LATCH
#6
DI
D0
SDI
8
R
POWER-
ON
PRESET
GND
V
SS
Each VR has its own VR latch which holds its programmed
resistance value. These VR latches are updated from an internal
serial-to-parallel shift register that is loaded from a standard
3-wire serial-input digital interface. Eleven data bits make up
the data word clocked into the serial input register. The first
three bits are decoded to determine which VR latch will be
loaded with the last eight bits of the data word when the CS
strobe is returned to logic high. A serial data output pin at
the opposite end of the serial register (AD5204 only) allows
simple daisy-chaining in multiple VR applications without
additional external decoding logic.
An optional reset (PR) pin forces all the AD5204 wipers to the
midscale position by loading 80H into the VR latch.
The AD5204/AD5206 is available in both surface mount
(SOL-24), TSSOP-24 and the 24-lead plastic DIP package. All
parts are guaranteed to operate over the extended industrial
temperature range of –40°C to +85°C. For additional single,
dual, and quad channel devices, see the AD8400/AD8402/
AD8403 products.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
AD5204/AD5206–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (V = +5 V ؎ 10% or +3 V ؎ 10%, V = 0 V, V = +V , V = 0 V, –40؇C < T < +85؇C
unless otherwise noted.)
DD
SS
A
DD
B
A
Parameter
Symbol
Conditions
Min
Typ1
Max
Units
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
Resistor Differential NL2
Resistor Nonlinearity Error2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
Nominal Resistance Match
Wiper Resistance
R-DNL
R-INL
∆RAB
∆RAB/∆T
∆R/RAB
RW
RWB, VA = No Connect
RWB, VA = No Connect
TA = +25°C
VAB = VDD, Wiper = No Connect
CH1 to 2, 3, 4, or 5, 6; VAB = VDD
IW = 1 V/R, VDD = +5 V
–1
–2
–30
±1/4
±1/2
+1
+2
+30
LSB
LSB
%
ppm/°C
%
700
0.25
50
1.5
100
Ω
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs
Resolution
N
DNL
INL
8
–1
–2
Bits
LSB
LSB
ppm/°C
LSB
Differential Nonlinearity4
±1/4
±1/2
15
–1
+1
+1
+2
Integral Nonlinearity4
Voltage Divider Temperature Coefficient ∆VW/∆T
Full-Scale Error
Zero-Scale Error
Code = 40H
Code = 7FH
Code = 00H
VWFSE
VWZSE
–2
0
0
+2
LSB
RESISTOR TERMINALS
Voltage Range5
VA, VB, VW
CA, CB
CW
IA_SD
ICM
VSS
VDD
V
Capacitance6 Ax, Bx
Capacitance6 Wx
f = 1 MHz, Measured to GND, Code = 40H
f = 1 MHz, Measured to GND, Code = 40H
45
60
0.01
1
pF
pF
µA
nA
Shutdown Current7
Common-Mode Leakage
5
VA = VB = VW = 0, VDD = +2.7 V, VSS = –2.5 V
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Output Logic High
Output Logic Low
VIH
VIL
VOH
VOL
IIL
VDD = +5 V/+3 V
VDD = +5 V/+3 V
RPULL–UP = 1 kΩ to +5 V
IOL = 1.6 mA, VLOGIC = +5 V
VIN = 0 V or +5 V
2.4/2.1
4.9
V
V
V
V
µA
pF
0.8/0.6
0.4
±1
Input Current
Input Capacitance6
CIL
5
POWER SUPPLIES
Power Single Supply Range
Power Dual Supply Range
Positive Supply Current
Negative Supply Current
Power Dissipation8
VDD Range
VDD/SS Range
IDD
ISS
PDISS
VSS = 0 V
2.7
±2.3
5.5
±2.7
60
60
0.3
V
V
µA
µA
mW
%/%
VIH = +5 V or VIL = 0 V
VSS = –2.5 V, VDD = +2.7 V
VIH = +5 V or VIL = 0 V
∆VDD = +5 V ± 10%
12
12
Power Supply Sensitivity
PSS
0.0002 0.005
DYNAMIC CHARACTERISTICS6, 9
Bandwidth –3 dB
BW_10K
BW_50K
BW_100K
THDW
tS
RAB = 10 kΩ
RAB = 50 kΩ
RAB = 100 kΩ
VA = 1.414 V rms, VB = 0 V dc, f = 1 kHz
VA = 5 V, VB = 0 V, ±1 LSB Error Band
RWB = 5 kΩ, f = 1 kHz, PR = 0
721
137
69
0.004
2/9/18
9
kHz
kHz
kHz
%
µs
nV/√Hz
Total Harmonic Distortion
VW Settling Time (10K/50K/100K)
Resistor Noise Voltage
eN_WB
INTERFACE TIMING CHARACTERISTICS Applies to All Parts6, 10
Input Clock Pulsewidth
Data Setup Time
tCH, tCL
tDS
tDH
tPD
tCSS
tCSW
tRS
tCSH0
tCSH1
tCS1
Clock Level High or Low
20
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Hold Time
CLK to SDO Propagation Delay11
CS Setup Time
RL = 2 kΩ, CL < 20 pF
1
150
15
40
90
0
0
10
CS High Pulsewidth
Reset Pulsewidth
CLK Fall to CS Fall Setup
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
NOTES
1Typicals represent average readings at +25°C and VDD = +5 V.
2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-
tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 23 test circuit. I W = VDD/R
for both VDD = +3 V or VDD = +5 V.
3VAB = VDD, Wiper (VW) = No connect.
4INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See Figure 22 test circuit.
–2–
REV. 0
AD5204/AD5206
5Resistor Terminals A, B, W, have no limitations on polarity with respect to each other.
6Guaranteed by design and not subject to production test.
7Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode.
8PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
9All dynamic characteristics use VDD = +5 V.
10See timing diagrams for location of measured values. All input control voltages are specified with t R = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage
level of 1.5 V. Switching characteristics are measured using both VDD = +3 V or +5 V.
11Propagation delay depends on value of VDD, RL and CL. See Operation section.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C, unless otherwise noted)
Package Power Dissipation . . . . . . . . . . . . . . (TJ max–TA)/θJA
Thermal Resistance θJA
P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
TSSOP-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143°C/W
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +7 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, –7 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD
Ax–Bx, Ax–Wx, Bx–Wx . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Digital Input and Output Voltage to GND . . . . . . . 0 V, +7 V
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (TJ MAX) . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5204/AD5206 features proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD5204/AD5206
1
tRS
SDI
CLK
CS
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
1
0
1
0
PR
tS
V
DD
0V
؎1 LSB
V
OUT
RDAC LATCH LOAD
؎1 LSB ERROR BAND
Figure 3. AD5204 Preset Timing Diagram
V
DD
V
OUT
0V
Figure 1. Timing Diagram
1
0
SDI
(DATA IN)
Ax OR Dx
Ax OR Dx
tDS
tDH
1
0
SDO
(DATA OUT)
Ax OR Dx
Ax OR Dx
tPD_MAX
tCS1
tCH
1
0
CLK
tCSH0
tCSH1
tCL
tCSS
1
0
tCSW
tS
CS
V
؎1 LSB
DD
V
OUT
؎1 LSB ERROR BAND
0V
Figure 2. Detail Timing Diagram
ORDERING GUIDE
Model
k⍀
Temperature Range
Package Descriptions
24-Lead Narrow Body (PDIP)
24-Lead Wide Body (SOIC)
24-Lead Thin Shrink SO Package (TSSOP)
Package Options
AD5204BN10
AD5204BR10
AD5204BRU10
10
10
10
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
N-24
R-24/SOL-24
RU-24
AD5204BN50
AD5204BR50
AD5204BRU50
50
50
50
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
24-Lead Narrow Body (PDIP)
24-Lead Wide Body (SOIC)
24-Lead Thin Shrink SO Package (TSSOP)
N-24
R-24/SOL-24
RU-24
AD5204BN100
AD5204BR100
AD5204BRU100
100
100
100
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
24-Lead Narrow Body (PDIP)
24-Lead Wide Body (SOIC)
24-Lead Thin Shrink SO Package (TSSOP)
N-24
R-24/SOL-24
RU-24
AD5206BN10
AD5206BR10
AD5206BRU10
AD5206BN50
AD5206BR50
AD5206BRU50
AD5206BN100
AD5206BR100
AD5206BRU100
10
10
10
50
50
50
100
100
100
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
24-Lead Narrow Body (PDIP)
24-Lead Wide Body (SOIC)
24-Lead Thin Shrink SO Package (TSSOP)
24-Lead Narrow Body (PDIP)
24-Lead Wide Body (SOIC)
24-Lead Thin Shrink SO Package (TSSOP)
24-Lead Narrow Body (PDIP)
24-Lead Wide Body (SOIC)
N-24
R-24/SOL-24
RU-24
N-24
R-24/SOL-24
RU-24
N-24
R-24/SOL-24
RU-24
24-Lead Thin Shrink SO Package (TSSOP)
The AD5204/AD5206 contains 5,925 transistors. Die size; 92 mil × 114 mil, 10,488 sq. mil.
–4–
REV. 0
AD5204/AD5206
AD5206 PIN CONFIGURATION
AD5204 PIN CONFIGURATION
NC
NC
1
2
24 B4
1
2
24
23
22
21
20
19
18
17
A6
W6
B4
W4
A4
B2
W2
A2
A1
W1
23
22
21
20
19
18
17
W4
A4
B2
W2
A2
A1
W1
3
3
GND
CS
B6
4
4
GND
CS
5
5
PR
AD5204
(NOT TO
SCALE)
AD5206
(NOT TO
SCALE)
6
V
6
V
DD
DD
7
7
SDI
SHDN
SDI
8
8
CLK
CLK
9
16 B1
9
16 B1
V
SS
10
11
15
14
A3
10
11
15
14
SDO
B5
A3
V
W3
W5
W3
SS
13 B3
NC 12
13 B3
A5 12
NC = NO CONNECT
AD5204 PIN FUNCTION DESCRIPTIONS
AD5206 PIN FUNCTION DESCRIPTIONS
Pin
No.
Pin
No.
Name
Description
Name
Description
1, 2,
12
3
4
1
2
3
4
5
A6
W6
B6
GND
CS
A Terminal RDAC #6.
Wiper RDAC #6, addr = 1012.
B Terminal RDAC #6.
Ground.
Chip Select Input, Active Low. When CS
returns high, data in the serial input register
is decoded based on the address bits and
loaded into the target RDAC latch.
Positive power supply, specified for
operation at both +3 V or +5 V. (Sum of
|VDD| + |VSS| <5.5 V.)
Serial Data Input. MSB First.
Serial Clock Input, positive edge triggered.
Negative Power Supply, specified for
operation at both 0 V or –2.7 V. (Sum of
|VDD| + |VSS| <5.5 V.)
B Terminal RDAC #5.
Wiper RDAC #5, addr = 1002.
A Terminal RDAC #5.
B Terminal RDAC #3.
Wiper RDAC #3, addr = 0102.
A Terminal RDAC #3.
B Terminal RDAC #1.
Wiper RDAC #1, addr = 0002.
A Terminal RDAC #1.
NC
GND
CS
Not Connected.
Ground.
Chip Select Input, Active Low. When CS
returns high, data in the serial input register
is decoded based on the address bits and
loaded into the target RDAC latch.
Active low preset to midscale; sets RDAC
registers to 80H.
Positive power supply, specified for
operation at both +3 V or +5 V. (Sum of
|VDD| + |VSS| <5.5 V.)
Active low input. Terminal A open-circuit.
Shutdown controls Variable Resistors #1
through #4.
Serial Data Input. MSB First.
Serial Clock Input, positive edge triggered.
Serial Data Output, Open Drain transistor
requires pull-up resistor.
Negative Power Supply, specified for
operation at both 0 V or –2.7 V. (Sum of
|VDD| + |VSS| <5.5 V.)
B Terminal RDAC #3.
Wiper RDAC #3, addr = 0102.
A Terminal RDAC #3.
B Terminal RDAC #1.
Wiper RDAC #1, addr = 0002.
A Terminal RDAC #1.
A Terminal RDAC #2.
Wiper RDAC #2, addr = 0012.
B Terminal RDAC #2.
5
6
PR
6
VDD
VDD
7
8
9
SDI
CLK
VSS
7
SHDN
8
9
10
SDI
CLK
SDO
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
B5
W5
A5
B3
W3
A3
B1
W1
A1
A2
W2
B2
A4
W4
B4
11
VSS
13
14
15
16
17
18
19
20
21
22
23
24
B3
W3
A3
B1
W1
A1
A2
W2
B2
A4
W4
B4
A Terminal RDAC #2.
Wiper RDAC #2, addr = 0012.
B Terminal RDAC #2.
A Terminal RDAC #4.
Wiper RDAC #4, addr = 0112.
B Terminal RDAC #4.
A Terminal RDAC #4.
Wiper RDAC #4, addr = 0112.
B Terminal RDAC #4.
–5–
REV. 0
–Typical Performance Characteristics
AD5204/AD5206
120
110
V
/V = 2.7V/0V
DD SS
100
90
80
70
60
50
10k⍀
0
V
V
V
= ؎2.7V
= –2.7V
= 100mV rms
–2
DD
SS
A
–4
DATA = 80
H
50k⍀
V
A
V
/V = 5.5V/0V
DD SS
100k⍀
V
/V = ؎2.7V
DD SS
OP42
40
30
–3.0 –2.0 –1.0
0
1.0
2.0
3.0
4.0
5.0
6.0
1k
10k
100k
1M
COMMON MODE – V
FREQUENCY – Hz
Figure 4. Incremental Wiper ON Resistance vs. Voltage
Figure 7. –3 dB Bandwidth vs. Terminal Resistance,
±2.7 V Dual Supply Operation
–5.99
–6.00
0
DATA = 80
DATA = 40
H
–6
–12
–18
H
–6.01
–6.02
DATA = 20
DATA = 10
DATA = 08
DATA = 04
DATA = 02
H
H
H
H
H
10k⍀
–6.03
–24
–30
–36
–42
–48
50k⍀
V
V
V
= 2.7V
= –2.7V
= 100mV rms
DD
SS
A
–6.04
–6.05
–6.06
–6.07
100k⍀
DATA = 80
H
T
= +25؇C
A
V
A
DATA = 01
H
V
V
V
V
= 2.7V
A
DD
SS
A
A
OP42
= –2.7V
= 100mV rms
= +25؇C
–6.08
–6.09
–54
–60
V
= 0V
OP42
B
T
100
1k
10k
100k
1k
10k
100k
1M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 5. Gain Flatness vs. Frequency
Figure 8. Bandwidth vs. Code, 10K Version
0
DATA = 80
H
–6
–12
–18
DATA = 40
H
DATA = 20
DATA = 10
DATA = 08
10k⍀
H
H
H
0
V
V
V
= 2.7V
= 0V
= 100mV rms
–24
–30
–36
–42
–48
–2
–4
DD
SS
A
DATA = 80
H
50k⍀
DATA = 04
DATA = 02
T
= +25؇C
H
H
H
A
2.7V
100k⍀
DATA = 01
V
OP42
V
V
V
T
= 2.7V
= –2.7V
DD
A
SS
+1.5V
–54
–60
= 100mV rms
OP42
A
= +25؇C
A
1k
10k
100k
1M
1k
10k
100k
1M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 6. –3 dB Bandwidth vs. Terminal Resistance,
2.7 V Single Supply Operation
Figure 9. Bandwidth vs. Code, 50K Version
–6–
REV. 0
AD5204/AD5206
0
8
7
6
5
4
3
2
1
T
= +25؇C
DATA = 80
A
H
–6
DATA = 40
H
–12
–18
I
, V /V = 5.5V/0V, DATA = 55H
DD DD SS
DATA = 20
DATA = 10
DATA = 08
DATA = 04
DATA = 02
H
H
H
H
I
I
, V /V = ؎2.7V, DATA = 55H
SS DD SS
–24
–30
–36
–42
–48
, V /V = 5,5V/0V, DATA = FFH
DD DD SS
I
, V /V = ؎2.7V, DATA = FFH
SS DD SS
H
H
I
, V /V = 2.7V/0V, DATA = FFH
DATA = 01
V
DD DD SS
V
V
V
T
= 2.7V
= –2.7V
I
, V /V = ؎2.7V/0V, DATA = 55H
DD
DD DD SS
A
SS
–54
–60
= 100mV rms
OP42
A
= +25؇C
A
0
10k
1k
10k
100k
1M
100k
FREQUENCY – Hz
1M
10M
FREQUENCY – Hz
Figure 10. Bandwidth vs. Code, 100K Version
Figure 13. Supply Current vs. Clock Frequency
2.5
2.0
60
T
= +25؇C
A
50
V
= –3.0V ؎ 10%
SS
V
= 5.0V ؎ 10%
40
30
DD
SINGLE SUPPLY
1.0
0.1
0.5
0.0
V
= V
DD
SS
DUAL SUPPLY
= 0V
V
SS
V
= 3.0V ؎ 10%
DD
20
10
0
10
1.0
2.0
3.0
4.0
5.0
6.0
100
1k
10k
100k
FREQUENCY – Hz
SUPPLY VOLTAGE V – Volts
DD
Figure 14. Power Supply Rejection vs. Frequency
Figure 11. Digital Input Trip Point vs. Supply Voltage
100
1.0
I
AT V /V = ؎2.7V
DD SS
SS
T
= +25؇C
A
V
V
= +2.7V
= –2.7V
= +25؇C
DD
SS
10
T
A
0.1
R
= 10k⍀
AB
I
AT V /V = 5.5V/0V
DD SS
DD
1
0.01
NONINVERTING TEST CIRCUIT
INVERTING TEST CIRCUIT
I
AT V /V = ؎2.7V
DD SS
DD
0.1
0.001
0.01
I
AT V /V = 2.7V/0V
DD SS
DD
0.0001
0.001
0
10
100
1k
10k
100k
1
2
3
4
5
6
FREQUENCY – Hz
INCREMENTAL INPUT LOGIC VOLTAGE – Volts
Figure 15. Total Harmonic Distortion Plus Noise vs.
Frequency
Figure 12. Supply Current vs. Input Logic Voltage
–7–
REV. 0
AD5204/AD5206
OPERATION
data 00H. This B terminal connection has a wiper contact resis-
tance of 45 Ω. The second connection (10 kΩ part) is the first
tap point located at 84 Ω [= RBA (nominal resistance)/256 + RW
= 84 Ω + 45 Ω] for data 01H. The third connection is the next
tap point representing 78 + 45 = 123 Ω for data 02H. Each LSB
data value increase moves the wiper up the resistor ladder until
the last tap point is reached at 10006 Ω. The wiper does not
directly connect to the A terminal. See Figure 16 for a simplified
diagram of the equivalent RDAC circuit.
The AD5204/AD5206 provides a four-/six-channel, 256-position
digitally-controlled variable resistor (VR) device. Changing the
programmed VR settings is accomplished by clocking in a 11-
bit serial data word into the SDI (Serial Data Input) pin. The
format of this data word is three address bits, MSB first, fol-
lowed by eight data bits, MSB first. Table I provides the serial
register data word format.
Table I. Serial-Data Word Format
The general transfer equation determining the digitally pro-
grammed output resistance between Wx and Bx is:
ADDR
DATA
B10 B9 B8
B7 B6 B5 B4 B3 B2 B1 B0
R
WB (Dx) = (Dx)/256 × RBA + RW
(1)
where Dx is the data contained in the 8-bit RDACx latch, and
RBA is the nominal end-to-end resistance.
A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB MSB
LSB
210
28 27
20
For example, when VB = 0 V and A terminal is open-circuit, the
following output resistance values will be set for the following
RDAC latch codes (applies to the 10K potentiometer):
See Table IV for the AD5204/AD5206 address assignments to
decode the location of VR latch receiving the serial register data
in Bits B7 through B0. VR outputs can be changed one at a
time in random sequence. The AD5204 presets to a midscale by
asserting the PR pin, simplifying fault condition recovery at
power up. Both parts have an internal power ON preset that
places the wiper in a preset midscale condition at power ON. In
addition, the AD5204 contains a power shutdown SHDN pin
which places the RDAC in a zero power consumption state
where Terminals Ax are open circuited and the wiper Wx is
connected to Bx resulting in only leakage currents being con-
sumed in the VR structure. In shutdown mode the VR latch
settings are maintained, so that, returning to operational mode
from power shutdown, the VR settings return to their previous
resistance values.
Table II.
D
(DEC)
RWB-⍀
Output State
255
128
1
10006
5045
84
Full Scale
Midscale (PR = 0 Condition)
1 LSB
0
45
Zero Scale (Wiper Contact Resistance)
Note that in the zero-scale condition a finite wiper resistance of
45 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum value of 20 mA to
avoid degradation or possible destruction of the internal switch
contact.
Ax
R
S
Like the mechanical potentiometer the RDAC replaces, it is
totally symmetrical. The resistance between the Wiper W and
SHDN
R
Terminal A produces a digitally controlled resistance RWA
.
S
D7
D6
D5
D4
D3
D2
D1
D0
When these terminals are used the B terminal should be tied to
the wiper. Setting the resistance value for RWA starts at a maxi-
mum value of resistance and decreases as the data loaded in the
latch is increased in value. The general transfer equation for this
operation is:
R
S
Wx
RDAC
LATCH
&
R
WA (Dx) = (256–Dx)/256 × RBA + RW
(2)
where Dx is the data contained in the 8-bit RDACx latch, and
RBA is the nominal end-to-end resistance. For example, when
VA = 0 V and B terminal is tied to the Wiper W the following
output resistance values will be set for the following RDAC
latch codes:
DECODER
R
S
Bx
Table III.
Figure 16. AD5204/AD5206 Equivalent RDAC Circuit
D
(DEC)
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
RWA-⍀
Output State
The nominal resistance of the RDAC between Terminals A and
B are available with values of 10 kΩ, 50 kΩ and 100 kΩ. The
last digits of the part number determine the nominal resistance
value, e.g., 10 kΩ = 10; 100 kΩ = 100. The nominal resistance
(RAB) of the VR has 256 contact points accessed by the wiper
terminal, plus the B terminal contact. The eight-bit data word
in the RDAC latch is decoded to select one of the 256 possible
settings. The wiper’s first connection starts at the B terminal for
255
128
1
84
Full Scale
Midscale (PR = 0 Condition)
1 LSB
5045
10006
10045
0
Zero Scale
–8–
REV. 0
AD5204/AD5206
The typical distribution of RBA from channel-to-channel matches
within ±1%. However, device-to-device matching is process lot
dependent, having a ±30% variation. The change in RBA with
temperature has a 700 ppm/°C temperature coefficient.
transfer data to the next package’s SDI pin. The pull-up resistor
termination voltage may be larger than the VDD supply of the
AD5204 SDO output device, e.g., the AD5204 could operate at
VDD = 3.3 V and the pull-up for interface to the next device
could be set at +5 V. This allows for daisy chaining several
RDACs from a single processor serial-data line. Clock period
needs to be increased when using a pull-up resistor to the SDI
pin of the following device in the series. Capacitive loading at
the daisy chain node SDO-SDI between devices must be ac-
counted for to successfully transfer data. When daisy chaining is
used, the CS should be kept low until all the bits of every pack-
age are clocked into their respective serial registers insuring that
the address bits and data bits are in the proper decoding loca-
tion. This would require 22 bits of address and data complying
to the word format provided in Table I if two AD5204 four-
channel RDACs are daisy chained. During shutdown (SHDN)
the SDO output pin is forced to the off (logic high state) to
disable power dissipation in the pull-up resistor. See Figure 19
for equivalent SDO output circuit schematic.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates an output voltage
proportional to the input voltage applied to a given terminal.
For example, connecting A terminal to +5 V and B terminal to
ground produces an output voltage at the wiper which can be
any value starting at zero volts up to 1 LSB less than +5 V. Each
LSB of voltage is equal to the voltage applied across Terminal
AB divided by the 256-position resolution of the potentiometer
divider. The general equation defining the output voltage with
respect to ground for any given input voltage applied to termi-
nals AB is:
V
W (Dx) = Dx/256 × VAB + VB
(3)
Operation of the digital potentiometer in the divider mode results
in more accurate operation over temperature. Here the output
voltage is dependent on the ratio of the internal resistors not the
absolute value, therefore, the drift improves to 15 ppm/°C.
Table IV. Input Logic Control Truth Table
CLK CS PR SHDN Register Activity
L
P
L
L
H
H
H
H
No SR effect, enables SDO pin.
Shift one bit in from the SDI pin.
The eleventh previously entered bit
is shifted out of the SDO pin.
Load SR data into RDAC latch based
on A2, A1, A0 decode (Table V).
No Operation.
Sets all RDAC latches to midscale,
wiper centered and SDO latch
cleared.
Latches all RDAC latches to 80H.
Open circuits all Resistor A termi-
nals, connects W to B, turns off
SDO output transistor.
AD5204/AD5206
V
CS
DD
A1
W1
B1
CLK
D7
EN
RDAC
LATCH
#1
X
P
H
H
ADDR
DEC
A2
A1
A0
DO
SDO
(AD5204
ONLY)
X
X
H
X
H
L
H
H
R
D0
D7
SER
REG
A4/A6
W4/W6
B4/B6
X
X
H
H
P
H
H
L
D7
D0
RDAC
LATCH
#4/#6
DI D0
SDI
R
8
NOTE: P = positive edge, X = don’t care, SR = shift register.
SHDN
(AD5204
ONLY)
Table V. Address Decode Table
PR
(AD5204 ONLY)
GND
A2
A1
A0
Latch Decoded
Figure 17. Block Diagram
DIGITAL INTERFACING
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
RDAC#1
RDAC#2
RDAC#3
RDAC#4
RDAC#5 AD5206 Only
RDAC#6 AD5206 Only
The AD5204/AD5206 contain a standard three-wire serial input
control interface. The three inputs are clock (CLK), CS and
serial data input (SDI). The positive-edge sensitive CLK input
requires clean transitions to avoid clocking incorrect data into
the serial input register. Standard logic families work well. If
mechanical switches are used for product evaluation they should
be debounced by a flip-flop or other suitable means. Figure 17
shows more detail of the internal digital circuitry. When CS is
taken active low the clock loads data into the serial register on
each positive clock edge, see Table IV. When using a positive
(VDD) and negative (VSS) supply voltage, the logic levels are still
referenced to digital ground (GND).
The data setup and data hold times in the specification table
determine the data valid time requirements. The last 11 bits of
the data word entered into the serial register are held when CS
returns high. At the same time CS goes high it gates the address
decoder enabling one of four or six positive edge triggered RDAC
latches, see Figure 18 detail.
The serial-data-output (SDO) pin contains an open drain n-
channel FET. This output requires a pull-up resistor in order to
–9–
REV. 0
AD5204/AD5206
I
AD5204/AD5206
MS
RDAC 1
RDAC 2
I
= 1V/R
NOMINAL
CS
DUT
A
W
V+ Ϸ V
DD
W
ADDR
DECODE
V
–[V
+ I (R II R )]
W2
W1 W AW BW
V
W
R
= ––––––––––––––––––––––––––
W
V+
I
RDAC 4/6
W
B
WHERE V
= V
WHEN I = 0
MS W
W1
CLK
SDI
AND V
= V
WHEN I = 1/R
V
W2
MS
W
MS
SERIAL
REGISTER
Figure 18. Equivalent Input Control Logic
Figure 24. Wiper Resistance Test Circuit
The target RDAC latch is loaded with the last eight bits of the
serial data word completing one DAC update. Four separate 8-
bit data words must be clocked in to change all four VR settings.
V
A
V+ = V ± 10%
DD
⌬V
MS
A
B
V
PSRR (dB) = 20 LOG ( ––––– )
DD
W
⌬V
DD
V+
~
⌬V
%
SHDN
MS
PSS (%/%) = –––––––
⌬V
V
MS
%
DD
CS
SDO
GND
SERIAL
REGISTER
Q
D
SDI
Figure 25. Power Supply Sensitivity Test Circuit (PSS,
PSRR)
CK
RS
CLK
PR
A
DUT
B
Figure 19. Detail SDO Output Schematic of the AD5204
+5V
W
V
IN
All digital pins are protected with a series input resistor and
parallel Zener ESD structure shown in Figure 20. Applies to
digital pins CS, SDI, SDO, PR, SHDN, CLK
V
OP279
OUT
OFFSET
GND
+
OFFSET BIAS
340k⍀
LOGIC
Figure 26. Inverting Programmable Gain Test Circuit
V
SS
+5V
Figure 20. ESD Protection of Digital Pins
OP279
V
OUT
V
IN
W
A, B, W
OFFSET
GND
DUT
OFFSET BIAS
A
B
V
SS
Figure 21. ESD Protection of Resistor Terminals
Figure 27. Noninverting Programmable Gain Test Circuit
V+ = V
DUT
DD
1LSB = V+/256
+15V
A
A
W
W
V+
V
IN
+
DUT
B
V
V
OP42
MS
OUT
B
OFFSET
GND
2.5V
–15V
Figure 22. Potentiometer Divider Nonlinearity Error Test
Circuit (INL, DNL)
Figure 28. Gain vs. Frequency Test Circuit
NO CONNECT
DUT
0.1V
R
=
SW
I
DUT
I
SW
W
A
CODE = ØØ
H
W
W
+
B
B
0.1V
I
SW
V
MS
V
TO V
DD
SS
Figure 23. Resistor Position Nonlinearity Error (Rheostat
Operation; R-INL, R-DNL)
Figure 29. Incremental ON Resistance Test Circuit
–10–
REV. 0
AD5204/AD5206
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Lead Narrow Body PDIP
(N-24)
1.275 (32.30)
1.125 (28.60)
24
13
0.280 (7.11)
0.240 (6.10)
1
12
0.325 (8.25)
0.300 (7.62)
PIN 1
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.195 (4.95)
0.115 (2.93)
0.150
(3.81)
MIN
0.200 (5.05)
0.125 (3.18)
0.015 (0.381)
0.008 (0.204)
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
SEATING
PLANE
0.070 (1.77)
0.045 (1.15)
24-Lead SOIC
(R-24/SOL-24)
0.6141 (15.60)
0.5985 (15.20)
24
13
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.3937 (10.00)
1
12
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
؋
45؇ 8؇
0؇
SEATING
PLANE
0.0500 0.0192 (0.49)
0.0118 (0.30)
0.0040 (0.10)
0.0500 (1.27)
0.0157 (0.40)
0.0125 (0.32)
0.0091 (0.23)
(1.27)
0.0138 (0.35)
BSC
24-Lead Thin Shrink SO Package (TSSOP)
(RU-24)
0.311 (7.90)
0.303 (7.70)
24
13
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
12
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0433 (1.10)
MAX
8؇
0؇
0.0256 (0.65) 0.0118 (0.30)
0.028 (0.70)
0.020 (0.50)
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
BSC
0.0075 (0.19)
–11–
REV. 0
相关型号：
AD5204BRU10-REEL
IC QUAD 10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO24, MO-153AD, TSSOP-24, Digital Potentiometer
ADI
AD5204BRU100-REEL
IC QUAD 100K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO24, MO-153AD, TSSOP-24, Digital Potentiometer
ADI
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