AD5260BRU50 [ADI]
1-/2-Channel 15 V Digital Potentiometers; 1 / 2通道15 V数字电位器
| 型号： | AD5260BRU50 |
| 厂家： | 
ADI |
| 描述： | 1-/2-Channel 15 V Digital Potentiometers |
| 文件： | 总20页 (文件大小：841K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1-/2-Channel
15 V Digital Potentiometers
a
AD5260/AD5262
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
256 Positions
A
W
B
AD5260 – 1-Channel
AD5262 – 2-Channel (Independently Programmable)
Potentiometer Replacement
SHDN
AD5260
20 k⍀, 50 k⍀, 200 k⍀
V
DD
RDAC
Low Temperature Coefficient 35 ppm/؇C
4-Wire SPI-Compatible Serial Data Input
5 V to 15 V Single-Supply; ؎5.5 V Dual-Supply Operation
Power ON Mid-Scale Preset
REGISTER
V
SS
V
L
POWER-ON
RESET
PR
CS
LOGIC
8
APPLICATIONS
CLK
SDI
GND
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Stereo Channel Audio Level Control
Programmable Voltage to Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
SDO
SERIAL INPUT REGISTER
A1 W1 B1
A2 W2 B2
Low Resolution DAC Replacement
SHDN
GENERAL DESCRIPTION
V
DD
The AD5260/AD5262 provide a single- or dual-channel, 256-
position, digitally controlled variable resistor (VR) device.* These
devices perform the same electronic adjustment function as a
potentiometer or variable resistor. Each channel of the AD5260/
AD5262 contains a fixed resistor with a wiper contact that taps the
fixed resistor value at a point determined by a digital code loaded
into the SPI-compatible serial-input register. The resistance between
the wiper and either end point of the fixed resistor varies linearly
with respect to the digital code transferred into the VR latch. The
variable resistor offers a completely programmable value of resistance,
between the A terminal and the wiper or the B terminal and the wiper.
The fixed A to B terminal resistance of 20 kW, 50 kW, or 200 kW has
a nominal temperature coefficient of 35 ppm/∞C. Unlike the majority
of the digital potentiometers in the market, these devices can operate
up to 15 V or ±5 V provided proper supply voltages are furnished.
RDAC1 REGISTER
RDAC2 REGISTER
V
SS
V
L
POWER-ON
RESET
PR
CS
LOGIC
8
CLK
SDI
SDO
SERIAL INPUT REGISTER
GND
AD5262
100
R
R
WB
WA
75
50
25
0
Each VR has its own VR latch, which holds its programmed resistance
value. These VR latches are updated from an internal serial-to-parallel
shift register, which is loaded from a standard 3-wire serial-input
digital interface. The AD5260 contains an 8-bit serial register
while the AD5262 contains a 9-bit serial register. Each bit is clocked
into the register on the positive edge of the CLK. The AD5262
address bit determines the corresponding VR latch to be loaded
with the last 8 bits of the data word during the positive edging of
CS strobe. A serial data output pin at the opposite end of the serial
register enables simple daisy chaining in multiple VR applications
without additional external decoding logic. An optional reset pin
(PR) forces the wiper to the mid-scale position by loading 80H into
the VR latch.
0
64
128
192
256
CODE – Decimal
Figure 1. RWA and RWB vs. Code
The AD5260/AD5262 are available in thin surface-mount TSSOP-14
and TSSOP-16 packages. All parts are guaranteed to operate over
the extended industrial temperature range of –40∞C to +85∞C.
*The terms digital potentiometers, VR, and RDAC are used interchangeably.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
(VDD = +15 V, VSS = 0 V or, VDD = +5 V, VSS = –5 V, VL = +5 V, VA = +5 V,
AD5260/AD5262–SPECIFICATIONS V = 0 V, – 40؇C < T < +85؇C unless otherwise noted.)
B
A
ELECTRICAL CHARACTERISTICS 20 kW, 50 kW, 200 kW VERSIONS
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS RHEOSTAT MODE Specifications apply to all VRs
Resistor Differential NL2
Resistor Nonlinearity2
R-DNL
R-INL
ꢀRAB
ꢀRAB/ꢀT
RW
RWB, VA = NC
RWB, VA = NC
TA = 25∞C
Wiper = No Connect
IW = 1 V/RAB
–1
–1
–30
±1/4
±1/2
+1
+1
30
LSB
LSB
%
ppm/∞C
W
%
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
Wiper Resistance
35
60
0.1
0.05
150
Channel Resistance Matching (AD5262 only) ꢀRWB/RWB
Resistance Drift ꢀRAB
Ch 1 and 2 RWB, DX = 80H
%
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply to all VRs
Resolution
N
DNL
INL
8
–1
–1
Bits
LSB
LSB
ppm/∞C
LSB
LSB
Differential Nonlinearity4
Integral Nonlinearity4
±1/4
±1/2
5
–1
1
+1
+1
Voltage Divider Temperature Coefficient DVW/DT
Code = 80H
Code = FFH
Code = 00H
Full-Scale Error
Zero-Scale Error
VWFSE
VWZSE
–2
0
+0
2
RESISTOR TERMINALS
Voltage Range5
VA, B, W
CA,B
VSS
VDD
V
pF
Capacitance6 Ax, Bx
f = 5 MHz,
measured to GND, Code = 80H
f = 1 MHz,
measured to GND, Code = 80H
VA =VB = VDD /2
25
55
1
Capacitance6 Wx
CW
pF
Common-Mode Leakage Current
Shut Down Current7
ICM
ISHDN
nA
mA
5
DIGITAL INPUTS and OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
VIH
VIL
VIH
VIL
VOH
VOL
IIL
2.4
2.1
4.9
V
V
V
V
V
V
mA
pF
0.8
0.6
VL = 3 V, VSS = 0 V
VL = 3 V, VSS = 0 V
RPULL-UP = 2 kW to 5 V
IOL = 1.6 mA, VLOGIC = 5 V
VIN = 0 V or 5 V
Output Logic High (SDO)
Output Logic Low (SDO)
Input Current8
0.4
±1
Input Capacitance6
CIL
5
POWER SUPPLIES
Logic Supply
VL
VDD RANGE
VDD/SS RANGE
IL
IDD
ISS
PDISS
2.7
4.5
±4.5
5.5
16.5
±5.5
60
1
1
V
V
V
mA
mA
mA
mW
Power Single-Supply Range
Power Dual-Supply Range
Logic Supply Current
Positive Supply Current
Negative Supply Current
Power Dissipation9
VSS = 0 V
VL = 5 V
VIH = 5 V or VIL = 0 V
VSS = –5 V
VIH = 5 V or VIL = 0 V,
VDD = +5 V, VSS = –5 V
DVDD = +5 V, ±10%
0.3
Power Supply Sensitivity
PSS
0.003
0.01
%/%
DYNAMIC CHARACTERISTICS6, 10
Bandwidth –3 dB
Total Harmonic Distortion
BW
THDW
RAB = 20 kW/50 kW/200 kW
VA = 1 VRMS, VB = 0 V,
f = 1 kHz, RAB = 20 kW
VA = +5 V, VB = –5 V,
±1 LSB error band, RAB = 20 kW
VA = VDD, VB = 0 V,
310/130/30
0.014
kHz
%
V
W Settling Time
tS
5
ms
Crosstalk11
CT
Measure VW with Adjacent
RDAC Making Full-Scale
Code Change (AD5262 only)
VA1 = VDD, VB1 = 0V,
Measure VW1 with
VW2 = 5 V p-p @ f = 10 kHz,
1
nV–s
Analog Crosstalk
Resistor Noise Voltage
CTA
–64
13
dB
R
AB = 20 kW/200 kW (AD5262 only)
eN_WB
RWB = 20 kW
f = 1 kHz
nV/÷Hz
–2–
REV. 0
AD5260/AD5262
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INTERFACE TIMING CHARACTERISTICS apply to all parts6, 12
Clock Frequency
Input Clock Pulsewidth
Data Setup Time
fCLK
CH, tCL
tDS
25
MHz
ns
ns
ns
ns
ns
ns
ns
ns
t
Clock level high or low
20
10
10
1
Data Hold Time
tDH
tPD
tCSS
tCSW
tRS
CLK to SDO Propagation Delay13
CS Setup Time
RL = 1 kΩ, CL < 20pF
160
5
CS High Pulsewidth
Reset Pulsewidth
20
50
0
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
tCSH
tCS1
10
ns
NOTES
The AD5260/AD5262 contains 1,968 transistors. Die Size: 89 mil. × 105 mil. 9,345 sq. mil.
1Typicals represent average readings at 25°C and VDD = +5 V, VSS = –5 V.
2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. IW = VDD/R for both VDD = +5 V, VSS = –5 V.
3VAB = VDD, Wiper (VW) = No connect.
4INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0V. DNL
specification limits of 1 LSB maximum are Guaranteed Monotonic operating conditions.
5Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6Guaranteed by design and not subject to production test.
7Measured at the Ax terminals. All Ax terminals are open-circuit in shutdown mode.
8Worst-case supply current consumed when input all logic-input levels set at 2.4 V, standard characteristic of CMOS logic.
9PDISS is calculated from (IDD ϫ VDD). CMOS logic level inputs result in minimum power dissipation.
10 All dynamic characteristics use VDD = +5 V, VSS = –5 V, VL = +5 V.
11 Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.
12 See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
Switching characteristics are measured using VL = 5 V.
13 Propagation delay depends on value of VDD, RL, and CL.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Thermal Resistance3 θ JA
(TA = 25°C, unless otherwise noted.)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +15 V
V
SS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, –7 V
TSSOP-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C/W
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD
AX – BX, AX – WX, BX – WX
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Intermittent2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
Digital Inputs and Output Voltage to GND . . . . . . . 0 V, 7 V
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (TJ MAX) . . . . . . . . . . . 150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
2Maximum terminal current is bounded by the maximum current handling of the
switches, maximum power dissipation of the package, and maximum applied
voltage across any two of the A, B, and W terminals at a given resistance setting.
3Package Power Dissipation = (TJ MAX – TA)/θ JA
–3–
REV. 0
AD5260/AD5262
ORDERING GUIDE
Package
Package
Option
No. of Parts
per Container
Branding
Information*
Model
RAB (kW)
Temperature
Description
AD5260BRU20
AD5260BRU20-REEL7
AD5260BRU50
AD5260BRU50-REEL7
AD5260BRU200
AD5260BRU200-REEL7
AD5262BRU20
AD5262BRU20-REEL7
AD5262BRU50
AD5262BRU50-REEL7
AD5262BRU200
20
20
50
50
200
200
20
20
50
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
TSSOP-14
TSSOP-14
TSSOP-14
TSSOP-14
TSSOP-14
TSSOP-14
TSSOP-16
TSSOP-16
TSSOP-16
TSSOP-16
TSSOP-16
TSSOP-16
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
96
1000
96
1000
96
1000
96
1000
96
1000
96
AD5260B20
AD5260B20
AD5260B50
AD5260B50
AD5260B200
AD5260B200
AD5262B20
AD5262B20
AD5262B50
AD5262B50
AD5262B200
AD5262B200
50
200
200
AD5262BRU200-REEL7
1000
*
Line 1 contains part number, line 2 contains differentiating detail by part type and ADI logo symbol, line 3 contains date code YWW.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5260/AD5262 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. 0
AD5260/AD5262
TableI. AD52608-BitSerial-DataWordFormat
DATA
Table II. AD5262 9-Bit Serial-Data Word Format
ADDR
DATA
B7 B6 B5 B4 B3 B2 B1 B0
D7 D6 D5 D4 D3 D2 D1 D0
B8
B7
B6 B5 B4 B3
B2 B1 B0
A0
D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
MSB
LSB
27
20
28
27
20
1
1
SDI
SDI
Ax OR Dx
Dx
D7 D6 D5 D4 D3 D2 D1 D0
RDAC REGISTER LOAD
(DATA IN)
0
1
0
tDH
tDS
CLK
1
0
SDO
0
1
A
x OR D
x
D
x (DATA OUT)
CS
tPD_MAX
tCS1
0
1
tCH
1
0
V
OUT
CLK
0
tCSH
tCL
Figure 2a. AD5260 Timing Diagram
tCSS
1
0
tCSW
tS
CS
V
؎1 LSB
DD
1
V
OUT
SDI
A0 D7 D6 D5 D4 D3 D2 D1 D0
؎1 LSB ERROR BAND
0V
0
1
CLK
0
1
Figure 2c. Detail Timing Diagram
RDAC REGISTER LOAD
CS
0
1
1
0
V
tRS
OUT
PR
0
tS
V
DD
0V
Figure 2b. AD5262 Timing Diagram
V
OUT
؎1 LSB
؎1 LSB ERROR BAND
Figure 2d. Preset Timing Diagram
REV. 0
–5–
AD5260/AD5262
AD5260 PIN CONFIGURATION
AD5262 PIN CONFIGURATION
14 SDO
1
2
3
4
5
6
7
16
15
A
W
B
1
2
3
4
5
6
7
8
SDO
A1
A2
NC
13
12
W2
V
L
W1
B1
14 B2
V
V
AD5260 11
AD5262
13
12
V
V
DD
SHDN
CLK
SS
L
TOP VIEW
10
TOP VIEW
V
GND
PR
DD
SS
(Not to Scale)
9
(Not to Scale)
11 GND
SHDN
CLK
SDI
SDI
8
10
CS
PR
9
CS
AD5260 PIN FUNCTION DESCRIPTIONS
AD5262 PIN FUNCTION DESCRIPTIONS
Pin
Number
Pin
Number
Mnemonic
Description
Mnemonic
Description
1
2
3
4
A
W
B
A Terminal
Wiper Terminal
B Terminal
Positive power supply, specified
for operation at both 5 V or 15 V.
(Sum of |VDD| + |VSS| £ 15 V)
Active low input. Terminal A
open-circuit. Shutdown controls.
Variable Resistors of RDAC.
Serial Clock Input, positive edge
triggered.
Serial Data Input
Chip Select Input, Active Low.
When CS returns high, data will
be loaded into the RDAC register.
Active low preset to mid-scale; sets
RDAC registers to 80H.
1
SDO
Serial Data Output, Open Drain
transistor requires pull-up resistor.
A Terminal RDAC #1
Wiper RDAC #1, address A0 = 02
B Terminal RDAC #1
Positive power supply, specified for
operation at both 5 V or 15 V.
(Sum of |VDD|+|VSS|£ 15 V)
Active low input. Terminal A
open-circuit. Shutdown controls
Variable Resistors #1 through #2.
Serial Clock Input, positive edge
triggered.
2
3
4
5
A1
W1
B1
VDD
VDD
5
6
SHDN
6
7
SHDN
CLK
7
8
SDI
CS
CLK
8
9
SDI
CS
Serial Data Input.
Chip Select Input, Active Low.
When CS returns high, data in
the serial input register is decoded,
based on the address Bit A0, and
loaded into the target RDAC register.
Active low preset to mid-scale sets
RDAC registers to 80H.
9
PR
10
11
GND
VSS
Ground
Negative Power Supply, specified
for operation from 0 V to –5 V.
Logic Supply Voltage, needs to be
same voltage as the digital logic
controlling the AD5260.
No Connect (Users should not
connect anything other than dummy
pad on this pin)
Serial Data Output, Open Drain
transistor requires pull-up resistor.
10
PR
12
13
14
VL
11
12
GND
VSS
Ground
Negative Power Supply, specified
for operation at both 0 V or –5 V
(Sum of |VDD| + |VSS| <15 V).
Logic Supply Voltage, needs to be
same voltage as the digital logic
controlling the AD5262.
NC
SDO
13
VL
14
15
16
B2
W2
A2
B Terminal RDAC #2
Wiper RDAC #2, address A0 = 12
A Terminal RDAC #2
–6–
REV. 0
AD5260/AD5262
THEORY OF OPERATION
The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register.
Standard logic families work well. If mechanical switches are used
for product evaluation, they should be debounced by a flip-flop or
other suitable means. Figure 3 shows more detail of the internal
digital circuitry. When CS is low, the clock loads data into the
serial register on each positive clock edge (see Table IV).
The AD5260/AD5262 provide a single- or dual-channel, 256-position
digitally controlled variable resistor (VR) device and operate up to
15 V maximum voltage. Changing the programmed VR settings
is accomplished by clocking an 8-/9-bit serial data word into the
SDI (Serial Data Input) pin. For the AD5262, the format of this
data word is one address bit. A0 represents the first bit B8, then
followed by eight data bits B7–B0 with MSB first. Tables I and II
provide the serial register data word format. See Table III for the
AD5262 address assignment to decode the location of the VR latch
receiving the serial register data in bits B7 through B0. VR outputs
can be changed one at a time in random sequence. The AD5260/
AD5262 presets to a mid-scale, simplifying fault condition recov-
ery at power-up. Mid-scale can also be achieved at any time by
asserting the PR pin. Both parts have an internal power ON preset
that places the wiper in a mid-scale preset condition at power ON.
Operation of the power ON preset function depends only on the
state of the VL pin.
Table IV. Truth Table
CLK CS PR SHDN Register Activity
L
≠*
L
L
H
H
H
H
No SR effect, enables SDO pin
Shift one bit in from the SDI pin.
The eighth previously entered bit is
shifted out of the SDO pin.
Load SR data into RDAC latch
No Operation
Sets all RDAC latches to Mid-Scale,
wiper centered, and SDO latch
cleared.
X
X
X
≠
H
X
H
H
L
H
H
H
The AD5260/AD5262 contains a power shutdown SHDN pin,
which places the RDAC in an almost zero power consumption
state where terminals Ax are open circuited, and the wiper W is con-
nected to B, resulting in only leakage currents being consumed in
the VR structure. In the shutdown mode, the VR latch settings are
maintained so that, returning to operational mode from power
shutdown, the VR settings return to their previous resistance values.
X
X
H
H
≠
H
H
L
Latches all RDAC latches to 80H.
Open circuits all resistor A–terminals,
connects W to B, turns off SDO
output transistor.
*≠ = positive edge, X = don’t care, SR = shift register
The data setup and data hold times in the specification table
determine the data valid time requirements. The AD5260 uses
an 8-bit serial input data register word that is transferred to the
internal RDAC register when the CS line returns to logic high.
For the AD5262 the last 9 bits of the data word entered into the
serial register are held when CS returns high. Any extra bits are
ignored. At the same time CS goes high, it gates the address
decoder enabling AD5262 one of two positive edge-triggered
AD5262 RDAC latches (see Figure 4).
Table III. AD5262 Address Decode Table
A0
Latch Loaded
0
1
RDAC#1
RDAC#2
DIGITAL INTERFACING
The AD5260/AD5262 contains a 4-wire SPI-compatible
digital interface (SDI, SDO, CS, and CLK). For the AD5260,
the 8-bit serial word must be loaded with MSB first, and the
format of the word is shown in Table I. For the AD5262, the
9-bit serial word must be loaded with address bit A0 first, then
MSB of the data. The format of the word is shown in Table II.
AD5260/AD5262
CS
RDAC 1
RDAC 2
ADDR
DECODE
CLK
SDI
SERIAL
REGISTER
V
V
DD
L
Figure 4. Equivalent Input Control Logic
CS
A1
W1
B1
The target RDAC latch is loaded with the last 8 bits of the serial data
word completing one RDAC update. For the AD5262, two separate
9-bit data words must be clocked in to change both VR settings.
RDAC
LATCH
#1
CLK
PR
EN
During shutdown (SHDN) the SDO output pin is forced to the
off (logic high state) to disable power dissipation in the pull-up
resistor. See Figure 5 for equivalent SDO output circuit schematic.
SDI
ADDR
DEC
A0
SER
REG
D7
D6
D5
D4
D3
D2
D1
D0
SHDN
A2
W2
B2
RDAC
LATCH
#2
SDO
CS
PR
D
Q
SERIAL
SDO
SDI
CLK
PR
REGISTER
CK RS
POWER-
ON
SHDN
PR
PRESET
V
GND
SS
Figure 5. Detail SDO Output Schematic of the AD5260
Figure 3. AD5262 Block Diagram
REV. 0
–7–
AD5260/AD5262
All digital inputs are protected with a series input resistor and
parallel Zener ESD structure as shown in Figure 6. This applies
to digital input pins CS, SDI, SDO, PR, SHDN, and CLK.
of this data sheet. An internal level shift circuit ensures that the
common-mode voltage range of the three terminals extends
from VSS to VDD regardless of the digital input level.
340⍀
POWER-UP SEQUENCE
LOGIC
Since there are diodes to limit the voltage compliance at termi-
nals A, B, and W (see Figure 9), it is important to power VDD/VSS
first before applying any voltage to terminals A, B, and W. Other-
wise, the diode will be forward biased such that VDD/VSS will be
powered unintentionally and may affect the rest of the user’s circuit.
The ideal power-up sequence is in the following order: GND,
VDD, VSS, VL, Digital Inputs, and VA/B/W. The order of powering
VA, VB, VW, and Digital Inputs is not important as long as they
are powered after VDD/VSS.
Figure 6. ESD Protection of Digital Pins
A, B, W
V
SS
Daisy-Chain Operation
Figure 7. ESD Protection of Resistor Terminals
The serial-data output (SDO) pin contains an open drain
n-channel FET. This output requires a pull-up resistor to trans-
fer data to the next package’s SDI pin. This allows for daisy
chaining several RDACs from a single processor serial data line.
The pull-up resistor termination voltage can be larger than the VDD
supply voltage. It is recommended to increase the Clock period
when using a pull-up resistor to the SDI pin of the following device
in series because capacitive loading at the daisy-chain node
SDO-SDI between devices may induce time delay to subsequent
devices. Users should be aware of this potential problem to achieve
data transfer successfully (see Figure 10). If two AD5260s are daisy-
chained, this requires a total of 16 bits of data. The first 8 bits,
complying with the format shown in Table I, go to U2, and the
second 8 bits with the same format go to U1. The CS should be
kept low until all 16 bits are clocked into their respective serial
registers, and the CS is then pulled high to complete the operation.
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum-lead length
layout design. The leads to the input should be as direct as pos-
sible with a minimum conductor length. Ground paths should
have low resistance and low inductance.
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to the
device should be bypassed with 0.01 mF–0.1 mF disc or chip ceram-
ics capacitors. Low-ESR 1 mF to 10 mF tantalum or electrolytic
capacitors should also be applied at the supplies to minimize any
transient disturbance (see Figure 8). Notice the digital ground
should also be joined remotely to the analog ground to minimize
the ground bounce.
V
DD
V
DD
؉
V
DD
C1
C3
C4
10F
0.1F
0.1F
؉
C2
AD5260
AD5260
U2
SDI SDO
R
P
10F
V
V
SS
GND
U1
SS
2.2k⍀
C MOSI
SDI SDO
SCLK SS
CLK
CLK
CS
CS
Figure 8. Power Supply Bypassing
TERMINAL VOLTAGE OPERATING RANGE
Figure 10. Daisy-Chain Configuration
RDAC STRUCTURE
The AD5260/AD5262 positive VDD and negative VSS power
supply defines the boundary conditions for proper 3-terminal
digital potentiometer operation. Supply signals present on termi-
nals A, B, and W that exceed VDD or VSS will be clamped by the
internal forward biased diodes (see Figure 9).
The RDAC contains a string of equal resistor segments, with an
array of analog switches, that act as the wiper connection. The
number of positions is the resolution of the device. The AD5260/
AD5262 have 256 connection points allowing it to provide better
than 0.4% set-ability resolution. Figure 11 shows an equivalent
structure of the connections between the three terminals that
make up one channel of the RDAC. The SWA and SWB will
always be ON, while one of the switches SW(0) to SW(2N – 1)
will be ON one at a time depending on the resistance position
decoded from the data bits. Since the switch is not ideal, there is
a 60 W wiper resistance, RW. Wiper resistance is a function of
supply voltage and temperature. The lower the supply voltage, the
higher the wiper resistance. Similarly, the higher the temperature,
the higher the wiper resistance. Users should be aware of the
contribution of the wiper resistance when accurate prediction of
the output resistance is needed.
V
DD
A
W
B
V
SS
Figure 9. Maximum Terminal Voltages Set by VDD and VSS
The ground pin of the AD5260/AD5262 device is primarily used
as a digital ground reference, which needs to be tied to the PCB’s
common ground. The digital input control signals to the AD5260/
AD5262 must be referenced to the device ground pin (GND),
and must satisfy the logic level defined in the specification table
–8–
REV. 0
AD5260/AD5262
Note that in the zero-scale condition a finite wiper resistance of
60 W is present. Care should be taken to limit the current flow
between W and B in this state to no more than 20 mA to avoid
degradation or possible destruction of the internal switches.
Ax
SHDN
R
R
S
S
D7
Like the mechanical potentiometer the RDAC replaces, the
AD5260/AD5262 parts are totally symmetrical. The resistance
between the wiper W and terminal A also produces a digitally
controlled complementary resistance RWA. Figure 12 shows the
symmetrical programmability of the various terminal connections.
When RWA is used, the B–terminal can be let floating or tied to the
wiper. Setting the resistance value for RWA starts at a maximum
value of resistance and decreases as the data loaded in the latch
is increased in value. The general equation for this operation is:
D6
D5
D4
D3
D2
D1
D0
R
S
Wx
Bx
RDAC
LATCH
AND
256 - D
256
DECODE
RWA D =
¥ R AB + RW
(2)
(
)
R
S
N
DIGITAL CIRCUITRY
R
= R /2
AB
S
For example, RAB = 20 kW, when VA = 0 V and B–terminal is open,
the following output resistance RWA will be set for the following
RDAC latch codes. The result will be the same if terminal B is
tied to W:
OMITTED FOR CLARITY
Figure 11. Simplified RDAC Architecture
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
D
RWA
The nominal resistances of the RDAC between terminals A and B
are available with values of 20 kW, 50 kW, and 200 kW. The final
three digits of the part number determine the nominal resistance
value, e.g., 20 kW = 20; 50 kW = 50; 200 kW = 200. The nominal
resistance (RAB) of the VR has 256 contact points accessed by the
wiper terminal, plus the B terminal contact. The 8-bit data in the
RDAC latch is decoded to select one of the 256 possible settings.
Assuming a 20 kW part is used, the wiper’s first connection starts
at the B terminal for data 00H. Since there is a 60 W wiper contact
resistance, such connection yields a minimum of 60 W resistance
between terminals W and B. The second connection is the first tap
point corresponds to 138 W (RWB = RAB/256 ꢁ RW = 78 W ꢁ 60 W)
for data 01H. The third connection is the next tap point represent-
ing 216 W (78 ꢂ 2 ꢁ 60) for data 02H and so on. Each LSB data
value increase moves the wiper up the resistor ladder until the last
tap point is reached at 19982 W [RAB ꢃ 1 LSB ꢁ RW]. The wiper
does not directly connect to the B terminal. See Figure 11 for a
simplified diagram of the equivalent RDAC circuit.
(DEC)
(W)
Output State
256
128
1
60
Full-Scale
Mid-Scale
1 LSB
10060
19982
20060
0
Zero-Scale
20
16
12
8
R
R
WB
WA
The general equation determining the digitally programmed
output resistance between W and B is:
4
R
= 20K⍀
AB
D
0
RWB D =
¥ R AB + RW
(1)
(
)
0
64
128
D – CODE in decimal
192
256
256
where D is the decimal equivalent of the binary code which is
loaded in the 8-bit RDAC register, and RAB is the nominal end-
to-end resistance.
Figure 12. AD5260/AD5262 Equivalent RDAC Circuit
The typical distribution of the nominal resistance RAB from
channel to channel matches within ±1%. Device-to-device match-
ing is process lot dependent with the worst case of ±30% variation.
On the other hand, since the resistance element is processed in
thin film technology, the change in RAB with temperature has a
low 35 ppm/∞C temperature coefficient.
For example, RAB = 20 kW, when VB = 0 V and A–terminal is
open circuit, the following output resistance values RWB will be
set for the following RDAC latch codes. The result will be the
same if terminal A is tied to W:
D
RWB
(DEC) (W)
Output State
256
128
1
19982
10060
138
Full-Scale (RAB – 1 LSB + RW)
Mid-Scale
1 LSB
0
60
Zero-Scale (wiper contact resistance)
REV. 0
–9–
—Typical Performance Characteristics
AD5260/AD5262
0.8
0.7
0.6
0.5
0.4
0.3
0.10
1.0
0.8
؉5V
V
SS
R
= ؉5V
= ؊5V
= 20k⍀
T
= ؉125؇C
A
DD
؉12V
؎5V
V
؉15V
0.05
0
؉5V
AB
0.6
0.4
T
= ؉85؇C
A
0.2
–0.05
–0.10
–0.15
–0.20
–0.25
0
؉12V
0.2
–0.2
–0.4
–0.6
–0.8
–1.0
؎5V
T
= ؊40؇C
A
0.1
0
T
= ؉25؇C
A
–0.1
–0.2
؉15V
0
32
64
96 128 160 192 224 256
CODE – Decimal
0
32
64
96 128 160 192 224 256
CODE – Decimal
0
32
64
96 128 160 192 224 256
CODE – Decimal
TPC 1. R-INL vs. Code vs.
Supply Voltages
TPC 2. R-DNL vs. Code vs.
Supply Voltages
TPC 3. INL vs. Code, VDD/VSS = ±5 V
0.5
0.4
0.3
0.5
0.4
0.3
0.2
0.2
0.1
؎5V
؉5V
0.3
T
= ؊40؇C
A
0.2
؎5V
T
= ؉25؇C
T
= ؉85؇C
A
؉15V
A
؉15V
0.1
0.1
0
0
0
–0.1
–0.2
–0.3
–0.4
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
T
= ؉125؇C
A
؉5V
–0.4
–0.5
0
32
64
96 128 160 192 224 256
CODE – Decimal
0
32
64
96 128 160 192 224 256
CODE – Decimal
0
32
64
96 128 160 192 224 256
CODE – Decimal
TPC 4. DNL vs. Code,
VDD/VSS = ±5 V
TPC 6. DNL vs. Code vs.
Supply Voltages
TPC 5. INL vs. Code vs.
Supply Voltages
1.0
0.5
2.0
124
104
84
64
44
24
4
R
@ V /V = ؉5V/0V
DD SS
ON
1.5
1.0
AVG +3
AVG +3
AVG
0.5
R
@V /V = ؉5V/؊5V
DD SS
ON
AVG –3
AVG
AVG –3
0
0
–0.5
–1.0
–1.5
–2.0
R
@ V /V = ؉15V/0V
DD SS
ON
–0.5
–1.0
0
5
10
15
20
0
5
10
15
20
؊5
؊1
3
7
11
15
V
– V – V
SS
V
– V – V
V
– V
DD
DD
SS
DD
TPC 7. INL vs. Supply Voltages
TPC 8. R-INL vs. Supply Voltages
TPC 9. Wiper ON Resistance vs.
Bias Voltage
–10–
REV. 0
AD5260/AD5262
0
–0.5
–1.0
–1.5
–2.0
–2.5
2.5
2.0
1.5
1.0
0.5
0
1
0.1
V
= ؉5V
LOGIC
V
= ؉5V
IH
V
= 0V
IL
V
/V = +5V/0V
DD SS
V
/V = +15V/0V
DD SS
V
/V = ؎5V
DD SS
V
/V = ؎5V
DD SS
V
/V = ؉15V/0V
DD SS
0.01
0.001
V
/V = +15V/0V
DD SS
V
/V = ؎5V
DD SS
V
/V = +5V/0V
DD SS
–40 –20
0
20
40
60
80
100
–40 –20
0
20
40
60
80
100
–40
–7
26
59
92
125
TEMPERATURE – ؇C
TEMPERATURE – ؇C
TEMPERATURE – ؇C
TPC 10. Full-Scale Error
TPC 11. Zero-Scale Error
TPC 12. Supply Current vs.
Temperature
28.0
27.5
27.0
26.5
26.0
25.5
25.0
24.5
1k
100
10
80
70
60
50
40
30
20
10
0
V
/V = 5V/0V V = 5V
DD SS LOGIC
V
/V = +15V/0V
DD SS
20k⍀
50k⍀
V
/V = ؎5V
DD SS
–10
–20
V
/V = 5V/0V V
= 3V
200k⍀
DD SS
LOGIC
– V
–40
–7
26
59
92
125
0
1
2
3
4
5
0
32
64
96 128 160 192 224 256
CODE – Decimal
V
TEMPERATURE – ؇C
IH
TPC 15. Rheostat Mode Tempco
DRWB/DT vs. Code
TPC 13. ILOGIC vs. Temperature
TPC 14. ILOGIC vs. Digital Input
Voltage
120
6
T
= 25؇C
CODE = FF
A
H
0
–6
100
50k⍀
80
80
40
H
H
–12
–18
–24
–30
–36
–42
–48
–54
60
20
10
08
H
H
H
20k⍀
40
20
0
04
02
H
H
–20
200k⍀
01
H
–40
–60
0
32
64
96 128 160 192 224 256
CODE – Decimal
1k
10k
100k
1M
FREQUENCY – Hz
TPC 16. Potentiometer Mode
DVWB/DT vs. Code
TPC 17. Gain vs. Frequency vs.
Code, RAB = 20 kW
–11–
REV. 0
AD5260/AD5262
6
6
0
6
0
T
= 25؇C
T
= 25؇C
A
f–3dB = 310kHz, R = 20k⍀
f–3dB = 131kHz, R = 50k⍀
CODE = FF
CODE = FF
H
A
H
0
–6
80
40
20
10
08
80
40
20
10
08
04
02
01
H
H
H
H
H
H
H
H
H
H
–6
–6
–12
–18
–24
–30
–36
–42
–48
–54
–12
–18
–24
–30
–36
–42
–48
–54
–12
–18
–24
–30
–36
–42
–48
–54
f–3dB = 30kHz, R = 200k⍀
04
02
01
H
H
H
H
H
H
V
= 50mV rms
DD SS
IN
–3dB
V
/V = ؎5V
BANDWIDTHS
1k
10k
100k
FREQUENCY – Hz
1M
1k
10k
FREQUENCY – Hz
100k
1k
10k
100k
1M
FREQUENCY – Hz
TPC 18. Gain vs. Frequency vs. Code
TPC 19. Gain vs. Frequency vs.
TPC 20. –3 dB Bandwidth
RAB = 50 kW
Code RAB = 200 kW
600
500
600
500
400
300
200
100
0
CODE = 80 , V = V , V = 0V
CODE = 80
H
A
DD
B
H
V
/V = ؎5V
= 25؇C
DD SS
A
T
–PSRR @ V = ؎5V DC ؎ 10% p-p AC
DD
CODE FF
H
R = 20k⍀
400
300
R = 200k⍀
V
/V = ؎5V
DD SS
R = 50k⍀
200
100
0
V
/V = +5V/0V
DD SS
+PSRR @ V = ؎5V DC ؎ 10% p-p AC
DD
CODE 55
H
10k
100k
1M
10M
100
1k
10k
100k
1M
100
1k
10k
100k
FREQUENCY – Hz
FREQUENCY – Hz
FREQUENCY – Hz
TPC 21. Normalized Gain
Flatness vs. Frequency
TPC 22. ILOGIC vs. Frequency
TPC 23. PSRR vs. Frequency
20mV/DIV
10mV/DIV
5V/DIV
5V/DIV
5V/DIV
1s/DIV
40ns/DIV
20s/DIV
TPC 24. Mid-Scale Glitch
Energy, Code 80H to 7FH
TPC 25. Large Signal Settling Time
TPC 26. Digital Feedthrough vs. Time
–12–
REV. 0
AD5260/AD5262
100
10
0.10
0.05
40
30
20
10
0
V
= V = OPEN
B
CODE = 80
H
DD SS
SS = 135 UNITS
A
A
CODE SET TO MID-SCALE
T
= 25؇C
V
= V = ؎5V
T = 150؇C
A
3 LOTS
AVG –3
SAMPLE SIZE = 135
0
AVG
1
–0.05
–0.10
–0.15
–0.20
R
= 20k⍀
AB
R
= 50k⍀
AB
AVG +3
0.1
R
= 200k⍀
AB
0.01
–0.50 –0.40 –0.30–0.20–0.10
0
0.10 0.20
0
32
64
96 128 160 192 224 256
CODE – Decimal
0
50 100 150 200 250 300 350 400 450 500
HOURS OF OPERATION AT 150؇C
CHANNEL-TO-CHANNEL R MATCH – %
AB
TPC 27. IMAX vs. Code
TPC 28. Long-Term Resistance Drift
TPC 29. Channel-to-Channel
Resistance Matching (AD5262)
TEST CIRCUITS
Test Circuits 1 to 9 define the test conditions used in the product specification table.
V
A
V+ = V
10%
PSRR (dB) = 20 LOG
DD
⌬V
MS
V+ = V
DUT
A
DD
N
(
%
)
1LSB = V+/2
⌬V
V
DD
DD
A
⌬V
MS
W
W
V+
V؉
PSS (%/%) =
⌬V
%
DD
B
B
V
V
MS
MS
Test Circuit 1. Potentiometer Divider
Nonlinearity Error (INL, DNL)
Test Circuit 4. Power Supply Sensitivity (PSS, PSSR)
A
+13V
NC
W
NC = NO CONNECT
V
DUT
DUT
IN
AD8610
–13V
V
I
OUT
W
A
OFFSET
GND
W
B
B
V
MS
Test Circuit 5. Gain vs. Frequency
Test Circuit 2. Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
0.1V
R
=
SW
I
SW
CODE = 00
DUT
H
W
DUT
I
= V /R
NOMINAL
DD
B
W
0.1V
I
A
SW
V
W
W
V
MS2
B
V
TO V
DD
SS
V
R
= [V
– V
]/I
W
MS2
MS1
A = NC
W
MS1
Test Circuit 6. Incremental ON Resistance
Test Circuit 3. Wiper Resistance
NC
I
V
A
B
CM
DD
W
DUT
V
GND
SS
V
CM
NC
Test Circuit 7. Common-Mode Leakage Current
REV. 0
–13–
AD5260/AD5262
TEST CIRCUITS (continued)
+5.0V
؎5V p-p
SS
CS
V
V
V
DD
DD
LOGIC
I
C
CLK
SDI
SCLK
MOSI
LOGIC
؎2.5V p-p
D = 80
GND
CS
CLK
SDI
H
GND
V
SS
–5.0V
DIGITAL INPUT
VOLTAGE
Figure 13. Bipolar Operation from Dual Supplies
Gain Control Compensation
Digital potentiometers are commonly used in gain control as in
the noninverting gain amplifier shown in Figure 14.
Test Circuit 8. VLOGIC Current vs. Digital Input Voltage
NC
C2
4.7pF
I
V
A
B
CM
DD
W
DUT
R2
V
GND
SS
200k⍀
B
V
CM
A
R1
W
NC
47k⍀
C1
25pF
Test Circuit 9. Analog Crosstalk
V
O
U1
V
i
Figure 14. Typical Noninverting Gain Amplifier
Notice that when the RDAC B terminal parasitic capacitance is
connected to the op amp noninverting node, it introduces a zero
for the 1/bO term with +20 dB/dec, whereas a typical op amp GBP
has –20 dB/dec characteristics. A large R2 and finite C1 can cause
this Zero’s frequency to fall well below the crossover frequency.
Hence the rate of closure becomes 40 dB/dec and the system has
0∞ phase margin at the crossover frequency. The output may ring
or oscillate if the input is a rectangular pulse or step function.
Similarly, it is also likely to ring when switching between two
gain values because this is equivalent to a step change at the input.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates output voltages at wiper-
to-B and wiper-to-A to be proportional to the input voltage at
A-to-B. Ignore the effect of the wiper resistance at the moment.
For example, connecting A-terminal to 5 V and B-terminal to
ground produces an output voltage at the wiper-to-B starting at
zero volts up to 1 LSB less than 5 V. Each LSB of voltage is equal
to the voltage applied across terminal AB divided by the 256 posi-
tion of the potentiometer divider. Since the AD5260/AD5262
operates from dual supplies, the general equation defining the
output voltage at VW with respect to ground for any given input
voltage applied to terminals AB is:
Depending on the op amp GBP, reducing the feedback resistor
may extend the Zero’s frequency far enough to overcome the prob-
lem. A better approach, however, is to include a compensation
capacitor C2 to cancel the effect caused by C1. Optimum compen-
sation occurs when R1 ꢂ C1 = R2 ꢂ C2. This is not an option
because of the variation of R2. As a result, one may use the relation-
ship above and scale C2 as if R2 is at its maximum value. Doing so
may overcompensate and compromise the performance slightly
when R2 is set at low values. However, it will avoid the ringing or
oscillation at the worst case. For critical applications, C2 should
be found empirically to suit the need. In general, C2 in the range
of a few pF to no more than a few tenths of pF is usually adequate
for the compensation.
D
256
VW D =
¥VAB +VB
(3)
(
)
Operation of the digital potentiometer in the divider mode results
in more accurate operation over temperature. Unlike the rheostat
mode, the output voltage is dependent on the ratio of the internal
resistors RWA and RWB and not the absolute values; therefore, the
drift reduces to 5 ppm/∞C.
APPLICATIONS
Bipolar DC or AC Operation from Dual Supplies
The AD5260/AD5262 can be operated from dual supplies enabling
control of ground referenced AC signals or bipolar operation.
The AC signal, as high as VDD/VSS, can be applied directly across
terminals A–B with output taken from terminal W. See Figure 13
for a typical circuit connection.
Similarly, there are W and A terminal capacitances connected to
the output (not shown). Fortunately their effect at this node is less
significant, and the compensation can be avoided in most cases.
Programmable Voltage Reference
For voltage divider mode operation, Figure 15, it is common
to buffer the output of the digital potentiometer unless the load is
much larger than RWB. Not only does the buffer serve the pur-
pose of impedance conversion, but it also allows a heavier load
to be driven.
–14–
REV. 0
AD5260/AD5262
Similar to the previous example, in the simpler (and much more
usual) case, where K = 1, a single digital pot AD5260, and U1
is replaced by a matched pair of resistors to apply Vi and – Vi at
the ends of the digital pot. The relationship becomes:
5V
1
U1
V
IN
AD5260
5V
3
V
OUT
A
W
Ê
Ë
R2ˆ Ê 2D2
ˆ
¯
GND
2
V
B
AD8601
A1
VO = 1+
- 1 ¥Vi
O
Á
˜ Á
˜
(6)
R1 256
¯ Ë
AD1582
If R2 is large, a few picofarad compensation capacitors may be
needed to avoid any gain peaking.
Figure 15. Programmable Voltage Reference
8-Bit Bipolar DAC
Figure 16 shows a low cost 8-bit bipolar DAC. It offers the same
number of adjustable steps but not the precision of conventional
DACs. The linearity and temperature coefficients, especially at low
values codes, are skewed by the effects of the digital potentiometer
wiper resistance. The output of this circuit is:
Table VIII shows the result of adjusting D, with A2 configured as a
unity gain, a gain of 2, and a gain of 10. The result is a bipolar
amplifier with linearly programmable gain and 256-step resolution.
Table VIII. Result of Bipolar Gain Amplifier
D
R1 = •, R2 = 0
R1 = R2
R2 = 9R1
0
64
128
192
255
–1
–0.5
0
0.5
0.968
–2
–1
0
–10
–5
0
Ê 2D
Ë 256
ˆ
¯
VO
=
- 1 ¥V
Á
˜
(4)
REF
1
5
+5V
1.937
9.680
AD5260
V
i
U2
V
O
OP2177
Programmable Voltage Source with Boosted Output
For applications that require high current adjustment such as a
laser diode driver or turnable laser, a boosted voltage source can
be considered (see Figure 18).
U1
W
B
V
IN
A2
A
–5V
R
R
V
OUT
+5V
؊5V
+5V
W1
REF
REF
TRIM
V
i
GND
V
O
ADR425
5V
OP2177
10k⍀
R1
P1
R
BIAS
A
B
C
C
A1
W
–5V
U1
N1
SIGNAL
LO
A1
I
L
Figure 16. 8-Bit Bipolar DAC
Bipolar Programmable Gain Amplifier
For applications that require bipolar gain, Figure 17 shows one
implementation. Digital potentiometer U1 sets the adjustment
range. The wiper voltage at W2 can therefore be programmed
between Vi and –KVi at a given U2 setting. Configuring A2 in
the noninverting mode allows linear gain and attenuation. The
transfer function is:
U1= AD5260
A1= AD8601, AD8605, AD8541
P1= FDP360P, NDS9430
N1= FDV301N, 2N7002
Figure 18. Programmable Boosted Voltage Source
In this circuit, the inverting input of the op amp forces the VO to be
equal to the wiper voltage set by the digital potentiometer. The
load current is then delivered by the supply via the P-Ch FET P1.
The N-Ch FET N1 simplifies the op amp driving requirement.
A1 needs to be the rail-to-rail input type. Resistor R1 is needed to
prevent P1 from not turning off once it is on. The choice of R1 is a
balance between the power loss of this resistor and the output turn-
off time. N1 can be any general-purpose signal FET; on the other
hand, P1 is driven in the saturation state, and therefore its power
Ê
ˆ
VO
Vi
Ê
Ë
R2ˆ
D2
256
= 1+
¥
¥ 1+ K - K
(
)
Á
˜
(5)
Á
˜
R1
¯
Ë
¯
where K is the ratio of RWB1/RWA1 set by U1.
V
DD
ADU52262
V
OP2177
O
handling must be adequate to dissipate (V – VO) ꢂ IL power. This
i
W2
B2
circuit can source a maximum of 100 mA at 5 V supply. Higher
current can be achieved with P1 in a larger package. Note, a single
N-Ch FET can replace P1, N1, and R1 altogether. However, the out-
put swing will be limited unless separate power supplies are used.
For precision application, a voltage reference such as ADR423,
ADR292, and AD1584 can be applied at the input of the digital
potentiometer.
R2
R1
C1
A2
A2
A1
V
SS
B1
W1
V
i
–KV
i
V
DD
ADU51262
OP2177
A1
Programmable 4-to-20 mA Current Source
A programmable 4-to-20 mA current source can be implemented
with the circuit shown in Figure 19. REF191 is a unique low
supply headroom and high current handling precision reference
V
SS
Figure 17. Bipolar Programmable Gain Amplifier
REV. 0
–15–
AD5260/AD5262
that can deliver 20 mA at 2.048 V. The load current is simply the
voltage across terminals B-to-W of the digital pot divided by RS.
Programmable Low-Pass Filter
Digital potentiometer AD5262 can be used to construct a second
order Sallen Key Low-Pass Filter (see Figure 21). The design
equations are:
VREF ¥ D
IL
=
(7)
RS
2
VO
Vi
wO
w
Q
=
=
؉5V
2
(9)
S2 + O S + wO
2
V
U1
IN
1
REF191
3
wO
(10)
(11)
0 TO (2.048 ؉ V )
L
SLEEP
6
R1R2C1C2
V
OUT
B
W
C1
AD5260
GND
4
1F
1
1
A
+5V
Q =
+
R1C1 R2C2
Users can first select some convenient values for the capacitors.
To achieve maximally flat bandwidth where Q = 0.707, let C1 be
twice the size of C2 and let R1 = R2. As a result, users can adjust
R1 and R2 to the same settings to achieve the desirable bandwidth.
U2
–
R
S
OP1177
+
102⍀
–2.048V TO V
L
V
L
R
L
100⍀
I
L
–5V
C1
Figure 19. Programmable 4-to-20 mA Current Source
+2.5V
The circuit is simple, but be aware that dual-supply op amps are
ideal because the ground potential of REF191 can swing from
–2.048 V at zero scale to VL at full scale of the potentiometer
setting. Although the circuit works under single supply, the pro-
grammable resolution of the system will be reduced.
R1
R2
A
B
A
B
V
i
AD8601
–2.5V
V
O
W
W
R
R
C2
Programmable Bidirectional Current Source
ADJUSTED TO
SAME SETTINGS
For applications that require bidirectional current control or higher
voltage compliance, a Howland current pump can be a solution
(see Figure 20). If the resistors are matched, the load current is:
Figure 21. Sallen Key Low-Pass Filter
Programmable Oscillator
R2A + R2B /R1
(
)
(8)
IL
=
¥VW
In a classic Wien-bridge oscillator, Figure 22, the Wien network
(R, R’, C, C’) provides positive feedback, while R1 and R2
provide negative feedback. At the resonant frequency, fo, the
overall phase shift is zero, and the positive feedback causes the
circuit to oscillate. With R = R’, C = C’, and R2 = R2A//(R2B+
RDIODE), the oscillation frequency is:
R2B
R1
R2
150k⍀
15k⍀
C1
10pF
+15V
1
RC
1
wO
=
or fO
=
(12)
2pRC
C2
A2
10pF
AD8016
+5V
where R is equal to RWA such that:
+15V
R
L
256 – D
256
A
R =
RAB
50⍀
R1
(13)
(14)
–15V
R2A
150k⍀
AD5260
W
V
L
OP2177
B
At resonance, setting
14.95k⍀
R
500⍀
L
R2
= 2
R1
A1
–5V
–15V
I
L
balances the bridge. In practice, R2/R1 should be set slightly larger
than 2 to ensure the oscillation can start. On the other hand, the
alternate turn-on of the diodes D1 and D2 ensures R2/R1 to be
smaller than 2 momentarily and therefore stabilizes the oscillation.
Figure 20. Programmable Bidirectional Current Source
Once the frequency is set, the oscillation amplitude can be tuned
by R2B since:
2
3
VO = IDR2B +VD
(15)
–16–
REV. 0
AD5260/AD5262
A
B
VO, ID, and VD are interdependent variables. With proper selection
of R2B, an equilibrium will be reached such that VO converges. R2B
can be in series with a discrete resistor to increase the amplitude,
but the total resistance cannot be too large to saturate the output.
W
R2
R1
In both circuits in Figures 21 and 22, the frequency tuning requires
that both RDACs be adjusted to the same settings. Since the two
channels will be adjusted one at a time, an intermediate state will
occur that may not be acceptable for certain applications. As a
result, different devices can also be used in daisy-chained mode so
that parts can be programmed to the same setting simultaneously.
R2 << R1
Figure 24. Lowering the Nominal Resistance
Figures 23 and 24 show that the digital potentiometers change steps
linearly. On the other hand, log taper adjustment is usually pre-
ferred in applications like audio control. Figure 25 shows another
way of resistance scaling. In this circuit, the smaller the R2 with
respect to RAB, the more the pseudo-log taper characteristic behaves.
FREQUENCY
ADJUSTMENT
C
R
2.2nF
10k⍀
VP
A
B
B
C
2.2nF
R
10k⍀
+5V
W
W
A
V
i
U1
OP1177
–5V
V
O
A
AD5262
W
V
R1
O
R1 = R1 = R2B = AD5262
D1 = D2 = 1N4148
VN
B
R2
R2A
2.1k⍀
D1
D2
R2B
10k⍀
B
W
A
R1
Figure 25. Resistor Scaling with Log Adjustment
Characteristics
1k⍀
AMPLITUDE
ADJUSTMENT
RDAC CIRCUIT SIMULATION MODEL
Figure 22. Programmable Oscillator with
Amplitude Control
The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the RDACs. Configured
as a potentiometer divider, the –3 dB bandwidth of the AD5260
(20 kW resistor) measures 310 kHz at half scale. TPC 20 provides
the large signal BODE plot characteristics of the three available
resistor versions 20 kW, 50 kW, and 200 kW. A parasitic simulation
model is shown in Figure 26. Listing I provides a macro model
net list for the 20 kW RDAC.
Resistance Scaling
The AD5260/AD5262 offer 20 kW, 50 kW, and 200 kW nominal
resistance. For users who need lower resistance and still maintain the
numbers of step adjustment, they can parallel multiple devices. For
example, Figure 23 shows a simple scheme of paralleling both
channels of the AD5262. To adjust half of the resistance linearly
per step, users need to program both channels coherently with
the same settings.
RDAC
20k⍀
A
B
V
C
W
DD
C
C
A
B
25pF
25pF
55pF
A2
B2
A1
B1
W
W1
W2
Figure 26. RDAC Circuit Simulation Model for RDAC = 20 kW
LD
Listing I. Macro Model Net List for RDAC
PARAM D=256, RDAC=20E3
Figure 23. Reduce Resistance by Half with Linear
Adjustment Characteristics
*
SUBCKT DPOT (A,W,B)
*
In voltage divider mode, a much lower resistance can be achieved
by paralleling a discrete resistor as shown in Figure 24. The equiva-
lent resistance becomes:
CA
RWA
CW
RWB
CB
*
A
A
W
W
B
0
W
0
B
0
25E-12
{(1-D/256)*RDAC+60}
55E-12
{D/256*RDAC+60}
25E-12
D
256
RWB _eq
=
R1§§ R2 + R
(16)
(17)
(
)
W
Ê
Ë
D ˆ
RWA_eq = 1-
R1§§ R2 + R
(
)
.ENDS DPOT
W
Á
˜
256
¯
REV. 0
–17–
AD5260/AD5262
DIGITAL POTENTIOMETER FAMILY SELECTION GUIDE1
Number
of VRs per Voltage
Number Package
Terminal
Interface
Data
Control
Nominal
Resistance
(k⍀)
Resolution
(No. of Wiper Current
Positions)
Power Supply
Part
Range (V)
(IDD) (A)
Packages
Comments
AD5201
1
±3, 5.5
3-Wire
10, 50
33
40
mSOIC-10
Full AC Specs, Dual
Supply, Power-On-
Reset, Low Cost
AD5220
AD7376
1
1
5.5
UP/DOWN 10, 50, 100
128
40
PDIP, SO-8,
mSOIC-8
No Rollover,
Power-On-Reset
±15, 28
3-Wire
3-Wire
10, 50, 100, 128
1000
100
PDIP-14,
SOL-16,
TSSOP-14
Single 28 V or Dual
±15 V Supply Operation
AD5200
1
±3, 5.5
10, 50
256
40
mSOIC-10
Full AC Specs, Dual
Supply, Power-On-Reset
AD8400
AD5260
1
1
5.5
3-Wire
3-Wire
1, 10, 50, 100 256
5
SO-8
Full AC Specs
±5, 15
20, 50, 200
256
60
TSSOP-14
5 V to 15 V or ±5 V
Operation,
TC < 50 ppm/∞C
AD5241
AD5231
1
1
±3, 5.5
2-Wire
3-Wire
10, 100,
1000
256
50
20
SO-14,
TSSOP-14
I2C Compatible,
TC < 50 ppm/∞C
±2.75, 5.5
10, 50, 100
1024
TSSOP-16
Nonvolatile Memory,
Direct Program, I/D,
±6 dB settability
AD5222
2
±3, 5.5
UP/DOWN 10, 50, 100, 128
1000
80
SO-14,
TSSOP-14
No Rollover, Stereo,
Power-On-Reset,
TC < 50 ppm/∞C
AD8402
AD5207
2
2
5.5
3-Wire
3-Wire
1, 10, 50,
100
256
256
5
PDIP, SO-14, Full AC Specs, nA
TSSOP-14
Shutdown Current
±3, 5.5
10, 50, 100
10, 50, 100
25, 250
40
TSSOP-14
Full AC Specs, Dual
Supply, Power-On-
Reset, SDO
AD5232
AD52352
2
2
±2.75, 5.5
±2.75, 5.5
3-Wire
3-Wire
256
20
20
TSSOP-16
TSSOP-16
Nonvolatile Memory,
Direct Program, I/D,
±6 dB Settability
1024
Nonvolatile Memory,
Direct Program,
TC < 50 ppm/∞C
AD5242
AD5262
2
2
±3, 5.5
±5, 15
2-Wire
3-Wire
10, 100,
1000
256
256
50
60
SO-16,
TSSOP-16
I2C Compatible,
TC < 50 ppm/∞C
20, 50, 200
TSSOP-16
5 V to 15 V or ±5 V
Operation,
TC < 50 ppm/∞C
AD5203
AD5233
4
4
5.5
3-Wire
3-Wire
10, 100
64
64
5
PDIP, SOL-24, Full AC Specs, nA
TSSOP-24
Shutdown Current
±2.75, 5.5
10, 50, 100
20
TSSOP-24
Nonvolatile Memory,
Direct Program, I/D,
±6 dB Settability
AD5204
AD8403
AD5206
4
4
6
±3, 5.5
5.5
3-Wire
3-Wire
3-Wire
10, 50, 100
256
60
5
PDIP, SOL-24, Full AC Specs, Dual
TSSOP-24 Supply, Power-On-Reset
1, 10, 50, 100 256
PDIP, SOL-24, Full AC Specs, nA
TSSOP-24 Shutdown Current
±3, 5.5
10, 50, 100
256
60
PDIP, SOL-24, Full AC Specs, Dual
TSSOP-24
Supply, Power-On-Reset
1For the most current information on digital potentiometers, check the website at: www.analog.com/DigitalPotentiometers
2Future product, consult factory for latest status.
–18–
REV. 0
AD5260/AD5262
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead TSSOP
(RU-14)
0.201 (5.10)
0.193 (4.90)
14
8
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
7
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0433 (1.10)
MAX
8؇
0.0256 0.0118 (0.30)
0؇
0.028 (0.70)
0.020 (0.50)
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
(0.65)
BSC
0.0075 (0.19)
16-Lead TSSOP
(RU-16)
0.201 (5.10)
0.193 (4.90)
16
9
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
8
PIN 1
0.0433 (1.10)
MAX
0.006 (0.15)
0.002 (0.05)
8؇
0؇
0.028 (0.70)
0.020 (0.50)
0.0256 (0.65) 0.0118 (0.30)
0.0079 (0.20)
0.0035 (0.090)
SEATING
PLANE
BSC
0.0075 (0.19)
REV. 0
–19–
–20–
相关型号：
AD5260BRUZ20-REEL7
IC 20K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO14, TSSOP-14, Digital Potentiometer
ADI
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