AD5260BRUZ200 [ADI]
1-/2-Channel 15 V Digital Potentiometer; 1 / 2通道15 V数字电位计
| 型号： | AD5260BRUZ200 |
| 厂家： | 
ADI |
| 描述： | 1-/2-Channel 15 V Digital Potentiometer |
| 文件： | 总24页 (文件大小：610K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1-/2-Channel 15 V Digital Potentiometer
AD5260/AD5262
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
A
W
B
256 positions
AD5260: 1 channel
AD5262: 2 channels (independently programmable)
Potentiometer replacement
SHDN
AD5260
V
DD
RDAC
REGISTER
20 kΩ, 50 kΩ, 200 kΩ
V
SS
Low temperature coefficient: 35 ppm/°C
4-wire, SPI-compatible serial data input
5 V to 15 V single-supply; 5.5 V dual-supply operation
Power on midscale preset
V
L
POWER-ON
RESET
PR
CS
LOGIC
8
CLK
SDI
SDO
SERIAL INPUT REGISTER
APPLICATIONS
GND
Mechanical potentiometer replacement
Instrumentation: gain, offset adjustment
Stereo channel audio level control
Figure 1. AD5260
A1 W1 B1
A2 W2 B2
Programmable voltage-to-current conversion
Programmable filters, delays, time constants
Line impedance matching
SHDN
V
DD
Low resolution DAC replacement
RDAC1
RDAC2
REGISTER
REGISTER
V
SS
GENERAL DESCRIPTION
V
L
The AD5260/AD5262 provide a single- or dual-channel, 256-
position, digitally controlled variable resistor (VR) device.1
These devices perform the same electronic adjustment function
as a potentiometer or variable resistor. Each channel of the
AD5260/AD5262 contains a fixed resistor with a wiper contact
that taps the fixed resistor value at a point determined by a
digital code loaded into the SPI-compatible serial-input register.
The resistance between the wiper and either end point of the
fixed resistor varies linearly with respect to the digital code
transferred into the VR latch. The variable resistor offers a
completely programmable value of resistance, between the A
terminal and the wiper or the B terminal and the wiper. The
fixed A-to-B terminal resistance of 20 Ω, 50 Ω, or 200 Ω has a
nominal temperature coefficient of 35 ppm/°C. Unlike the
majority of the digital potentiometers in the market, these
devices can operate up to 15 V or 5 V provided proper supply
voltages are furnished.
POWER-ON
RESET
PR
CS
LOGIC
8
CLK
SDI
SDO
SERIAL INPUT REGISTER
AD5262
GND
Figure 2. AD5262
edge of the CLK pin. The AD5262 address bit determines the
corresponding VR latch to be loaded with the last eight bits of
CS
the data word during the positive edging of
strobe. A serial
data output pin at the opposite end of the serial register enables
simple daisy-chaining in multiple VR applications without
additional external decoding logic. An optional reset pin (
forces the wiper to the midscale position by loading 0x80 into
the VR latch.
PR
)
The AD5260/AD5262 are available in thin surface-mount
14-lead TSSOP and 16-lead TSSOP packages. All parts are
guaranteed to operate over the extended industrial temperature
range of −40°C to +85°C.
Each VR has its own VR latch that holds its programmed
resistance value. These VR latches are updated from an internal
serial-to-parallel shift register, which is loaded from a standard
3-wire serial-input digital interface. The AD5260 contains an
8-bit serial register whereas the AD5262 contains a 9-bit serial
register. Each bit is clocked into the register on the positive
1 The terms digital potentiometers, VR, and RDAC are used interchangeably.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2002–2010 Analog Devices, Inc. All rights reserved.
AD5260/AD5262
TABLE OF CONTENTS
Features .............................................................................................. 1
Layout and Power Supply Bypassing ....................................... 18
Terminal Voltage Operating Range ......................................... 18
Power-Up Sequence ................................................................... 18
RDAC Circuit Simulation Model............................................. 18
Macro Model Net List for RDAC ............................................. 18
Applications Information.............................................................. 19
Bipolar DC or AC Operation from Dual Supplies................. 19
Gain Control Compensation .................................................... 19
Programmable Voltage Reference............................................ 19
8-Bit Bipolar DAC...................................................................... 19
Bipolar Programmable Gain Amplifier................................... 20
Programmable Voltage Source with Boosted Output ........... 20
Programmable 4 mA-to-20 mA Current Source ................... 20
Programmable Bidirectional Current Source......................... 21
Programmable Low-Pass Filter ................................................ 21
Programmable Oscillator .......................................................... 21
Resistance Scaling ...................................................................... 22
Outline Dimensions....................................................................... 23
Ordering Guide .......................................................................... 24
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—20 kΩ, 50 kΩ, 200 kΩ Versions .. 3
Timing Diagrams.......................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 9
Test Circuits..................................................................................... 14
Theory of Operation ...................................................................... 15
Digital Interfacing ...................................................................... 15
Daisy-Chain Operation ............................................................. 16
RDAC Structure.......................................................................... 16
Programming the Variable Resistor......................................... 16
Programming the Potentiometer Divider............................... 17
REVISION HISTORY
8/10—Rev. 0 to Rev. A
Changes to Figure 11 Caption and Figure 12 ................................9
Changes to Figure 31...................................................................... 12
Changes to Figure 35 Caption ...................................................... 13
Changes to Figure 43 and Figure 46............................................. 14
Deleted Potentiometer Family Selection Guide ......................... 18
Change to Programmable Voltage Source with Boosted Output
Section.............................................................................................. 20
Changes to Figure 64...................................................................... 21
Updated Outline Dimensions....................................................... 23
Changes to Ordering Guide.......................................................... 24
Updated Format..................................................................Universal
Deleted Figure 1; Renumbered Sequentially................................. 1
Changes to General Description Section ...................................... 1
Changes to Conditions of Channel Resistance Matching
(AD5262 only) Parameter, Voltage Divider Temperature
Coefficient Parameter, Full-Scale Error Parameter, and Zero-
Scale Error Parameter, Table 1........................................................ 3
Changes to Table 2 and Table 3....................................................... 5
Changes to Table 4............................................................................ 6
Changes to Table 5............................................................................ 7
Changes to Table 6............................................................................ 8
3/02—Revision 0: Initial Version
Rev. A | Page 2 of 24
AD5260/AD5262
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—20 kΩ, 50 kΩ, 200 kΩ VERSIONS
VDD = +15 V, VSS = 0 V, or VDD = +5 V, VSS = –5 V; VL = +5 V; VA = +5 V, VB = 0 V, −40°C < TA < +85°C, unless otherwise noted.
The AD5260/AD5262 contain 1968 transistors. Die size: 89 mil × 105 mil (9345 sq mil).
Table 1.
Parameter
Symbol
Conditions
Min
Typ1
Max Unit
DC CHARACTERISTICS RHEOSTAT MODE
Resistor Differential Nonlinearity2
Resistor Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
Wiper Resistance
Specifications apply to all VRs
RWB, VA = no connect
RWB, VA = no connect
TA = 25°C
Wiper = no connect
IW = 1 V/RAB
R-DNL
R-INL
ΔRAB
ΔRAB/ΔT
RW
ΔRWB/RWB
−1
−1
−30
±±
±ꢀ
+1
+1
30
LSB
LSB
%
ppm/°C
Ω
35
60
0.1
150
Channel Resistance Matching (AD5262 only)
Channel 1 and Channel 2 RWB
DX = 0x80
,
%
Resistance Drift
ΔRAB
0.05
%
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE
Resolution
Specifications apply to all VRs
N
8
Bits
Differential Nonlinearity4
Integral Nonlinearity4
Voltage Divider Temperature Coefficient
Full-Scale Error
DNL
INL
ΔVW/ΔT
WFSE
VWZSE
−1
−1
±1/4
±1/2
5
−1
1
+1
+1
LSB
LSB
ppm/°C
LSB
LSB
Code = half scale
Code = full scale
Code = zero scale
−2
0
+0
2
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range5
VA, B, W
CA,B
VSS
VDD
V
pF
Ax and Bx Capacitance6
f = 5 MHz, measured to GND,
code = half scale
f = 1 MHz, measured to GND,
code = half scale
25
55
1
Wx Capacitance6
CW
pF
Common-Mode Leakage Current
Shutdown Current7
DIGITAL INPUTS and OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
ICM
ISHDN
VA = VB = VDD/2
nA
μA
5
VIH
VIL
VIH
VIL
VOH
VOL
IIL
2.4
2.1
4.9
V
V
V
V
V
V
μA
pF
0.8
0.6
VL = 3 V, VSS = 0 V
VL = 3 V, VSS = 0 V
RPULL-UP = 2 kΩ to 5 V
IOL = 1.6 mA, VLOGIC = 5 V
VIN = 0 V or 5 V
Input Logic Low
Output Logic High (SDO)
Output Logic Low (SDO)
Input Current8
0.4
±1
Input Capacitance6
CIL
5
POWER SUPPLIES
Logic Supply
VL
VDD RANGE
VDD/SS RANGE
IL
IDD
ISS
PDISS
2.7
4.5
±4.5
5.5
16.5
±5.5
60
1
1
V
V
V
μA
μA
μA
mW
Power Single-Supply Range
Power Dual-Supply Range
Logic Supply Current
Positive Supply Current
Negative Supply Current
Power Dissipation9
VSS = 0 V
VL = 5 V
VIH = 5 V or VIL = 0 V
VSS= −5 V
VIH = 5 V or VIL = 0 V,
VDD = +5 V, VSS = –5 V
0.3
Power Supply Sensitivity
PSS
ΔVDD= +5 V, ±10%
0.003
0.01
%/%
Rev. A | Page 3 of 24
AD5260/AD5262
Parameter
DYNAMIC CHARACTERISTICS6, 10
Symbol
Conditions
Min
Typ1
Max Unit
Bandwidth –3 dB
Total Harmonic Distortion
BW
THDW
RAB = 20 kΩ/50 kΩ/200 kΩ
VA = 1 VRMS, VB = 0 V, f = 1 kHz,
RAB = 20 kΩ
310/130/30
0.014
kHz
%
VW Settling Time
Crosstalk11
tS
VA = +5 V, VB = −5 V, ±1 LSB
error band, RAB = 20 kΩ
VA = VDD, VB = 0 V, measure VW
with adjacent RDAC making
full-scale code change (AD5262
only)
5
1
μs
CT
nV-sec
Analog Crosstalk
CTA
VA1 = VDD, VB1 = 0 V, measure VW1
with VW2 = 5 V p-p at f = 10 kHz,
RAB = 20 kΩ/200 kΩ (AD5262
only)
–64
13
dB
Resistor Noise Voltage
INTERFACE TIMING CHARACTERISTICS6, 12
Clock Frequency
Input Clock Pulse Width
Data Setup Time
eN_WB
RWB = 20 kΩ, f = 1 kHz
nV/√Hz
Specifications apply to all parts
fCLK
tCH, tCL
tDS
tDH
tPD
25
MHz
ns
ns
ns
ns
Clock level high or low
RL = 1 kΩ, CL< 20 pF
20
10
10
1
Data Hold Time
CLK to SDO Propagation Delay13
160
CS
CS
tCSS
5
ns
Setup Time
tCSW
tRS
tCSH
tCS1
20
50
0
ns
ns
ns
ns
High Pulse Width
Reset Pulse Width
CS
CLK Fall to Rise Hold Time
CS
10
Rise to Clock Rise Setup
1 Typical values represent average readings at 25°C and VDD = +5 V, VSS = −5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. IW = VDD/R for both VDD = +5 V and
VSS = −5V.
3 VAB = VDD, wiper = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 Measured at the Ax terminals. All Ax terminals are open-circuit in shutdown mode.
8 Worst-case supply current consumed when all logic-input levels set at 2.4 V, which is the standard characteristic of CMOS logic.
9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
10 All dynamic characteristics use VDD = +5 V, VSS = −5 V, VL = +5 V.
11 Measured at VW where an adjacent VW is making a full-scale voltage change.
12 See Figure 5 for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
Switching characteristics are measured using VL = 5 V.
13 Propagation delay depends on value of VDD, RL, and CL.
Rev. A | Page 4 of 24
AD5260/AD5262
TIMING DIAGRAMS
Table 2. AD5260 8-Bit Serial Data Word Format
Data
B7 (MSB)
B6
D6
26
B5
D5
25
B4
D4
24
B3
D3
23
B2
D2
22
B1
D1
21
B0 (LSB)
D7
27
D0
20
Table 3. AD5262 9-Bit Serial Data Word Format
ADDR
Data
B3
B8
A0
28
B7 (MSB)
B6
D6
26
B5
D5
25
B4
D4
24
B2
D2
22
B1
B0 (LSB)
D7
27
D3
23
D1
21
D0
20
1
D7
D6
D5
D4
D3
D2
D1
D0
SDI
0
1
CLK
CS
0
1
RDAC REGISTER LOAD
0
1
V
OUT
0
Figure 3. AD5260 Timing Diagram
1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SDI
0
1
CLK
CS
0
1
RDAC REGISTER LOAD
0
1
V
OUT
0
Figure 4. AD5262 Timing Diagram
1
0
SDI
(DATA IN)
Ax OR Dx
Dx
tDS
tDH
1
0
SDO
(DATA OUT)
A'x OR D'x
D'x
tPD
tCH
tCS1
1
0
CLK
CS
tCSH
tCL
tCSS
1
0
tCSW
tS
V
DD
V
OUT
±1 LSB
±1 LSB ERROR BRAND
0V
Figure 5. Detailed Timing Diagram
tRS
1
PR
0
tS
V
DD
0V
±1 LSBD
±1 LSB ERROR BAND
Figure 6. Preset Timing Diagram
Rev. A | Page 5 of 24
AD5260/AD5262
ABSOLUTE MAXIMUM RATINGS
TA =25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4.
Parameter
Rating
VDD to GND
VSS to GND
VDD to VSS
−0.3 V to +17 V
0 V to −7 V
17 V
VL to GND
0 V to +7 V
VSS, VDD
VA, VB, VW to GND
AX to BX, AX to WX, BX to WX
Intermittent1
Continuous
ESD CAUTION
±20 mA
±5 mA
Digital Inputs and Output Voltage
to GND
−0.3 V to VL + 0.3 V, or
+7 V (whichever is less)
Operating Temperature Range
Maximum Junction Temperature
−40°C to +85°C
150°C
(TJ MAX
)
Storage Temperature Range
Lead Temperature (Soldering,10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
−65°C to +150°C
300°C
215°C
220°C
Thermal Resistance2 θJA
14-Lead TSSOP
16-Lead TSSOP
206°C/W
150°C/W
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance setting.
2 Package power dissipation = (TJ MAX − TA)/θJA
.
Rev. A | Page 6 of 24
AD5260/AD5262
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
14
13
12
11
10
9
A
W
B
SDO
NC
AD5260
TOP VIEW
(Not to Scale)
V
L
V
V
SS
DD
SHDN
CLK
SDI
GND
PR
8
CS
NC = NO CONNECT
Figure 7. AD5260 Pin Configuration
Table 5. AD5260 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
A
A Terminal.
2
3
W
B
Wiper Terminal.
B Terminal.
4
5
VDD
SHDN
CLK
SDI
CS
Positive Power Supply. Specified for operation at both 5 V or 15 V (sum of |VDD| + |VSS| ≤ 15 V).
Active Low Input. Terminal A, open-circuit. Shutdown controls variable resistor.
Serial Clock Input, Positive Edge Triggered.
6
7
8
Serial Data Input.
Chip Select Input, Active Low. When CS returns high, data is loaded into the RDAC register.
Active Low Preset to Midscale. Sets RDAC registers to 0x80.
Ground.
Negative Power Supply. Specified for operation from 0 V to −5 V.
Logic Supply Voltage. Needs to be the same voltage as the digital logic controlling the AD5260.
No Connect. Users should not connect anything other than a dummy pad on this pin.
Serial Data Output. Open-drain transistor requires a pull-up resistor.
9
PR
10
11
12
13
14
GND
VSS
VL
NC
SDO
Rev. A | Page 7 of 24
AD5260/AD5262
16
1
2
3
4
5
6
7
8
A2
SDO
A1
15 W2
14 B2
W1
B1
AD5262
TOP VIEW
(Not to Scale)
13
12
11
10
9
V
V
L
V
DD
SS
SHDN
CLK
SDI
GND
PR
CS
Figure 8. AD5262 Pin Configuration
Table 6. AD5262 Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
3
4
5
6
7
8
9
SDO
A1
W1
B1
VDD
SHDN
CLK
SDI
CS
Serial Data Output. Open-drain transistor requires a pull-up resistor.
A Terminal RDAC 1.
Wiper RDAC 1, Address A0 = 0.
B Terminal RDAC 1.
Positive Power Supply. Specified for operation at both 5 V or 15 V. (Sum of |VDD| + |VSS| ≤ 15 V)
Active Low Input. Terminal A, open-circuit. Shutdown controls variable Resistor 1 through Resistor R2.
Serial Clock Input, Positive Edge Triggered.
Serial Data Input.
Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded, based on the
Address Bit A0, and loaded into the target RDAC register.
Active Low Preset to Midscale. Sets RDAC registers to 0x80.
10
11
12
13
14
15
16
PR
GND
VSS
VL
B2
W2
A2
Ground.
Negative Power Supply. Specified for operation at either 0 V or −5 V (sum of |VDD| + |VSS| < 15 V).
Logic Supply Voltage. Needs to be same voltage as the digital logic controlling the AD5262.
B Terminal RDAC 2.
Wiper RDAC 2, Address A0 = 1.
A Terminal RDAC 2.
Rev. A | Page 8 of 24
AD5260/AD5262
TYPICAL PERFORMANCE CHARACTERISTICS
0.5
0.4
0.8
0.7
0.6
V
V
R
= +5V
= –5V
= 20kΩ
DD
SS
T
T
T
T
= +85°C
= +125°C
= +25°C
= –40°C
A
A
A
A
AB
0.3
+5V
0.2
0.5
0.1
0.4
0.3
0
–0.1
–0.2
–0.3
–0.4
–0.5
0.2
+12V
±5V
0.1
0
–0.1
+15V
192
–0.2
0
32
64
96
128
160
192
224
256
0
32
64
96
128
160
224
256
CODE (Decimal)
CODE (Decimal)
Figure 12. DNL vs. Code
Figure 9. R-INL vs. Code vs. Supply Voltages
0.3
0.2
0.10
0.05
+5V
±5V
+15V
0.1
0
0
–0.05
–0.10
–0.15
–0.20
–0.25
–0.1
–0.2
–0.3
–0.4
+5V
±5V
+12V
+15V
0
32
64
96
128
160
192
224
256
0
32
64
96
128
160
192
224
256
CODE (Decimal)
CODE (Decimal)
Figure 13. INL vs. Code vs. Supply Voltages
Figure 10. R-DNL vs. Code vs. Supply Voltages
0.5
0.4
1.0
0.8
V
V
R
= +5V
= –5V
= 20kΩ
DD
SS
±5V
+15V
+5V
T
= +125°C
A
0.3
0.6
AB
0.2
0.4
T
= +85°C
A
0.1
T
= –40°C
0.2
A
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.2
–0.4
–0.6
–0.8
–1.0
T
= +25°C
A
0
32
64
96
128
160
192
224
256
0
32
64
96
128
160
192
224
256
CODE (Decimal)
CODE (Decimal)
Figure 14. DNL vs. Code vs. Supply Voltages
Figure 11. INL vs. Code
Rev. A | Page 9 of 24
AD5260/AD5262
1.0
2.5
2.0
1.5
1.0
0.5
0
AVG + 3σ
0.5
0
V
/V = +15/0V
DD SS
AVG
AVG – 3σ
V
/V = ±5V
DD SS
V
/V = +5V/0V
DD SS
–0.5
–1.0
0
5
10
|V – V | (V)
15
20
20
15
–40
–20
0
20
40
60
80
100
100
125
TEMPERATURE (°C)
DD
SS
Figure 15. INL vs. Supply Voltages
Figure 18. Full-Scale Error vs. Temperature
2.0
1.5
1.0
0.5
2.5
2.0
1.5
1.0
0.5
0
AVG + 3σ
AVG
V
/V = +5V/0V
DD SS
AVG – 3σ
0
V
/V = ±5V
DD SS
–0.5
–1.0
V
/V = +15/0V
DD SS
–1.5
–2.0
0
5
10
|V – V | (V)
15
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
DD
SS
Figure 19. Zero-Scale Error vs. Temperature
Figure 16. R-INL vs. Supply Voltages
1
124
104
84
64
44
24
4
R
@ V /V = +5V/0V
DD SS
ON
V
V
V
= 5V
= 5V
= 0V
LOGIC
IH
IL
0.1
R
@ V /V = +5V/–5V
DD SS
ON
0.01
0.001
V
/V = +15/0V
DD SS
R
@ V /V = +15V/0V
DD SS
ON
V
/V = ±5V
DD SS
–5
–1
3
7
11
–40
–7
26
59
92
V
(V)
TEMPERATURE (°C)
DD
Figure 17. Wiper On Resistance vs. Bias Voltage
Figure 20. Supply Current vs. Temperature
Rev. A | Page 10 of 24
AD5260/AD5262
120
100
80
28.0
27.5
27.0
26.5
26.0
25.5
25.0
24.5
20kΩ
50kΩ
60
V
/V = +15/0V
DD SS
40
20
V
/V = ±5V
DD SS
0
–20
–40
–60
200kΩ
0
32
64
96
128
160
192
224
256
–40
–7
26
59
92
125
TEMPERATURE (°C)
CODE (Decimal)
Figure 21. ILOGIC vs. Temperature
Figure 24. Potentiometer Mode Tempco ΔVWB/ΔT vs. Code
1000
100
10
6
T
= 25°C
A
CODE = 0xFF
0x80
0
–6
V
V
/V = 5V/0V
DD SS
0x40
= 5V
LOGIC
–12
–18
–24
–30
–36
–42
–48
–54
0x20
0x10
0x08
0x04
V
/V = 5V/0V
DD SS
V
= 3V
LOGIC
0x02
0x01
0
0.5
1.0
1.5
2.0
2.5
(V)
3.0
3.5
4.0
4.5
5.0
1k
10k
100k
1M
V
FREQUENCY (Hz)
IH
Figure 22. ILOGIC vs. Digital Input Voltage
Figure 25. Gain vs. Frequency vs. Code, RAB = 20 kΩ
6
0
80
70
60
50
40
30
20
10
0
T
= 25°C
A
CODE = 0xFF
0x80
–6
0x40
–12
–18
–24
–30
–36
–42
–48
–54
20kΩ
50kΩ
0x20
0x10
0x08
0x04
0x02
0x01
–10
–20
200kΩ
1k
10k
100k
1M
0
32
64
96
128
160
192
224
256
CODE (Decimal)
FREQUENCY (Hz)
Figure 23. Rheostat Mode Tempco ΔRWB /ΔT vs. Code
Figure 26. Gain vs. Frequency vs. Code, RAB = 50 kΩ
Rev. A | Page 11 of 24
AD5260/AD5262
600
500
400
300
200
100
0
6
T
= 25°C
A
CODE = 0xFF
0
–6
0x80
0x40
0x20
0x10
0x08
CODE 0xFF
–12
–18
–24
–30
–36
–42
–48
–54
V
/V = ±5V
DD SS
0x04
0x02
0x01
V
/V = +5V/0V
DD SS
CODE 0x55
10k
100k
FREQUENCY (Hz)
1M
10M
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 30. ILOGIC vs. Frequency
Figure 27. Gain vs. Frequency vs. Code, RAB = 200 kΩ
60
50
40
30
20
10
0
6
0
CODE = 0x80, V = V , V = 0V
f–3dB = 310kHz, R = 20kΩ
f–3dB = 131kHz, R = 50kΩ
A
DD
B
–6
–PSRR @ V
= ±5V DC ± 10% p-p AC
DD
–12
–18
–24
–30
–36
–42
–48
–54
f–3dB = 30kHz, R = 200kΩ
+PSRR @ V
= ±5V DC ± 10% p-p AC
DD
–3dB
BANDWIDTHS
V
V
= 50mV rms
IN
/V = ±5V
DD SS
1k
10k
100k
1M
100
1k
10k
FREQUENCY (Hz)
100k
1M
FREQUENCY (Hz)
Figure 28. −3 dB Bandwidth
Figure 31. PSRR vs. Frequency
0.3
0.2
CODE = 0x80
/V = ±5V
V
DD SS
T
= 25°C
A
0.1
0
R = 20kΩ
20mV/DIV
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
R = 50kΩ
R = 200kΩ
5V/DIV
100
1k
10k
100k
1µs/DIV
FREQUENCY (Hz)
Figure 32. Midscale Glitch Energy, Code 0x80 to 0x7F
Figure 29. Normalized Gain Flatness vs. Frequency
Rev. A | Page 12 of 24
AD5260/AD5262
0.10
0.05
CODE = 0x80
/V = ±5V
SAMPLE SIZE = 135 UNITS
V
DD SS
AVG – 3σ
0
AVG
–0.05
–0.10
–0.15
–0.20
5V/DIV
5V/DIV
AVG + 3σ
0
50
100 150 200 250 300 350 400 450 500
HOURS OF OPERATION AT 150°C
20µs/DIV
Figure 36. Long-Term Resistance Drift
Figure 33. Large Signal Settling Time
40
30
20
10
0
CODE SET TO MIDSCALE
= 150°C
3 LOTS
T
A
SAMPLE SIZE = 135 UNITS
10mV/DIV
–0.50 –0.40 –0.30 –0.20
–0.10
0
0.10 0.20
40ns/DIV
CHANNEL-TO-CHANNEL R MATCH (%)
AB
Figure 34. Digital Feedthrough vs. Time
Figure 37. Channel-to-Channel Resistance Matching (AD5262)
100
10
V
T
= V = OPEN
B
= 25°C
A
A
1
R
= 20kΩ
AB
R
= 50kΩ
AB
0.1
0.01
R
= 200kΩ
AB
0
32
64
96
128
160
192
224
256
CODE (Decimal)
Figure 35. Theoretical Maximum Current vs. Code
Rev. A | Page 13 of 24
AD5260/AD5262
TEST CIRCUITS
Figure 38 to Figure 46 define the test conditions used in Table 1.
0.1V
R
=
W
I
W
DUT
CODE = 0x00
V+ = V
1LSB = V+/2
W
DUT
A
DD
N
B
0.1V
I
W
W
V+
B
V
MS
V
TO V
SS DD
A = NC
Figure 43. Incremental On Resistance
Figure 38. Potentiometer Divider Nonlinearity Error (INL, DNL)
NC
NC
NC = NO CONNECT
DUT
I
W
V
A
I
DD
A
B
CM
W
W
DUT
B
V
GND
SS
V
CM
V
MS
NC
Figure 44. Common-Mode Leakage Current
Figure 39. Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
V
LOGIC
I
LOGIC
CS
CLK
SDI
DUT
I
= V /R
DD NOMINAL
W
A
V
W
W
V
MS2
DIGITAL INPUT
VOLTAGE
B
V
R
= (V
– V
)/I
MS1
W
MS1
MS2 W
Figure 40. Wiper Resistance
Figure 45. VLOGIC Current vs. Digital Input Voltage
V
DD
A1
A2
RDAC2
W2
V
A
RDAC1
V+ = V ± 10%
V
DD
IN
∆V
MS
DD
W1
PSRR (dB) = 20 log
V
(
)
NC
OUT
∆V
V
DD
A
∆V
∆V
%
%
MS
B2
V
W
SS
V+
PSS (%/%) =
MS
B1
DD
B
V
C
= 20 log (V
/V )
TA
OUT IN
NC = NO CONNECT
Figure 41. Power Supply Sensitivity (PSS, PSSR)
Figure 46. Analog Crosstalk
A
+13V
W
V
IN
DUT
AD8610
–13V
V
OUT
OFFSET
GND
B
Figure 42. Gain vs. Frequency
Rev. A | Page 14 of 24
AD5260/AD5262
THEORY OF OPERATION
The AD5260/AD5262 provide a single- or dual-channel, 256-
position, digitally controlled variable resistor (VR) device and
operate up to 15 V maximum voltage. Changing the programmed
VR settings is accomplished by clocking an 8-/9-bit serial data
word into the SDI (serial data input) pin. For the AD5262, the
format of this data word is one address bit. A0 represents the
first bit, B8, followed by eight data bits, B7 to B0, with MSB
first. Table 2 and Table 3 provide the serial register data word
format. See Table 7 for the AD5262 address assignment to decode
the location of the VR latch receiving the serial register data in
Bit B7 through Bit B0. VR outputs can be changed one at a time
in random sequence. The AD5260/AD5262 preset to a midscale,
simplifying fault condition recovery at power-up. Midscale can
V
V
DD
L
CS
A1
W1
B1
RDAC
LATCH
1
CLK
PR
EN
SDI
ADDR
DEC
A0
SER
REG
D7
D6
D5
D4
D3
D2
D1
D0
A2
W2
B2
RDAC
LATCH
2
PR
SDO
PR
also be achieved at any time by asserting the
pin. Both parts
have an internal power-on preset that places the wiper in a
midscale preset condition at power-on. Operation of the power-
on preset function depends only on the state of the VL pin.
POWER-
ON
PRESET
PR
SHDN
GND
V
SS
Figure 47. AD5262 Block Diagram
SHDN
The AD5260/AD5262 contain a power shutdown
pin
that places the RDAC in an almost zero power consumption
state where Terminals Ax are open circuited and the Wiper W
is connected to B, resulting in only leakage currents being con-
sumed in the VR structure. In the shutdown mode, the VR latch
settings are maintained so that, when returning to operational
mode from power shutdown, the VR settings return to their
previous resistance values.
The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register. Stand-
ard logic families work well. If mechanical switches are used for
product evaluation, they should be debounced by a flip-flop or
other suitable means. Figure 47 shows more detail of the inter-
CS
nal digital circuitry. When
is low, the clock loads data into
the serial input register on each positive clock edge (see Table 8).
Table 8. Truth Table1
Table 7. AD5262 Address Decode Table
A0
Latch Loaded
CS
PR
SHDN
CLK
Register Activity
0
RDAC1
Low Low High High
No SR effect, enables SDO pin.
1
RDAC2
Low High High
Shift one bit in from the SDI pin.
The eighth previously entered
bit is shifted out of the SDO pin.
Load SR data into RDAC latch.
No operation.
Sets all RDAC latches to half
scale, wiper centered, and SDO
latch cleared.
↑
DIGITAL INTERFACING
The AD5260/AD5262 contain a 4-wire SPI-compatible digital
X
X
X
High High
High High High
↑
CS
interface (SDI, SDO, , and CLK). For the AD5260, the 8-bit
serial word must be loaded with the MSB first. The format of
the word is shown in Table 2. For the AD5262, the 9-bit serial
word must be loaded with Address Bit A0 first, then the MSB
of the data. The format of the word is shown in Table 3.
X
Low High
X
X
High
High
Latches all RDAC latches to 0x80.
Open circuits all Resistor A
↑
High High Low
terminals, connects W to B, and
turns off SDO output transistor.
1
↑ = positive edge, X = don’t care, SR = shift register.
The data setup and data hold times in Table 1 determine the
data valid time requirements. The AD5260 uses an 8-bit serial
input data register word that is transferred to the internal
CS
RDAC register when the
AD5262, the last nine bits of the data word entered into the
CS
line returns to logic high. For the
serial register are held when
CS
returns high. Any extra bits are
goes high, it gates the address
ignored. At the same time
decoder, enabling one of two positive edge-triggered AD5262
RDAC latches (see Figure 48).
Rev. A | Page 15 of 24
AD5260/AD5262
AD5260/AD5262
CS
registers, and the
operation.
pin is then pulled high to complete the
CS
RDAC1
RDAC2
ADDR
DECODE
V
DD
CLK
SDI
SERIAL
REGISTER
AD5260
AD5260
U2
R
P
2.2kΩ
MICRO-
CONTROLLER
U1
Figure 48. Equivalent Input Control Logic
MOSI
SDI SDO
SDI SDO
SCLK SS
CLK
CLK
CS
CS
The target RDAC latch is loaded with the last eight bits of
the serial data word completing one RDAC update. For the
AD5262, two separate 9-bit data words must be clocked in to
change both VR settings.
Figure 52. Daisy-Chain Configuration
SHDN
During shutdown (
), the SDO output pin is forced to the
RDAC STRUCTURE
off (logic high) state to disable power dissipation in the pull-up
resistor. See Figure 49 for the equivalent SDO output circuit
schematic.
The RDAC contains a string of equal resistor segments with an
array of analog switches that act as the wiper connection. The
number of positions is the resolution of the device. The AD5260/
AD5262 have 256 connection points, allowing it to provide better
than 0.4% settability resolution. Figure 53 shows an equivalent
structure of the connections between the three terminals that
make up one channel of the RDAC. SWA and SWB are always
on, while one of the switches SW(0) to SW(2N – 1) is on one at a
time, depending on the resistance position decoded from the
data bits. Because the switch is not ideal, there is a 60 Ω wiper
resistance, RW. Wiper resistance is a function of supply voltage
and temperature. The lower the supply voltage is, the higher the
wiper resistance becomes. Similarly, the higher the temperature
is, the higher the wiper resistance becomes. Users should be
aware of the contribution of the wiper resistance when accurate
prediction of the output resistance is needed.
SHDN
SDO
CS
D
Q
SERIAL
REGISTER
SDI
CLK
PR
CK RS
Figure 49. Detail SDO Output Schematic of the AD5260
All digital inputs are protected with a series input resistor and
parallel Zener ESD structure as shown in Figure 50. This applies
CS
PR SHDN
to the , SDI, SDO,
,
, and CLK digital input pins.
340Ω
LOGIC
Ax
SHDN
R
S
Figure 50. ESD Protection of Digital Pins
A, B, W
R
R
S
D7
D6
D5
D4
D3
D2
D1
D0
V
SS
S
Figure 51. ESD Protection of Resistor Terminals
DAISY-CHAIN OPERATION
Wx
The serial data output (SDO) pin contains an open-drain N-
channel FET. This output requires a pull-up resistor to transfer
data to the SDI pin of the next package. This allows for daisy-
chaining several RDACs from a single processor serial data line.
The pull-up resistor termination voltage can be larger than the
RDAC
LATCH
AND
DECODE
R
S
VDD supply voltage. It is recommended to increase the clock
Bx
DIGITAL CIRCUITRY
OMITTED FOR CLARITY
N
= R /2
AB
R
S
period when using a pull-up resistor to the SDI pin of the
following device in series because capacitive loading at the
daisy-chain node connecting SDO and SDI between devices
may induce time delay to subsequent devices. Users should
be aware of this potential problem to achieve data transfer
successfully (see Figure 52). If two AD5260s are daisy-chained,
this requires a total of 16 bits of data. The first eight bits, complying
with the format shown in Table 2, go to U2, and the second
Figure 53. Simplified RDAC Architecture
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistances of the RDAC between Terminal A and
Terminal B are available with values of 20 kΩ, 50 kΩ, and 200 kΩ.
The final three digits of the part number determine the nominal
resistance value, for example, 20 kΩ = 20, 50 kΩ = 50, 200 kΩ =
200. The nominal resistance (RAB) of the VR has 256 contact points
CS
eight bits with the same format go to U1. The
pin should be
kept low until all 16 bits are clocked into their respective serial
Rev. A | Page 16 of 24
AD5260/AD5262
accessed by the wiper terminal, plus the B terminal contact. The
8-bit data in the RDAC latch is decoded to select one of the 256
possible settings. Assuming a 20 kΩ part is used, the wiper’s first
connection starts at the B terminal for data 0x00. Because there
is a 60 Ω wiper contact resistance, such a connection yields a
minimum of 60 Ω resistance between Terminal W and Terminal B.
The second connection is the first tap point corresponding to
138 Ω (RWB = RAB/256 RW = 78 Ω + 60 Ω) for Data 0x01. The third
connection is the next tap point representing 216 Ω (78 × 2 + 60)
for Data 0x02, and so on. Each LSB data value increase moves
the wiper up the resistor ladder until the last tap point is reached at
19,982 Ω (RAB − 1 LSB + RW). The wiper does not directly connect
to the B terminal. See Figure 53 for a simplified diagram of the
equivalent RDAC circuit.
set for the RDAC latch codes shown in Table 10. The result is
the same if Terminal B is tied to Terminal W.
Table 10. RWA vs. Code
RDAC (Dec)
RWA (Ω)
Output State
Full scale
Half scale
1 LSB
256
128
1
60
10,060
19,982
20,060
0
Zero scale
20
R
R
WB
WA
16
12
8
The general equation determining the digitally programmed
output resistance between W and B is
D
256
R
WB (D) =
×RAB + RW
(1)
4
where D is the decimal equivalent of the binary code that is
R
= 20kΩ
AB
loaded in the 8-bit RDAC register and RAB is the nominal end-
to-end resistance.
0
0
64
128
CODE (Decimal)
192
256
For example, when RAB = 20 kΩ, VB = 0 V, and the A terminal is
open circuit, the following output resistance values of RWB are
set for the RDAC latch codes shown in Table 9. The result is the
same if Terminal A is tied to W.
Figure 54. AD5260/AD5262 Equivalent RDAC Circuit
The typical distribution of the nominal resistance RAB from
channel to channel matches within 1%. Device-to-device
matching is process lot-dependent with the worst case of
30% variation. However, because the resistance element
is processed in thin film technology, the change in RAB with
temperature has a low 35 ppm/°C temperature coefficient.
Table 9. RWB vs. Code
RDAC (Dec)
RWB (Ω) Output State
256
128
1
19,982
10,060
138
Full scale (RAB – 1 LSB + RW)
Midscale
1 LSB
PROGRAMMING THE POTENTIOMETER DIVIDER
0
60
Zero-scale (wiper contact resistance)
Voltage Output Operation
The digital potentiometer easily generates output voltages at
wiper-to-B and wiper-to-A to be proportional to the input
voltage at A-to-B. Ignore the effect of the wiper resistance. For
example, connecting the A terminal to 5 V and the B terminal
to ground produces an output voltage at W-to-B starting at 0 V
up to 1 LSB less than 5 V. Each LSB of voltage is equal to the
voltage applied across Terminal A and Terminal B divided by
the 256 positions of the potentiometer divider. Because the
AD5260/AD5262 operate from dual supplies, the general
equation defining the output voltage at VW with respect to
ground for any given input voltage applied to Terminal A and
Terminal B is
Note that in the zero-scale condition, a finite wiper resistance of
60 Ω is present. Care should be taken to limit the current flow
between W and B in this state to no more than 20 mA to avoid
degradation or possible destruction of the internal switches.
Like the mechanical potentiometer the RDAC replaces, the
AD5260/AD5262 are completely symmetrical. The resistance
between Wiper W and Terminal A also produces a digitally
controlled complementary resistance, RWA. Figure 54 shows the
symmetrical programmability of the various terminal connec-
tions. When RWA is used, the B terminal can be left floating or
tied to the wiper. Setting the resistance value for RWA starts at a
maximum value of resistance and decreases as the data loaded
in the latch is increased in value. The general equation for this
operation is
D
VW (D) =
×VAB +VB
(3)
256
256 − D
256
Operation of the digital potentiometer in the divider mode
R
WA (D) =
×RAB + RW
(2)
results in more accurate operation over temperature. Unlike the
rheostat mode, the output voltage is dependent on the ratio of
the internal resistors, RWA and RWB, and not the absolute values;
therefore, the drift reduces to 5 ppm/°C.
For example, when RAB = 20 kΩ, VA = 0 V, and the B terminal is
open circuit, the following output resistance values of RWA are
Rev. A | Page 17 of 24
AD5260/AD5262
voltage range of the three terminals extends from VSS to VDD
regardless of the digital input level.
LAYOUT AND POWER SUPPLY BYPASSING
It is good practice to employ a compact, minimum lead length
layout design. The leads to the input should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
POWER-UP SEQUENCE
Because there are diodes to limit the voltage compliance at
Terminal A, Terminal B, and Terminal W (see Figure 56), it is
important to power VDD/VSS first before applying any voltage to
the A, B, and W terminals. Otherwise, the diode becomes forward
biased such that VDD/VSS are powered unintentionally and may
affect the rest of the user’s circuit. The ideal power-up sequence
is in the following order: GND, VDD, VSS, VL, the digital inputs,
and VA/VB/VW. The order of powering VA/VB/VW and the digital
inputs is not important as long as they are powered after VDD/VSS.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with 0.01 μF to 0.1 μF disc or
chip ceramic capacitors. Low ESR 1 μF to 10 μF tantalum or
electrolytic capacitors should also be applied at the supplies to
minimize any transient disturbance (see Figure 55). Note that
the digital ground should also be joined remotely to the analog
ground to minimize the ground bounce.
RDAC CIRCUIT SIMULATION MODEL
V
V
DD
DD
The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the RDACs. Configured
as a potentiometer divider, the −3 dB bandwidth of the AD5260
(20 kΩ resistor) measures 310 kHz at half scale. Figure 28 provides
the large signal Bode plot characteristics of the three available
resistor versions 20 kΩ, 50 kΩ, and 200 kΩ. A parasitic simula-
tion model is shown in Figure 57. The following section provides a
macro model net list for the 20 kΩ RDAC.
+
C1
C2
C3
C4
10µF
0.1µF
0.1µF
+
10µF
V
V
GND
SS
SS
Figure 55. Power Supply Bypassing
TERMINAL VOLTAGE OPERATING RANGE
RDAC
20kΩ
The AD5260/AD5262 positive VDD and negative VSS power
supply defines the boundary conditions for proper 3-terminal
digital potentiometer operation. Supply signals present on the
A, B, and W terminals that exceed VDD or VSS are clamped by
the internal forward-biased diodes (see Figure 56).
A
B
C
W
C
C
B
A
25pF
25pF
55pF
W
V
DD
Figure 57. RDAC Circuit Simulation Model for RDAC 20 kΩ
A
MACRO MODEL NET LIST FOR RDAC
PARAM D=256, RDAC=20E3
W
B
*
SUBCKT DPOT (A,W,B)
*
V
SS
CA
RWA
CW
RWB
CB
*
A
A
W
W
B
0
W
0
B
0
25E-12
{(1-D/256)*RDAC+60}
55E-12
{D/256*RDAC+60}
25E-12
Figure 56. Maximum Terminal Voltages Set by VDD and VSS
The ground pin of the AD5260/AD5262 device is primarily
used as a digital ground reference, which needs to be tied to the
common ground of the PCB. The digital input control signals to
the AD5260/AD5262 must be referenced to the device ground
pin (GND), and must satisfy the logic level defined in Table 1.
An internal level shift circuit ensures that the common-mode
.ENDS DPOT
Rev. A | Page 18 of 24
AD5260/AD5262
APPLICATIONS INFORMATION
it avoids the ringing or oscillation at the worst case. For critical
applications, C2 should be found empirically to suit the need.
In general, C2 in the range of a few picofarads (pF) to no more
than a few tenths of pF is usually adequate for the compensation.
BIPOLAR DC OR AC OPERATION FROM DUAL
SUPPLIES
The AD5260/AD5262 can be operated from dual supplies
enabling control of ground referenced ac signals or bipolar
operation. The ac signal, as high as VDD/VSS, can be applied
directly across Terminal A and Terminal B with output taken
from Terminal W. See Figure 58 for a typical circuit connection.
Similarly, there are W and A terminal capacitances connected to
the output (not shown). Fortunately, their effect at this node is less
significant, and the compensation can be avoided in most cases.
PROGRAMMABLE VOLTAGE REFERENCE
+5.0V
For voltage divider mode operation, shown in Figure 60, it is
common to buffer the output of the digital potentiometer unless
the load is much larger than RWB. Not only does the buffer serve
the purpose of impedance conversion, but it also allows a
heavier load to be driven.
V
DD
V
DD
SS
CS
±5V p-p
MICROCONTROLLER
SCLK
±2.5V p-p
D = 0x80
CLK
SDI
MOSI
GND
5V
GND
V
1
U1
SS
V
IN
–5.0V
AD5260
5V
3
V
Figure 58. Bipolar Operation from Dual Supplies
OUT
A
W
GND
GAIN CONTROL COMPENSATION
V
O
B
AD8601
A1
2
AD1582
Digital potentiometers are commonly used in gain control as in
the noninverting gain amplifier shown in Figure 59.
C2
4.7pF
Figure 60. Programmable Voltage Reference
8-BIT BIPOLAR DAC
R2
200kΩ
Figure 61 shows a low cost 8-bit bipolar DAC. It offers the same
number of adjustable steps but not the precision of conventional
DACs. The linearity and temperature coefficients, especially at low
values codes, are skewed by the effects of the digital potentiometer
wiper resistance. The output of this circuit is
B
A
R1
47kΩ
W
C1
25pF
V
U1
O
V
i
2D
256
Figure 59. Typical Noninvertng Gain Amplifier
⎛
⎜
⎝
⎞
⎠
VO
=
−1 ×V
(4)
⎟
REF
Note that when the RDAC B terminal parasitic capacitance is
connected to the op amp noninverting node, it introduces a zero
for the 1/βO term with +20 dB/dec, whereas a typical op amp
gain bandwidth product (GBP) has −20 dB/dec characteristics.
A large R2 and finite C1 can cause this zero’s frequency to fall
well below the crossover frequency. Therefore, the rate of
closure becomes 40 dB/dec and the system has 0 phase margin
at the crossover frequency. The output may ring or oscillate if
the input is a rectangular pulse or step function. Similarly, it is
also likely to ring when switching between two gain values
because this is equivalent to a step change at the input.
+5V
AD5260
V
i
U2
V
O
OP2177
U1
W
B
V
IN
A
A2
–5V
–5V
R
R
V
OUT
+5V
+5V
W1
REF
REF
TRIM
GND
ADR425
OP2177
A1
–5V
Depending on the op amp GBP, reducing the feedback resistor
may extend the zero’s frequency far enough to overcome the
problem. A better approach, however, is to include a compensa-
tion capacitor, C2, to cancel the effect caused by C1. Optimum
compensation occurs when R1 × C1 = R2 × C2. This is not an
option because of the variation of R2. As a result, the R1 × C1 =
R2 × C2 relationship can be used, and scale C2 as if R2 is at its
maximum value. Doing so may overcompensate and compromise
the performance slightly when R2 is set at low values. However,
Figure 61. 8-Bit Bipolar DAC
Rev. A | Page 19 of 24
AD5260/AD5262
BIPOLAR PROGRAMMABLE GAIN AMPLIFIER
PROGRAMMABLE VOLTAGE SOURCE WITH
BOOSTED OUTPUT
For applications that require bipolar gain, Figure 62 shows one
implementation. Digital Potentiometer U1 sets the adjustment
range. The wiper voltage at W2 can therefore be programmed
between Vi and −KVi at a given U2 setting. Configuring A2 in
the noninverting mode allows linear gain and attenuation. The
transfer function is
For applications that require high current adjustment such as a
laser diode driver or tunable laser, a boosted voltage source can
be considered (see Figure 63).
V
i
V
O
5V
10kΩ
R1
P1
R
BIAS
VO
Vi
R2
R1
D2
256
⎛
⎝
⎞ ⎛
⎠ ⎝
⎞
⎟
⎠
= 1+
×
×
(1+ K
)
− K
(5)
A
B
⎜
⎟ ⎜
C
C
W
U1
N1
SIGNAL
LO
I
L
A1
where K is the ratio of RWB1/RWA1 set by U1.
V
DD
U1 = AD5260
A1 = AD8601, AD8605, AD8541
P1 = FDP360P, NDS9430
N1 = FDV301N, 2N7002
U2
V
OP2177
O
AD5262
W2
B2
Figure 63. Programmable Boosted Voltage Source
R2
R1
C1
A2
A1
A2
V
SS
In this circuit, the inverting input of the op amp forces VO to be
equal to the wiper voltage set by the digital potentiometer. The
load current is then delivered by the supply via the P-channel
FET, P1. The N-channel FET, N1, simplifies the op amp driving
requirement. A1 must be the rail-to-rail input type. Resistor R1
is needed to prevent P1 from turning off once it is on. The choice
of R1 is a balance between the power loss of this resistor and
the output turn-off time. N1 can be any general-purpose signal
FET. However, P1 is driven in the saturation state, and there-
fore, its power handling must be adequate to dissipate (Vi − VO)
× IL power. This circuit can source a maximum of 100 mA at 5 V
supply. Higher current can be achieved with P1 in a larger pack-
age. Note that a single N-channel FET can replace P1, N1, and
R1 altogether. However, the output swing is limited unless sepa-
rate power supplies are used. For a precision application, a
voltage reference such as the ADR423, ADR292, or AD1584 can
be applied at the input of the digital potentiometer.
B1
W1
V
i
–KV
i
V
DD
U1
AD5262
OP2177
A1
V
SS
Figure 62. Bipolar Programmable Gain Amplifier
Similar to the previous example, in the simpler and more
common case, where K = 1, with a single digital potentiometer,
AD5260, U1 is replaced by a matched pair of resistors to apply
Vi and −Vi at the ends of the digital potentiometer. The relation-
ship becomes
R2 2D2
⎛
⎝
⎞⎛
⎞
⎠
VO = 1+
−1 ×V
(6)
⎜
⎟⎜
⎟
i
R1 256
⎠⎝
If R2 is large, a few picofarad compensation capacitors may be
needed to avoid any gain peaking.
PROGRAMMABLE 4 mA-TO-20 mA CURRENT
SOURCE
Table 11 shows the result of adjusting D, with A2 configured as
a unity gain, a gain of 2, and a gain of 10. The result is a bipolar
amplifier with linearly programmable gain and 256-step
resolution.
A programmable 4 mA-to-20 mA current source can be
implemented with the circuit shown in Figure 64. REF191 is a
unique low supply headroom and high current handling
precision reference that can deliver 20 mA at 2.048 V. The load
current is simply the voltage across Terminal B to Terminal W
of the digital potentiometer, divided by RS.
Table 11. Result of Bipolar Gain Amplifier
D
R1 = ∞, R2 = 0
R1 = R2
R2 = 9 × R1
V
REF ×D
RS
0
64
128
192
255
−1
−0.5
0
+0.5
+0.968
−2
−1
0
+1
−10
−5
0
+5
+9.680
IL
=
(7)
+1.937
Rev. A | Page 20 of 24
AD5260/AD5262
+5V
1
1
Q =
+
(11)
R1C1 R2C2
2
U1
V
S
Users can first select any convenient value for the capacitors. To
achieve maximally flat bandwidth where Q = 0.707, let C1 be
twice the size of C2 and let R1 = R2. As a result, users can adjust
R1 and R2 to the same settings to achieve the desirable bandwidth.
C1
REF191
3
0V TO (2.048V + V )
L
SLEEP
OUTPUT
6
B
A
W
C1
1µF
AD5260
GND
4
+5V
U2
+2.5V
–
R
S
102Ω
OP1177
+
R1
R2
–2.048 TO V
L
A
B
A
B
V
L
V
i
R
L
AD8601
–2.5V
V
O
W
W
100Ω
I
L
–5V
R
R
Figure 64. Programmable 4-to-20 mA Current Source
C2
The circuit is simple, but be aware that dual-supply op amps are
ideal because the ground potential of REF191 can swing from
−2.048 V at zero scale to VL at full scale of the potentiometer
setting. Although the circuit works under single supply, the
programmable resolution of the system is reduced.
ADJUSTED TO
SAME SETTINGS
Figure 66. Sallen Key Low-Pass Filter
PROGRAMMABLE OSCILLATOR
In a classic Wien-bridge oscillator (see Figure 67), the Wien
network (R, R’, C, C’) provides positive feedback, whereas R1
and R2 provide negative feedback. At the resonant frequency, fo,
the overall phase shift is zero, and the positive feedback causes
the circuit to oscillate. With R = R’, C = C’, and R2 = R2A//(R2B +
RDIODE), the oscillation frequency is
PROGRAMMABLE BIDIRECTIONAL CURRENT
SOURCE
For applications that require bidirectional current control or
higher voltage compliance, a Howland current pump can be a
solution (see Figure 65). If the resistors are matched, the load
current is
1
RC
1
ωO
=
or fO
=
(12)
(13)
(14)
(
R2A + R2B
R2B
)
R1
2πRC
IL
=
×VW
(8)
where R is equal to RWA such that
R1'
150kΩ
R2'
15kΩ
256 − D
256
R =
RAB
C1
10pF
+15V
At resonance, setting
R2
= 2
R1
A2
C2
10pF
AD8016
–15V
+5V
+15V
balances the bridge. In practice, R2/R1 should be set slightly
R
50Ω
L
larger than 2 to ensure the oscillation can start. However, the
alternate turn-on of the diodes, D1 and D2, ensures R2/R1 to
be smaller than 2 momentarily and therefore stabilizes the
oscillation.
A
R1
150kΩ
AD5260
W
V
I
OP2177
L
B
R2A
14.95kΩ
R
500Ω
L
A1
–5V
When the frequency is set, the oscillation amplitude can be
tuned by R2B because
L
–15V
Figure 65. Programmable Bidirectional Current Source
2
3
VO = ID R2B +VD
(15)
PROGRAMMABLE LOW-PASS FILTER
Digital Potentiometer AD5262 can be used to construct a
second-order, Sallen-Key low-pass filter (see Figure 66). The
design equations are
VO, ID, and VD are interdependent variables. With proper
selection of R2B, an equilibrium is reached such that VO
converges. R2B can be in series with a discrete resistor to
increase the amplitude, but the total resistance cannot be too
large to saturate the output.
2
VO
Vi
ωO
ωO
=
(9)
S2 +
S +ωO
2
Q
In both circuits in Figure 66 and Figure 67, the frequency tuning
requires that both RDACs be adjusted to the same settings.
Because the two channels are adjusted one at a time, an intermedi-
1
ωO
=
(10)
R1R2C1C2
Rev. A | Page 21 of 24
AD5260/AD5262
ate state occurs that may not be acceptable for certain applications.
As a result, different devices can also be used in daisy-chained
mode so that parts can be programmed to the same setting
simultaneously.
In voltage divider mode, a much lower resistance can be achieved
by paralleling a discrete resistor as shown in Figure 69. The
equivalent resistance becomes
D
256
RWB _ eq
=
(R1// R2)+ RW
(16)
(17)
FREQUENCY
ADJUSTMENT
C'
R'
2.2nF
10kΩ
VP
D
⎛
⎝
⎞
RWA _ eq = 1−
(R1//R2) + R
⎟
A
B
B
R
10kΩ
⎜
W
C
2.2nF
256
⎠
+5V
W
W
A
A
U1
V
OP1177
–5V
O
AD5262
W
R2
R1
R1 = R1' = R2B = AD5262
D1 = D2 = 1N4148
VN
R2A
2.1kΩ
D1
D2
R2B
B
R2 << R1
10kΩ
B
A
R1
1kΩ
W
Figure 69. Lowering the Nominal Resistance
AMPLITUDE
ADJUSTMENT
Figure 68 and Figure 69 show that the digital potentiometers
change steps linearly. However, log taper adjustment is usually
preferred in applications like audio control. Figure 70 shows
another method of resistance scaling. In this circuit, the smaller
R2 is with respect to RAB, the more the pseudo-log taper
characteristic behaves.
Figure 67. Programmable Oscillator with Amplitude Control
RESISTANCE SCALING
The AD5260/AD5262 offer 20 kΩ, 50 kΩ, and 200 kΩ nominal
resistance. For users who need lower resistance and still main-
tain the numbers of step adjustment, they can place multiple
devices in parallel. For example, Figure 68 shows a simple
scheme of paralleling both channels of the AD5262. To adjust
half of the resistance linearly per step, users need to program
both channels coherently with the same settings.
V
i
A
R1
W
V
O
B
R2
V
DD
Figure 70. Resistor Scaling with Log Adjustment Characteristics
A2
B2
A1
B1
W1
W2
LD
Figure 68. Reduce Resistance by Half with Linear Adjustment Characteristics
Rev. A | Page 22 of 24
AD5260/AD5262
OUTLINE DIMENSIONS
5.10
5.00
4.90
14
8
7
4.50
4.40
4.30
6.40
BSC
1
PIN 1
0.65 BSC
1.05
1.00
0.80
1.20
MAX
0.20
0.09
0.75
0.60
0.45
8°
0°
0.15
0.05
COPLANARITY
0.10
SEATING
PLANE
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 71. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 72. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
Rev. A | Page 23 of 24
AD5260/AD5262
ORDERING GUIDE
Model1
AD5260BRUZ20
AD5260BRUZ20-RL7
AD5260BRUZ50
AD5260BRUZ50-REEL7
AD5260BRUZ200
AD5260BRUZ200-RL7
AD5262BRU20
AD5262BRU20-REEL7
AD5262BRU50
AD5262BRU50-REEL7
AD5262BRU200
AD5262BRU200-REEL7
AD5262BRUZ20
AD5262BRUZ20-RL7
AD5262BRUZ50
RAB (kΩ)
20
20
50
50
200
200
20
20
50
Temperature
Package Description
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
Evaluation Board
Package Option
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
No. of Parts per Container
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
96
1000
96
1000
96
1000
96
1000
96
1000
96
1000
96
1000
96
50
200
200
20
20
50
50
200
200
AD5262BRUZ50-RL7
AD5262BRUZ200
AD5262BRUZ200-RL7
EVAL-AD5262EBZ
1000
96
1000
1 Z = RoHS Compliant Part.
©2002–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02695-0-8/10(A)
Rev. A | Page 24 of 24
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