AD532SD883B [ADI]
Internally Trimmed Integrated Circuit Multiplier; 内部微调集成电路乘法器
| 型号： | AD532SD883B |
| 厂家： | 
ADI |
| 描述： | Internally Trimmed Integrated Circuit Multiplier |
| 文件： | 总17页 (文件大小：521K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Internally Trimmed
Integrated Circuit Multiplier
AD532
FUNCTIONAL BLOCK DIAGRAM
FEATURES
X
1
Pretrimmed to 1.0% (AD532K)
V
X
X
2
No external components required
Guaranteed 1.0% maximum 4-quadrant error (AD532K)
Differential Inputs for (X1 − X2) (Y1 − Y2)/10 V transfer
function
R
R
X
Z
Y
Y
1
OUTPUT
V
Y
2
10R
Monolithic construction, low cost
V
OS
(X – X ) (Y – Y )
1
2
1
2
APPLICATIONS
R
V
=
OUT
10V
Multiplication, division, squaring, square rooting
Algebraic computation
(WITH Z TIED TO OUTPUT)
Figure 1.
Power measurements
Instrumentation applications
Available in chip form
well qualified for instrumentation applications, as it can provide
an output signal that is the product of two transducer generated
input signals.
GENERAL DESCRIPTION
The AD532 is the first pretrimmed single chip monolithic
multiplier/divider. It guarantees a maximum multiplying error
of ±1.0% and a ±10 V output voltage without the need for any
external trimming resistors or output op amp. Because the AD532
is internally trimmed, its simplicity of use provides design
engineers with an attractive alternative to modular multipliers,
and its monolithic construction provides significant advantages
in size, reliability and economy. Further, the AD532 can be used
as a direct replacement for other IC multipliers that require
external trim networks.
GUARANTEED PERFORMANCE OVER
TEMPERATURE
The AD532J and AD532K are specified for maximum multiplying
errors of ±2% and ±1% of full scale, respectively at 25°C, and
are rated for operation from 0°C to 70°C. The AD532S has a
maximum multiplying error of ±1% of full scale at 25°C; it is
also 100% tested to guarantee a maximum error of ±4% at the
extended operating temperature limits of −55°C and +125°C.
All devices are available in either the hermetically-sealed TO-
100 metal can, TO-116 ceramic DIP or LCC packages. The J, K,
and S grade chips are also available.
FLEXIBILITY OF OPERATION
The AD532 multiplies in four quadrants with a transfer function of
(X1 − X2)(Y1 − Y2)/10 V, divides in two quadrants with a 10 V
Z/(X1 − X2) transfer function, and square roots in one quadrant
ADVANTAGES OF ON-THE-CHIP TRIMMING OF
THE MONOLITHIC AD532
10 V Z
with a transfer function of ±±
. In addition to these basic
functions, the differential X and Y inputs provide significant
operating flexibility both for algebraic computation and transducer
instrumentation applications. Transfer functions, such as XY/10 V,
(X2 − Y2)/1 0 V, ±X2/10 V, and 10 V Z/(X1 − X2), are easily attained
and are extremely useful in many modulation and function
generation applications, as well as in trigonometric calculations
for airborne navigation and guidance applications, where the
monolithic construction and small size of the AD532 offer
considerable system advantages. In addition, the high CMRR
(75 dB) of the differential inputs makes the AD532 especially
1. True ratiometric trim for improved power supply rejection.
2. Reduced power requirements since no networks across
supplies are required.
3. More reliable because standard monolithic assembly
techniques can be used rather than more complex hybrid
approaches.
4. High impedance X and Y inputs with negligible circuit
loading.
5. Differential X and Y inputs for noise rejection and additional
computational flexibility.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Fax: 781.461.3113 ©2001–2011 Analog Devices, Inc. All rights reserved.
IMPORTANT LINKS for the AD532*
Last content update 09/06/2013 05:27 pm
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AD532
TABLE OF CONTENTS
Features .............................................................................................. 1
Functional Description.................................................................. 10
AD532 Performance Characteristics ........................................... 11
Nonlinearity ................................................................................ 11
AC Feedthrough ......................................................................... 11
Common-Mode Rejection........................................................ 11
Dynamic Characteristics........................................................... 11
Power Supply Considerations................................................... 11
Noise Characteristics ................................................................. 11
Applications..................................................................................... 12
Replacing Other IC Multipliers................................................ 12
Square Root................................................................................. 13
Difference of Squares................................................................. 13
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 15
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Flexibility of Operation................................................................ 1
Guaranteed Performance Over Temperature ........................... 1
Advantages of On-The-Chip Trimming of The Monolithic
AD532............................................................................................ 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Thermal Resistance .......................................................................... 5
Chip Dimensions And Bonding Diagram ................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 8
REVISION HISTORY
2/11—Rev. C to Rev. D
Updated Format..................................................................Universal
Added Pin Configuration and Function Descriptions
Section................................................................................................ 6
Added Typical Performance Characteristics Section .................. 8
Changes to Figure 11........................................................................ 8
Changes to Figure 12 and Figure 13............................................... 9
Changes to Ordering Guide .......................................................... 15
Rev. D | Page 2 of 16
AD532
SPECIFICATIONS
At 25°C, VS = ±15 V, R ≥ 2 kΩ VOS grounded, unless otherwise noted.
Table 1.
AD532J
Typ
AD532K
Typ
AD532S
Typ
Conditions
Model
Min
Max Min
Max Min
Max
Unit
MULTIPLIER PERFORMANCE
Transfer Function
(X1 − X2 )(Y −Y2 )
(X1 − X2 )(Y −Y2 )
(X1 − X2 )(Y −Y2 )
1
1
1
10V
10V
10V
Total Error
–10 V ≤ X, Y ≤ +10 V
1.5
2.0
0.7
1.0
0.5
1.0
%
TA = Minimum to Maximum
Total Error vs. Temperature
Supply Rejection
Nonlinearity, X
Nonlinearity, Y
Feedthrough, X
2.5
1.5
4.0
0.04
%
0.04
0.05
0.8
0.3
50
0.03
0.05
0.5
0.2
30
0.01
0.05
0.5
0.2
30
%/°C
%/%
%
%
mV
15 V 10%
X = 20 V p-p, Y = 10 V
Y = 20 V p-p, X = 10 V
Y nulled, X = 20 V p-p 50 Hz
200
150
100
80
100
80
Feedthrough, Y (X Nulled,
Y = 20 V p-p 50 Hz)
Feedthrough vs. Temperature
Feedthrough vs. Power Supply
DYNAMICS
30
25
25
mV
2.0
0.25
1.0
0.25
1.0
0.25
mV p-p/°C
mV/%
Small Signal BW
1% Amplitude Error
Slew Rate
VOUT = 0.1 rms
1
1
1
MHz
kHz
V/μs
μs
75
45
1
75
45
1
75
45
1
VOUT 20 p-p
to 2%, ΔVOUT = 20 V
Settling Time
NOISE
Wideband Noise
f = 5 Hz to 10 kHz
f = 5 Hz to 5 MHz
0.6
3.0
0.6
3.0
0.6
3.0
mV (rms)
mV (rms)
OUTPUT
Voltage Swing
10
13
10
13
10
13
V
Impedance
f ≤ 1 kHz
1
1
1
Ω
Offset Voltage
40
0.7
2.5
30
30
2.0
mV
mV/°C
mV/%
Offset Voltage vs. Temperature
Offset Voltage vs. Supply
INPUT AMPLIFIERS (X, Y, and Z)
Signal Voltage Range
0.7
2.5
2.5
10
Differential or CM
10
10
V
operating differential
CMRR
40
50
50
dB
Input Bias Current
X, Y Inputs
X, Y Inputs TMIN to TMAX
Z Input
Z Input TMIN to TMAX
Offset Current
Differential Resistance
DIVIDER PERFORMANCE
Transfer Function
Total Error
3
10
10
1.5
8
5
25
0.1
4
1.5
8
5
25
0.1
10
4
μA
μA
μA
μA
μA
MΩ
15
15
30
0.3
10
10
Xl > X2
10 V Z/(X1 − X2)
10 V Z/(X1 − X2)
10 V Z/(X1 − X2)
VX = −10 V, −10 V ≤ VZ ≤
+10 V
VX = −1 V, −10 V ≤ VZ ≤
+10 V
2
4
1
3
1
3
%
%
Rev. D | Page 3 of 16
AD532
AD532J
Typ
AD532K
Typ
AD532S
Typ
Conditions
Model
Min
Max Min
Max Min
Max
Unit
(X1 − X2 )2
10V
(X1 − X2 )2
10V
(X1 − X2 )2
10V
SQUARE PERFORMANCE
Transfer Function
Total Error
0.8
0.4
0.4
%
%
SQUARE ROOTER PERFORMANCE
Transfer Function
10 V Z
−√
1.5
10 V Z
1.0
10 V Z
−√
−√
Total Error
0 V ≤ VZ ≤ 10 V
1.0
POWER SUPPLY SPECIFICATIONS
Supply Voltage
Rated Performance
Operating
Supply Current
Quiescent
15
15
15
V
V
10
18
10
18
10
22
6
4
6
4
6
4
mA
Rev. D | Page 4 of 16
AD532
THERMAL RESISTANCE
CHIP DIMENSIONS AND BONDING DIAGRAM
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Contact factory for latest dimensions.
Dimensions are shown in inches and (mm).
Table 2. Thermal Resistance
Package Type
0.107
θJA
150
85
θJC
25
22
22
Unit
°C/W
°C/W
°C/W
(2.718)
–V
S
OUTPUT
H-10A
E-20A
D-14
Z
85
X
1
0.062
(1.575)
+V
S
Y
1
GND
X
V
Y
2
2
OS
Figure 2.
ESD CAUTION
Rev. D | Page 5 of 16
AD532
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Y
2
V
OS
Y
1
+V
S
GND
AD532
TOP VIEW
(Not to Scale)
Z
X
2
X
OUT
1
–V
S
Figure 3. 10-Lead Header Pin Configuration (H-10)
2
3
1
20 19
18
17
16
15
–V
4
5
6
7
8
Y
S
2
NC
NC
NC
NC
NC
AD532
V
TOP VIEW
(Not to Scale)
OS
NC
14
GND
9
10 11 12 13
NC = NO CONNECT.
DO NOT CONNECT TO THIS PIN.
Figure 4. 20-Lead Leadless Chip Carrier Pin Configuration (E-20A)
1
2
3
4
5
6
7
14
13
12
11
10
9
Z
+V
S
OUT
Y
Y
V
1
2
–V
S
AD532
TOP VIEW
NC
NC
NC
OS
(Not to Scale)
GND
X
2
8
X
NC
1
NC = NO CONNECT.
DO NOT CONNECT TO THIS PIN.
Figure 5. 14-Lead Side Braize DIP (D-14)
Table 3. 10 Lead Header Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
4
5
6
7
8
Y1
+VS
Z
OUT
−VS
X1
Y Multiplicand Input 1
Positive Supply Voltage
Dual Purpose Input
Product Output
Negative Supply Voltage
X Multiplicand Input 1
X Multiplicand Input 2
Common
X2
GND
VOS
Y2
9
10
Output Offset Adjust
Y Multiplicand Input 2
Rev. D | Page 6 of 16
AD532
Table 4. 20 Lead Leadless Chip Carrier Pin Function Descriptions
Pin No.
Mnemonic
Description
2
3
4
Z
Dual Purpose Input
Product Output
Negative Supply Voltage
No Connection
OUT
−VS
NC
1, 5, 6, 7, 8, 9, 11, 12,
15, 17
10
13
14
16
18
19
20
X1
X2
GND
VOS
Y2
X Multiplicand Input 1
X Multiplicand Input 2
Common
Output Offset Adjust
Y Multiplicand Input 2
Y Multiplicand Input 1
Positive Supply Voltage
Y1
+VS
Table 5. 14 Lead Side Braize DIP Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
Z
Dual Purpose Input
Product Output
Negative Supply Voltage
No Connection
X Multiplicand Input 1
X Multiplicand Input 2
Common
Output Offset Adjust
Y Multiplicand Input 2
Y Multiplicand Input 1
Positive Supply Voltage
OUT
−VS
NC
X1
4, 5, 6
7
9
10
11
12
13
14
X2
GND
VOS
Y2
Y1
+VS
Rev. D | Page 7 of 16
AD532
TYPICAL PERFORMANCE CHARACTERISTICS
70
60
50
40
30
20
10
0
1
Y COMMON-MODE REJ
(X – X ) = +10V
1
2
X
IN
X COMMON-MODE REJ
(Y – Y ) = +10V
Y
IN
1
2
0.1
100
1k
10k
100k
1M
10M
0.01
FREQUENCY (Hz)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
Figure 9. CMRR vs. Frequency
PEAK SIGNAL AMPLITUDE (V)
Figure 6. Distortion vs. Peak Signal Amplitude
1
100
10
1
20V p-p SIGNAL
R
= 2kΩ, C = 1000pF
L
L
R
= 2kΩ, C = 0pF
L
L
0.1
X
IN
Y
IN
0.01
10k
100k
FREQUENCY (Hz)
1M
10M
0.1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 10. Frequency Response, Multiplying
Figure 7. Distortion vs. Frequency
10
V
= 0.1 × V sin ωT
X
Z
1k
Y FEEDTHROUGH
100
10
1
1
V
= 10V
X
X FEEDTHROUGH
V
= 1V
X
V
= 5V
X
0.1
10k
100
1k
10k
100k
1M
10M
100k
FREQUENCY (Hz)
1M
10M
FREQUENCY (Hz)
Figure 11. Frequency Response, Dividing
Figure 8. Feedthrough vs. Frequency
Rev. D | Page 8 of 16
AD532
5
4
3
2
1
0
14
12
10
8
SATURATED OUTPUT
SWING
MAX X OR Y INPUT
FOR 1% LINEARITY
6
4
10
100
1k
10k
100k
10
12
14
16
18
20
22
FREQUENCY (Hz)
POWER SUPPLY VOLTAGE (V)
Figure 13. Spot Noise vs. Frequency
Figure 12. Signal Swing vs. Supply
Rev. D | Page 9 of 16
AD532
FUNCTIONAL DESCRIPTION
The functional block diagram for the AD532 is shown in
Figure 1and the complete schematic in Figure 14. In the
multiplying and squaring modes, Z is connected to the output
to close the feedback around the output op amp. In the divide
mode, it is used as an input terminal.
zero during production. The product of the two inputs is resolved
in the multiplier cell using Gilbert’s linearized transconductance
technique. The cell is laser trimmed to obtain VOUT = (X1 −
X2)(Y1 − Y2)/10 volts. The built-in op amp is used to obtain low
output impedance and make possible self-contained operation.
The residual output voltage offset can be zeroed at VOS in critical
applications. Otherwise, the VOS pin should be grounded.
The X and Y inputs are fed to high impedance differential
amplifiers featuring low distortion and good common-mode
rejection. The amplifier voltage offsets are actively laser trimmed to
X
2
+V
Z
S
R6
R8
R16
R23
R2
R27
C1
Q21
Q2
Q1
R33
Q8
Q7
Q14Q15
Q16 Q17
Q25
R20
R34
R22
V
OS
R9
R1
Q10
Y
X
1
Q9
R30
R13
R31
R21
Q3
Q4
1
Q26
Q22
Q23
Q24
R3
R28
R29
COM
OUTPUT
Q18
R10
R32
Q12
Q5
Q6
Q11
Q27
R19
Q20
R11
R14
Q19
R24 R25
Q13
Q28
R12
R5
R4
R15
R26
–V CAN
S
R18
Y
2
Figure 14. Schematic Diagram
Rev. D | Page 10 of 16
AD532
AD532 PERFORMANCE CHARACTERISTICS
Multiplication accuracy is defined in terms of total error at 25°C
with the rated power supply. The value specified is in percent of
full scale and includes XIN and YIN nonlinearities, feedback and
scale factor error. To this must be added such application-
dependent error terms as power supply rejection, common-
mode rejection and temperature coefficients (although worst
case error over temperature is specified for the AD532S). Total
expected error is the rms sum of the individual components
because they are uncorrelated.
COMMON-MODE REJECTION
The AD532 features differential X and Y inputs to enhance its
flexibility as a computational multiplier/divider. Common-mode
rejection for both inputs as a function of frequency is shown in
Figure 9. It is measured with X1 = X2 = 20 V (p-p), (Y1 − Y2) =
10 V dc and Y1 = Y2 = 20 V (p-p), (X1 − X2) = 10 V dc.
DYNAMIC CHARACTERISTICS
The closed loop frequency response of the AD532 in the multiplier
mode typically exhibits a 3 dB bandwidth of 1 MHz and rolls
off at 6 dB/octave, thereafter. Response through all inputs is
essentially the same as shown in Figure 10. In the divide mode,
the closed loop frequency response is a function of the absolute
value of the denominator voltage as shown in Figure 11.
Accuracy in the divide mode is only a little more complex. To
achieve division, the multiplier cell must be connected in the
feedback of the output op amp as shown in Figure 17. In this
configuration, the multiplier cell varies the closed loop gain of
the op amp in an inverse relationship to the denominator voltage.
Therefore, as the denominator is reduced, output offset, band-
width, and other multiplier cell errors are adversely affected.
The divide error and drift are then εm × 10 V/X1 − X2) where εm
represents multiplier full-scale error and drift, and (X1 − X2) is
the absolute value of the denominator.
Stable operation is maintained with capacitive loads to 1000 pF
in all modes, except the square root for which 50 pF is a safe
upper limit. Higher capacitive loads can be driven if a 100 Ω
resistor is connected in series with the output for isolation.
POWER SUPPLY CONSIDERATIONS
NONLINEARITY
Although the AD532 is tested and specified with ±15 V dc supplies,
it may be operated at any supply voltage from ±10 V to ±18 V
for the J and K versions, and ±10 V to ±22 V for the S version.
The input and output signals must be reduced proportionately
to prevent saturation; however, with supply voltages below ±15 V,
as shown in Figure 12. Because power supply sensitivity is not
dependent on external null networks as in other conventionally
nulled multipliers, the power supply rejection ratios are improved
from 3 to 40 times in the AD532.
Nonlinearity is easily measured in percent harmonic distortion.
The curves of Figure 6 and Figure 7 characterize output distortion
as a function of input signal level and frequency respectively,
with one input held at plus or minus 10 V dc. In Figure 7, the
sine wave amplitude is 20 V (p-p).
AC FEEDTHROUGH
AC feedthrough is a measure of the multiplier’s zero suppression.
With one input at zero, the multiplier output should be zero
regardless of the signal applied to the other input. Feedthrough
as a function of frequency for the AD532 is shown in Figure 8.
It is measured for the condition VX = 0, VY = 20 V (p-p) and
VY = 0, VX = 20 V (p-p) over the given frequency range. It
consists primarily of the second harmonic and is measured in
millivolts peak-to-peak.
NOISE CHARACTERISTICS
All AD532s are screened on a sampling basis to assure that output
noise will have no appreciable effect on accuracy. Typical spot
noise vs. frequency is shown in Figure 13.
Rev. D | Page 11 of 16
AD532
APPLICATIONS
The performance and ease of use of the AD532 is achieved
through the laser trimming of thin-film resistors deposited
directly on the monolithic chip. This trimming-on-the-chip
technique provides a number of significant advantages in terms
of cost, reliability and flexibility over conventional in-package
trimming of off-the-chip resistors mounted or deposited on a
hybrid substrate.
Squaring
Z
S
X
X
1
2
V
AD532
OUT
OUT
Y
Y
1
2
V
IN
10V
+V
+V
V
–V
OS
V
=
S
2
OUT
V
IN
(OPTIONAL)
20kΩ
–V
S
S
First and foremost, trimming on the chip eliminates the need
for a hybrid substrate and the additional bonding wires that are
required between the resistors and the multiplier chip. By trimming
more appropriate resistors on the AD532 chip itself, the second
input terminals that were once committed to external trimming
networks have been freed to allow fully differential operation at
both the X and Y inputs. Further, the requirement for an input
attenuator to adjust the gain at the Y input has been eliminated,
letting the user take full advantage of the high input impedance
properties of the input differential amplifiers. Therefore, the
AD532 offers greater flexibility for both algebraic computation
and transducer instrumentation applications.
Figure 16. Squarer Connection
The squaring circuit in Figure 16 is a simple variation of the
multiplier. The differential input capability of the AD532,
however, can be used to obtain a positive or negative output
response to the input, a useful feature for control applications,
as it might eliminate the need for an additional inverter
somewhere else.
Division
Z
10VZ
V
=
OUT
X
X
Z
X
X
1
2
AD532
OUT
V
OUT
Finally, provision for fine trimming the output voltage offset has
been included. This connection is optional, however, as the AD532
has been factory-trimmed for total performance as described in
the listed specifications.
Y
Y
1
+V
+V
–V
S
2
S
1kΩ
(SF)
47kΩ
2.2kΩ
10kΩ
20kΩ
(X )
REPLACING OTHER IC MULTIPLIERS
0
–V
S
S
Existing designs using IC multipliers that require external
trimming networks can be simplified using the pin-for-pin
replaceability of the AD532 by merely grounding the X2, Y2 and
Figure 17. Divider Connection
The AD532 can be configured as a two-quadrant divider by
connecting the multiplier cell in the feedback loop of the op
amp and using the Z terminal as a signal input, as shown in
Figure 17. It should be noted, however, that the output error is
given approximately by 10 V εm/(X1 − X2), where εm is the total
error specification for the multiply mode; and bandwidth by
fm × (X1 − X2)/10 V, where fm is the bandwidth of the multiplier.
Further, to avoid positive feedback, the X input is restricted to
negative values. Thus, for single-ended negative inputs (0 V to
−10 V), connect the input to X and the offset null to X2; for
single-ended positive inputs (0 V to +10 V), connect the input
to X2 and the offset null to X1. For optimum performance, gain
(S.F.) and offset (X0) adjustments are recommended as shown
and explained in Table 6.
V
OS terminals. The VOS terminal should always be grounded
when unused.
Multiplication
X
X
Z
1
2
AD532 OUT
V
OUT
Y
Y
1
2
V
OS
(X – X ) (Y – Y )
1
2
1
2
V
=
OUT
10V
(OPTIONAL)
+V
20kΩ
–V
S
S
Figure 15. Multiplier Connection
For operation as a multiplier, the AD532 should be connected
as shown in Figure 15. The inputs can be fed differentially to the
X and Y inputs, or single-ended by simply grounding the
unused input. Connect the inputs according to the desired
polarity in the output. The Z terminal is tied to the output to
close the feedback loop around the op amp (see Figure 1). The
offset adjust VOS is optional and is adjusted when both inputs
are zero volts to obtain zero out, or to buck out other system
offsets.
For practical reasons, the useful range in denominator input is
approximately 500 mV ≤ |(X1 − X2)| ≤ 10 V. The voltage offset
adjust (VOS), if used, is trimmed with Z at zero and (X1 − X2) at
full scale.
Rev. D | Page 12 of 16
AD532
10 V Z
obtain −1.0 V dc in the output, VOUT = −±
performance, gain (S.F.) and offset (X0) adjustments are recom-
mended as shown and explained in Table 6.
. For optimum
Table 6. Adjustment Procedure (Divider or Square Rooter)
Divider Square Rooter
Adjust for: With: Adjust: for:
VOUT VOUT
With:
Adjust
X
Z
Z
DIFFERENCE OF SQUARES
Scale Factor −10 V +10 V −10 V
X0 (Offset) −1 V +0.1 V −1 V
+10 V −10 V
+0.1 V −1 V
Z
X
X
X
Y
1
2
V
OUT
AD532
Repeat if required.
OUT
Y
Y
1
20kΩ
20kΩ
2
2
X
– Y
+V
V
–V
OS S
V
=
2
S
SQUARE ROOT
OUT
–Y
10V
Z
10kΩ
(OPTIONAL)
20kΩ
V
= 10VZ
OUT
AD741KH
X
Z
1
2
X
+V
–V
S
S
AD532
OUT
V
OUT
Y
Y
Figure 19. Differential of Squares Connection
1
2
+V
+V
–V
S
S
The differential input capability of the AD532 allows for the
algebraic solution of several interesting functions, such as the
difference of squares, X2 − Y2/10 V. As shown in Figure 19, the
AD532 is configured in the square mode, with a simple unity
gain inverter connected between one of the signal inputs (Y)
and one of the inverting input terminals (−YIN) of the multiplier.
The inverter should use precision (0.1%) resistors or be otherwise
trimmed for unity gain for best accuracy.
1kΩ
(SF)
47kΩ
2.2kΩ
10kΩ
20kΩ
(X )
0
–V
S
S
Figure 18. Square Rooter Connection
The connections for square root mode are shown in Figure 18.
Similar to the divide mode, the multiplier cell is connected in
the feedback of the op amp by connecting the output back to
both the X and Y inputs. The diode D1 is connected as shown to
prevent latch-up as ZIN approaches 0 volts. In this case, the VOS
adjustment is made with ZIN = +0.1 V dc, adjusting VOS to
Rev. D | Page 13 of 16
AD532
OUTLINE DIMENSIONS
0.005 (0.13) MIN
0.080 (2.03) MAX
8
14
0.310 (7.87)
1
0.220 (5.59)
7
PIN 1
0.100 (2.54)
BSC
0.320 (8.13)
0.290 (7.37)
0.765 (19.43) MAX
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.070 (1.78)
0.030 (0.76)
0.023 (0.58)
0.014 (0.36)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 20. 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]
(D-14)
Dimensions shown in inches and (millimeters)
0.200 (5.08)
0.075 (1.91)
REF
REF
0.100 (2.54)
0.064 (1.63)
0.100 (2.54) REF
0.095 (2.41)
0.015 (0.38)
MIN
0.075 (1.90)
3
19
18
20
4
8
0.028 (0.71)
0.022 (0.56)
1
0.358 (9.09)
0.342 (8.69)
SQ
0.358
0.011 (0.28)
0.007 (0.18)
R TYP
(9.09)
MAX
SQ
BOTTOM
VIEW
0.050 (1.27)
BSC
14
0.075 (1.91)
13
9
REF
45° TYP
0.088 (2.24)
0.054 (1.37)
0.055 (1.40)
0.045 (1.14)
0.150 (3.81)
BSC
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 21. 20-Terminal Ceramic Leadless Chip Carrier [LCC]
(E-20-1)
Dimensions shown in inches and (millimeters)
REFERENCE PLANE
0.500 (12.70)
0.160 (4.06)
MIN
0.185 (4.70)
0.165 (4.19)
0.110 (2.79)
6
7
5
8
0.021 (0.53)
0.016 (0.40)
0.115
(2.92)
BSC
4
0.045 (1.14)
0.025 (0.65)
9
3
10
0.034 (0.86)
0.025 (0.64)
2
1
0.230 (5.84)
BSC
BASE & SEATING PLANE
0.040 (1.02) MAX
0.050 (1.27) MAX
36° BSC
DIMENSIONS PER JEDEC STANDARDS MO-006-AF
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 22. 10-Pin Metal Header Package [TO-100]
(H-10)
Dimensions shown in inches and (millimeters)
Rev. D | Page 14 of 16
AD532
ORDERING GUIDE
Model1
Temperature Range
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
Package Description
Chip
14-Lead SBDIP
Package Option
AD532JCHIPS
AD532JD
AD532JDZ
AD532JH
AD532JHZ
AD532KD
AD532KDZ
AD532KH
AD532KHZ
AD532SCHIPS
AD532SD
AD532SD/883B
AD532SE/883B
AD532SH
D-14
D-14
H-10
H-10
D-14
D-14
H-10
H-10
14-Lead SBDIP
10-Pin Metal Header Package [TO-100]
10-Pin Metal Header Package [TO-100]
14-Lead SBDIP
14-Lead SBDIP
10-Pin Metal Header Package [TO-100]
10-Pin Metal Header Package [TO-100]
Chip
14-Lead SBDIP
14-Lead SBDIP
20-Terminal LCC
10-Pin Metal Header Package [TO-100]
10-Pin Metal Header Package [TO-100]
0°C to 70°C
−55°C to +125°C
−55°C to +125°C
−55°C to +125°C
−55°C to +125°C
−55°C to +125°C
−55°C to +125°C
D-14
D-14
E-20-1
H-10
H-10
AD532SH/883B
1 Z = RoHS Compliant Part.
Rev. D | Page 15 of 16
AD532
NOTES
©2001–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00502-0-2/11(D)
Rev. D | Page 16 of 16
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