AD7988-1 [ADI]
16-Bit Lower Power; 16位低功耗
| 型号： | AD7988-1 |
| 厂家： | 
ADI |
| 描述： | 16-Bit Lower Power |
| 文件： | 总24页 (文件大小：463K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16-Bit Lower Power
PulSAR ADCs in MSOP/LFCSP (QFN)
Data Sheet
AD7988-1/AD7988-5
FEATURES
GENERAL DESCRIPTION
Low power dissipation
AD7988-5: 3.5 mW @ 500 kSPS
AD7988-1: 700 µW @ 100 kSPS
16-bit resolution with no missing codes
Throughput: 100 kSPS/500 kSPS options
INL: 0.6 LSB typical, 1.25 LSB maximum
SINAD: 91.5 dB @ 10 kHz
The AD7988-1/AD7988-5 are 16-bit, successive approximation,
analog-to-digital converters (ADC) that operate from a single
power supply, VDD. The AD7988-1 offers a 100 kSPS throughput,
and the AD7988-5 offers a 500 kSPS throughput. They are low
power, 16-bit sampling ADCs with a versatile serial interface
port. On the CNV rising edge, they sample an analog input,
IN+, between 0 V to VREF with respect to a ground sense, IN−.
The reference voltage, REF, is applied externally and can be set
independent of the supply voltage, VDD.
THD: −114 dB @ 10 kHz
Pseudo differential analog input range
0 V to VREF with VREF from 2.5 V to 5.5 V
Any input range and easy to drive with the ADA4841-1
No pipeline delay
Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V
logic interface
The SPI-compatible serial interface also features the ability to
daisy-chain several ADCs on a single 3-wire bus using the SDI
input. It is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic using
the separate supply, VIO.
The AD7988-1/AD7988-5 generics are housed in a 10-lead
MSOP or a 10-lead LFCSP (QFN) with operation specified
from −40°C to +125°C.
SPI-/QSPI-/MICROWIRE™-/DSP-compatible serial interface
Daisy-chain multiple ADCs
10-lead MSOP and 10-lead, 3 mm × 3 mm LFCSP (QFN),
same space as SOT-23
Table 1. MSOP, LFCSP (QFN) 14-/16-/18-Bit PulSAR® ADCs
Wide operating temperature range: −40°C to +125°C
400 kSPS to
500 kSPS
AD76902
≥1000
kSPS
AD79822 ADA4941-1
AD79842 ADA4841-1
ADA4941-1
Bits
100 kSPS
250 kSPS
ADC Driver
APPLICATIONS
181
AD76912
Battery-powered equipment
Low power data acquisition systems
Portable medical instruments
ATE equipment
Data acquisitions
Communications
161
163
AD7684
AD76872
AD76882
AD76932
AD76862
AD7988-52
ADA4841-1
AD7680
AD7683
AD7988-12
AD7940
AD76852
AD7694
AD79802 ADA4841-1
ADA4841-1
ADA4841-1
143
AD79422
AD79462
ADA4841-1
1 True differential.
2 Pin-for-pin compatible.
3 Pseudo differential.
TYPICAL APPLICATION DIAGRAM
2.5V TO 5V 2.5V
VIO
SDI
1.8V TO 5.5V
REF VDD
0V TO V
REF
IN+ AD7988-1/ SCK
3- OR 4-WIRE INTERFACE
(SPI, DAISY CHAIN, CS)
IN– AD7988-5
SDO
GND
CNV
Figure 1.
Rev. B
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2012 Analog Devices, Inc. All rights reserved.
AD7988-1/AD7988-5
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Analog Inputs ............................................................................. 16
Driver Amplifier Choice ........................................................... 16
Voltage Reference Input ............................................................ 17
Power Supply............................................................................... 17
Digital Interface.......................................................................... 17
Applications....................................................................................... 1
General Description......................................................................... 1
Typical Application Diagram.......................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Terminology ...................................................................................... 9
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 14
Circuit Information.................................................................... 14
Converter Operation.................................................................. 14
Typical Connection Diagram ................................................... 15
CS
CS
Mode, 3-Wire........................................................................ 18
Mode 4-Wire......................................................................... 19
Chain Mode ................................................................................ 20
Applications Information.............................................................. 21
Interfacing to Blackfin® DSP..................................................... 21
Layout .......................................................................................... 21
Evaluating the Performance of the AD7988-x........................ 21
Outline Dimensions....................................................................... 22
Ordering Guide .......................................................................... 23
REVISION HISTORY
5/12—Rev. A to Rev. B
Changes to Table 3.............................................................................4
Updated Outline Dimensions ........................................................22
2/12—Rev. 0 to Rev. A
Added LFCSP Thermal Impedance Values................................... 7
Updated Outline Dimensions ....................................................... 23
Changes to Ordering Guide .......................................................... 23
2/12—Revision 0: Initial Version
Rev. B | Page 2 of 24
Data Sheet
AD7988-1/AD7988-5
SPECIFICATIONS
VDD = 2.5 V, VIO = 2.3 V to 5.5 V, V REF = 5 V, T A = –40°C to +125°C, unless otherwise noted.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
RESOLUTION
16
Bits
ANALOG INPUT
Voltage Range
Absolute Input Voltage
IN+ − IN−
IN+
IN−
0
−0.1
−0.1
VREF
VREF + 0.1
+0.1
V
V
V
Analog Input CMRR
Leakage Current at 25°C
Input Impedance
fIN = 1 kHz
Acquisition phase
60
1
dB
nA
See the Analog Inputs section
ACCURACY
No Missing Codes
Differential Linearity Error
16
−0.9
Bits
VREF = 5 V
VREF = 2.5 V
VREF = 5 V
VREF = 2.5 V
VREF = 5 V
VREF = 2.5 V
0.4
0.55
0.6
0.65
0.6
1.0
2
0.35
0.08
0.54
0.1
+0.9
LSB1
LSB1
LSB1
LSB1
LSB1
LSB1
LSB1
ppm/°C
mV
Integral Linearity Error
Transition Noise
−1.25
−0.5
+1.25
2
Gain Error, TMIN to TMAX
Gain Error Temperature Drift
Zero Error, TMIN to TMAX
Zero Temperature Drift
Power Supply Sensitivity
2
+0.5
ppm/°C
LSB1
VDD = 2.5 V ± 5%
THROUGHPUT
AD7988-1
Conversion Rate
VIO ≥ 2.3 V up to 85°C, VIO ≥ 3.3 V above 85°C up to
125°C
Full-scale step
0
0
100
500
kSPS
ns
Transient Response
AD7988-5
Conversion Rate
VIO ≥ 2.3 V up to 85°C, VIO ≥ 3.3 V above 85°C up to
125°C
Full-scale step
500
400
kSPS
ns
Transient Response
AC ACCURACY
Dynamic Range
VREF = 5 V
VREF = 2.5 V
fO = 10 kSPS
fIN = 10 kHz, VREF = 5 V
fIN = 10 kHz, VREF = 2.5 V
fIN = 10 kHz
fIN = 10 kHz
fIN = 10 kHz, VREF = 5 V
fIN = 10 kHz, VREF = 2.5 V
92
87
111
91
86.5
−110
−114
91.5
87.0
dB3
dB3
dB3
dB3
dB3
dB3
dB3
dB3
dB3
Oversampled Dynamic Range
Signal-to-Noise Ratio, SNR
90
Spurious-Free Dynamic Range, SFDR
Total Harmonic Distortion, THD
Signal-to-(Noise + Distortion), SINAD
1 LSB means least significant bit. With the 5 V input range, 1 LSB is 76.3 µV.
2 See the Terminology section. These specifications include full temperature range variation, but not the error contribution from the external reference.
3 All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
Rev. B | Page 3 of 24
AD7988-1/AD7988-5
Data Sheet
VDD = 2.5 V, VIO = 2.3 V to 5.5 V, V REF = 5 V, T A = –40°C to +125°C, unless otherwise noted.
Table 3.
Parameter
REFERENCE
Voltage Range
Load Current
SAMPLING DYNAMICS
−3 dB Input Bandwidth
Aperture Delay
DIGITAL INPUTS
Logic Levels
VIL
Test Conditions/Comments
VREF = 5 V
Min
Typ
Max
Unit
2.4
5.1
V
µA
250
10
2.0
MHz
ns
VDD = 2.5 V
VIO > 3 V
VIO > 3 V
VIO ≤ 3 V
VIO ≤ 3 V
–0.3
0.7 × VIO
–0.3
0.9 × VIO
−1
−1
0.3 × VIO
VIO + 0.3
0.1 × VIO
VIO + 0.3
+1
V
V
V
V
µA
µA
VIH
VIL
VIH
IIL
IIH
+1
DIGITAL OUTPUTS
Data Format
Pipeline Delay
Serial 16 bits straight binary
Conversion results available immediately
after completed conversion
VOL
VOH
ISINK = 500 µA
ISOURCE = −500 µA
0.4
V
V
VIO − 0.3
POWER SUPPLIES
VDD
VIO
2.375
2.3
2.5
2.625
5.5
V
V
Specified performance
VIO Range
1.8
5.5
V
nA
µW
Standby Current1, 2
VDD and VIO = 2.5 V, 25°C
10 kSPS throughput
0.35
70
AD7988-1 Power Dissipation
100 kSPS throughput
700
µW
1
5
mW
mW
nJ/sample
AD7988-5 Power Dissipation
Energy per Conversion
TEMPERATURE RANGE
500 kSPS throughput
3.5
7.0
Specified Performance
TMIN to TMAX
−40
+125
°C
1 With all digital inputs forced to VIO or GND as required.
2 During the acquisition phase.
Rev. B | Page 4 of 24
Data Sheet
AD7988-1/AD7988-5
TIMING SPECIFICATIONS
VDD = 2.37 V to 2.63 V, VIO = 3.3 V to 5.5 V, −40°C to +125°C unless otherwise stated. See Figure 2 and Figure 3 for load conditions.
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
AD7988-1
Throughput Rate
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
100
9.5
kHz
μs
ns
tCONV
tACQ
tCYC
500
10
Time Between Conversions
μs
AD7988-5
Throughput Rate
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
500
1.6
kHz
μs
ns
μs
ns
tCONV
tACQ
tCYC
tCNVH
tSCK
400
2
500
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
10.5
12
13
ns
ns
ns
ns
15
SCK Period (Chain Mode)
tSCK
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
11.5
13
14
16
4.5
4.5
3
ns
ns
ns
ns
ns
ns
ns
tSCKL
tSCKH
tHSDO
tDSDO
9.5
11
12
14
ns
ns
ns
ns
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
VIO Above 3 V
tEN
10
15
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VIO Above 2.3V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (Chain Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
tDIS
tSSDICNV
tHSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
5
2
0
5
5
2
3
Rev. B | Page 5 of 24
AD7988-1/AD7988-5
Data Sheet
500µA
I
OL
1.4V
TO SDO
C
L
20pF
500µA
I
OH
Figure 2. Load Circuit for Digital Interface Timing
1
Y% VIO
1
X% VIO
tDELAY
tDELAY
2
2
V
V
V
IH
IH
2
2
V
IL
IL
1
2
FOR VIO ≤ 3.0V, X = 90 AND Y = 10; FOR VIO > 3.0V X = 70, AND Y = 30.
MINIMUM V AND MAXIMUM V USED. SEE DIGITAL INPUTS
IH
IL
SPECIFICATIONS IN TABLE 3.
Figure 3. Voltage Levels for Timing
Rev. B | Page 6 of 24
Data Sheet
AD7988-1/AD7988-5
ABSOLUTE MAXIMUM RATINGS
Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Analog Inputs
IN+,1 IN−1 to GND
Supply Voltage
REF, VIO to GND
VDD to GND
VDD to VIO
−0.3 V to VREF + 0.3 V or 130 mA
−0.3 V to +6 V
−0.3 V to +3 V
+3 V to −6 V
Digital Inputs to GND
Digital Outputs to GND
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
10-Lead MSOP
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
−65°C to +125°C
150°C
ESD CAUTION
200°C/W
80°C/W
10-Lead LFCSP
θJC Thermal Impedance
10-Lead MSOP
44°C/W
10-Lead LFCSP
15°C/W
Reflow Soldering
JEDEC Standard (J-STD-020)
1 See the Analog Inputs section.
Rev. B | Page 7 of 24
AD7988-1/AD7988-5
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
REF
VDD
IN+
1
2
3
4
5
10 VIO
AD7988-1/
AD7988-5
TOP VIEW
(Not to Scale)
9
8
7
6
SDI
SCK
SDO
CNV
REF
VDD
IN+
1
2
3
4
5
10 VIO
IN–
AD7988-1/
AD7988-5
TOP VIEW
(Not to Scale)
9
8
7
6
SDI
GND
SCK
SDO
CNV
IN–
NOTES
GND
1. THE EXPOSED PAD CAN BE CONNECTED TO GND.
Figure 4. 10-Lead MSOP Pin Configuration
Figure 5. 10-Lead LFCSP (QFN) Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1
REF
AI
Reference Input Voltage. The VREF range is from 2.4 V to 5.1 V. It is referred to the GND pin. The GND pin
should be decoupled closely to the REF pin with a 10 µF capacitor.
2
3
VDD
IN+
P
AI
Power Supply.
Analog Input. It is referred to IN−. The voltage range, for example, the difference between IN+ and IN−, is
0 V to VREF
.
4
5
6
IN−
GND
CNV
AI
P
DI
Analog Input Ground Sense. Connect to the analog ground plane or to a remote sense ground.
Power Supply Ground.
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and
selects the interface mode of the part: chain mode or CS mode. In CS mode, the SDO pin is enabled when
CNV is low. In chain mode, the data should be read when CNV is high.
7
8
9
SDO
SCK
SDI
DO
DI
DI
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as
follows:
Chain mode is selected if this pin is low during the CNV rising edge. In this mode, SDI is used as a data
input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data
level on SDI is output on SDO with a delay of 16 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable
the serial output signals when low.
10
VIO
EP
P
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V,
or 5 V).
Exposed Pad. The exposed pad can be connected to GND.
1AI = analog input, DI = digital input, DO = digital output, and P = power.
Rev. B | Page 8 of 24
Data Sheet
AD7988-1/AD7988-5
TERMINOLOGY
Effective Resolution
Integral Nonlinearity Error (INL)
Effective resolution is calculated as
Effective Resolution = log2(2N/RMS Input Noise)
and is expressed in bits.
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 30).
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in dB. It is measured
with a signal at −60 dBFS to include all noise sources and DNL
artifacts.
Offset Error
The first transition should occur at a level ½ LSB above analog
ground (38.1 µV for the 0 V to 5 V range). The offset error is
the deviation of the actual transition from that point.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in dB.
Gain Error
The last transition (from 111 … 10 to 111 … 11) should
occur for an analog voltage 1½ LSB below the nominal full
scale (4.999886 V for the 0 V to 5 V range). The gain error is
the deviation of the actual level of the last transition from the
ideal level after the offset is adjusted out.
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in dB.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Aperture Delay
Effective Number of Bits (ENOB)
Aperture delay is the measure of the acquisition performance. It
is the time between the rising edge of the CNV input and when
the input signal is held for a conversion.
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD by the following formula:
ENOB = (SINADdB − 1.76)/6.02
Transient Response
and is expressed in bits.
Transient response is the time required for the ADC to
accurately acquire its input after a full-scale step function is
applied.
Noise-Free Code Resolution
Noise-free code resolution is the number of bits beyond which
it is impossible to distinctly resolve individual codes. It is
calculated as
Noise-Free Code Resolution = log2(2N/Peak-to-Peak Noise)
and is expressed in bits.
Rev. B | Page 9 of 24
AD7988-1/AD7988-5
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 2.5 V, VREF = 5.0 V, VIO = 3.3 V, unless otherwise noted.
0
0
–20
fS = 500kSPS
fS = 100kSPS
fIN = 10kHz
SNR = 86.7dB
THD = –110.4dB
SFDR = 103.9dB
SINAD = 86.6dB
fIN = 10kHz
–20
–40
SNR = 91.17dB
THD = –113.63dB
SFDR = 110.30dB
SINAD = 91.15dB
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
0
50
100
150
200
250
0
10
20
30
40
50
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 6. AD7988-5 FFT Plot, VREF = 5 V
Figure 9. AD7988-1 FFT Plot, VREF = 2.5 V
0
–20
1.25
1.00
0.75
0.50
0.25
0
POSITIVE INL: +0.40 LSB
NEGATIVE INL: –0.35 LSB
fS = 500kSPS
fIN = 10kHz
SNR = 86.8dB
THD = –111.4dB
SFDR = 105.9dB
SINAD = 86.8dB
–40
–60
–80
–100
–120
–140
–160
–180
–0.25
–0.50
–0.75
–1.00
–1.25
0
16384
32768
CODE
49152
65536
0
50
100
150
200
250
FREQUENCY (kHz)
Figure 10. Integral Nonlinearity vs. Code, VREF = 5 V
Figure 7. AD7988-5 FFT Plot, VREF = 2.5 V
1.25
1.00
0
POSITIVE INL: +0.45 LSB
NEGATIVE INL: –0.29 LSB
fS = 100kSPS
fIN = 10kHz
–20
–40
SNR = 91.09dB
0.75
THD = –113.12dB
SFDR = 110.30dB
SINAD = 91.05dB
0.50
0.25
–60
–80
0
–100
–120
–140
–160
–180
–0.25
–0.50
–0.75
–1.00
–1.25
0
16384
32768
CODE
49152
65536
0
10
20
30
40
50
FREQUENCY (kHz)
Figure 11. Integral Nonlinearity vs. Code, VREF = 2.5 V
Figure 8. AD7988-1 FFT Plot, VREF = 5 V
Rev. B | Page 10 of 24
Data Sheet
AD7988-1/AD7988-5
1.00
0.75
0.50
0.25
0
60k
50k
40k
30k
20k
10k
0
POSITIVE INL: +0.18 LSB
NEGATIVE INL: –0.21 LSB
50970
45198
–0.25
–0.50
–0.75
18848
12424
1217
2290
94
30
0
0
1
0
0
–1.00
0
7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005 8006
CODE IN HEX
16384
32768
CODE
49152
65536
Figure 15. Histogram of a DC Input at the Code Transition, VREF = 2.5 V
Figure 12. Differential Nonlinearity vs. Code, VREF = 5 V
1.00
0.75
0.50
0.25
0
100
16
15
14
POSITIVE INL: +0.25 LSB
NEGATIVE INL: –0.22 LSB
SNR
SINAD
ENOB
95
90
–0.25
–0.50
–0.75
–1.00
85
80
13
12
0
16384
32768
CODE
49152
65536
2.25
2.75
3.25
3.75
4.25
4.75
5.25
REFERENCE VOLTAGE (V)
Figure 13. Differential Nonlinearity vs. Code, VREF = 2.5 V
Figure 16. SNR, SINAD, and ENOB vs. Reference Voltage
180k
160k
140k
120k
100k
80k
60k
40k
20k
0
60k
162595
53412
50k
40k
30k
20k
10k
0
37417
31540
52720
42731
7285
5807
1291
852
590
512
19
29
11
0
0
22
2
0
0
0
0
0
0
0
8003 8004 8005 8006 8007 8008 8009 800A 800B 800C 800D 800E 800F
CODE IN HEX
7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005 8006
CODE IN HEX
Figure 14. Histogram of a DC Input at the Code Center, VREF = 5 V
Figure 17. Histogram of a DC Input at the Code Center, VREF = 2.5 V
Rev. B | Page 11 of 24
AD7988-1/AD7988-5
Data Sheet
95
93
91
89
87
85
95
94
93
92
91
90
89
88
87
86
85
–55
–35
–15
5
25
45
65
85
105
125
2.625
2.625
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
TEMPERATURE (°C)
INPUT LEVEL (dB OF FULL SCALE)
Figure 21. SNR vs. Temperature
Figure 18. SNR vs. Input Level
–95
–100
–105
–110
–115
115
110
105
100
95
0.7
0.6
0.5
0.4
0.3
0.2
I
VDD
SFDR
I
REF
THD
I
VIO
–120
–125
90
85
0.1
0
2.375
2.425
2.475
2.525
2.575
2.25
2.75
3.25
3.75
4.25
4.75
5.25
VDD VOLTAGE (V)
REFERENCE VOLTAGE (V)
Figure 22. Operating Currents vs. Supply (AD7988-5)
Figure 19. THD, SFDR vs. Reference Voltage
100
95
90
85
80
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
I
VDD
I
REF
I
VIO
2.375
2.425
2.475
2.525
2.575
10
100
1k
VDD VOLTAGE (V)
FREQUENCY (kHz)
Figure 20. SINAD vs. Frequency
Figure 23. Operating Currents vs. Supply (AD7988-1)
Rev. B | Page 12 of 24
Data Sheet
AD7988-1/AD7988-5
–85
0.14
0.12
0.10
008
I
VDD
–90
–95
–100
–105
–110
–115
–120
0.06
I
REF
0.04
0.02
0
I
VIO
–125
10
–55
–35
–15
5
25
45
65
85
105
125
100
1k
TEMPERATURE (°C)
FREQUENCY (kHz)
Figure 24. THD vs. Frequency
Figure 27. Operating Currents vs. Temperature (AD7988-1)
8
–110
–112
–114
–116
–118
–120
7
6
5
4
3
2
1
I
+ I
VIO
VDD
0
–55
–35
–15
5
25
45
65
85
105
125
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 25. THD vs. Temperature
Figure 28. Power-Down Currents vs. Temperature
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
I
VDD
I
REF
I
VIO
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
Figure 26. Operating Currents vs. Temperature (AD7988-5)
Rev. B | Page 13 of 24
AD7988-1/AD7988-5
Data Sheet
THEORY OF OPERATION
IN+
SWITCHES CONTROL
MSB
LSB
SW+
32,768C 16,384C
4C
4C
2C
2C
C
C
C
C
BUSY
REF
CONTROL
COMP
LOGIC
GND
OUTPUT CODE
32,768C 16,384C
MSB
LSB
SW–
CNV
IN–
Figure 29. ADC Simplified Schematic
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to GND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Therefore, the capacitor arrays are used as sampling capacitors
and acquire the analog signal on the IN+ and IN− inputs. When
the acquisition phase is completed and the CNV input goes high, a
conversion phase is initiated. When the conversion phase begins,
SW+ and SW− are opened first. The two capacitor arrays are then
disconnected from the inputs and connected to the GND input.
Therefore, the differential voltage between the IN+ and IN−
inputs captured at the end of the acquisition phase are applied
to the comparator inputs, causing the comparator to become
unbalanced. By switching each element of the capacitor array
between GND and REF, the comparator input varies by binary
weighted voltage steps (VREF/2, VREF/4 … VREF/65,536). The
control logic toggles these switches, starting with the MSB, to
bring the comparator back into a balanced condition. After the
completion of this process, the part returns to the acquisition phase
and the control logic generates the ADC output code.
CIRCUIT INFORMATION
The AD7988-1/AD7988-5 devices are fast, low power, single-
supply, precise 16-bit ADCs that use a successive approximation
architecture.
The AD7988-1 is capable of converting 100,000 samples per
second (100 kSPS), whereas the AD7988-5 is capable of a
throughput of 500 kSPS, and they power down between
conversions. When operating at 10 kSPS, for example, the
ADC consumes 70 µW typically, ideal for battery-powered
applications.
The AD7988-x provides the user with on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple multiplexed channel applications.
The AD7988-x can be interfaced to any 1.8 V to 5 V digital logic
family. It is housed in a 10-lead MSOP or a tiny 10-lead LFCSP
(QFN) that combines space savings and allows flexible
configurations.
CONVERTER OPERATION
Because the AD7988-x has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
The AD7988-x is a successive approximation ADC based on a
charge redistribution DAC. Figure 29 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary weighted capacitors, which are
connected to the two comparator inputs.
Rev. B | Page 14 of 24
Data Sheet
AD7988-1/AD7988-5
Transfer Functions
Table 7. Output Codes and Ideal Input Voltages
Analog Input
The ideal transfer characteristic for the AD7988-x is shown in
Figure 30 and Table 7.
Description
VREF = 5 V
Digital Output Code (Hex)
FSR – 1 LSB
4.999924 V
FFFF1
8001
8000
7FFF
0001
00002
Midscale + 1 LSB 2.500076 V
Midscale 2.5 V
Midscale – 1 LSB 2.499924 V
–FSR + 1 LSB
–FSR
111 ... 111
111 ... 110
111 ... 101
76.3 µV
0 V
1 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND).
2 This is also the code for an underranged analog input (VIN+ − VIN− below VGND).
TYPICAL CONNECTION DIAGRAM
Figure 31 shows an example of the recommended connection
diagram for the AD7988-x when multiple supplies are available.
000 ... 010
000 ... 001
000 ... 000
–FSR
–FSR + 1LSB
+FSR – 1 LSB
–FSR + 0.5LSB
+FSR – 1.5 LSB
ANALOG INPUT
Figure 30. ADC Ideal Transfer Function
1
V+
REF
2.5V
2
10µF
100nF
V+
1.8V TO 5.5V
100nF
20Ω
REF
VDD
VIO
0V TO V
REF
3
IN+
IN–
SDI
SCK
SDO
CNV
2.7nF
AD7988-1/
AD7988-5
V–
5
3- OR 4-WIRE INTERFACE
4
GND
1
2
3
4
5
SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION.
IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
SEE THE DRIVER AMPLIFIER CHOICE SECTION.
OPTIONAL FILTER. SEE THE ANALOG INPUTS SECTION.
SEE THE DIGITAL INTERFACE SECTION FOR THE MOST CONVENIENT INTERFACE MODE.
C
REF
Figure 31. Typical Application Diagram with Multiple Supplies
Rev. B | Page 15 of 24
AD7988-1/AD7988-5
Data Sheet
ANALOG INPUTS
DRIVER AMPLIFIER CHOICE
Figure 32 shows an equivalent circuit of the input structure of
the AD7988-x.
Although the AD7988-x is easy to drive, the driver amplifier
needs to meet the following requirements:
The two diodes, D1 and D2, provide ESD protection for the
analog inputs, IN+ and IN−. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more
than 0.3 V, because this causes these diodes to become forward-
biased and start conducting current. These diodes can handle a
forward-biased current of 130 mA maximum. For instance,
these conditions may eventually occur when the input buffer’s
supplies are different from VDD. In such a case (for example, an
input buffer with a short circuit), the current limitation can be
used to protect the part.
•
The noise generated by the driver amplifier must be kept as
low as possible to preserve the SNR and transition noise
performance of the AD7988-x. The noise coming from the
driver is filtered by the AD7988-x analog input circuit’s
one-pole, low-pass filter made by RIN and CIN or by the
external filter, if one is used. Because the typical noise of
the AD7988-x is 47.3 µV rms, the SNR degradation due to
the amplifier is
47.3
REF
SNRLOSS = 20 log
π
47.32 + f−3dB (NeN )2
D1
2
C
IN
R
IN
IN+
OR IN–
where:
–3dB is the input bandwidth in MHz of the AD7988-x
C
D2
PIN
f
GND
(10 MHz) or the cutoff frequency of the input filter, if
one is used.
Figure 32. Equivalent Analog Input Circuit
N is the noise gain of the amplifier (for example, 1 in buffer
configuration).
eN is the equivalent input noise voltage of the op amp,
The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these
differential inputs, signals common to both inputs are rejected.
in nV/√Hz.
During the acquisition phase, the impedance of the analog
inputs (IN+ and IN−) can be modeled as a parallel combination of
Capacitor CPIN and the network formed by the series connection of
•
•
For ac applications, the driver should have a THD
performance commensurate with the AD7988-x.
For multichannel multiplexed applications, the driver ampli-
fier and the AD7988-x analog input circuit must settle for
a full-scale step onto the capacitor array at a 16-bit level
(0.0015%, 15 ppm). In the amplifier data sheet, settling at
0.1% to 0.01% is more commonly specified. This may
differ significantly from the settling time at a 16-bit level
and should be verified prior to driver selection.
RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically
400 Ω and is a lumped component made up of serial resistors
and the on resistance of the switches. CIN is typically 30 pF and
is mainly the ADC sampling capacitor. During the conversion
phase, when the switches are opened, the input impedance is
limited to CPIN. RIN and CIN make a one-pole, low-pass filter that
reduces undesirable aliasing effects and limits the noise.
Table 8. Recommended Driver Amplifiers
When the source impedance of the driving circuit is low, the
AD7988-x can be driven directly. Large source impedances
significantly affect the ac performance, especially THD. The dc
performances are less sensitive to the input impedance. The
maximum source impedance depends on the amount of THD
that can be tolerated. The THD degrades as a function of the
source impedance and the maximum input frequency.
Amplifier
ADA4841-1
AD8021
AD8022
OP184
Typical Application
Very low noise, small size, and low power
Very low noise and high frequency
Low noise and high frequency
Low power, low noise, and low frequency
5 V single-supply, low noise
AD8655
AD8605, AD8615
5 V single-supply, low power
Rev. B | Page 16 of 24
Data Sheet
AD7988-1/AD7988-5
To ensure optimum performance, VDD should be roughly half
of REF, the voltage reference input. For example, if REF is 5.0 V,
VDD should be set to 2.5 V ( 5%). If REF = 2.5V, and VDD =
2.5 V, performance is degraded as can be seen in Table 2.
VOLTAGE REFERENCE INPUT
The AD7988-x voltage reference input, REF, has a dynamic
input impedance and should therefore be driven by a low
impedance source with efficient decoupling between the REF
and GND pins, as explained in the Layout section.
The AD7988-x powers down automatically at the end of each
conversion phase.
When REF is driven by a very low impedance source, for example,
a reference buffer using the AD8031 or the AD8605, a ceramic
chip capacitor is appropriate for optimum performance.
DIGITAL INTERFACE
Although the AD7988-x has a reduced number of pins, it offers
flexibility in its serial interface modes.
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For example, a 22 µF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR43x reference.
CS
The AD7988-x, when in
mode, is compatible with SPI, QSPI™,
and digital hosts. This interface can use either a 3-wire or 4-wire
interface. A 3-wire interface using the CNV, SCK, and SDO
signals minimizes wiring connections and is useful, for
instance, in isolated applications. A 4-wire interface using the
SDI, CNV, SCK, and SDO signals allows CNV, which initiates
the conversions, to be independent of the readback timing
(SDI). This is useful in low jitter sampling or simultaneous
sampling applications.
If desired, a reference-decoupling capacitor value as small as
2.2 µF can be used with a minimal impact on performance,
especially DNL.
Regardless, there is no need for an additional lower value ceramic
decoupling capacitor (for example, 100 nF) between the REF
and GND pins.
The AD7988-x, when in chain mode, provides a daisy-chain
feature using the SDI input for cascading multiple ADCs on a
single data line, similar to a shift register.
POWER SUPPLY
The AD7988-x uses two power supply pins: a core supply, VDD,
and a digital input/output interface supply, VIO. VIO allows
direct interface with any logic between 1.8 V and 5.0 V. To
reduce the number of supplies needed, VIO and VDD can be
tied together. The AD7988-x is independent of power supply
sequencing between VIO and VDD. Additionally, it is very
insensitive to power supply variations over a wide frequency
range, as shown in Figure 33.
The mode in which the part operates depends on the SDI level
CS
when the CNV rising edge occurs.
mode is selected if SDI is
high, and chain mode is selected if SDI is low. The SDI hold
time is such that when SDI and CNV are connected together,
the chain mode is selected.
The user must time out the maximum conversion time prior to
readback.
80
75
70
65
60
55
1
10
100
1k
FREQUENCY (kHz)
Figure 33. PSRR vs. Frequency
Rev. B | Page 17 of 24
AD7988-1/AD7988-5
Data Sheet
When CNV goes low, the MSB is output onto SDO. The remaining
data bits are then clocked by subsequent SCK falling edges. The
data is valid on both SCK edges. Although the rising edge can
be used to capture the data, a digital host using the SCK falling
edge allows a faster reading rate, provided that it has an acceptable
hold time. After the 16th SCK falling edge or when CNV goes
high, whichever is earlier, SDO returns to high impedance.
CS MODE, 3-WIRE
This mode is typically used when a single AD7988-x is
connected to an SPI-compatible digital host. The connection
diagram is shown in Figure 34, and the corresponding timing is
given in Figure 35.
With SDI tied to VIO, a rising edge on CNV initiates a conver-
CS
sion, selects the
mode, and forces SDO to high impedance.
When the conversion is complete, the AD7988-x enters the
acquisition phase and powers down.
CONVERT
DIGITAL HOST
DATA IN
CNV
VIO
AD7988-1/
AD7988-5
SDI
SDO
SCK
CLK
CS
Figure 34. 3-Wire Mode Connection Diagram
SDI = 1
tCYC
tCNVH
CNV
tCONV
tACQ
ACQUISITION
CONVERSION
ACQUISITION
tSCK
tSCKL
1
2
3
14
15
16
SCK
SDO
tHSDO
tSCKH
tDIS
tEN
tDSDO
D15
D14
D13
D1
D0
CS
Figure 35. 3-Wire Mode Serial Interface Timing (SDI High)
Rev. B | Page 18 of 24
Data Sheet
AD7988-1/AD7988-5
When the conversion is complete, the AD7988-x enters the
acquisition phase and powers down. Each ADC result can
be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are then
clocked by subsequent SCK falling edges. The data is valid on
both SCK edges. Although the rising edge can be used to capture
the data, a digital host using the SCK falling edge allows a faster
reading rate, provided that it has an acceptable hold time. After
the 16th SCK falling edge or when SDI goes high, whichever is
earlier, SDO returns to high impedance and another AD7988-x
can be read.
CS MODE 4-WIRE
This mode is typically used when multiple AD7988-x devices
are connected to an SPI-compatible digital host.
A connection diagram example using two AD7988-x devices is
shown in Figure 36, and the corresponding timing is given in
Figure 37.
With SDI high, a rising edge on CNV initiates a conversion,
CS
selects the
mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
time elapses and then held high for the maximum conversion time.
CS2
CS1
CONVERT
CNV
CNV
DIGITAL HOST
AD7988-1/
AD7988-5
AD7988-1/
AD7988-5
SDI
SDO
SDI
SDO
SCK
SCK
DATA IN
CLK
CS
Figure 36. 4-Wire Mode Connection Diagram
tCYC
CNV
tCONV
tACQ
ACQUISITION
tSSDICNV
CONVERSION
ACQUISITION
SDI (CS1)
tHSDICNV
SDI (CS2)
SCK
tSCK
tSCKL
1
2
3
14
15
16
17
18
30
31
32
tHSDO
tSCKH
tEN
tDIS
tDSDO
SDO
D15
D14
D13
D1
D0
D15
D14
D1
D0
CS
Figure 37. 4-Wire Mode Serial Interface Timing
Rev. B | Page 19 of 24
AD7988-1/AD7988-5
Data Sheet
phase and the subsequent data readback. When the conversion
is complete, the MSB is output onto SDO and the AD7988-x
enters the acquisition phase and powers down. The remaining
data bits stored in the internal shift register are clocked by
subsequent SCK falling edges. For each ADC, SDI feeds the
input of the internal shift register and is clocked by the SCK
falling edge. Each ADC in the chain outputs its data MSB first,
and 16 × N clocks are required to read back the N ADCs. The
data is valid on both SCK edges. Although the rising edge can
be used to capture the data, a digital host using the SCK falling
edge allows a faster reading rate and, consequently, more
AD7988-x devices in the chain, provided that the digital host
has an acceptable hold time. The maximum conversion rate
may be reduced due to the total readback time.
CHAIN MODE
This mode can be used to daisy-chain multiple AD7988-x
devices on a 3-wire serial interface. This feature is useful for
reducing component count and wiring connections, for example,
in isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7988-x devices is
shown in Figure 38, and the corresponding timing is given in
Figure 39.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion and selects the chain
mode. In this mode, CNV is held high during the conversion
CONVERT
CNV
CNV
DIGITAL HOST
DATA IN
AD7988-1/
AD7988-5
AD7988-1/
AD7988-5
SDI
SDO
SDI
SDO
A
SCK
B
SCK
CLK
Figure 38. Chain Mode Connection Diagram
SDI = 0
A
tCYC
CNV
tCONV
tACQ
CONVERSION
ACQUISITION
ACQUISITION
tSCK
tSCKL
tSSCKCNV
SCK
1
2
3
A
B
14
15
16
17
18
30
31
32
tSSDISCK
tSCKH
tHSCKCNV
tHSDISCK
tEN
SDO = SDI
A
D
15
D
14
D
D
13
13
D
A
1
D
A
0
B
A
A
tHSDO
tDSDO
D
B
15
D
14
D
1
D
0
D
15
D
14
D 1
A
D 0
A
SDO
B
B
B
A
A
B
Figure 39. Chain Mode Serial Interface Timing
Rev. B | Page 20 of 24
Data Sheet
AD7988-1/AD7988-5
APPLICATIONS INFORMATION
Using at least one ground plane is recommended. It can be
common or split between the digital and analog section. In the
latter case, join the planes underneath the AD7988-x devices.
INTERFACING TO BLACKFIN® DSP
The AD7988-x can easily connect to a DSP SPI or SPORT. The
SPI configuration is straightforward, using the standard SPI
interface as shown in Figure 40.
The AD7988-x voltage reference input, REF, has a dynamic input
impedance. Decouple REF with minimal parasitic inductances
by placing the reference decoupling ceramic capacitor close to,
but ideally right up against, the REF and GND pins and connect-
ing them with wide, low impedance traces.
SPI_CLK
SPI_MISO
SPI_MOSI
SCK
SDO
CNV
AD7988-1/
AD7988-5
BLACKFIN
DSP
Finally, decouple the power supplies of the AD7988-x, VDD and
VIO, with ceramic capacitors, typically 100 nF, placed close to
the AD7988-x and connected using short and wide traces to
provide low impedance paths and to reduce the effect of glitches
on the power supply lines.
Figure 40. Typical Connection to Blackfin SPI Interface
Similarly, the SPORT interface can be used to interface to this
ADC. The SPORT interface has some benefits in that it can use
direct memory access (DMA) and provides a lower jitter CNV
signal generated from a hardware counter.
An example of a layout following these rules is shown in Figure 42
and Figure 43.
Some glue logic may be required between SPORT and the
AD7988-x interface. The evaluation board for the AD7988-x
interfaces directly to the SPORT of the Blackfin-based (ADSP-
BF-527) SDP board. The configuration used for the SPORT
interface requires the addition of some glue logic as shown in
Figure 41. The SCK input to the ADC was gated off when CNV
was high to keep the SCK line static while converting the data,
thereby ensuring the best integrity of the result. This approach
uses an AND gate and a NOT gate for the SCK path. The other
logic gates used on the RSCLK and RFS paths are for delay
matching purposes and may not be necessary where path
lengths are short.
EVALUATING THE PERFORMANCE OF THE
AD7988-x
The evaluation board package for the AD7988-x (EVAL-AD7988-
5SDZ) includes a fully assembled and tested evaluation board,
documentation, and software for controlling the board from a
PC via the EVAL-SDP-CB1Z.
AD7988-1/
AD7988-5
This is one approach to using the SPORT interface for this ADC;
there may be other solutions equal to this approach.
VDRIVE
DR
SDO
RSCLK
TSCLK
SCK AD7988-1/
AD7988-5
BLACKFIN
DSP
RFS
TFS
Figure 42. Example Layout of the AD7988-x (Top Layer)
CNV
Figure 41. Evaluation Board Connection to Blackfin Sport Interface
LAYOUT
Design the printed circuit board (PCB) that houses the AD7988-x
so that the analog and digital sections are separated and confined
to certain areas of the board. The pinout of the AD7988-x, with all
the analog signals on the left side and all the digital signals on
the right side, eases this task.
Avoid running digital lines under the device because these couple
noise onto the die, unless a ground plane under the AD7988-x is
used as a shield. Fast switching signals, such as CNV or clocks,
should never run near analog signal paths. Avoid crossover of
digital and analog signals.
Figure 43. Example Layout of the AD7988-x (Bottom Layer)
Rev. B | Page 21 of 24
AD7988-1/AD7988-5
OUTLINE DIMENSIONS
Data Sheet
3.10
3.00
2.90
10
1
6
5
5.15
4.90
4.65
3.10
3.00
2.90
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.70
0.55
0.40
0.15
0.05
0.23
0.13
6°
0°
0.30
0.15
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 44.10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
2.48
2.38
2.23
3.10
3.00 SQ
0.50 BSC
2.90
6
10
PIN 1 INDEX
EXPOSED
PAD
1.74
1.64
1.49
AREA
0.50
0.40
0.30
5
1
PIN 1
INDICATOR
TOP VIEW
BOTTOM VIEW
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.25
0.20
0.20 REF
Figure 45. 10-Lead Lead Frame Chip Scale Package [QFN (LFCSP_WD)]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
Rev. B | Page 22 of 24
Data Sheet
AD7988-1/AD7988-5
ORDERING GUIDE
Integral
Nonlinearity
Temperature
Range
Ordering
Quantity
Package
Option
Model1
Notes
Package Description
10-Lead MSOP
Branding
C7E
AD7988-1BRMZ
1.25 LSB max
1.25 LSB max
1.25 LSB max
1.25 LSB max
1.25 LSB max
1.25 LSB max
1.25 LSB max
1.25 LSB max
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Tube, 50
RM-10
AD7988-1BRMZ-RL7
AD7988-1BCPZ-RL
AD7988-1BCPZ-RL7
AD7988-5BRMZ
Reel, 1,000
Reel, 5,000
Reel, 1,500
Tube, 50
10-Lead MSOP
RM-10
C7E
10-Lead QFN (LFCSP_WD)
10-Lead QFN (LFCSP_WD)
10-Lead MSOP
CP-10-9
CP-10-9
RM-10
C7X
C7X
C7Q
C7Q
C7Y
AD7988-5BRMZ-RL7
AD7988-5BCPZ-RL
AD7988-5BCPZ-RL7
EVAL-AD7988-5SDZ
Reel, 1,000
Reel, 5,000
Reel, 1,500
10-Lead MSOP
RM-10
10-Lead QFN (LFCSP_WD)
10-Lead QFN (LFCSP_WD)
CP-10-9
CP-10-9
C7Y
2
3
Evaluation Board with AD7988-5
Populated; Use for Evaluation of Both
AD7988-1 and AD7988-5.
EVAL-SDP-CB1Z
System Demonstration Board, Used as a
Controller Board for Data Transfer via
USB Interface to PC.
1 Z = RoHS Compliant Part.
2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-SDZ-CB1Z for evaluation/demonstration purposes.
3 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the SD designator.
Rev. B | Page 23 of 24
AD7988-1/AD7988-5
NOTES
Data Sheet
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10231-0-5/12(B)
Rev. B | Page 24 of 24
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