AD8147ACPZ-REEL [ADI]
IC,DIFFERENTIAL AMPLIFIER,TRIPLE,BIPOLAR,LLCC,24PIN,PLASTIC;型号: | AD8147ACPZ-REEL |
厂家: | ADI |
描述: | IC,DIFFERENTIAL AMPLIFIER,TRIPLE,BIPOLAR,LLCC,24PIN,PLASTIC 放大器 |
文件: | 总17页 (文件大小:694K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Triple Differential Driver
for Wideband Video
Preliminary Technical Data
AD8146/AD8147/AD8148
Functional Block Diagrams
FEATURES
Triple high-speed fully differential driver
700 MHz −3 dB 2Vp-p bandwidth (AD8146/7)
540 MHz −3 dB 2Vp-p bandwidth (AD8148)
175 MHz 0.1dB 2Vp-p bandwidth
2600 V/µs slew rate
5ns settling time to 1%
Internal common-mode feedback network
Output balance error −60 dB @ 50 MHz
Fixed gain (AD8146/AD8147: G = 2, AD8148: G = 4)
Differential or single-ended in to differential out
Drives doubly-terminated 100 Ω UTP cable
Adjustable output common-mode voltage (AD8146)
On-chip sync-on-common-mode encoding (AD8147/8)
Output pull-down feature for line isolation
Low offset: 4 mV typical output referred
Low power: 48mA @ 5V for 3 drivers (AD8146)
Wide supply voltage range: +5 V to 5 V
Available in a small 4mm × 4mm LFCSP
24
23
22
21
20
19
OPD
1
2
3
4
5
18
17
V
V
C
OCM
AD8146
V
S–
S+
–IN A
+IN A
16 –IN C
15 +IN C
B
V
14
V
S–
A
C
S–
–OUT A
6
13 –OUT C
7
8
9
10
11
12
APPLICATIONS
QXGA or 1080p video transmission
KVM networking
Video over UTP (unshielded twisted pair)
Differential signal multiplexing
GENERAL DESCRIPTION
multiplexing over the same twisted pair cable.
The AD8146/AD8147/AD8148 are high-speed triple, differ-
ential or single-ended input to differential output drivers.
The AD8146 and AD8147 have a fixed gain of 2, and the
AD8148 has a fixed gain of 4. They are all specifically de-
signed for the highest resolution component video signals, but
can be used for any type of analog signals or high speed data
transmission over either Category 5 unshielded twisted UTP
cable or differential printed circuit board transmission lines.
These drivers can be used in with the AD8145 triple differ-
ential-to-singled-ended amps and AD8117 cross-point
switches to produce a video distribution system capable of
supporting UXGA or 1080p signals.
Manufactured on Analog Devices’ second generation XFCB
bipolar process, the drivers have large signal bandwidths of
700 MHz and fast slew rates. They have an internal com-
mon-mode feedback feature that provides output amplitude
and phase matching that is balanced to −60 dB at 50 MHz,
suppressing even-order harmonics and minimizing radiated
electromagnetic interference (EMI). They are available in 24-
lead LFCSP packages and operate over −40°C to +85°C.
The AD8146 allows the common-mode voltage of each output
to be set to any level, and can be used to transmit signals. The
AD8147 and AD8148 encode the vertical and horizontal sync
signals on the common-mode voltages of the outputs. The out-
puts of all can be set to low voltage states to be used with
series diodes for line isolation, allowing easy differential
Rev.PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2006 Analog Devices, Inc. All rights reserved.
AD8146/AD8147/AD8148
TABLE OF CONTENTS
Specifications..................................................................................... 3
Output Common-Mode Control ............................................. 11
Sync-On-Common-Mode......................................................... 11
Applications..................................................................................... 13
Driving RGB Video Signals Over Category-5 UTP Cable.... 13
Output Pull-Down ..................................................................... 14
KVM Networks........................................................................... 14
Video Sync-On-Common-Mode............................................. 14
Layout and Power Supply Decoupling Considerations .... 15
Exposed Paddle (EP).................................................................. 16
Outline Dimensions....................................................................... 17
Ordering Guide .......................................................................... 17
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Theory of Operation ...................................................................... 10
Definition of Terms.................................................................... 10
Analyzing an Application Circuit............................................. 10
Closed-Loop Gain ...................................................................... 10
Calculating an Application Circuit’s Input Impedance ......... 11
Input Common-Mode Voltage Range in Single-Supply
Applications .................................................................................. 11
Driving a Capacitive Load......................................................... 11
REVISION HISTORY
12/06—Revision Pr0: Initial Version
Rev. PrA | Page 2 of 17
AD8146/AD8147/AD8148
SPECIFICATIONS
VS = 5V, VOCM = 0 V, @ 25°C, RL, dm = 200 Ω, unless otherwise noted. TMIN to TMAX = −40°C to +85°C.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
DIFFERENTIAL INPUT AC
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
−3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
VO = 0.2 V p-p
900
MHz
MHz
MHz
V/µs
ns
VO = 2 V p-p, AD8146, AD8147/AD8148
VO = 2 V p-p, AD8146, AD8147/AD8148
VO = 2 V p-p, 25% to 75%
VO = 2 V Step
700/540
175/120
2600
5
Settling Time to 1%
Isolation between Amplifiers
DIFFERENTIAL INPUT DC
Input Common-Mode Voltage Range
Input Resistance
f = 10 MHz, between Amplifiers
TBD
dB
−5 to +5
1.0
1.13
1
V
Differential
Single-Ended Input
Differential
kΩ
kΩ
pF
dB
Input Capacitance
DC CMRR
∆VOUT, dm/∆VIN, cm, ∆VIN, cm = 1 V
−45
DIFFERENTIAL OUTPUT
Differential Signal Gain
∆VOUT, dm/∆VIN, dm; ∆VIN, dm = 1 V, AD8146,
AD8147
∆VOUT, dm/∆VIN, dm; ∆VIN, dm = 1 V, AD8148
Each Single-Ended Output
AD8146, AD8147/AD8148
TMIN to TMAX
2
4
V/V
V/V
V
mV
µV/°C
dB
Output Voltage Swing
Output Offset Voltage
Output Offset Drift
VS− + 2.45
VS+ – 2.15
+4/+7
TBD
−60
Output Balance Error
∆VOUT, cm/∆VIN, dm, ∆VOUT, dm = 2 V p-p, f = 50
MHz
DC
−66
dB
Output Voltage Noise (RTO)
Output Short-Circuit Current
AD8146
f = 1 MHz, AD8146, AD8147/AD8148
25/42
TBD
nV/√Hz
mA
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
∆VOCM = 100 mV p-p
VOCM = −1 V to +1 V, 25% to 75%
∆VOCM = 1 V
330
1000
1
MHz
V/µs
V/V
DC Gain
VOCM INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
3.1
70
V
kΩ
Input Offset Voltage
Input Offset Voltage Drift
DC CMRR
−6
50
−42
mV
µV/°C
dB
TMIN to TMAX
∆VOUT, dm/∆VOCM, ∆VOCM = 1 V
AD8147/AD8148
SYNC DYNAMIC PERFORMANCE
Slew Rate
VOUT, cm = −1 V to +1 V; 25% to 75%
1000
V/µs
HSYNC AND VSYNC INPUTS
Input Low Voltage
Input High Voltage
TBD
TBD
V
V
SYNC LEVEL INPUT
Setting to 0.5 V Pulse Levels
Gain to Red Common-Mode Output
Gain to Green Common-Mode Output
Gain to Blue Common-Mode Output
0.5
1
2
V
∆VO, cm/∆VSYNC LEVEL
∆VO, cm/∆VSYNC LEVEL
∆VO, cm/∆VSYNC LEVEL
V/V
V/V
V/V
1
Rev. PrA | Page 3 of 17
AD8146/AD8147/AD8148
Parameter
Conditions
Min
Typ
Max
Unit
POWER SUPPLY
Operating Range
Quiescent Current
+4.5
5.5
V
AD8146
AD8147,AD8148
∆VOUT, dm/∆VS; ∆VS = 1 V
52
60
−84
mA
mA
dB
PSRR
OUTPUT PULL-DOWN
OPD Input Low Voltage
OPD Input High Voltage
OPD Input Bias Current
OPD Assert Time
TBD
TBD
TBD
100
100
VS− + 0.86
V
V
µA
ns
ns
V
OPD De-Assert Time
Output Voltage When OPD Asserted
Each Output, OPD Input @ VS+
Rev. PrA | Page 4 of 17
AD8146/AD8147/AD8148
VS = 5 V or 2.5V, VOCM = midsupply, @ 25°C, RL, dm = 200 Ω, unless otherwise noted. TMIN to TMAX = −40°C to +85°C.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
DIFFERENTIAL INPUT AC Specs
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
−3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
VO = 0.2 V p-p
760
MHz
MHz
MHz
V/µs
ns
VO = 2 V p-p, AD8146, AD8147/AD8148
VO = 2 V p-p, AD8146, AD8147/AD8148
VO = 2 V p-p, 25% to 75%
VO = 2 V Step
600/475
150/120
2300
5
Settling Time to 1%
Isolation Between Amplifiers
DIFFERENTIAL INPUT DC Specs
Input Common-Mode Voltage Range
Input Resistance
f = 10 MHz, between Amplifiers
TBD
dB
0 to 5
1.0
1.13
1
V
Differential
Single-Ended Input
Differential
kΩ
kΩ
pF
dB
Input Capacitance
DC CMRR
∆VOUT, dm/∆VIN, cm, ∆VIN, cm = 1 V
−50
DIFFERENTIAL OUTPUT
Differential Signal Gain
∆VOUT, dm/∆VIN, dm; ∆VIN, dm = 1 V, AD8146,
AD8147
∆VOUT, dm/∆VIN, dm; ∆VIN, dm = 1 V, AD8148
Each Single-Ended Output
AD8146, AD8147/AD8148
TMIN to TMAX
2
4
V/V
V/V
V
mV
µV/°C
dB
Output Voltage Swing
Output Offset Voltage
Output Offset Drift
VS− + 1.25
VS+ − 1.20
+4/+7
30
−60
Output Balance Error
∆VOUT, cm/∆VIN, dm, ∆VOUT, dm = 2 V p-p, f = 50
MHz
DC
−66
dB
Output Voltage Noise (RTO)
Output Short-Circuit Current
AD8146
f = 1 MHz, AD8146, AD8147/AD8148
25/42
TBD
nV/√Hz
mA
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
∆VOCM = 100 mV p-p
VOCM = −1 V to +1 V, 25% to 75%
∆VOCM = 1 V, TMIN to TMAX
290
700
1
MHz
V/µs
V/V
DC Gain
VOCM INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
1.25 to 3.85
70
V
kΩ
Input Offset Voltage
Input Offset Voltage Drift
DC CMRR
+2
50
−42
mV
µV/°C
dB
TMIN to TMAX
∆VO, dm/∆VOCM; ∆VOCM = 1 V
AD8147/AD8148
SYNC DYNAMIC PERFORMANCE
Slew Rate
VOUT, cm = −1 V to +1 V; 25% to 75%
1000
V/µs
HSYNC AND VSYNC INPUTS
Input Low Voltage
Input High Voltage
TBD
TBD
V
V
SYNC LEVEL INPUT
Setting to 0.5 V Pulse Levels
Gain to Red Common-Mode Output
Gain to Green Common-Mode Output
Gain to Blue Common-Mode Output
0.5
1
2
V
∆VO, cm/∆VSYNC LEVEL
∆VO, cm/∆VSYNC LEVEL
∆VO, cm/∆VSYNC LEVEL
V/V
V/V
V/V
1
Rev. PrA | Page 5 of 17
AD8146/AD8147/AD8148
Parameter
Conditions
Min
Typ
Max
Unit
POWER SUPPLY
Operating Range
Quiescent Current
+4.5
5.5
V
AD8146
AD8147, AD8148
∆VOUT, dm/∆VS; ∆VS = 1 V
43
47
−84
mA
mA
dB
PSRR
OUTPUT PULL-DOWN
OPD Input Low Voltage
OPD Input High Voltage
OPD Input Bias Current
OPD Assert Time
TBD
TBD
TBD
100
100
VS− + 0.79
V
V
µA
ns
ns
V
OPD De-Assert Time
Output Voltage When OPD Asserted
Each Output, OPD Input @ VS+
Rev. PrA | Page 6 of 17
AD8146/AD8147/AD8148
ABSOLUTE MAXIMUM RATINGS
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The load current consists of differential
and common-mode currents flowing to the loads, as well as
currents flowing through the internal differential and common-
mode feedback loops. The internal resistor tap used in the
common-mode feedback loop places a 4 kΩ differential load on
the output. Differential feedback network resistor values are
given in the Theory of Operation section. RMS output voltages
should be considered when dealing with ac signals.
Table 3.
Parameter
Rating
Supply Voltage
11 V
All VOCM
VS
Power Dissipation
Input Common-Mode Voltage
Storage Temperature
Operating Temperature Range
Lead Temperature Range
(Soldering 10 sec)
See Figure 1
VS
−65°C to +125°C
−40°C to +85°C
300°C
Junction Temperature
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at these or any
other conditions above those indicated in the operational sec-
tion of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Airflow reduces θJA. Also, more metal directly in contact with
the package leads from metal traces, through holes, ground,
and power planes reduces the θJA. The exposed paddle on the
underside of the package must be soldered to a pad on the PCB
surface that is thermally connected to a ground plane in order
to achieve the specified θJA.
Figure 1 shows the maximum safe power dissipation in the
package versus ambient temperature for the 24-lead LFCSP
(70°C/W) package on a JEDEC standard 4-layer board with the
underside paddle soldered to a pad that is thermally connected
to a ground plane. θJA values are approximations.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, i.e., θJA is specified
for the device soldered in a circuit board in still air.
Table 4. Thermal Resistance with the Underside Pad
Connected to the Plane
4.0
Package Type/PCB Type
θJA
Unit
3.5
24-Lead LFCSP/4-Layer
70
°C/W
3.0
2.5
2.0
Maximum Power Dissipation
The maximum safe power dissipation in the AD8146/AD8147
package is limited by the associated rise in junction temperature
(TJ) on the die. At approximately 150°C, which is the glass tran-
sition temperature, the plastic changes its properties. Even tem-
porarily exceeding this temperature limit may change the
stresses that the package exerts on the die, permanently shifting
the parametric performance of the AD8146/AD8147. Exceeding
a junction temperature of 175°C for an extended period of time
can result in changes in the silicon devices potentially causing
failure.
1.5
LFCSP
1.0
0.5
0
–40
–20
0
20
40
60
80
AMBIENT TEMPERATURE (°C)
Figure 1. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features proprie-
tary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
Rev. PrA | Page 7 of 17
AD8146/AD8147/AD8148
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
24
23
22
21
20
19
OPD
1
2
3
4
5
18
17
V
V
C
OCM
AD8146
V
S–
S+
–IN A
+IN A
16 –IN C
15 +IN C
B
V
14
V
S–
A
C
S–
–OUT A
6
13 –OUT C
7
8
9
10
11
12
Figure 2. AD8146 24-Lead LFCSP
Table 5. AD8146 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
OPD
Output Pull-Down
2, 5, 14, 21
VS−
Negative Power Supply Voltage
3
−IN A
Inverting Input, Amplifier A
4
+IN A
Noninverting Input, Amplifier A
6
7
−OUT A
+OUT A
VS+
Negative Output, Amplifier A
Positive Output, Amplifier A
Positive Power Supply Voltage
8, 11, 17, 24
9
+OUT B
−OUT B
+OUT C
−OUT C
+IN C
Positive Output, Amplifier B
Negative Output, Amplifier B
Positive Output, Amplifier C
Negative Output, Amplifier C
Noninverting Input, Amplifier C
Inverting Input, Amplifier C
Voltage Applied to This Pin Controls Output Common-Mode Voltage, Amplifier C
Voltage Applied to This Pin Controls Output Common-Mode Voltage, Amplifier B
Voltage Applied to This Pin Controls Output Common-Mode Voltage, Amplifier A
Noninverting Input, Amplifier B
10
12
13
15
16
18
19
20
22
23
−IN C
VOCM
VOCM
VOCM
C
B
A
+IN B
−IN B
Inverting Input, Amplifier B
Rev. PrA | Page 8 of 17
AD8146/AD8147/AD8148
Figure 3. AD8147 24-Lead LFCSP
Table 6. AD8147/AD8148 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
OPD
Output Pull-Down.
2, 5, 14, 21
3
4
6
VS−
−IN R
+IN R
Negative Power Supply Voltage.
Inverting Input, Red Amplifier.
Noninverting Input, Red Amplifier.
Negative Output, Red Amplifier.
Positive Output, Red Amplifier.
Positive Power Supply Voltage.
Positive Output, Green Amplifier.
Negative Output, Green Amplifier.
Positive Output, Blue Amplifier.
Negative Output, Blue Amplifier.
Noninverting Input, Blue Amplifier.
Inverting Input, Blue Amplifier.
−OUT R
+OUT R
VS+
+OUT G
−OUT G
+OUT B
−OUT B
+IN B
7
8, 11, 17, 24
9
10
12
13
15
16
18
−IN B
SYNC LEVEL
The voltage applied to this pin controls the amplitude of the sync pulses that are applied to the
common-mode voltages.
19
20
22
23
HSYNC
VSYNC
+IN G
−IN G
GND
Horizontal Sync Pulse Input.
Vertical Sync Pulse Input.
Noninverting Input, Green Amplifier.
Inverting Input, Green Amplifier.
Signal Ground Reference
Exposed Paddle
Rev. PrA | Page 9 of 17
AD8146/AD8147/AD8148
THEORY OF OPERATION
Each differential driver differs from a conventional op amp in
that it has two outputs whose voltages move in opposite direc-
tions. Like an op amp, it relies on high open-loop gain and
negative feedback to force these outputs to the desired voltages.
The drivers make it easy to perform single-ended-to-differential
conversion, common-mode level shifting, and amplification of
differential signals.
Common-mode voltage refers to the average of two node volt-
ages with respect to a common reference. The output common-
mode voltage is defined as
(VOP +VON
)
VOUT,cm
=
2
Output Balance
Output balance is a measure of how well the differential output
signals are matched in amplitude and how close they are to
exactly 180° apart in phase. Balance is most easily determined
by placing a well-matched resistor divider between the differen-
tial output voltage nodes and comparing the magnitude of the
signal at the divider’s midpoint with the magnitude of the dif-
ferential signal. By this definition, output balance error is the
magnitude of the change in output common-mode voltage
divided by the magnitude of the change in output differential-
mode voltage in response to a differential input signal.
Previous differential drivers, both discrete and integrated
designs, have been based on using two independent amplifiers
and two independent feedback loops, one to control each of the
outputs. When these circuits are driven from a single-ended
source, the resulting outputs are typically not well balanced.
Achieving a balanced output has typically required exceptional
matching of the amplifiers and feedback networks.
DC common-mode level shifting has also been difficult with
previous differential drivers. Level shifting has required the use
of a third amplifier and feedback loop to control the output
common-mode level. Sometimes, the third amplifier has also
been used to attempt to correct an inherently unbalanced
circuit. Excellent performance over a wide frequency range has
proven difficult with this approach.
∆VOUT,cm
Output Balance Error =
∆VOUT,dm
ANALYZING AN APPLICATION CIRCUIT
The drivers use high open-loop gain and negative feedback to
force their differential and common-mode output voltages to
minimize the differential and common-mode input error volt-
ages. The differential input error voltage is defined as the volt-
age between the differential inputs labeled VAP and VAN in
Figure 4. For most purposes, this voltage can be assumed to be
zero. Similarly, the difference between the actual output
common-mode voltage and the voltage applied to VOCM can also
be assumed to be zero. Starting from these two assumptions, any
application circuit can be analyzed.
Each of the drivers uses two feedback loops to
separately control the differential and common-mode output
voltages. The differential feedback, set by the internal resistors,
controls only the differential output voltage. The internal
common-mode feedback loop controls only the common-mode
output voltage. This architecture makes it easy to arbitrarily set
the output common-mode level by simply applying a voltage to
the VOCM input. The output common-mode voltage is forced, by
internal common-mode feedback, to equal the voltage applied to
the VOCM input, without affecting the differential output voltage.
CLOSED-LOOP GAIN
The driver architecture results in outputs that are highly bal-
anced over a wide frequency range without requiring external
components or adjustments. The common-mode feedback loop
forces the signal component of the output common-mode volt-
age to be zeroed. The result is nearly perfectly balanced differ-
ential outputs of identical amplitude that are exactly 180° apart
in phase.
The differential mode gain of the circuit in Figure 4 can be de-
scribed by the following equation.
VOUT,dm
VIN,dm
RF
RG
=
= 2
where RF = 1.0 kΩ and RG = 500 Ω nominally for the AD8146
and AD8147, and RF = 2.0 kΩ and RG = 500 Ω nominally for the
AD8148.
DEFINITION OF TERMS
Differential Voltage
Differential voltage refers to the difference between two node
voltages that are balanced with respect to each other. For exam-
ple, in Figure 4 the output differential voltage (or equivalently
output differential mode voltage) is defined as
R
F
V
R
AP
AN
G
G
+
V
V
ON
IP
V
R
V
V
OCM
L, dm
OUT, dm
IN, dm
–
V
V
OP
IN
V
R
R
F
VOUT,dm
=
(
VOP −VON
)
Figure 4.
Rev. PrA | Page 10 of 17
AD8146/AD8147/AD8148
DRIVING A CAPACITIVE LOAD
A purely capacitive load can react with the output
impedance of the AD8146/AD8147 to reduce phase margin,
resulting in high frequency ringing in the pulse response. The
best way to minimize this effect is to place a small resistor in
series with each of the amplifier’s outputs to buffer the load
capacitance.
CALCULATING AN APPLICATION CIRCUIT’S INPUT
IMPEDANCE
The effective input impedance of a circuit such as that in
Figure 4 at VIP and VIN depends on whether the amplifier is be-
ing driven by a single-ended or differential signal source. For
balanced differential input signals, the differential input imped-
ance, RIN, dm, between the inputs VIP and VIN for all devices is
simply
OUTPUT COMMON-MODE CONTROL
The AD8146 allows the user to control each of the three
common-mode output levels independently through the three
RIN,dm = 2× RG = 1.0 kΩ
VOCM input pins. The VOCM pins pass a signal to the common-
mode output level of each of their respective amplifiers with
330 MHz of small signal bandwidth and an internally fixed
gain of one. In this way, additional control and communication
signals can be embedded on the common-mode levels as the
user sees fit.
In the case of a single-ended input signal (for example, if VIN is
grounded and the input signal is applied to VIP), the input
impedance becomes:
⎛
⎜
⎞
⎟
RG
RF
RG + RF
⎜
⎜
⎟
⎟
RIN,dm
=
With no external circuitry, the level at the VOCM input of each
amplifier defaults to approximately mid-supply. An internal
resistive divider with an impedance of approximately 100 kΩ
sets this level. To limit common-mode noise in dc common-
mode applications, external bypass capacitors should be
connected from each of the VOCM input pins to ground.
1−
⎜
⎜
⎟
⎟
2×
(
)
⎝
⎠
The single-ended input impedance of the AD8146 and AD8147
is therefore 750 Ω, and is 833 Ω for the AD8148.
The circuit’s input impedance is effectively higher than it would
be for a conventional op amp connected as an inverter because
a fraction of the differential output voltage appears at the inputs
as a common-mode signal, partially bootstrapping the voltage
across the input resistor RG.
SYNC-ON-COMMON-MODE
The AD8147 and AD8148 are targeted at driving RGB video
signals over UTP cable. The excellent balance of the differential
outputs ensures low radiated energy from each of the twisted
pairs. The common-mode outputs of each of the R, G, and B
differential outputs are set using circuitry contained within the
devices. This circuitry embeds the horizontal and vertical sync
pulses on the three common-mode outputs in a way that also
results in low radiated energy. For a more detailed description
of the sync scheme, see the Applications section.
INPUT COMMON-MODE VOLTAGE RANGE IN SINGLE-
SUPPLY APPLICATIONS
The driver inputs are designed to facilitate level-shifting of
ground referenced input signals on a single power supply. For a
single-ended input, this would imply, for example, that the volt-
age at VIN in Figure 4 would be 0 V when the amplifier’s nega-
tive power supply voltage was also set to 0 V.
The sync-on-common-mode circuit generates a current based
on the SYNC LEVEL input pin (Pin 18). With SYNC LEVEL
input tied to GND, the common-mode output of all drivers is
set at (VS+ + VS−)/2. Using a resistor divider, a voltage can be
applied between GND and SYNC LEVEL that determines the
maximum deviation of the common-mode outputs from their
midsupply level. If, for instance, SYNC LEVEL = 0.5 V and the
supply voltage is 5 V, then the common-mode outputs fall
within an envelope of 2.5 V 0.5 V. The state of each VOUT, cm out-
put based on the HSYNC and VSYNC inputs is determined by the
equations defined in the Applications section.
It is important to ensure that the common-mode voltage at the
amplifier inputs, VAP and VAN, stays within its specified range.
Since voltages VAP and VAN are driven to be essentially equal by
negative feedback, the amplifier’s input common-mode voltage
can be expressed as a single term, VACM. VACM can be calculated
as follows
VOCM + 2VICM
VACM
=
3
where VICM is the common-mode voltage of the input signal, i.e.,
VIP + VIN
VICM
=
.
2
Rev. PrA | Page 11 of 17
AD8146/AD8147/AD8148
out concern of overdriving the inputs. The input path from
HSYNC and VSYNC inputs to the switches in the current mode
level-shifting circuit are well matched to eliminate false switch-
ing transients. This maximizes common-mode balance and
minimizes radiated energy.
The sync-on-common-mode circuit can be used by directly
applying the HSYNC and VSYNC signals to the respective AD8147
or AD8148 inputs. The logic thresholds of the HSYNC and VSYNC
inputs are set relative to GND. The exposed paddles of the
AD8147 and AD8148 are used as the GND references. The
robustness of the HSYNC and VSYNC inputs therefore allows them
to be driven directly off the output of a computer video card with-
Rev. PrA | Page 12 of 17
AD8146/AD8147/AD8148
APPLICATIONS
DRIVING RGB VIDEO SIGNALS OVER CATEGORY-5
UTP CABLE
The foremost application of the drivers is the transmission of
RGB video signals over UTP cable in KVM networks. Single-
ended video signals are easily converted to differential signals
for transmission over the cable, and the internally fixed gain of
2 or 4 automatically compensates for the losses incurred by the
source and load terminations. The common topologies used in
KVM networks, such as daisy-chained, star, and point-to-point,
are supported by the drivers. Figure 5 shows the AD8146 in a
triple single-ended-to-differential application when driven from
a 75 Ω source, which is typical of how RGB video is driven over
an UTP cable. In applications that use the OPD feature, Schot-
tky diodes are placed in series with each of the 49.9 Ω resistors
in the outputs.
Figure 5. AD8146 in Single-Ended-to-Differential Application
Rev. PrA | Page 13 of 17
AD8146/AD8147/AD8148
In the daisy-chained and star networks that use diodes for isola-
tion, return paths are required for the common-mode currents
that flow through the series diodes. A common-mode tap can
be implemented at each receiver by splitting the100 Ω termina-
tion resistor into two 50 Ω resistors in series. The diode currents
are routed from the tap between the 50 Ω resistors back to the
respective transmitters over one of the wires of the fourth
twisted pair in the UTP cable. Series resistors in the common-mode
return path are generally required to set the desired diode current.
OUTPUT PULL-DOWN
The output pull-down feature, when used in conjunction with
series Schottky diodes, offers a convenient means to connect a
number of driver outputs together to form a video network. The
OPD pin is a binary input that controls the state of the outputs.
Its binary input level is referenced to GND (see the
Specifications tables for the logic levels). When the OPD input
is driven to its low state, the output is enabled and operates in its
normal fashion. In this state, the VOCM input can be used to pro-
vide a positive bias on the series diodes, allowing the drivers to
transmit signals over the network. When the OPD input is
driven to its high state, the outputs of the drivers are forced to a
low voltage, irrespective of the level on the VOCM input, reverse-
biasing the series diodes and thus presenting high impedance to
the network. This feature allows a three-state output to be real-
ized that maintains its high impedance state even when the
drivers are not powered. This condition can occur in KVM net-
works where the drivers do not all reside in the same module,
and some modules in the network are not powered.
In point-to-point networks, there is one transmitter and one
receiver per cable, and the switching is generally implemented
with a crosspoint switch. In this case, there is no need to use
diodes or the output pull-down feature.
Diode and crosspoint switching are by no means the only type
of switching that can be used with the drivers. Many other types
of mechanical, electromechanical, and electronic switches can
be used.
VIDEO SYNC-ON-COMMON-MODE
It is recommended that the output pull-down feature only be
used in conjunction with series diodes in such a way as to
ensure that the diodes are reverse-biased when the output pull-
down feature is asserted, since some loading conditions can
prevent the output voltage from being pulled all the way down.
In computer video applications, the horizontal and vertical sync
signals are often separate from the video information
signals. For example, in typical computer monitor applications,
the red, green, and blue (RGB) color signals are transmitted
over separate cables, as are the vertical and horizontal sync sig-
nals. When transmitting these types of video signals over long
distances on UTP cable, it is desirable to reduce the required
number of physical channels. One way to do this is to encode
the vertical and horizontal sync signals as weighted sums and
differences of the output common-mode signals. The RGB color
signals are each transmitted differentially over separate physical
channels. The fact that the differential and common-mode sig-
nals are orthogonal allows the RGB color and sync signals to be
separated at the channel’s receiver.
KVM NETWORKS
In daisy-chained KVM networks, the drivers are distributed
along one cable and a triple receiver is located at one end.
Schottky diodes in series with the driver outputs are biased such
that the one driver that is transmitting video signals has its
diodes forward-biased and the disabled drivers have their
diodes reverse-biased. The output common-mode voltage, set
by the VOCM input, supplies the forward-biased voltage. When
the output pull-down feature is asserted, the differential outputs
are pulled to a low voltage, reverse-biasing the diodes.
Cat-5 cable contains four balanced twisted-pair physical chan-
nels that can support both differential and common-mode sig-
nals. Transmitting typical computer monitor video over this
cable can be accomplished by using three of the twisted pairs
for the RGB and sync signals and one wire of the fourth pair as
a return path for the Schottky diode bias currents. Each color is
transmitted differentially, one on each of the three pairs, and the
encoded sync signals are transmitted among the common-
mode signals of each of the three pairs. To minimize EMI from
the sync signals, the common-mode signals on each of the three
pairs produced by the sync encoding scheme induce electric
and magnetic fields that for the most part cancel each other. A
conceptual block diagram of the sync encoding scheme is pre-
sented in Figure 6. Since the AD8147 and AD8148 have the sync
encoding scheme implemented internally, the user simply ap-
plies the horizontal and vertical sync signals to the appropriate
inputs. (See the Specification tables for the definitions of the
high and low levels of the horizontal and vertical sync pulse
voltages).
In star networks, all cables radiate out from a central hub,
which contains a triple receiver. The series diodes are all located
at the receiver in the star network. Only one ray of the star is
transmitting at a given time, and all others are isolated by the
reverse-biased diodes. Diode biasing is controlled in the same
way as in the daisy-chained network.
Rev. PrA | Page 14 of 17
AD8146/AD8147/AD8148
3.1
3.0
2.9
G
2.8
2.7
2.6
2.5
2.4
2.3
R
B
2.2
2.1
2.0
5.0
4.5
4.0
3.5
3.0
2.5
H
V
SYNC
2.0
1.5
1.0
SYNC
0.5
0
Figure 6. AD8147/AD8148 Sync-On-Common-Mode Encoding Scheme
0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05
1.06 1.07
TIME (µs)
Figure 7. AD8147 Sync-On-Common-Mode Signals in Single 5 V Application
The transmitted common-mode sync signal magnitudes are
scaled by applying a dc voltage to the SYNC LEVEL input, ref-
erenced to GND. The difference between the voltage applied to
the SYNC LEVEL input and GND sets the peak deviation of the
encoded sync signals about the midsupply common-mode volt-
age. For example, with the SYNC LEVEL input set at 500 mV,
the deviation of the encoded sync pulses about the nominal
midsupply common-mode voltage is typically 500 mV. The
equations in Figure 6 describe how the VSYNC and HSYNC signals
are encoded on each color’s midsupply common-mode signal.
In these equations, the weights of the VSYNC and HSYNC signals
are ±1 (+1 for high, −1 for low), and the constant K is equal to
the peak deviation of the encoded sync signals.
LAYOUT AND POWER SUPPLY DECOUPLING
CONSIDERATIONS
Standard high speed PCB layout practices should be adhered to
when designing with the drivers. A solid ground plane is rec-
ommended and good wideband power supply decoupling net-
works should be placed as close as possible to the supply pins.
Small surface-mount ceramic capacitors are recommended for
these networks, and tantalum capacitors are recommended for
bulk supply decoupling.
Figure 7 shows how the sync signals appear on each common-
mode voltage in a single 5 V supply application when the volt-
age applied to the SYNC LEVEL input is 500 mV, which is the
typical setting for most applications.
Rev. PrA | Page 15 of 17
AD8146/AD8147/AD8148
top of the board that is connected to an inner plane with several
thermal vias. Since the AD8147 and AD8148 use the paddle as
a ground reference, it must be connected to a ground plane
when using these parts.
EXPOSED PADDLE (EP)
The LFCSP-24 package has an exposed paddle on the underside
of its body. In order to achieve the specified thermal resistance,
it must have a good thermal connection to one of the PCB
planes. The exposed paddle must be soldered to a pad on the
Rev. PrA | Page 16 of 17
AD8146/AD8147/AD8148
OUTLINE DIMENSIONS
0.60 MAX
4.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
19
24
1
18
0.50
BSC
2.25
2.10 SQ
1.95
PIN 1
INDICATOR
TOP
VIEW
3.75
BSC SQ
BOTTOM
VIEW
0.50
0.40
0.30
13
12
6
7
0.25 MIN
2.50 REF
0.80 MAX
0.65TYP
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.30
0.23
0.18
0.20 REF
SEATING
PLANE
COMPLIANTTOJEDECSTANDARDSMO-220-VGGD-2
Figure 8. 24-Lead Lead Frame Chip Scale Package [LFCSP],
4 mm× 4 mm (CP-24)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Package
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
24-Lead LFCSP
24-Lead LFCSP
24-Lead LFCSP
24-Lead LFCSP
24-Lead LFCSP
24-Lead LFCSP
24-Lead LFCSP
24-Lead LFCSP
24-Lead LFCSP
Package Outline
CP-24
CP-24
CP-24
CP-24
CP-24
CP-24
CP-24
CP-24
AD8146ACPZ-RL2
AD8146ACPZ-REEL7
AD8146ACPZ-REEL
AD8147ACPZ-RL2
AD8147ACPZ-REEL7
AD8147ACPZ-REEL
AD8148ACPZ-RL2
AD8148ACPZ-REEL7
AD8148ACPZ-REEL
CP-24
© 2006 Analog Devices, Inc. All rights reserved. Trademarks and regis-
tered trademarks are the property of their respective owners.
PR04769–0–12/06(PrA)
Rev. PrA | Page 17 of 17
相关型号:
AD8147ACPZ-RL1
IC 1 CHANNEL, VIDEO AMPLIFIER, QCC24, 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-2, LFCSP-24, Audio/Video Amplifier
ADI
AD8148ACPZ-R21
IC 1 CHANNEL, VIDEO AMPLIFIER, QCC24, 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-2, LFCSP-24, Audio/Video Amplifier
ADI
AD8148ACPZ-R71
IC 1 CHANNEL, VIDEO AMPLIFIER, QCC24, 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-2, LFCSP-24, Audio/Video Amplifier
ADI
©2020 ICPDF网 联系我们和版权申明