AD817ANZ [ADI]
High Speed, Low Power Wide Supply Range Amplifier; 高速，低功耗，宽电源电压范围放大器
| 型号： | AD817ANZ |
| 厂家： | 
ADI |
| 描述： | High Speed, Low Power Wide Supply Range Amplifier |
| 文件： | 总12页 (文件大小：208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Speed, Low Power
Wide Supply Range Amplifier
a
AD817
CO NNECTIO N D IAGRAM
FEATURES
Low Cost
High Speed
50 MHz Unity Gain Bandw idth
350 V/ s Slew Rate
8-P in P lastic Mini-D IP (N) and
SO IC (R) P ackages
45 ns Settling Tim e to 0.1% (10 V Step)
Flexible Pow er Supply
NULL
8
7
6
5
1
2
3
4
NULL
–IN
AD817
+VS
Specified for Single (+5 V) and
Dual (؎5 V to ؎15 V) Pow er Supplies
Low Pow er: 7.5 m A m ax Supply Current
High Output Drive Capability
Drives Unlim ited Capacitive Load
50 m A Minim um Output Current
Excellent Video Perform ance
70 MHz 0.1 dB Bandw idth (Gain = +1)
0.04% & 0.08؇ Differential Gain & Phase Errors
@ 3.58 MHz
+IN
OUTPUT
NC
–VS
TOP VIEW
NC = NO CONNECT
T he AD817 is fully specified for operation with a single +5 V
power supply and with dual supplies from ±5 V to ±15 V. T his
power supply flexibility, coupled with a very low supply current
of 7.5 mA and excellent ac characteristics under all power sup-
ply conditions, make the AD817 the ideal choice for many de-
manding yet power sensitive applications.
Available in 8-Pin SOIC and 8-Pin Plastic Mini-DIP
P RO D UCT D ESCRIP TIO N
In applications such as ADC buffers and line drivers the AD817
simplifies the design task with its unique combination of a
50 mA minimum output current and the ability to drive
unlimited capacitive loads.
T he AD817 is a low cost, low power, single/dual supply, high
speed op amp which is ideally suited for a broad spectrum of
signal conditioning and data acquisition applications. T his
breakthrough product also features high output current drive
capability and the ability to drive an unlimited capacitive load
while still maintaining excellent signal integrity.
T he AD817 is available in 8-pin plastic mini-DIP and SOIC
packages.
T he 50 MHz unity gain bandwidth, 350 V/µs slew rate and set-
tling time of 45 ns (0.1%) make possible the processing of high
speed signals common to video and imaging systems. Further-
more, professional video performance is attained by offering dif-
ferential gain & phase errors of 0.04% & 0.08° @ 3.58 MHz
and 0.1 dB flatness to 70 MHz (gain = +1).
O RD ERING GUID E
Tem perature
Range
P ackage
D escription
P ackage
O ption
Model
AD817AN
AD817AR
–40°C to +85°C 8-Pin Plastic DIP
–40°C to +85°C 8-Pin Plastic SOIC R-8
N-8
1kΩ
3.3µF
5V
500ns
+V
S
100
90
0.01µF
100pF
LOAD
HP
PULSE
GENERATOR
1kΩ
V
IN
7
2
3
TEKTRONIX
P6201 FET
PROBE
V
OUT
6
AD817
50Ω
C
L
4
0.01µF
3.3µF
10
1000pF
0%
1000pF
LOAD
–V
S
AD817 Driving a Large Capacitive Load
REV. B
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norw ood. MA 02062-9106, U.S.A.
Tel: 617/ 329-4700 Fax: 617/ 326-8703
(@ T = +25؇C, unless otherwise noted)
AD817–SPECIFICATIONS
A
AD 817A
Typ
P aram eter
Conditions
VS
Min
Max
Units
DYNAMIC PERFORMANCE
Unity Gain Bandwidth
±5 V
30
45
25
18
40
10
35
50
29
30
70
20
MHz
MHz
MHz
MHz
MHz
MHz
±15 V
0, +5 V
±5 V
±15 V
0, +5 V
Bandwidth for 0.1 dB Flatness
Full Power Bandwidth1
Gain = +1
VOUT = 5 V p-p
RLOAD = 500 Ω
VOUT = 20 V p-p
RLOAD = 1 kΩ
RLOAD = 1 kΩ
Gain = 1
±5 V
15.9
MHz
±15 V
±5 V
±15 V
0, +5 V
±5 V
±15 V
±5 V
±15 V
±15 V
±15 V
±5 V
5.6
MHz
V/µs
V/µs
V/µs
ns
ns
ns
ns
dB
Slew Rate
200
300
150
250
350
200
45
45
70
Settling T ime to 0.1%
Settling T ime to 0.01%
–2.5 V to +2.5 V
0 V–10 V Step, AV = –1
–2.5 V to +2.5 V
0 V–10 V Step, AV = –1
FC = 1 MHz
70
63
T otal Harmonic Distortion
Differential Gain Error
(RLOAD = 150 Ω)
NT SC
Gain = +2
0.04
0.05
0.11
0.08
0.06
0.14
0.08
0.1
%
%
%
0, +5 V
±15 V
±5 V
Differential Phase Error
(RLOAD = 150 Ω)
NT SC
Gain = +2
0.1
0.1
Degrees
Degrees
Degrees
0, +5 V
INPUT OFFSET VOLT AGE
±5 V to ±15 V
±5 V, ±15 V
±5 V, ±15 V
±5 V
0.5
2
3
mV
mV
µV/°C
T MIN to TMAX
Offset Drift
10
INPUT BIAS CURRENT
3.3
6.6
10
4.4
µA
µA
µA
T MIN
T MAX
INPUT OFFSET CURRENT
25
200
500
nA
nA
nA/°C
T MIN to TMAX
Offset Current Drift
OPEN LOOP GAIN
0.3
VOUT = ±2.5 V
RLOAD = 500 Ω
T MIN to TMAX
RLOAD = 150 Ω
VOUT = ±10 V
RLOAD = 1 kΩ
T MIN to TMAX
VOUT = ±7.5 V
RLOAD = 150 Ω
(50 mA Output)
2
1.5
1.5
4
3
V/mV
V/mV
V/mV
±15 V
±15 V
4
2.5
6
5
V/mV
V/mV
2
4
V/mV
COMMON-MODE REJECT ION
POWER SUPPLY REJECT ION
VCM = ±2.5 V
VCM = ±12 V
±5
±15 V
±15 V
78
86
80
100
120
100
dB
dB
dB
VS = ±5 V to ±15 V
T MIN to TMAX
75
72
86
dB
dB
INPUT VOLT AGE NOISE
INPUT CURRENT NOISE
f = 10 kHz
f = 10 kHz
±5 V, ±15 V
±5 V, ±15 V
15
nV/√Hz
pA/√Hz
1.5
–2–
REV. B
AD817
AD 817A
Typ
P aram eter
Conditions
VS
Min
Max
Units
INPUT COMMON-MODE
VOLT AGE RANGE
±5 V
+3.8
–2.7
+13
–12
+3.8
+1.2
+4.3
–3.4
+14.3
–13.4
+4.3
+0.9
V
V
V
V
V
V
±15 V
0, +5 V
OUT PUT VOLT AGE SWING
RLOAD = 500 Ω
RLOAD = 150 Ω
RLOAD = 1 kΩ
RLOAD = 500 Ω
RLOAD = 500 Ω
±5 V
±5 V
±15 V
±15 V
0, +5 V
3.3
3.2
3.8
3.6
13.7
13.4
±V
±V
±V
±V
13.3
12.8
+1.5,
+3.5
50
V
Output Current
±15 V
±5 V
0, +5 V
±15 V
mA
mA
mA
mA
50
30
Short-Circuit Current
INPUT RESIST ANCE
INPUT CAPACIT ANCE
OUT PUT RESIST ANCE
90
300
1.5
8
kΩ
pF
Ω
Open Loop
POWER SUPPLY
Operating Range
Dual Supply
Single Supply
±2.5
+5
±18
+36
7.5
7.5
7.5
7.5
V
V
mA
mA
mA
mA
Quiescent Current
±5 V
±5 V
±15 V
±15 V
7.0
7.0
T MIN to TMAX
T MIN to TMAX
NOT ES
1Full power bandwidth = slew rate/2 π VPEAK
.
Specifications subject to change without notice.
ABSO LUTE MAXIMUM RATINGS1
2.0
1.5
1.0
0.5
0
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
8-PIN MINI-DIP PACKAGE
T
= +150°C
J
Internal Power Dissipation2
Plastic (N) . . . . . . . . . . . . . . . . . . . . . . See Derating Curves
Small Outline (R) . . . . . . . . . . . . . . . . . See Derating Curves
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . ±6 V
Output Short Circuit Duration . . . . . . . . See Derating Curves
Storage T emperature Range N, R . . . . . . . . . –65°C to +125°C
Operating T emperature Range . . . . . . . . . . . . –40°C to +85°C
Lead T emperature Range (Soldering 10 sec) . . . . . . . . +300°C
8-PIN SOIC PACKAGE
NOT ES
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2Specification is for device in free air: 8-pin plastic package: θJA = 100°C/watt;
8-pin SOIC package: θJA = 160°C/watt.
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE –
°C
Maxim um Power Dissipation vs. Tem perature
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD817 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–3–
AD817–Typical Characteristics
20
8.0
15
7.5
7.0
+VCM
+85°C
+25°C
10
-40°C
–VCM
5
0
6.5
6.0
0
5
10
15
20
0
5
10
SUPPLY VOLTAGE – ±Volts
15
20
SUPPLY VOLTAGE – ± Volts
Figure 1. Com m on-Mode Voltage Range vs. Supply
Figure 4. Quiescent Supply Current vs. Supply Voltage
for Various Tem peratures
20
15
400
350
300
R
= 500Ω
L
10
5
R
= 150Ω
L
250
200
0
0
5
10
15
20
0
5
10
15
20
SUPPLY VOLTAGE – ±Volts
SUPPLY VOLTAGE – ±Volts
Figure 5. Slew Rate vs. Supply Voltage
Figure 2. Output Voltage Swing vs. Supply
100
10
1
30
25
VS = ±15V
20
15
10
0.1
VS = ±5V
5
0.01
0
1k
10k
100k
FREQUENCY – Hz
1M
10M
100M
10
100
1k
10k
LOAD RESISTANCE – Ω
Figure 3. Output Voltage Swing vs. Load Resistance
Figure 6. Closed-Loop Output Im pedance vs. Frequency
–4–
REV. B
AD817
7
6
5
100
+100
PHASE ±5V OR
±15V SUPPLIES
80
60
40
20
0
+80
+60
+40
+20
0
GAIN ±15V SUPPLIES
4
3
2
1
GAIN ±5V SUPPLIES
R
= 1kΩ
L
–20
1k
–60 –40 –20
0
20
40
60
80
100 120 140
10k
100k
1M
10M
100M
1G
TEMPERATURE –
°C
FREQUENCY – Hz
Figure 7. Input Bias Current vs. Tem perature
Figure 10. Open-Loop Gain and Phase Margin
vs. Frequency
130
7
±15V
6
110
SOURCE CURRENT
5
90
±5V
4
SINK CURRENT
70
3
2
1
50
30
–60 –40 –20
0
20
40
60
80
100 120 140
100
1k
10k
LOAD RESISTANCE – Ohms
TEMPERATURE – °C
Figure 8. Short Circuit Current vs. Tem perature
Figure 11. Open Loop Gain vs. Load Resistance
100
100
90
80
80
60
40
20
80
60
POSITIVE
SUPPLY
PHASE MARGIN
70
60
NEGATIVE
SUPPLY
50
GAIN BANDWIDTH
40
30
20
10
40
20
–60 –40 –20
0
20
40
60
80
100 120 140
100
1k
10k
100k
1M
10M
100M
TEMPERATURE – °C
FREQUENCY – Hz
Figure 9. Unity Gain Bandwidth and Phase Margin
vs. Tem perature
Figure 12. Power Supply Rejection vs. Frequency
REV. B
–5–
AD817–Typical Characteristics
120
–40
V
= 1V p-p
IN
GAIN = +2
–50
–60
100
80
–70
2nd HARMONIC
–80
3rd HARMONIC
60
40
–90
–100
1k
10k
100k
FREQUENCY – Hz
1M
10M
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
Figure 13. Com m on-Mode Rejection vs. Frequency
Figure 16. Harm onic Distortion vs. Frequency
30
50
40
30
20
10
0
R
= 1kΩ
L
20
10
0
R
= 150Ω
L
100k
1M
10M
FREQUENCY – Hz
100M
3
10
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
Figure 14. Large Signal Frequency Response
Figure 17. Input Voltage Noise Spectral Density
10
380
0.1%
8
6
4
360
340
0.01%
0.01%
1%
1%
2
0
–2
–4
–6
–8
–10
320
300
0.1%
0
20
40
60
80
100
120
140
160
–60 –40 –20
0
20
40
60
80
100 120 140
SETTLING TIME – ns
TEMPERATURE – °C
Figure 15. Output Swing and Error vs. Settling Tim e
Figure 18. Slew Rate vs. Tem perature
–6–
REV. B
AD817
0.05
0.04
1kΩ
DIFF GAIN
3.3µF
+VS
0.01µF
0.03
0.1
0.08
0.06
0.04
7
AD817
4
TEKTRONIX
7A24
PREAMP
TEKTRONIX
P6201 FET
PROBE
2
3
VOUT
HP
6
PULSE (LS)
OR FUNCTION
(SS)
100Ω
50Ω
VIN
DIFF PHASE
0.01µF
GENERATOR
RL
3.3µF
–VS
±5
±10
SUPPLY VOLTAGE – Volts
±15
Figure 19. Differential Gain and Phase vs.
Supply Voltage
Figure 22. Noninverting Am plifier Connection
5
50ns
5V
4
0.1dB
1kΩ
V
C
FLATNESS
S
C
1kΩ
CC
100
90
3
2
±15V 3pF
±5V 4pF
+5V 6pF
VOUT
VIN
16MHz
14MHz
12MHz
1
0
V
= ±15V
S
–1
–2
–3
–4
–5
V
V
= ±5V
S
10
0%
= +5V
S
5V
100k
1M
10M
100M
FREQUENCY – Hz
Figure 20. Closed-Loop Gain vs. Frequency,
Gain = –1
Figure 23. Noninverting Large Signal Pulse
Response, RL = 1 kΩ
5
200mV
20ns
0.1dB
4
3
2
1
1kΩ
V
FLATNESS
S
100
90
±15V
70MHz
±5V 26MHz
V
OUT
V
IN
150Ω
+5V
17MHz
V
= ±15V
S
0
–1
–2
–3
–4
–5
V
= ±5V
S
10
0%
V
= +5V
S
200mV
100k
1M
10M
FREQUENCY – Hz
100M
Figure 21. Closed-Loop Gain vs. Frequency,
Gain = +1
Figure 24. Noninverting Sm all Signal Pulse
Response, RL = 1 kΩ
REV. B
–7–
AD817–Typical Characteristics
5V
5V
50ns
50ns
100
90
100
90
10
10
0%
0%
5V
5V
Figure 25. Noninverting Large Signal Pulse
Figure 28. Inverting Large Signal Pulse
Response, RL = 150 Ω
Response, RL = 1 kΩ
200mV
20ns
200mV
50ns
100
90
100
90
10
10
0%
0%
200mV
200mV
Figure 26. Noninverting Sm all Signal Pulse
Figure 29. Inverting Sm all Signal Pulse
Response, RL = 150 Ω
Response, RL = 1 kΩ
1kΩ
3.3µF
+V
S
0.01µF
HP
PULSE (L
R
1kΩ
IN
)
SIG
V
IN
7
AD817
4
OR FUNCTION
(S
TEKTRONIX
7A24
PREAMP
TEKTRONIX
P6201 FET
PROBE
2
3
V
OUT
)
SIG
6
GENERATOR
50Ω
0.01µF
3.3µF
R
L
–V
S
Figure 27. Inverting Am plifier Connection
–8–
REV. B
AD817
+VS
D RIVING CAP ACITIVE LO AD S
T he internal compensation of the AD817, together with its high
output current drive, permit excellent large signal performance
while driving extremely high capacitive loads.
1kΩ
OUTPUT
3.3µF
CF
+VS
–IN
+IN
0.01µF
RIN
1kΩ
HP
PULSE
GENERATOR
VIN
7
AD817
4
TEKTRONIX
7A24
PREAMP
TEKTRONIX
P6201 FET
PROBE
2
3
VOUT
6
50Ω
0.01µF
3.3µF
CL
1000pF
–VS
NULL 1
NULL 8
–VS
Figure 31. Sim plified Schem atic
INP UT CO NSID ERATIO NS
Figure 30a. Inverting Am plifier Driving a 1000 pF
Capacitive Load
An input protection resistor (RIN in Figure 22) is required in cir-
cuits where the input to the AD817 will be subjected to tran-
sient or continuous overload voltages exceeding the +6 V
maximum differential limit. T his resistor provides protection for
the input transistors by limiting their maximum base current.
5V
500ns
100
90
100pF
For high performance circuits, it is recommended that a “bal-
ancing” resistor be used to reduce the offset errors caused by
bias current flowing through the input and feedback resistors.
T he balancing resistor equals the parallel combination of RIN
and RF and thus provides a matched impedance at each input
terminal. T he offset voltage error will then be reduced by more
than an order of magnitude.
10
1000pF
0%
5V
GRO UND ING & BYP ASSING
When designing high frequency circuits, some special precau-
tions are in order. Circuits must be built with short interconnect
leads. When wiring components, care should be taken to pro-
vide a low resistance, low inductance path to ground. Sockets
should be avoided, since their increased interlead capacitance
can degrade circuit bandwidth.
Figure 30b. Inverting Am plifier Pulse Response While
Driving Capacitive Loads
TH EO RY O F O P ERATIO N
T he AD817 is a low cost, wide band, high performance opera-
tional amplifier which effectively drives heavy capacitive or resis-
tive loads. It also provides a constant slew rate, bandwidth and
settling time over its entire specified temperature range.
Feedback resistors should be of low enough value (<1 kΩ) to
assure that the time constant formed with the inherent stray
capacitance at the amplifier’s summing junction will not limit
performance. T his parasitic capacitance, along with the parallel
resistance of RF/RIN, form a pole in the loop transmission which
may result in peaking. A small capacitance (1 pF–5 pF) may be
used in parallel with the feedback resistor to neutralize this effect.
T he AD817 (Figure 31) consists of a degenerated NPN differ-
ential pair driving matched PNPs in a folded-cascode gain stage.
T he output buffer stage employs emitter followers in a class AB
amplifier which delivers the necessary current to the load while
maintaining low levels of distortion.
Power supply leads should be bypassed to ground as close as
possible to the amplifier pins. Ceramic disc capacitors of 0.1 µF
are recommended.
T he capacitor, CF, in the output stage mitigates the effect of
capacitive loads. At low frequencies, and with low capacitive
loads, the gain from the compensation node to the output is
very close to unity. In this case, CF is bootstrapped and does not
contribute to the overall compensation capacitance of the device.
As the capacitive load is increased, a pole is formed with the
output impedance of the output stage. T his reduces the gain,
and therefore, CF is incompletely bootstrapped. Effectively,
some fraction of CF contributes to the overall compensation
capacitance, reducing the unity gain bandwidth. As the load
capacitance is further increased, the bandwidth continues to fall,
maintaining the stability of the amplifier.
+VS
2
3
7
6
AD817
8
1
4
10kΩ
VOS ADJUST
–VS
Figure 32. Offset Null Configuration
REV. B
–9–
AD817
O FFSET NULLING
Measuring the rapid settling time of AD817 (45 ns to 0.1% and
70 ns to 0.01%–10 V step) requires applying an input pulse with
a very fast edge and an extremely flat top. With the AD817 con-
figured in a gain of –1, a clamped false summing junction re-
sponds when the output error is within the sum of two diode
voltages (ª1 volt). T he signal is then amplified 20 times by a
clamped amplifier whose output is connected directly to a sam-
pling oscilloscope. Figures 33 and 34 show the settling time of
the AD817, with a 10 volt step applied.
T he input offset voltage of the AD817 is inherently very low.
However, if additional nulling is required, the circuit shown in
Figure 32 can be used. T he null range of the AD817 in this con-
figuration is ±15 mV.
AD 817 SETTLING TIME
Settling time is comprised primarily of two regions. T he first is
the slew time in which the amplifier is overdriven, where the
output voltage rate of change is at its maximum. T he second is
the linear time period required for the amplifier to settle to
within a specified percent of the final value.
0
–2
–4
–6
–8
–10
10
8
6
4
0.20
0.15
0.10
0.05
0
2
0
0.05
0
0.05
0.05
0.10
0.15
0.20
0
50
100 150 200 250 300 350 400
Figure 34. Settling Tim e in ns 0 V to –10 V
0
50
100 150 200 250 300 350 400
Figure 33. Settling Tim e in ns 0 V to +10 V
2×
HP2835
15pF
1MΩ
ERROR AMPLIFIER
V
OUTPUT × 10
ERROR
5
3
2
100Ω
2×
HP2835
SETTLING
OUTPUT
AD829
6
0.47µF
4
SHORT, DIRECT
7
CONNECTION TO
0.01µF
0.47µF
TEKTRONIX TYPE 11402
OSCILLOSCOPE PREAMP
INPUT SECTION
0.01µF
ERROR
SIGNAL
OUTPUT
+V
–V
S
S
100Ω
1.9kΩ
0 TO ±10V
POWER
SUPPLY
NOTE:
USE CIRCUIT BOARD
WITH GROUND PLANE
EI&S
DL1A05GM
MERCURY RELAY
FALSE
SUMMING
NODE
NULL
ADJUST
7, 8
1kΩ
100Ω
1kΩ
500Ω
2
50Ω
COAX
CABLE
DEVICE
UNDER
TEST
13
TTL LEVEL
5–18pF
SIGNAL
GENERATOR
50Hz
TEKTRONIX P6201
FET PROBE TO
TEKTRONIX TYPE
11402
1, 14
500Ω
2
3
OUTPUT
6
AD817
50Ω
OSCILLOSCOPE
PREAMP INPUT
SECTION
10pF
SCOPE PROBE
CAPACITANCE
7
4
0.01µF
2.2µF
DIGITAL
GROUND
0.01µF
2.2µF
+V
S
ANALOG
GROUND
–V
S
Figure 35. Settling Tim e Test Circuit
–10–
REV. B
AD817
+V
A H IGH P ERFO RMANCE AD C INP UT BUFFER
High performance analog to digital converters (ADCs) require
input buffers with correspondingly high bandwidths and very
low levels of distortion. T ypical requirements include distortion
levels of –60 dB to –70 dB for a 1 volt p-p signal and band-
widths of 10 MHz or more. In addition, an ADC buffer may
need to drive very large capacitive loads.
S
R3
1kΩ
3.3µF
SELECT C1, R1, R2 & R3
FOR DESIRED LOW
FREQUENCY CORNER.
(R2 = R1 + R3)
C2
0.1µF
0.01µF
R1
9kΩ
T he circuit of Figure 36 is useful for driving high speed convert-
ers such as the differential input of the AD733, 10-bit ADC.
T his circuit may be used with other converters with only minor
modifications. Using the AD817 provides the user with the op-
tion of either operating the buffer in differential mode or from a
single +5 volt supply. Operating from a +5 volt power supply
helps to avoid overdriving the ADC—a common problem with
buffers operating at higher supply voltages.
7
C
OUT
2
3
C1
0.1µF
6
V
AD817
OUT
V
R
150Ω
IN
L
4
C
L
200pF
R2
10kΩ
C3
0.1µF
Figure 37. Single Supply Am plifier Configuration
SINGLE SUP P LY O P ERATIO N
Combining R3 with C2 forms a low-pass filter with a corner
frequency of 1.5 kHz. T his is needed to maintain amplifier
PSRR, since the supply is connected to VIN through the input
divider. T he values for RL and CL were chosen to demonstrate
the AD817’s exceptional output drive capability. In this con-
figuration, the output is centered around 2.5 V. In order to
eliminate the static dc current associated with this level, C3 was
inserted in series with RL.
Another exciting feature of the AD817 is its ability to perform
well in a single supply configuration. T he AD817 is ideally
suited for applications that require low power dissipation and
high output current and those which need to drive large capaci-
tive loads, such as high speed buffering and instrumentation.
Referring to Figure 37, careful consideration should be given to
the proper selection of component values. T he choices for this
particular circuit are: R1+ R3//R2 combine with C1 to form a
low frequency corner of approximately 300 Hz.
1kΩ
+V
S
0.1µF
1kΩ
7
2
3
V
AD817
6
26
INA
50Ω
COAX
CABLE
0.1µF
4
V
IN
500mVp-p
MAX
AD773
–V
S
52.5Ω
10-BIT
18MHz
ADC
+V
S
0.1µF
7
3
2
AD817
6
27 V
INB
1kΩ
0.1µF
4
+V
+5V
COMMON
–5V
S
–V
S
100µF
25V
ADREF43
VOLTAGE
REFERENCE
+2.5V
1kΩ
100µF
25V
–V
S
Figure 36. A Differential Input Buffer for High Bandwidth ADCs
REV. B
–11–
AD817
H IGH SP EED D AC BUFFER
(10.24 V for a 1 kΩ resistor). Note that since the DAC gener-
ates a positive current to ground, the voltage at the amplifier
output will be negative. A 100 Ω series resistor between the
noninverting amplifier input and ground minimizes the offset
effects of op amp input bias currents.
T he wide bandwidth and fast settling time of the AD817 make
it a very good output buffer for high speed current output D/A
converters like the AD668. As shown in Figure 38, the op amp
establishes a summing node at ground for the DAC output. T he
output voltage is determined by the amplifier’s feedback resistor
+15V
10µF
TO ANALOG
GROUND PLANE
0.1µF
1
MSB
VCC 24
23
22
21
REFCOM
REFIN1
REFIN2
2
3
1V NOMINAL
REFERENCE INPUT
10kΩ
4
5
1kΩ
I OUT 20
100Ω
ANALOG
OUTPUT
AD668
DIGITAL
INPUTS
6
RLOAD
19
18
17
16
AD817
ANALOG GROUND PLANE
7
ACOM
LCOM
IBPO
ANALOG
SUPPLY
GROUND
8
10µF
9
0.1µF
–15V
10
11
12
15
14
V
EE
THCOM
VTH
1kΩ
100pF
+5V
LSB
13
Figure 38. High Speed DAC Buffer
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
8-P in P lastic Mini-D IP
(N-8)
8-P in SO IC
(SO -8)
8
5
0.25
(6.35)
8
1
5
4
0.31
(7.87)
PIN 1
0.1574 (4.00)
0.1497 (3.80)
PIN 1
1
4
0.2440 (6.20)
0.2284 (5.80)
0.30 (7.62)
REF
0.39 (9.91) MAX
0.1968 (5.00)
0.1890 (4.80)
0.035±0.01
(0.89±0.25)
0.0196 (0.50)
0.0099 (0.25)
x 45
°
0.165±0.01
(4.19±0.25)
0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0040 (0.10)
0.011±0.003
(0.28±0.08)
0.18±0.03
(4.57±0.76)
8
0
°
°
0.125
(3.18)
MIN
0.0500 (1.27)
0.0160 (0.41)
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0098 (0.25)
0.0075 (0.19)
15
°
0°
0.10
(2.54)
0.018±0.003
(0.46±0.08)
0.033
(0.84)
NOM
SEATING
PLANE
BSC
–12–
REV. B
相关型号：
AD817AREEL
IC OP-AMP, 4000 uV OFFSET-MAX, 50 MHz BAND WIDTH, PDSO8, PLASTIC, SOIC-8, Operational Amplifier
ADI
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