AD8227 [ADI]
Wide Supply Range, Rail-to-Rail Output Instrumentation Amplifier; 宽电源电压范围，轨到轨输出仪表放大器
| 型号： | AD8227 |
| 厂家： | 
ADI |
| 描述： | Wide Supply Range, Rail-to-Rail Output Instrumentation Amplifier |
| 文件： | 总24页 (文件大小：521K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Wide Supply Range, Rail-to-Rail
Output Instrumentation Amplifier
AD8227
FEATURES
PIN CONFIGURATION
Gain set with 1 external resistor
Gain range: 5 to 1000
Input voltage goes below ground
Inputs protected beyond supplies
Very wide power supply range
Single supply: 2.2 V to 36 V
AD8227
1
2
3
4
8
7
6
5
–IN
+V
S
R
R
V
OUT
G
G
REF
–V
+IN
S
TOP VIEW
(Not to Scale)
Dual supply: 1.5 V to 18 V
Bandwidth (G = 5): 250 kHz
Figure 1.
CMRR (G = 5): 100 dB minimum (B Grade)
Input noise: 24 nV/√Hz
Typical supply current: 350 μA
Specified temperature: −40°C to +125°C
8-lead SOIC and MSOP packages
Table 1. Instrumentation Amplifiers by Category1
General
Purpose
Zero
Drift
Military
Grade
Low
Power
High Speed
PGA
AD8220
AD8221
AD8222
AD8224
AD8228
AD8295
AD8231
AD8290
AD8293
AD8553
AD8556
AD8557
AD620
AD621
AD524
AD526
AD624
AD627
AD623
AD8223
AD8226
AD8227
AD8250
AD8251
AD8253
APPLICATIONS
Industrial process controls
Bridge amplifiers
Medical instrumentation
Portable data acquisition
Multichannel systems
1 See www.analog.com for the latest selection of instrumentation amplifiers.
GENERAL DESCRIPTION
The AD8227 is ideal for multichannel, space-constrained
applications. With its MSOP package and 125°C temperature
rating, the AD8227 thrives in tightly packed, zero airflow designs.
The AD8227 is a low cost, wide supply range instrumentation
amplifier that requires only one external resistor to set any gain
between 5 and 1000.
The AD8227 is available in 8-pin MSOP and SOIC packages.
It is fully specified for −40°C to +125°C operation.
The AD8227 is designed to work with a variety of signal voltages.
A wide input range and rail-to-rail output allow the signal to
make full use of the supply rails. Because the input range can
also go below the negative supply, small signals near ground can
be amplified without requiring dual supplies. The AD8227
operates on supplies ranging from 1.5 ꢀ to 18 ꢀ ꢁ2.2 ꢀ to
36 ꢀ single supply).
For a similar instrumentation amplifier with a gain range of 1 to
1000, see the AD8226.
The robust AD8227 inputs are designed to connect to real-
world sensors. In addition to its wide operating range, the
AD8227 can handle voltages beyond the rails. For example,
with a 5 ꢀ supply, the part is guaranteed to withstand 35 ꢀ
at the input with no damage. Minimum as well as maximum
input bias currents are specified to facilitate open wire detection.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2009 Analog Devices, Inc. All rights reserved.
AD8227
TABLE OF CONTENTS
Features .............................................................................................. 1
Gain Selection............................................................................. 19
Reference Terminal .................................................................... 20
Input ꢀoltage Range................................................................... 20
Layout .......................................................................................... 20
Input Bias Current Return Path ............................................... 21
Input Protection ......................................................................... 21
Radio Frequency Interference ꢁRFI)........................................ 21
Applications Information.............................................................. 22
Differential Drive ....................................................................... 22
Precision Strain Gage................................................................. 22
Driving an ADC ......................................................................... 23
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
Applications....................................................................................... 1
Pin Configuration............................................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 19
Architecture................................................................................. 19
REVISION HISTORY
5/09—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
AD8227
SPECIFICATIONS
+ꢀS = +15 ꢀ, −ꢀS = −15 ꢀ, ꢀREF = 0 ꢀ, TA = 25°C, G = 5, RL = 10 kΩ, specifications referred to input, unless otherwise noted.
Table 2.
Test Conditions/
Comments
A Grade
Typ
B Grade
Typ
Parameter
Min
Max
Min
Max
Unit
COMMON-MODE REJECTION RATIO VCM = −10 V to +10 V
DC to 60 Hz
G = 5
G = 10
G = 100
G = 1000
5 kHz
90
96
105
105
100
105
110
110
dB
dB
dB
dB
G = 5
G = 10
G = 100
G = 1000
80
86
86
86
80
86
86
86
dB
dB
dB
dB
NOISE
Total noise:
eN = √(eNI2 + (eNO/G)2)
Voltage Noise, 1 kHz
Input Voltage Noise, eNI
Output Voltage Noise, eNO
24
310
25
315
24
310
25
315
nV/√Hz
nV/√Hz
RTI
f = 0.1 Hz to 10 Hz
G = 5
G = 10
G = 100 to 1000
Current Noise
1.5
0.9
0.5
100
3
1.5
0.9
0.5
100
3
μV p-p
μV p-p
μV p-p
fA/√Hz
pA p-p
f = 1 kHz
f = 0.1 Hz to 10 Hz
VOLTAGE OFFSET
Total offset voltage:
V
OS = VOSI + (VOSO/G)
Input Offset, VOSI
Average Temperature Drift
Output Offset, VOSO
Average Temperature Drift
Offset RTI vs. Supply (PSR)
G = 5
G = 10
G = 100
G = 1000
VS = 5 V to 15 V
TA = −40°C to +125°C
VS = 5 V to 15 V
TA = −40°C to +125°C
VS = 5 V to 15 V
200
2
1000
10
100
1
500
5
μV
μV/°C
μV
0.2
2
0.2
2
μV/°C
90
96
105
105
100
105
110
110
dB
dB
dB
dB
INPUT CURRENT
Input Bias Current1
TA = +25°C
TA = +125°C
TA = −40°C
TA = −40°C to +125°C
TA = +25°C
5
5
5
20
15
30
70
27
25
35
5
5
5
20
15
30
70
27
25
35
nA
nA
nA
pA/°C
nA
Average Temperature Drift
Input Offset Current
1.5
1.5
2
1.5
1.5
2
TA = +125°C
TA = −40°C
nA
nA
Average Temperature Drift
REFERENCE INPUT
RIN
TA = −40°C to +125°C
5
5
pA/°C
60
12
60
12
kΩ
μA
V
IIN
Voltage Range
−VS
+VS
−VS
+VS
Reference Gain to Output
Reference Gain Error
1
0.01
1
0.01
V/V
%
Rev. 0 | Page 3 of 24
AD8227
Test Conditions/
Comments
A Grade
Typ
B Grade
Typ
Parameter
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G = 5
Min
Max
Min
Max
Unit
250
200
50
250
200
50
kHz
kHz
kHz
kHz
G = 10
G = 100
G = 1000
5
5
Settling Time 0.01%
G = 5
10 V step
14
14
μs
G = 10
15
15
μs
G = 100
35
35
μs
G = 1000
275
0.8
275
0.8
μs
V/μs
Slew Rate2
GAIN3
G = 5 to 100
G = 5 + (80 kΩ/RG)
Gain Range
Gain Error
5
1000
5
1000
V/V
VOUT = −10 V to +10 V
G = 5
0.04
0.3
0.02
0.15
%
%
G = 10 to 1000
Gain Nonlinearity
G = 5
G = 10
G = 100
VOUT = −10 V to +10 V
RL ≥ 2 kΩ
RL ≥ 2 kΩ
RL ≥ 2 kΩ
RL ≥ 2 kΩ
10
15
15
750
10
15
50
150
ppm
ppm
ppm
ppm
G = 1000
Gain vs. Temperature
G = 5
G > 5
TA = −40°C to +125°C
5
5
ppm/°C
ppm/°C
−100
−100
INPUT
VS = 1.5 V to +36 V
Impedance
Differential
Common Mode
Operating Voltage Range4
0.8||2
0.4||2
0.8||2
0.4||2
GΩ||pF
GΩ||pF
V
V
V
V
TA = +25°C
TA = +125°C
TA = −40°C
TA = −40°C to +125°C
−VS − 0.1
−VS − 0.05
−VS − 0.15
+VS − 40
+VS − 0.8 −VS − 0.1
+VS − 0.6 −VS − 0.05
+VS − 0.9 −VS − 0.15
+VS − 0.8
+VS − 0.6
+VS − 0.9
−VS + 40
Overvoltage Range
OUTPUT
−VS + 40
+VS − 40
Output Swing
RL = 10 kΩ to ground
TA = −40°C to +85°C
TA = +85°C to +125°C
TA = −40°C to +125°C
−VS + 0.2
−VS + 0.2
−VS + 0.1
+VS − 0.2 −VS + 0.2
+VS − 0.3 −VS + 0.2
+VS − 0.1 −VS + 0.1
+VS − 0.2
+VS − 0.3
+VS − 0.1
V
V
V
mA
RL = 100 kΩ to ground
Short-Circuit Current
POWER SUPPLY
13
13
Operating Range
Quiescent Current
Dual-supply operation
TA = +25°C
TA = −40°C
TA = +85°C
TA = +125°C
1.5
18
425
325
525
600
+125
1.5
18
425
325
525
600
+125
V
350
250
450
525
350
250
450
525
μA
μA
μA
μA
°C
TEMPERATURE RANGE
−40
−40
1 The input stage uses pnp transistors, so input bias current always flows into the part.
2 At high gains, the part is bandwidth limited rather than slew rate limited.
3 For G > 5, gain error specifications do not include the effects of External Resistor RG.
4 Input voltage range of the AD8227 input stage. The input range depends on the common-mode voltage, differential voltage, gain, and reference voltage. See the
Input Voltage Range section for more information.
Rev. 0 | Page 4 of 24
AD8227
+ꢀS = 2.7 ꢀ, −ꢀS = 0 ꢀ, ꢀREF = 0 ꢀ, TA = 25°C, G = 5, RL = 10 kΩ, specifications referred to input, unless otherwise noted.
Table 3.
Test Conditions/
Comments
A Grade
Typ
B Grade
Typ
Parameter
Min
Max
Min
Max
Unit
COMMON-MODE REJECTION RATIO VCM = 0 V to 1.7 V
DC to 60 Hz
G = 5
G = 10
G = 100
G = 1000
5 kHz
90
96
105
105
100
105
110
110
dB
dB
dB
dB
G = 5
G = 10
G = 100
G = 1000
80
86
86
86
80
86
86
86
dB
dB
dB
dB
NOISE
Total noise:
eN = √(eNI2 + (eNO/G)2)
Voltage Noise, 1 kHz
Input Voltage Noise, eNI
Output Voltage Noise, eNO
25
310
28
330
25
310
28
330
nV/√Hz
nV/√Hz
RTI
f = 0.1 Hz to 10 Hz
G = 5
G = 10
G = 100 to 1000
Current Noise
1.5
0.8
0.5
100
3
1.5
0.8
0.5
100
3
μV p-p
μV p-p
μV p-p
fA/√Hz
pA p-p
f = 1 kHz
f = 0.1 Hz to 10 Hz
VOLTAGE OFFSET
Total offset voltage:
VOS = VOSI + (VOSO/G)
Input Offset, VOSI
Average Temperature Drift
Output Offset, VOSO
Average Temperature Drift
Offset RTI vs. Supply (PSR)
G = 5
G = 10
G = 100
G = 1000
VS = 0 V to 1.7 V
TA = −40°C to +125°C
VS = 0 V to 1.7 V
TA = −40°C to +125°C
VS = 0 V to 1.7 V
200
2
1000
10
100
1
500
5
μV
μV/°C
μV
0.2
2
0.2
2
μV/°C
90
96
105
105
100
105
110
110
dB
dB
dB
dB
INPUT CURRENT
Input Bias Current1
TA = +25°C
TA = +125°C
TA = −40°C
TA = −40°C to +125°C
TA = +25°C
5
5
5
20
15
30
70
27
25
35
5
5
5
20
15
30
70
27
25
35
nA
nA
nA
pA/°C
nA
Average Temperature Drift
Input Offset Current
1.5
1.5
2
1.5
1.5
2
TA = +125°C
TA = −40°C
nA
nA
Average Temperature Drift
REFERENCE INPUT
RIN
TA = −40°C to +125°C
5
5
pA/°C
60
12
60
12
kΩ
μA
V
IIN
Voltage Range
−VS
+VS
−VS
+VS
Reference Gain to Output
Reference Gain Error
1
0.01
1
0.01
V/V
%
Rev. 0 | Page 5 of 24
AD8227
Test Conditions/
Comments
A Grade
Typ
B Grade
Typ
Parameter
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G = 5
Min
Max
Min
Max
Unit
250
200
50
250
200
50
kHz
kHz
kHz
kHz
G = 10
G = 100
G = 1000
5
5
Settling Time 0.01%
G = 5
2 V step
6
6
μs
G = 10
6
6
μs
G = 100
G = 1000
Slew Rate2
GAIN3
30
275
0.6
30
275
0.6
μs
μs
V/μs
G = 5 to 10
G = 5 + (80 kΩ/RG)
Gain Range
Gain Error
G = 5
G = 10 to 1000
Gain vs. Temperature
G = 5
5
1000
5
1000
V/V
VOUT = 0.8 V to 1.8 V
VOUT = 0.2 V to 2.5 V
TA = −40°C to +125°C
0.04
0.3
0.04
0.3
%
%
5
5
ppm/°C
ppm/°C
G > 5
−100
−100
INPUT
−VS = 0 V; +VS = 2.7 V to
36 V
Impedance
Differential
Common Mode
Operating Voltage Range4
0.8||2
0.4||2
0.8||2
0.4||2
GΩ||pF
GΩ||pF
V
V
V
V
TA = +25°C
TA = −40°C
TA = +125°C
TA = −40°C to +125°C
−0.1
+VS − 0.7
+VS − 0.9
+VS − 0.6
−VS + 40
−0.1
+VS − 0.7
+VS − 0.9
+VS − 0.6
−VS + 40
−0.15
−0.05
+VS − 40
−0.15
−0.05
+VS − 40
Overvoltage Range
OUTPUT
Output Swing
RL = 2 kΩ to 1.35 V
RL = 10 kΩ to 1.35 V
Short-Circuit Current
POWER SUPPLY
TA = −40°C to +125°C
0.2
0.1
+VS − 0.2
+VS − 0.1
0.2
0.1
+VS − 0.2
+VS − 0.1
V
V
mA
13
13
Operating Range
Quiescent Current
Single-supply operation
+VS = 2.7 V
2.2
36
2.2
36
V
TA = +25°C
TA = −40°C
TA = +85°C
TA = +125°C
325
250
425
475
400
325
500
550
+125
325
250
425
475
400
325
500
550
+125
μA
μA
μA
μA
°C
TEMPERATURE RANGE
−40
−40
1 Input stage uses pnp transistors, so input bias current always flows into the part.
2 At high gains, the part is bandwidth limited rather than slew rate limited.
3 For G > 5, gain error specifications do not include the effects of External Resistor RG.
4 Input voltage range of the AD8227 input stage. The input range depends on the common-mode voltage, differential voltage, gain, and reference voltage. See the
Input Voltage Range section for more information.
Rev. 0 | Page 6 of 24
AD8227
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
θJA is specified for a device in free air.
Parameter
Rating
Supply Voltage
18 V
Table 5.
Package
Output Short-Circuit Current
Maximum Voltage at −IN or +IN
Minimum Voltage at −IN or +IN
REF Voltage
Indefinite
−VS + 40 V
+VS − 40 V
VS
θJA
Unit
°C/W
°C/W
8-Lead MSOP, 4-Layer JEDEC Board
8-Lead SOIC, 4-Layer JEDEC Board
135
121
Storage Temperature Range
Operating Temperature Range
Maximum Junction Temperature
−65°C to +150°C
−40°C to +125°C
140°C
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 7 of 24
AD8227
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD8227
1
2
3
4
8
7
6
5
–IN
+V
S
R
R
V
OUT
G
G
REF
–V
+IN
S
TOP VIEW
(Not to Scale)
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
Negative Input.
1
−IN
2, 3
4
RG
+IN
Gain Setting Pins. Place a gain resistor between these two pins.
Positive Input.
5
−VS
Negative Supply.
6
REF
Reference. This pin must be driven by low impedance.
7
8
VOUT
+VS
Output.
Positive Supply.
Rev. 0 | Page 8 of 24
AD8227
TYPICAL PERFORMANCE CHARACTERISTICS
T = 25°C, ꢀS = 15 ꢀ, RL = 10 kꢂ, unless otherwise noted.
500
400
300
200
100
0
MEAN: 15.9
SD: 196.50
MEAN: 0.0668
SD: 0.065827
1000
800
600
400
200
0
–900
–600
–300
0
300
600
900
–0.9
–0.6
–0.3
0
0.3
0.6
0.9
OUTPUT V (µV)
INPUT V DRIFT (µV)
OS
OS
Figure 3. Typical Distribution of Output Offset Voltage
Figure 6. Typical Distribution of Input Offset Voltage Drift, G = 100
MEAN: 20.4
SD: 0.5893
MEAN: –0.701
SD: 0.676912
1000
700
600
500
400
300
200
800
600
400
200
0
100
0
–6
–4
–2
0
2
4
6
16
18
20
22
(nA)
24
26
POSITIVE I
OUTPUT V DRIFT (µV)
BIAS
OS
Figure 7. Typical Distribution of Input Bias Current
Figure 4. Typical Distribution of Output Offset Voltage Drift
MEAN: –5.90
SD: 15.8825
MEAN: –0.027
SD: 0.079173
1000
1000
800
800
600
600
400
200
0
400
200
0
–200
–150 –100
–50
0
50
100
150
200
–0.9
–0.6
–0.3
0
0.3
0.6
0.9
INPUT V (µV)
I
(nA)
OS
OS
Figure 5. Typical Distribution of Input Offset Voltage
Figure 8. Typical Distribution of Input Offset Current
Rev. 0 | Page 9 of 24
AD8227
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.6
+0.02V, +1.5V
+0.02V, +1.5V
V
= 0V
V
= 0V
REF
REF
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
+2.67V, +1.2V
+2.67V, +1.2V
+0.02V, +1.35V
+0.02V, +1.35V
V
+2.67V, +1.1V
+2.7V, +1.1V
V
= 1.35V
= 1.35V
REF
REF
+2.7V, 0V
+0.02V, –0.15V
+0.02V, –0.3V
+2.67V, –0.25V
+2.67V, –0.25V
2.5 3.0
+0.02V, –0.25V
+0.02V, –0.3V
–0.2
–0.4
–0.2
–0.4
+2.67V, –0.15V
+1.35V, –0.3V
1.5 2.0
+1.35V, –0.3V
1.5 2.0
OUTPUT VOLTAGE (V)
–0.5
0
0.5
1.0
–0.5
0
0.5
1.0
2.5
3.0
OUTPUT VOLTAGE (V)
Figure 9. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, Vs = 2.7 V, G = 5
Figure 12. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, Vs = 2.7 V, G = 100
5
5
V
= 0V
V
= 0V
REF
REF
+0.02V, +4.25V
+0.02V, +4V
+0.02V, +4.25V
+0.02V, +4V
+4.96V, +3.75V
4
3
2
+4.96V, +3.75V
+4.96V, +3.5V
4
3
2
1
+4.96V, +3.5V
V
= 2.5V
V
= 2.5V
REF
REF
1
0
+4.96V, +0.2V
+4.96V, –0.05V
+0.01V, –0.05V
+0.02V, –0.3V
+4.96V, –0.2V
+4.96V, –0.25V
0
+0.02V, –0.25V
+0.02V, –0.3V
+2.5V, –0.3V
+2.5V, –0.3V
–1
–1
–0.5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
OUTPUT VOLTAGE (V)
–0.5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
OUTPUT VOLTAGE (V)
Figure 10. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, Vs = 5 V, G = 5
Figure 13. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, Vs = 5 V, G = 100
6
6
0V, +4.2V
0V, +4.2V
–4.98V, +3.7V
+4.96V, +3.7V
–4.96V, +3.75V
4
2
0
4
2
0
+4.96V, +3.25V
–2
–4
–6
–2
–4
–6
0V, –5.3V
0
0V, –5.3V
0
–4.97V, –4.8V
–6 –4
+4.96V, –4.8V
4
–4.96V, –5.1V
–4
+4.96V, –5.1V
4 6
–2
2
6
–6
–2
2
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Figure 11. Input Common-Mode Voltage vs. Output Voltage,
Dual Supply, Vs = 5 V, G = 5
Figure 14. Input Common-Mode Voltage vs. Output Voltage,
Dual Supply, Vs = 5 V, G = 100
Rev. 0 | Page 10 of 24
AD8227
20
16
14
12
10
8
0.5
0.4
0.3
0.2
0.1
V
= ±15V, G = 5
V
= ±15V
S
S
0V, +14.2V
0V, +11.2V
15
10
5
+14.94V, +12.7V
–14.96V, +12.7V
V
OUT
–11.96V,
+10V
+11.94V,
+10V
6
4
2
I
IN
V
= ±12V
0
0
–2
0
S
–0.1
–0.2
–0.3
–5
–10
–15
–20
–4
–6
–11.96V,
–11.1V
+11.94V,
–11.1V
–8
–10
–12
0V, –12.3V
0V, –15.3V
–0.4
–0.5
–14.96V, –13.8V
+14.94V, –13.8V
–14
–16
–20
–15
–10
–5
0
5
10
15
20
–40 –35 –30 –25 –20 –15 –10 –5
0
5
10 15 20 25 30 35 40
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 15. Input Common-Mode Voltage vs. Output Voltage,
Dual Supply, Vs = 15 V, G = 5
Figure 18. Input Overvoltage Performance, G = 5, Vs = 15 V
20
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
0.6
0.5
0.4
0.3
0.2
0.1
0
V
= 2.7V, G = 100
V
= ±15V
S
S
0V, +14.2V
0V, +11.2V
15
10
5
+14.94V, +12.7V
–14.96V, +12.7V
V
OUT
–11.96V,
+10V
+11.94V,
+10V
V
= ±12V
0
S
I
IN
–0.1
–5
–10
–15
–20
1.00
0.75
–0.2
–0.3
–11.96V,
–11.3V
+11.94V,
–11.3V
0.50
0.25
0
–0.4
–0.5
–0.6
0V, –12.3V
0V, –15.3V
–14.96V, –14V
–15 –10
+14.94V, –14V
10 15 20
–20
–5
0
5
–40 –35 –30 –25 –20 –15 –10 –5
0
5
10 15 20 25 30 35 40
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 16. Input Common-Mode Voltage vs. Output Voltage,
Dual Supply, Vs = 15 V, G = 100
Figure 19. Input Overvoltage Performance, G = 100, Vs = 2.7 V
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
0.6
0.5
0.4
0.3
0.2
0.1
0
16
14
12
10
8
0.5
0.4
0.3
0.2
0.1
V
= 2.7V, G = 5
V
= ±15V, G = 100
S
S
V
OUT
V
OUT
6
4
2
0
–2
0
I
IN
I
IN
–0.1
–0.1
–0.2
–0.3
–4
1.00
0.75
–0.2
–0.3
–6
–8
–10
–12
0.50
0.25
0
–0.4
–0.5
–0.6
–0.4
–0.5
–14
–16
–40 –35 –30 –25 –20 –15 –10 –5
0
5
10 15 20 25 30 35 40
–40 –35 –30 –25 –20 –15 –10 –5
0
5
10 15 20 25 30 35 40
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 17. Input Overvoltage Performance, G = 5, Vs = 2.7 V
Figure 20. Input Overvoltage Performance, G = 100, Vs = 15 V
Rev. 0 | Page 11 of 24
AD8227
33
31
29
27
25
23
21
19
17
15
140
120
–0.14V
G = 1000
100
80
G = 100
+4.23V
60
G = 10
G = 5
40
20
0
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0.1
1
10
100
1k
10k
100k
COMMON-MODE VOLTAGE (V)
FREQUENCY (Hz)
Figure 21. Input Bias Current vs. Common-Mode Voltage, Vs = 5 V
Figure 24. Negative PSRR vs. Frequency
40
70
60
–15.01V
35
G = 1000
50
30
25
G = 100
40
30
+14.03V
G = 10
G = 5
20
20
10
15
10
5
0
–10
–20
–30
0
–16
–12
–8
–4
0
4
8
12
16
100
1k
10k
100k
1M
10M
COMMON-MODE VOLTAGE (V)
FREQUENCY (Hz)
Figure 22. Input Bias Current vs. Common-Mode Voltage, Vs = 15 V
Figure 25. Gain vs. Frequency, VS = 15 V
160
70
60
G = 1000
G = 1000
G = 100
140
G = 10
50
120
G = 100
G = 5
40
100
80
60
40
20
0
30
G = 10
G = 5
20
10
0
–10
–20
–30
0.1
1
10
100
1k
10k
100k
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 23. Positive PSRR vs. Frequency, RTI
Figure 26. Gain vs. Frequency, VS = 2.7 V
Rev. 0 | Page 12 of 24
AD8227
160
35
30
25
20
15
10
5
150
V
V
= ±15V
= 0V
–IN BIAS CURRENT
+IN BIAS CURRENT
OFFSET CURRENT
S
G = 1000
G = 100
REF
140
120
100
80
125
100
75
50
25
0
G = 10
G = 5
60
40
20
0
0.1
1
10
100
1k
10k
100k
–45 –30 –15
0
15 30 45 60 75 90 105 120 135
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 27. CMRR vs. Frequency, RTI
Figure 30. Input Bias Current and Offset Current vs. Temperature
300
200
160
140
120
100
80
G = 1000
G = 100
G = 10
G = 5
100
0
60
40
20
0
–100
–200
–300
–20
–40
0
20
40
60
80
100
120
0.1
1
10
100
1k
10k
100k
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 28. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance
Figure 31. Gain Error vs. Temperature, G = 5
0.3
10
8
0.2
0.1
0
6
4
2
0
–2
–4
–0.1
–0.2
–0.3
–6
–8
–10
–40
0
10 20 30 40 50 60 70
80 90 100 110 120
–20
0
20
40
60
80
100
120
WARM-UP TIME (s)
TEMPERATURE (°C)
Figure 29. Change in Input Offset Voltage vs. Warm-Up Time
Figure 32. CMRR vs. Temperature, G = 5
Rev. 0 | Page 13 of 24
AD8227
+V
15
10
5
S
–40°C
+25°C
+85°C
+105°C
+125°C
–0.2
–0.4
–0.6
–0.8
–40°C
+25°C
+85°C
+105°C
+125°C
0
–V
S
–5
–10
–15
–0.2
–0.4
–0.6
–0.8
100
1k
10k
100k
2
4
6
8
10
12
14
16
18
LOAD (Ω)
SUPPLY VOLTAGE (±V )
S
Figure 33. Input Voltage Limit vs. Supply Voltage
Figure 36. Output Voltage Swing vs. Load Resistance
+V
+V
S
S
–0.1
–0.2
–0.3
–0.4
–0.2
–0.4
–0.6
–0.8
–40°C
+25°C
+85°C
+105°C
+125°C
–40°C
+25°C
+85°C
+105°C
+125°C
+0.4
+0.3
+0.2
+0.1
+0.8
+0.6
+0.4
+0.2
–V
–V
S
S
2
4
6
8
10
12
14
16
18
0.01
0.1
1
10
SUPPLY VOLTAGE (±V )
OUTPUT CURRENT (mA)
S
Figure 34. Output Voltage Swing vs. Supply Voltage, RL = 10 kΩ
Figure 37. Output Voltage Swing vs. Output Current
40
+V
S
G = 5
–0.2
–0.4
30
20
10
0
–40°C
+25°C
+85°C
+105°C
+125°C
–0.6
–0.8
–1.0
–1.2
+1.2
+1.0
+0.8
+0.6
+0.4
+0.2
–10
–20
–30
–40
–V
S
–10
–8
–6
–4
–2
0
2
4
6
8
10
2
4
6
8
10
12
14
16
18
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (±V )
S
Figure 35. Output Voltage Swing vs. Supply Voltage, RL = 2 kΩ
Figure 38. Gain Nonlinearity, G = 5, RL ≥ 2 kΩ
Rev. 0 | Page 14 of 24
AD8227
40
1k
G = 10
30
20
10
0
100
G = 5 (67nV/ Hz)
–10
–20
–30
–40
G = 10 (40nV/ Hz)
G = 100 (26nV/ Hz)
G = 1000 (25nV/ Hz)
BANDWIDTH
LIMITED
10
–10
–8
–6
–4
–2
0
2
4
6
8
10
1
10
100
1k
10k
100k
OUTPUT VOLTAGE (V)
FREQUENCY (Hz)
Figure 39. Gain Nonlinearity, G = 10, RL ≥ 2 kΩ
Figure 42. Voltage Noise Spectral Density vs. Frequency
160
G = 1000, 200nV/DIV
G = 100
120
80
40
0
G = 5, 1µV/DIV
–40
–80
–120
–160
–10
–8
–6
–4
–2
0
2
4
6
8
10
OUTPUT VOLTAGE (V)
Figure 43. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 5, G = 1000
Figure 40. Gain Nonlinearity, G = 100, RL ≥ 2 kΩ
1k
400
G = 1000
300
200
100
0
100
–100
–200
–300
–400
10
1
10
100
1k
10k
–10
–8
–6
–4
–2
0
2
4
6
8
10
FREQUENCY (Hz)
OUTPUT VOLTAGE (V)
Figure 44. Current Noise Spectral Density vs. Frequency
Figure 41. Gain Nonlinearity, G = 1000, RL ≥ 2 kΩ
Rev. 0 | Page 15 of 24
AD8227
5V/DIV
13.8µs TO 0.01%
16.8µs TO 0.001%
0.002%/DIV
40µs/DIV
1.5pA/DIV
1s/DIV
Figure 45. 0.1 Hz to 10 Hz Current Noise
Figure 48. Large-Signal Pulse Response and Settling Time, G = 10,
10 V Step, VS = 15 V
30
25
20
15
10
5
5V/DIV
35µs TO 0.01%
50µs TO 0.001%
0.002%/DIV
40µs/DIV
0
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 46. Large-Signal Frequency Response
Figure 49. Large-Signal Pulse Response and Settling Time, G = 100,
10 V Step, VS = 15 V
5V/DIV
5V/DIV
275µs TO 0.01%
350µs TO 0.001%
13.4µs TO 0.01%
16.6µs TO 0.001%
0.002%/DIV
0.002%/DIV
40µs/DIV
200µs/DIV
Figure 50. Large-Signal Pulse Response and Settling Time, G = 1000,
10 V Step, VS = 15 V
Figure 47. Large-Signal Pulse Response and Settling Time, G = 5,
10 V Step, VS = 15 V
Rev. 0 | Page 16 of 24
AD8227
20mV/DIV
4µs/DIV
20mV/DIV
20µs/DIV
Figure 51. Small-Signal Pulse Response, G = 5, RL = 10 kΩ, CL = 100 pF
Figure 53. Small-Signal Pulse Response, G = 100, RL = 10 kΩ, CL = 100 pF
20mV/DIV
4µs/DIV
20mV/DIV
100µs/DIV
Figure 52. Small-Signal Pulse Response, G = 10, RL = 10 kΩ, CL = 100 pF
Figure 54. Small-Signal Pulse Response, G = 1000, RL = 10 kΩ, CL = 100 pF
Rev. 0 | Page 17 of 24
AD8227
340
330
C
= 47pF
L
NO LOAD
320
310
300
290
C
= 100pF
L
C
= 147pF
L
20mV/DIV
4µs/DIV
0
2
4
6
8
10
12
14
16
18
SUPPLY VOLTAGE (±V )
S
Figure 55. Small-Signal Pulse Response with Various Capacitive Loads,
G = 5, RL = Infinity
Figure 57. Supply Current vs. Supply Voltage
35
30
25
SETTLED TO 0.001%
20
15
SETTLED TO 0.01%
10
5
0
2
4
6
8
10
12
14
16
18
20
STEP SIZE (V)
Figure 56. Settling Time vs. Step Size, VS = 15 V, Dual Supply
Rev. 0 | Page 18 of 24
AD8227
THEORY OF OPERATION
+V
–V
+V
–V
S
S
R
G
NODE 3
NODE 4
R3
50kΩ
S
S
R1
8kΩ
R2
8kΩ
+V
–V
S
R4
10kΩ
NODE 2
V
A3
OUT
+V
–V
NODE 1
R5
10kΩ
S
R6
50kΩ
S
ESD AND
OVERVOLTAGE
PROTECTION
ESD AND
OVERVOLTAGE
PROTECTION
REF
Q1
Q2
+IN
–IN
A1
A2
S
V
R
R
BIAS
B
B
–V
DIFFERENCE
AMPLIFIER STAGE
S
GAIN STAGE
Figure 58. Simplified Schematic
ARCHITECTURE
GAIN SELECTION
The AD8227 is based on the classic three op amp topology. This
topology has two stages: a preamplifier to provide differential
amplification followed by a difference amplifier that removes
the common-mode voltage and provides additional amplifica-
tion. Figure 58 shows a simplified schematic of the AD8227.
Placing a resistor across the RG terminals sets the gain of the
AD8227. The gain can be calculated by referring to Table 7 or
by using the following gain equation:
80 kΩ
RG =
G − 5
The first stage works as follows. To maintain a constant voltage
across the bias resistor, RB, Amplifier A1 must keep Node 3 at a
constant diode drop above the positive input voltage. Similarly,
Amplifier A2 keeps Node 4 at a constant diode drop above the
negative input voltage. Therefore, a replica of the differential
input voltage is placed across the gain setting resistor, RG. The
current that flows across this resistance must also flow through
the R1 and R2 resistors, creating a gained differential signal
between the A2 and A1 outputs. Note that, in addition to a
gained differential signal, the original common-mode signal,
shifted a diode drop up, is also still present.
Table 7. Gains Achieved Using Common Resistor Values
Standard Table Value of RG
Calculated Gain
No resistor
100 kΩ
49.9 kΩ
26.7 kΩ
20 kΩ
5
5.8
6.6
8
9
16 kΩ
10
10 kΩ
13
5.36 kΩ
2 kΩ
19.9
45
The second stage is a difference amplifier, composed of
Amplifier A3 and the R3 through R6 resistors. This stage
removes the common-mode signal from the amplified
differential signal and gains it by 5.
1.78 kΩ
1 kΩ
49.9
85
845 Ω
412 Ω
162 Ω
80.6 Ω
99.7
199
499
998
The transfer function of the AD8227 is
V
OUT = G × ꢁVIN+ − VIN−) + VREF
where:
The AD8227 defaults to G = 5 when no gain resistor is used.
The tolerance and gain drift of the RG resistor should be added
to the specifications of the AD8227 to determine the total gain
accuracy of the system. When the gain resistor is not used, gain
error and gain drift are minimal.
80 kΩ
G = 5 +
RG
Rev. 0 | Page 19 of 24
AD8227
Common-Mode Rejection Ratio over Frequency
REFERENCE TERMINAL
Poor layout can cause some of the common-mode signals to be
converted to differential signals before reaching the in-amp.
Such conversions occur when one input path has a frequency
response that is different from the other. To keep CMRR over
frequency high, the input source impedance and capacitance of
each path should be closely matched. Additional source resis-
tance in the input path ꢁfor example, for input protection) should
be placed close to the in-amp inputs, which minimizes the
interaction of the source resistance with parasitic capacitance
from the PCB traces.
The output voltage of the AD8227 is developed with respect to
the potential on the reference terminal. This is useful when the
output signal needs to be offset to a precise midsupply level. For
example, a voltage source can be tied to the REF pin to level-
shift the output so that the AD8227 can drive a single-supply
ADC. The REF pin is protected with ESD diodes and should
not exceed either +ꢀS or −ꢀS by more than 0.3 ꢀ.
For best performance, source impedance to the REF terminal
should be kept below 2 ꢂ. As shown in Figure 58, the reference
terminal, REF, is at one end of a 50 kΩ resistor. Additional imped-
ance at the REF terminal adds to this 50 kΩ resistor and results
in amplification of the signal connected to the positive input.
The amplification from the additional RREF can be calculated as
follows:
Parasitic capacitance at the gain setting pins can also affect CMRR
over frequency. If the board design has a component at the gain
setting pins ꢁfor example, a switch or jumper), the component
should be chosen so that the parasitic capacitance is as small as
possible.
6ꢁ50 kΩ + RREF)/ꢁ60 kΩ + RREF
)
Power Supplies
Only the positive signal path is amplified; the negative path
is unaffected. This uneven amplification degrades CMRR.
A stable dc voltage should be used to power the instrumentation
amplifier. Noise on the supply pins can adversely affect perfor-
mance. See the PSRR performance curves in Figure 23 and
Figure 24 for more information.
INCORRECT
CORRECT
A 0.1 μF capacitor should be placed as close as possible to each
supply pin. As shown in Figure 61, a 10 μF tantalum capacitor
can be used farther away from the part. In most cases, it can be
shared by other precision integrated circuits.
AD8227
AD8227
REF
REF
V
V
+
+V
OP1177
–
S
0.1µF
10µF
Figure 59. Driving the Reference Pin
+IN
–IN
INPUT VOLTAGE RANGE
V
OUT
R
G
Most instrumentation amplifiers have a very limited output
voltage swing when the common-mode voltage is near the
upper or lower limit of the part’s input range. The AD8227 has
very little of this limitation. See Figure 9 through Figure 16 for
the input common-mode range vs. output voltage of the part.
AD8227
LOAD
REF
0.1µF
10µF
LAYOUT
–V
S
Figure 61. Supply Decoupling, REF, and Output Referred to Local Ground
To ensure optimum performance of the AD8227 at the PCB
level, care must be taken in the design of the board layout. The
pins of the AD8227 are arranged in a logical manner to aid in
this task.
References
The output voltage of the AD8227 is developed with respect to
the potential on the reference terminal. Care should be taken to
tie REF to the appropriate local ground.
1
2
3
4
8
7
6
5
+V
V
–IN
S
R
G
OUT
R
REF
G
+IN
–V
S
AD8227
TOP VIEW
(Not to Scale)
Figure 60. Pinout Diagram
Rev. 0 | Page 20 of 24
AD8227
The other AD8227 terminals should be kept within the supplies.
All terminals of the AD8227 are protected against ESD.
INPUT BIAS CURRENT RETURN PATH
The input bias current of the AD8227 must have a return path to
ground. When the source, such as a thermocouple, cannot provide
a return current path, one should be created, as shown in Figure 62.
For applications where the AD8227 encounters voltages beyond
the allowed limits, external current limiting resistors and low
leakage diode clamps such as the BAꢀ199L, the FJH1100s, or
the SP720 should be used.
INCORRECT
+V
CORRECT
+V
S
S
RADIO FREQUENCY INTERFERENCE (RFI)
RF rectification is often a problem when amplifiers are used in
applications that have strong RF signals. The disturbance can
appear as a small dc offset voltage. High frequency signals can
be filtered with a low-pass RC network placed at the input of
the instrumentation amplifier, as shown in Figure 63. The filter
limits the input signal bandwidth, according to the following
relationship:
AD8227
AD8227
REF
REF
REF
REF
–V
S
–V
S
TRANSFORMER
TRANSFORMER
1
+V
+V
S
S
FilterFrequencyDIFF
FilterFrequencyCM
=
2πRꢁ2CD +CC )
1
=
2πRCC
AD8227
AD8227
REF
where CD ≥ 10 CC.
10MΩ
+V
S
–V
–V
S
S
0.1µF
+IN
10µF
THERMOCOUPLE
THERMOCOUPLE
C
1nF
C
+V
+V
S
S
R
4.02kΩ
C
C
C
V
C
D
10nF
OUT
R
G
AD8227
R
R
1
R
REF
fHIGH-PASS
=
AD8227
2πRC
AD8227
–IN
4.02kΩ
C
REF
C
C
1nF
0.1µF
10µF
–V
–V
S
S
–V
S
CAPACITIVELY COUPLED
CAPACITIVELY COUPLED
Figure 63. RFI Suppression
Figure 62. Creating an Input Bias Current Return Path
CD affects the differential signal and CC affects the common-
mode signal. ꢀalues of R and CC should be chosen to minimize
RFI. A mismatch between R × CC at the positive input and
R × CC at the negative input degrades the CMRR of the AD8227.
By using a value of CD one magnitude larger than CC, the effect
of the mismatch is reduced, and performance is improved.
INPUT PROTECTION
The AD8227 has very robust inputs and typically does not need
additional input protection. Input voltages can be up to 40 ꢀ
from the opposite supply rail. For example, with a +5 ꢀ positive
supply and a −8 ꢀ negative supply, the part can safely withstand
voltages from −35 ꢀ to +32 ꢀ. Unlike some other instrumentation
amplifiers, the part can handle large differential input voltages
even when the part is in high gain. Figure 17 through Figure 20
show the behavior of the part under overvoltage conditions.
Rev. 0 | Page 21 of 24
AD8227
APPLICATIONS INFORMATION
Tips for Best Differential Output Performance
DIFFERENTIAL DRIVE
For best ac performance, an op amp with at least 2 MHz gain
bandwidth and 1 ꢀ/μs slew rate is recommended. Good choices
for op amps are the AD8641, AD8515, or AD820.
Figure 64 shows how to configure the AD8227 for differential
output.
+IN
Keep trace lengths from resistors to the inverting terminal of
the op amp as short as possible. Excessive capacitance at this
node can cause the circuit to be unstable. If capacitance cannot
be avoided, use lower value resistors.
+OUT
AD8227
–IN
REF
R
R
V
BIAS
–
+
PRECISION STRAIN GAGE
OP AMP
The low offset and high CMRR over frequency of the AD8227
make it an excellent choice for bridge measurements. The
bridge can be connected directly to the inputs of the amplifier
ꢁsee Figure 65).
–OUT
RECOMMENDED OP AMPS: AD8515, AD8641, AD820.
5V
RECOMMENDED R VALUES: 5kΩ to 20kΩ.
Figure 64. Differential Output Using an Op Amp
10µF
0.1µF
The differential output is set by the following equation:
350Ω
350Ω
350Ω
350Ω
+IN
–IN
+
V
DIFF_OUT = VOUT+ − VOUT− = Gain × ꢁVIN+ − VIN−
The common-mode output is set by the following equation:
CM_OUT = ꢁVOUT+ − VOUT−)/2 = VBIAS
)
R
AD8227
G
–
2.5V
V
The advantage of this circuit is that the dc differential accuracy
depends on the AD8227 and not on the op amp or the resistors.
This circuit takes advantage of the AD8227’s precise control of
its output voltage relative to the reference voltage. Op amp dc
performance and resistor matching affect the dc common-mode
output accuracy. However, because common-mode errors are
likely to be rejected by the next device in the signal chain, these
errors typically have little effect on overall system accuracy.
Figure 65. Precision Strain Gage
Rev. 0 | Page 22 of 24
AD8227
Option 2 shows a circuit for driving higher frequency signals.
It uses a precision op amp ꢁAD8616) with relatively high band-
width and output drive. This amplifier can drive a resistor and
capacitor with a much higher time constant and is, therefore,
suited for higher frequency applications.
DRIVING AN ADC
Figure 66 shows several different methods for driving an ADC.
The ADC in the ADuC7026 microcontroller was chosen for
this example because it has an unbuffered charge sampling
architecture that is typical of most modern ADCs. This type of
architecture typically requires an RC buffer stage between the
ADC and the amplifier to work correctly.
Option 3 is useful for applications where the AD8227 needs to
run off a large voltage supply but drives a single-supply ADC.
In normal operation, the AD8227 output stays within the ADC
range, and the AD8616 simply buffers it. However, in a fault
condition, the output of the AD8227 may go outside the supply
range of both the AD8616 and the ADC. This is not an issue in
the circuit, because the 10 kΩ resistor between the two amplifiers
limits the current into the AD8616 to a safe level.
Option 1 shows the minimum configuration required to drive
a charge sampling ADC. The capacitor provides charge to the
ADC sampling capacitor, and the resistor shields the AD8227
from the capacitance. To keep the AD8227 stable, the RC time
constant of the resistor and capacitor needs to stay above 5 μs.
This circuit is mainly useful for lower frequency signals.
OPTION 1: DRIVING LOW FREQUENCY SIGNALS
3.3V
3.3V
AV
DD
ADC0
100Ω
AD8227
REF
100nF
ADuC7026
OPTION 2: DRIVING HIGH FREQUENCY SIGNALS
3.3V
3.3V
AD8227
10Ω
REF
ADC1
AD8616
10nF
OPTION 3: PROTECTING ADC FROM LARGE VOLTAGES
+15V
AD8227
–15V
3.3V
10kΩ
10Ω
REF
AD8616
ADC2
AGND
10nF
Figure 66. Driving an ADC
Rev. 0 | Page 23 of 24
AD8227
OUTLINE DIMENSIONS
3.20
3.00
2.80
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
PIN 1
0.25 (0.0098)
0.10 (0.0040)
0.65 BSC
8°
0°
0.95
0.85
0.75
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.10 MAX
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.80
0.60
0.40
8°
0°
0.15
0.00
0.38
0.22
0.23
0.08
COMPLIANT TO JEDEC STANDARDS MS-012-AA
SEATING
PLANE
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 67. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Figure 68. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
Branding
Y1S
Y1S
AD8227ARMZ1
AD8227ARMZ-RL1
AD8227ARMZ-R71
AD8227ARZ1
AD8227ARZ-RL1
AD8227ARZ-R71
AD8227BRMZ1
AD8227BRMZ-RL1
AD8227BRMZ-R71
AD8227BRZ1
8-Lead MSOP
RM-8
RM-8
RM-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
R-8
R-8
R-8
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
8-Lead SOIC_N
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
8-Lead SOIC_N
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
Y1S
Y1U
Y1U
Y1U
AD8227BRZ-RL1
AD8227BRZ-R71
1 Z = RoHS Compliant Part.
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07759-0-5/09(0)
Rev. 0 | Page 24 of 24
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