AD8802ANZ [ADI]
IC 12, SERIAL INPUT LOADING, 0.6 us SETTLING TIME, 8-BIT DAC, PDIP20, PLASTIC, DIP-20, Digital to Analog Converter;
| 型号： | AD8802ANZ |
| 厂家： | 
ADI |
| 描述： | IC 12, SERIAL INPUT LOADING, 0.6 us SETTLING TIME, 8-BIT DAC, PDIP20, PLASTIC, DIP-20, Digital to Analog Converter 输入元件 光电二极管 转换器 |
| 文件： | 总16页 (文件大小：489K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12 Channel, 8-Bit TrimDACs
with Power Shutdown
a
AD8802/AD8804
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Low Cost
Replaces 12 Potentiometers
Individually Programmable Outputs
3-Wire SPI Compatible Serial Input
Power Shutdown <55 Watts Including IDD & IREF
Midscale Preset, AD8802
V
CS
DD
AD8802/AD8804
V
REFH
CLK
DAC
D7
D0
O1
O2
1
DAC
REG
#1
EN
O3
O4
O5
D11
D10
D9
ADDR
DEC
Separate VREFL Range Setting, AD8804
+3 V to +5 V Single Supply Operation
R
D8
O6
O7
D7
O8
SER
REG
APPLICATIONS
O9
Automatic Adjustment
Trimmer Replacement
Video and Audio Equipment Gain and Offset Adjustment
Portable and Battery Operated Equipment
O10
O11
O12
D
D0
SDI
DAC
12
D7
D0
DAC
REG
#12
8
R
SHDN
GENERAL DESCRIPTION
GND
V
RS
(AD8802 ONLY)
REFL
(AD8804 ONLY)
The 12-channel AD8802/AD8804 provides independent digitally-
controllable voltage outputs in a compact 20-lead package. This
potentiometer divider TrimDAC® allows replacement of the
mechanical trimmer function in new designs. The AD8802/
AD8804 is ideal for dc voltage adjustment applications.
Each DAC has its own DAC latch that holds its output state.
These DAC latches are updated from an internal serial-to-
parallel shift register that is loaded from a standard 3-wire
serial input digital interface. The serial-data-input word is
decoded where the first 4 bits determine the address of the DAC
latches to be loaded with the last 8 bits of data. The AD8802/
AD8804 consumes only 10 µA from 5 V power supplies. In ad-
dition, in shutdown mode reference input current consumption
is also reduced to 10 µA while saving the DAC latch settings for
use after return to normal operation.
Easily programmed by serial interfaced microcontroller ports,
the AD8802 with its midscale preset is ideal for potentiometer
replacement where adjustments start at a nominal value. Appli-
cations such as gain control of video amplifiers, voltage con-
trolled frequencies and bandwidths in video equipment,
geometric correction and automatic adjustment in CRT com-
puter graphic displays are a few of the many applications ideally
suited for these parts. The AD8804 provides independent con-
trol of both the top and bottom end of the potentiometer divider
allowing a separate zero-scale voltage setting determined by the
VREFL pin. This is helpful for maximizing the resolution of
devices with a limited allowable voltage control range.
The AD8802/AD8804 is available in the 20-pin plastic DIP, the
SOIC-20 surface mount package, and the 1 mm thin TSSOP-20
package.
Internally the AD8802/AD8804 contains 12 voltage-output
digital-to-analog converters, sharing a common reference-
voltage input.
TrimDAC is a registered trademark of Analog Devices, Inc.
REV. 0
© Analog Devices, Inc., 1995
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
(VDD = +3 V ؎ 10% or +5 V ؎ 10%, VREFH = +VDD, VREFL = 0 V, –40؇C
AD8802/AD8804–SPECIFICATIONS ≤TA ≤ +85؇C unless otherwise noted)
Parameter
Symbol
Conditions
Min
Typ1
Max
Units
STATIC ACCURACY
Specifications apply to all DACs
Resolution
Differential Nonlinearity Error
Integral Nonlinearity Error
Full-Scale Error
Zero Code Error
DAC Output Resistance
Output Resistance Match
N
8
Bits
LSB
LSB
LSB
LSB
kΩ
DNL
INL
GFSE
VZSE
ROUT
∆R/RO
Guaranteed Monotonic
–1
–1.5
–1
–1
3
±1/4
±1/2
1/2
1/4
5
+1
+1.5
+1
+1
8
1.5
%
REFERENCE INPUT
Voltage Range2
VREFH
VREFL
RREFH
RREFL
CREF0
CREF1
0
0
VDD
VDD
V
V
kΩ
kΩ
pF
pF
Pin Available on AD8804 Only
Digital Inputs = 55H, VREFH = VDD
Digital Inputs = 55H, VREFL = VDD
Digital Inputs all Zeros
REFH Input Resistance
REFL Input Resistance3
Reference Input Capacitance3
1.2
1.2
32
Digital Inputs all Ones
32
DIGITAL INPUTS
Logic High
Logic Low
Logic High
Logic Low
VIH
VIL
VIH
VIL
IIL
VDD = +5 V
VDD = +5 V
VDD = +3 V
VDD = +3 V
2.4
2.1
V
V
V
V
µA
pF
0.8
0.6
±1
Input Current
VIN = 0 V or + 5 V
Input Capacitance3
CIL
5
POWER SUPPLIES4
Power Supply Range
Supply Current (CMOS)
Supply Current (TTL)
Shutdown Current
VDD Range
IDD
IDD
IREFH
PDISS
PSRR
2.7
5.5
10
4
10
55
V
µA
mA
µA
µW
%/%
VIH = VDD or VIL = 0 V
VIH = 2.4 V or VIL = 0.8 V, VDD = +5.5 V
SHDN = 0
VIH = VDD or VIL = 0 V, VDD = +5.5 V
VDD = +5 V ± 10%
0.01
1
0.2
Power Dissipation
Power Supply Sensitivity
0.001
0.002
DYNAMIC PERFORMANCE3
VOUT Settling Time
Crosstalk
tS
CT
±1/2 LSB Error Band
0.6
50
µs
dB
Between Adjacent Outputs5
SWITCHING CHARACTERISTICS3, 6
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CS Setup Time
CS High Pulse Width
Reset Pulse Width
CLK Rise to CS Rise Hold Time
CS Rise to Clock Rise Setup
tCH, tCL
tDS
tDH
tCSS
tCSW
tRS
tCSH
tCS1
Clock Level High or Low
15
5
5
10
10
90
20
10
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
1Typicals represent average readings at +25°C.
2VREFH can be any value between GND and VDD, for the AD8804 VREFL can be any value between GND and VDD
3Guaranteed by design and not subject to production test.
.
4Digital Input voltages VIN = 0 V or VDD for CMOS condition. DAC outputs unloaded. PDISS is calculated from (IDD × VDD).
5Measured at a VOUT pin where an adjacent VOUT pin is making a full-scale voltage change (f = 100 kHz).
6See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of VDD) and timed from a voltage level of
1.6 V.
Specifications subject to change without notice.
–2–
REV. 0
AD8802/AD8804
PIN CONFIGURATIONS
ABSOLUTE MAXIMUM RATINGS
(TA = +25°C, unless otherwise noted)
20
19
18
17
20
19
18
17
16
15
14
13
12
11
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3, + 8 V
VREFX to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD
Outputs (Ox) to GND . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD
Digital Input Voltage to GND . . . . . . . . . . . . . . . . . 0 V, +8 V
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (TJ MAX) . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
Package Power Dissipation . . . . . . . . . . . . (TJ MAX – TA)/θJA
Thermal Resistance θJA,
V
1
2
V
1
2
V
V
DD
REFH
REFH
O1
DD
O1
RS
O12
O11
O10
O9
3
3
O2
O3
O4
O5
O6
O12
O11
O2
O3
O4
O5
O6
4
4
5
16 O10
15 O9
14 O8
5
AD8804
TOP VIEW
(Not to Scale)
AD8802
TOP VIEW
(Not to Scale)
6
6
O8
7
7
O7
8
8
13
SDI
SHDN
CS
O7
SHDN
CS
9
9
12 SDI
CLK
V
10
10
GND
11 CLK
GND
REFL
SOIC (SOL-20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
P-DIP (N-20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W
TSSOP-20 (RU-20) . . . . . . . . . . . . . . . . . . . . . . . . 155°C/W
AD8804 PIN DESCRIPTIONS
Pin Name Description
AD8802 PIN DESCRIPTIONS
Pin Name
Description
1
2
3
4
5
6
7
8
VREFH Common High-Side DAC Reference Input
1
2
3
4
5
6
7
8
VREF
O1
O2
O3
O4
O5
O6
Common DAC Reference Input
DAC Output #1, addr = 00002
DAC Output #2, addr = 00012
DAC Output #3, addr = 00102
DAC Output #4, addr = 00112
DAC Output #5, addr = 01002
DAC Output #6, addr = 01012
O1
O2
O3
O4
O5
O6
DAC Output #1, addr = 00002
DAC Output #2, addr = 00012
DAC Output #3, addr = 00102
DAC Output #4, addr = 00112
DAC Output #5, addr = 01002
DAC Output #6, addr = 01012
SHDN Reference input current goes to zero DAC latch
settings maintained
9
CS
Chip Select Input, Active Low. When CS returns
high, data in the serial input register is decoded
based on the address bits and loaded input the
target DAC register
SHDN Reference input current goes to zero. DAC
latch settings maintained
9
CS
Chip Select Input, Active Low. When CS
returns high, data in the serial input register is
decoded based on the address bits and loaded
into the target DAC register
10 GND
11 VREFL
12 CLK
13 SDI
14 O7
15 O8
16 O9
17 O10
18 O11
19 O12
20 VDD
Ground
Common Low-Side DAC Reference Input
Serial Clock Input, Positive Edge Triggered
Serial Data Input
10 GND
11 CLK
12 SDI
13 O7
Ground
DAC Output #7, addr = 01102
DAC Output #8, addr = 01112
DAC Output #9, addr = 10002
DAC Output #10, addr = 10012
DAC Output #11, addr = 10102
DAC Output #12, addr = 10112
Positive power supply, specified for operation at
both +3 V and +5 V
Serial Clock Input, Positive Edge Triggered
Serial Data Input
DAC Output #7, addr = 01102
DAC Output #8, addr = 01112
DAC Output #9, addr = 10002
DAC Output #10, addr = 10012
DAC Output #11, addr = 10102
DAC Output #12, addr = 10112
14 O8
15 O9
16 O10
17 O11
18 O12
19 RS
ORDERING GUIDE
Temperature Package
Package
Asynchronous Preset to Midscale Output
Setting. Loads all DAC Registers with 80H
Model
FTN
Range Description Option
AD8802AN
AD8802AR
AD8802ARU RS
AD8804AN
AD8804AR
AD8804ARU REFL
RS
RS
–40°C/+85°C PDIP-20
–40°C/+85°C SOL-20
–40°C/+85°C TSSOP-20
–40°C/+85°C PDIP-20
–40°C/+85°C SOL-20
–40°C/+85°C TSSOP-20
N-20
R-20
RU-20
N-20
R-20
20 VDD
Positive Power Supply, Specified for Operation
at Both +3 V and +5 V
REFL
REFL
RU-20
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD8802/AD8804–Typical Performance Characteristics
1
0.75
0.5
160
140
120
100
80
V
V
V
= +5V
DD
T
A
T
A
T
A
= +85°C
= +25°C
= –40°C
= +5V
= 0V
REFH
REFL
0.25
0
60
–0.25
–0.5
–0.75
–1
V
V
V
= +5V
DD
= +2V
= 0V
REFH
40
REFL
ONE DAC CHANGING WITH CODE,
OTHER DACs SET TO 00H
20
T
A
= +25°C
0
0
32
64
96
128
160
192
224
256
0
32
64
96
128
160
192
224
256
CODE – Decimal
CODE – Decimal
Figure 1. INL vs. Code
Figure 4. Input Reference Current vs. Code
1
0.75
0.5
10k
1k
T
A
T
A
T
A
= +85°C
= +25°C
= –40°C
V
V
= +5V
= +5V
DD
REFH
V
= 0V
REFL
V
V
= +5.5V
0.25
0
DD
= +5.5V
REF
100
–0.25
–0.5
–0.75
–1
10
0
V
V
= +2.7V
DD
= +2.7V
REF
–55
–35
–15
5
25
45
65
85
105
125
0
32
64
96
128
160
192
224
256
TEMPERATURE – °C
CODE – Decimal
Figure 5. Shutdown Current vs. Temperature
Figure 2. Differential Nonlinearity Error vs. Code
100k
1600
V
V
V
= +4.5V
DD
V
V
= +5.5V
10k
1k
DD
= +2.4V
= +4.5V
= 0V
REF
IN
1280
960
640
320
0
REFL
T
A
= +25°C
SS = 3600 PCS
100
10
V
V
= +5.5V
DD
= +5.5V
1
IN
0.1
0.01
0.001
–55
–35
–15
5
25
45
65
85
105
125
0
0.2
0.4
0.6
0.8
1.0
TEMPERATURE – °C
ABSOLUTE VALUE TOTAL UNADJUSTED ERROR – LSB
Figure 3. Total Unadjusted Error Histogram
Figure 6. Supply Current vs. Temperature
–4–
REV. 0
AD8802/AD8804
100
10
T
= +25°C
A
ALL DIGITAL INPUTS
TIED TOGETHER
OUTPUT1: OO → FF
H
H
V
= +5V
DD
100
90
V
= +5V
REF
1.0
f = 1MHz
V
DD
= +5V
0.1
0.01
0.001
0.0001
10
V
= +3V
0%
DD
10mV
200ns
TIME – 0.2µs/DIV
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
INPUT VOLTAGE – Volts
Figure 10. Adjacent Channel Clock Feedthrough
Figure 7. Supply Current vs. Logic Input Voltage
80
5mV
1µs
100
90
60
OUT1
5mV/DIV
V
= +5V
DD
OUTPUT1: 7F → 80
H
H
ALL OUTPUTS SET
TO MIDSCALE (80H)
V
= +5V
DD
V
= +5V
REF
40
20
0
CS
5V/DIV
10
0%
5V
TIME – 1µs/DIV
10
100
1k
FREQUENCY – Hz
10k
100k
Figure 11. Midscale Transition
Figure 8. Power Supply Rejection vs. Frequency
0.01
V
V
= +4.5V
DD
= +4.5V
REF
SS = 176 PCS
= 0V
2V
5µs
0.005
6V
4V
2V
0V
V
REFL
100
90
OUT
0
V
V
= +5V
DD
= +5V
REF
10
0%
0%
5V
0V
–0.005
CS
5V
TIME – 5µs/DIV
–0.01
0
100
200
300
400
500
600
HOURS OF OPERATION AT 150°C
Figure 9. Large-Signal Settling Time
Figure 12. Zero-Scale Error Accelerated by Burn-In
REV. 0
–5–
AD8802/AD8804
1.0
0.5
0.04
V
V
= +4.5V
DD
V
V
= +4.5V
DD
= +4.5V
REF
= +4.5V
REF
CODE = 55
H
SS = 176 PCS
SS = 176 PCS
0.02
x + 2σ
x + 2σ
x
x
0
–0.5
–1.0
0
–0.02
–0.04
x – 2σ
x – 2σ
200
300
400
500
600
200
300
400
500
600
0
100
0
100
HOURS OF OPERATION AT 150°C
HOURS OF OPERATION AT 150°C
Figure 14. REF Input Resistance Accelerated by Burn-In
Figure 13. Full-Scale Error Accelerated by Burn-In
1
OPERATION
SDI
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0
1
The AD8802/AD8804 provides twelve channels of program-
mable voltage output adjustment capability. Changing the pro-
grammed output voltage of each DAC is accomplished by
clocking in a 12-bit serial data word into the SDI (Serial Data
Input) pin. The format of this data word is four address bits,
MSB first, followed by 8 data bits, MSB first. Table I provides
the serial register data word format. The AD8802/AD8804 has
the following address assignments for the ADDR decode which
determines the location of the DAC register receiving the serial
register data in Bits B7 through B0:
CLK
0
1
DAC REGISTER LOAD
CS
0
+5V
V
OUT
0V
Figure 15a. Timing Diagram
DETAIL SERIAL DATA INPUT TIMING (RS = "1")
DAC# = A3 × 8 + A2 × 4 + A1 × 2 + A0 + 1
1
SDI
(DATA IN)
DAC outputs can be changed one at a time in random se-
quence. The fast serial-data loading of 33 MHz makes it pos-
sible to load all 12 DACs in as little time as 4.6 µs (13 × 12 ×
30 ns). The exact timing requirements are shown in Figure 15.
A
X
OR D
X
A
X
OR D
X
0
tDS
tCH
tDH
tCS1
1
CLK
0
1
0
tCL
tCSH
Table I. Serial-Data Word Format
tCSS
tCSW
CS
ADDR
DATA
tS
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
+5V
0V
±1/2 LSB
V
OUT
±1/2 LSB ERROR BAND
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB MSB
LSB
Figure 15b. Detail Timing Diagram
211 210 29 28
27 26 25 24 23 22 21 20
RESET TIMING
1
tRS
The AD8802 offers a midscale preset activated by the RS pin
simplifying initial setting conditions at first power-up. The
AD8804 has both a VREFH and a VREFL pin to establish indepen-
dent positive full-scale and zero-scale settings to optimize reso-
lution. Both parts offer a power shutdown SHDN which places
the DAC structure in a zero power consumption state resulting
in only leakage currents being consumed from the power supply
and VREF inputs. In shutdown mode the DACX register settings
are maintained. When returning to operational mode from
power shutdown the DAC outputs return to their previous volt-
age settings.
RS
0
tS
+5V
±1 LSB
V
OUT
2.5V
±1 LSB ERROR BAND
Figure 15c. Reset Timing Diagram
–6–
REV. 0
AD8802/AD8804
ladder, while the REFH reference is sourcing current into the
DAC ladder. The DAC design minimizes reference glitch cur-
rent maintaining minimum interference between DAC channels
during code changes.
PROGRAMMING THE OUTPUT VOLTAGE
The output voltage range is determined by the external refer-
ence connected to VREFH and VREFL pins. See Figure 16 for a
simplified diagram of the equivalent DAC circuit. In the case of
the AD8802 its VREFL is internally connected to GND and
therefore cannot be offset. VREFH can be tied to VDD and VREFL
can be tied to GND establishing a basic rail-to-rail voltage out-
put programming range. Other output ranges are established by
the use of different external voltage references. The general
transfer equation which determines the programmed output
voltage is:
DAC OUTPUTS (O1–O12)
The twelve DAC outputs present a constant output resistance of
approximately 5 kΩ independent of code setting. The distribu-
tion of ROUT from DAC-to-DAC typically matches within ±1%.
However device-to-device matching is process lot dependent
having a ±20% variation. The change in ROUT with temperature
has a 500 ppm/°C temperature coefficient. During power shut-
down all twelve outputs are open-circuited.
VO (Dx) = (Dx)/256 × (VREFH – VREFL) + VREFL
Eq. 1
where Dx is the data contained in the 8-bit DACx register.
V
TO OTHER DACS
P CH
CS
DD
AD8802/AD8804
V
REFH
CLK
DAC
D7
O1
O2
O3
O4
O5
O6
O7
O8
V
REFH
1
N CH
MSB
2R
DAC
REG
#1
EN
O
X
D11
D10
D9
ADDR
DEC
D0
R
R
R
D8
D7
DAC
REGISTER
SER
REG
O9
D7
D6
D0
O10
O11
O12
D
D0
SDI
2R
D7
D0
DAC
12
DAC
REG
#12
8
. .
. .
. .
.
.
R
.
SHDN
2R
2R
LSB
GND
V
RS
(AD8802 ONLY)
REFL
(AD8804 ONLY)
GND
Figure 17. Block Diagram
DIGITAL INTERFACING
V
REFL
Figure 16. AD8802/AD8804 Equivalent TrimDAC Circuit
The AD8802/AD8804 contains a standard three-wire serial in-
put control interface. The three inputs are clock (CLK), CS and
serial data input (SDI). The positive-edge sensitive CLK input
requires clean transitions to avoid clocking incorrect data into
the serial input register. Standard logic families work well. If
mechanical switches are used for product evaluation, they
should be debounced by a flip-flop or other suitable means. Fig-
ure 17 block diagram shows more detail of the internal digital
circuitry. When CS is taken active low, the clock can load data
into the serial register on each positive clock edge, see Table II.
For example, when VREFH = +5 V and VREFL = 0 V, the follow-
ing output voltages will be generated for the following codes:
Output State
(VREFH = +5 V, VREFL = 0 V)
D
VOx
255
128
1
4.98 V
2.50 V
0.02 V
0.00 V
Full Scale
Half Scale (Midscale Reset Value)
1 LSB
Zero Scale
0
Table II. Input Logic Control Truth Table
REFERENCE INPUTS (VREFH, VREFL
)
CS CLK
Register Activity
The reference input pins set the output voltage range of all
twelve DACs. In the case of the AD8802 only the VREFH pin is
available to establish a user designed full-scale output voltage.
The external reference voltage can be any value between 0 and
VDD but must not exceed the VDD supply voltage. The AD8804
has access to the VREFL which establishes the zero-scale output
voltage, any voltage can be applied between 0 V and VDD. VREFL
can be smaller or larger in voltage than VREFH since the DAC
design uses fully bidirectional switches as shown in Figure 16.
The input resistance to the DAC has a code dependent variation
which has a nominal worst case measured at 55H, which is ap-
proximately 1.2 kΩ. When VREFH is greater than VREFL, the
REFL reference must be able to sink current out of the DAC
1
0
X
P
No effect.
Shifts Serial Register One bit loading the next bit
in from the SDI pin.
Clock should be high when the CS returns to the
inactive state.
P
1
P = Positive Edge, X = Don’t Care.
The data setup and data hold times in the specification table
determine the data valid time requirements. The last 12 bits of
the data word entered into the serial register are held when CS
returns high. At the same time CS goes high it gates the address
decoder which enables one of the twelve positive-edge triggered
DAC registers, see Figure 18 detail.
REV. 0
–7–
AD8802/AD8804
+5V
DAC 1
DAC 2
CS
ADDR
DECODE
.
.
.
V
DD
DAC 12
AD8802/
AD8804
+
10µF
0.1µF
SERIAL
REGISTER
CLK
SDI
DGND
Figure 18. Equivalent Control Logic
The target DAC register is loaded with the last eight bits of the
serial data-word completing one DAC update. Twelve separate
12-bit data words must be clocked in to change all twelve out-
put settings.
Figure 21. Recommended Supply Bypassing for the
AD8802/AD8804
All digital inputs are protected with a series input resistor and
parallel Zener ESD structure shown in Figure 19. Applies to
digital input pins CS, SDI, RS, SHDN, CLK
Buffering the AD8802/AD8804 Output
In many cases, the nominal 5 kΩ output impedance of the
AD8802/AD8804 is sufficient to drive succeeding circuitry. If a
lower output impedance is required, an external amplifier can
be added. Several examples are shown in Figure 22. One ampli-
fier of an OP291 is used as a simple buffer to reduce the output
resistance of DAC A. The OP291 was chosen primarily for its
rail-to-rail input and output operation, but it also offers opera-
tion to less than 3 V, low offset voltage, and low supply current.
1kΩ
LOGIC
Figure 19. Equivalent ESD Protection Circuit
The next two DACs, B and C, are configured in a summing
arrangement where DAC C provides the coarse output voltage
setting and DAC B can be used for fine adjustment. The inser-
tion of R1 in series with DAC B attenuates its contribution to
the voltage sum node at the DAC C output.
Digital inputs can be driven by voltages exceeding the AD8802/
AD8804 VDD supply value. This allows 5 V logic to interface
directly to the part when it is operated at 3 V.
APPLICATIONS
Supply Bypassing
+5V
Precision analog products, such as the AD8802/AD8804, re-
quire a well filtered power source. Since the AD8802/AD8804
operate from a single +3 V to +5 V supply, it seems convenient
to simply tap into the digital logic power supply. Unfortunately,
the logic supply is often a switch-mode design, which generates
noise in the 20 kHz to 1 MHz range. In addition, fast logic gates
can generate glitches hundred of millivolts in amplitude due to
wiring resistances and inductances.
V
V
REFH
DD
OP291
V
H
SIMPLE BUFFER
0V TO 5V
V
L
V
H
V
L
R1
100kΩ
V
H
SUMMER CIRCUIT
WITH FINE TRIM
ADJUSTMENT
V
L
If possible, the AD8802/AD8804 should be powered directly
from the system power supply. This arrangement, shown in Fig-
ure 20, will isolate the analog section from the logic switching
transients. Even if a separate power supply trace is not available,
however, generous supply bypassing will reduce supply-line in-
duced errors. Local supply bypassing consisting of a 10 µF tan-
talum electrolytic in parallel with a 0.1 µF ceramic capacitor is
recommended (Figure 21).
AD8802/
AD8804
V
GND
REFL
DIGITAL INTERFACING
OMITTED FOR CLARITY
Figure 22. Buffering the AD8802/AD8804 Output
Increasing Output Voltage Swing
An external amplifier can also be used to extend the output volt-
age swing beyond the power supply rails of the AD8802/AD8804.
This technique permits an easy digital interface for the DAC,
while expanding the output swing to take advantage of higher
voltage external power supplies. For example, DAC A of Fig-
ure 23 is configured to swing from –5 V to +5 V. The actual
output voltage is given by:
TTL/CMOS
LOGIC
CIRCUITS
+
10µF
TANT
AD8802/
AD8804
0.1µF
+5V
POWER SUPPLY
Figure 20. Use Separate Traces to Reduce Power Supply
Noise
RF
RS
D
256
VOUT = 1+
×
× 5V – 5V
(
)
where D is the DAC input value (i.e., 0 to 255). This circuit can
be combined with the “fine/coarse” circuit of Figure 22 if, for
example, a very accurate adjustment around 0 V is desired.
–8–
REV. 0
AD8802/AD8804
R
R
S
+5V
F
+5V
100kΩ
100kΩ
0.1µF
10µF
+5V
V
REFH
V
DD
–5V TO +4.98V
V
DD
V
REFH
A
OP191
AD8802
SDI
RxD P3.0
SERIAL DATA
SHIFT REGISTER
–5V
SBUF
AD8802/
AD8804
O1
TxD
P3.1
+12V
SHIFT CLOCK
SCLK
RESET
SHDN
CS
P1.3
P1.2
P1.1
OP193
B
8051 µC
0V TO +10V
O12
V
GND
REFL
100kΩ
AD8804
ONLY
1.3 1.2 1.1
PORT 1
GND
100kΩ
Figure 24. Interfacing the 8051 µC to an AD8802/AD8804,
Using the Serial Port
Figure 23. Increasing Output Voltage Swing
Software for the 8051 Interface
DAC B of Figure 24 is in a noninverting gain of two configura-
tions, which increases the available output swing to +10 V. The
feedback resistors can be adjusted to provide any scaling of the
output voltage, within the limits of the external op amp power
supplies.
A software for the AD8802/AD8804 to 8051 interface is
shown in Listing 1. The routine transters the 8-bit data stored at
data memory location DAC_VALUE to the AD8802/AD8804
DAC addressed by the contents of location DAC_ADDR.
The subroutine begins by setting appropriate bits in the Serial
Control register to configure the serial port for Mode 0 opera-
tion. Next the DAC’s Chip Select input is set low to enable the
AD8802/AD8804. The DAC address is obtained from memory
location DAC_ADDR, adjusted to compensate for the 8051’s
serial data format, and moved to the serial buffer register. At
this point, serial data transmission begins automatically. When
all 8 bits have been sent, the Transmit Interrupt bit is set, and
the subroutine then proceeds to send the DAC value stored at
location DAC_VALUE. Finally the Chip Select input is re-
turned high, causing the appropriate AD8802/AD8804 output
voltage to change, and the subroutine ends.
Microcomputer Interfaces
The AD8802/AD8804 serial data input provides an easy inter-
face to a variety of single-chip microcomputers (µCs). Many µCs
have a built-in serial data capability that can be used for com-
municating with the DAC. In cases where no serial port is pro-
vided, or it is being used for some other purpose (such as an
RS-232 communications interface), the AD8802/AD8804 can
easily be addressed in software.
Twelve data bits are required to load a value into the AD8802/
AD8804 (4 bits for the DAC address and 8 bits for the DAC
value). If more than 12 bits are transmitted before the Chip Se-
lect input goes high, the extra (i.e., the most-significant) bits are
ignored. This feature is valuable because most µCs only transmit
data in 8-bit increments. Thus, the µC will send 16 bits to the
DAC instead of 12 bits. The AD8802/AD8804 will only re-
spond to the last 12 bits clocked into the SDI port, however, so
the serial data interface is not affected.
The 8051 sends data out of its shift register LSB first, while the
AD8802/AD8804 require data MSB first. The subroutine there-
fore includes a BYTESWAP subroutine to reformat the data.
This routine transfers the MSB-first byte at location SHIFT1 to
an LSB-first byte at location SHIFT2. The routine rotates the
MSB of the first byte into the carry with a Rotate Left Carry in-
struction, then rotates the carry into the MSB of the second byte
with a Rotate Right Carry instruction. After 8 loops, SHIFT2
contains the data in the proper format.
An 8051 µC Interface
A typical interface between the AD8802/AD8804 and an 8051
µC is shown in Figure 24. This interface uses the 8051’s internal
serial port. The serial port is programmed for Mode 0 opera-
tion, which functions as a simple 8-bit shift register. The 8051’s
Port 3.0 pin functions as the serial data output, while Port 3.1
serves as the serial clock.
The BYTESWAP routine in Listing 1 is convenient because the
DAC data can be calculated in normal LSB form. For example,
producing a ramp voltage on a DAC is simply a matter of re-
peatedly incrementing the DAC_VALUE location and calling
the LD_8802 subroutine.
When data is written to the Serial Buffer Register (SBUF, at
Special Function Register location 99H), the data is automati-
cally converted to serial format and clocked out via Port 3.0 and
Port 3.1. After 8 bits have been transmitted, the Transmit Inter-
rupt flag (SCON.1) is set and the next 8 bits can be transmitted.
If the µC’s hardware serial port is being used for other purposes,
the AD8802/AD8804 DAC can be loaded by using the parallel
port. A typical parallel interface is shown in Figure 25. The se-
rial data is transmitted to the DAC via the 8051’s Port 1.6 out-
put, while Port 1.6 acts as the serial clock.
The AD8802 and AD8804 require the Chip Select to go low at
the beginning of the serial data transfer. In addition, the SCLK
input must be high when the Chip Select input goes high at the
end of the transfer. The 8051’s serial clock meets this require-
ment, since Port 3.1 both begins and ends the serial data in the
high state.
Software for the interface of Figure 25 is contained in Listing 2. The
subroutine will send the value stored at location DAC_VALUE to
the AD8802/AD8804 DAC addressed by location DAC_ADDR.
The program begins by setting the AD8802/AD8804’s Serial
Clock and Chip Select inputs high, then setting Chip Select low
REV. 0
–9–
AD8802/AD8804
;
; This subroutine loads an AD8802/AD8804 DAC from an 8051 microcomputer,
; using the 8051’s serial port in MODE 0 (Shift Register Mode).
; The DAC value is stored at location DAC_VAL
; The DAC address is stored at location DAC_ADDR
;
; Variable declarations
;
PORT1
DATA
DATA
DATA
DATA
DATA
DATA
90H
40H
41H
042H
043H
44H
;SFR register for port 1
;DAC Value
;DAC Address
;high byte of 16-bit answer
;low byte of answer
;
DAC_VALUE
DAC_ADDR
SHIFT1
SHIFT2
SHIFT_COUNT
;
ORG
CLR
CLR
100H
SCON.7
SCON.6
;arbitrary start
;set serial
;data mode 0
DO_8802:
CLR
CLR
SCON.5
SCON.1
;clr transmit flag
;/RS, /SHDN, /CS high
;set the /CS low
;put DAC value in shift register
;
;send the address byte
;wait until 8 bits are sent
;clear the serial transmit flag
;send the DAC value
;
ORL
CLR
MOV
ACALL
MOV
JNB
PORT1.1,#00001110B
PORT1.1
SHIFT1,DAC_ADDR
BYTESWAP
SBUF,SHIFT2
SCON.1,ADDR_WAIT
SCON.1
SHIFT1,DAC_VALUE
BYTESWAP
SBUF,SHIFT2
SCON.1,VALU_WAIT
SCON.1
ADDR_WAIT:
VALU_WAIT:
CLR
MOV
ACALL
MOV
JNB
CLR
SETB
RET
;
;wait again
;clear serial flag
;/CS high, latch data
; into AD8801
PORT1.1
;
BYTESWAP:
SWAP_LOOP:
MOV
MOV
RLC
MOV
MOV
RRC
MOV
DJNZ
RET
SHIFT_COUNT,#8
A,SHIFT1
A
SHIFT1,A
A,SHIFT2
A
;Shift 8 bits
;Get source byte
;Rotate MSB to carry
;Save new source byte
;Get destination byte
;Move carry to MSB
;Save
SHIFT2,A
SHIFT_COUNT,SWAP_LOOP
;Done?
END
Listing 1. Software for the 8051 to AD8802/AD8804 Serial Port Interface
+5V
to start the serial interface process. The DAC address is loaded
into the accumulator and four Rotate Right shifts are per-
formed. This places the DAC address in the 4 MSBs of the ac-
cumulator. The address is then sent to the AD8802/AD8804 via
the SEND_SERIAL subroutine. Next, the DAC value is loaded
into the accumulator and sent to the AD8802/AD8804. Finally,
the Chip Select input is set high to complete the data transfer
V
V
REFH
DD
AD8804
8051 µC
P1.7
P1.6
P1.5
P1.4
SDI
O1
CLK
Unlike the serial port interface of Figure 24, the parallel port in-
terface only transmits 12 bits to the AD8802/AD8804. Also, the
BYTESWAP subroutine is not required for the parallel inter-
face, because data can be shifted out MSB first. However, the
results of the two interface methods are exactly identical. In
most cases, the decision on which method to use will be deter-
mined by whether or not the serial data port is available for
communication with the AD8802/AD8804.
CS
O12
SHDN
1.7 1.6 1.5 1.4
PORT 1
V
REFL
GND
Figure 25. An AD8802/AD8804-8051 µC Interface Using
Parallel Port 1
–10–
REV. 0
AD8802/AD8804
; This 8051 µC subroutine loads an AD8802 or AD8804 DAC with an 8-bit value,
; using the 8051’s parallel port #1.
; The DAC value is stored at location DAC_VALUE
; The DAC address is stored at location DAC_ADDR
;
; Variable declarations
PORT1
DAC_VALUE
DAC_ADDR
LOOPCOUNT
DATA
DATA
DATA
DATA
;
90H
40H
41H
43H
;SFR register for port 1
;DAC Value
;DAC Address (0 through 7)
;COUNT LOOPS
ORG
ORL
CLR
MOV
MOV
RR
RR
RR
RR
100H
PORT1,#11110000B
PORT1.5
LOOPCOUNT,#4
A,DAC_ADDR
A
A
A
A
;arbitrary start
LD_8804:
;set CLK, /CS and /SHDN high
;Set Chip Select low
;Address is 4 bits
;Get DAC address
;Rotate the DAC
;address to the Most
;Significant Bits (MSBs)
;
ACALL
MOV
MOV
ACALL
SETB
RET
SEND_SERIAL
LOOPCOUNT,#8
A,DAC_VALUE
SEND_SERIAL
PORT1.5
;Send the address
;Do 8 bits of data
;Send the data
;Set /CS high
;DONE
SEND_SERIAL:
RLC
MOV
CLR
A
;Move next bit to carry
;Move data to SDI
;Pulse the
PORT1.7,C
PORT1.6
SETB
DJNZ
RET;
END
PORT1.6
LOOPCOUNT,SEND_SERIAL
;CLK input
;Loop if not done
Listing 2. Software for the 8051 to AD8802/AD8804 Parallel Port Interface
An MC68HC11-to-AD8802/AD8804 Interface
A software routine for loading the AD8802/AD8804 from a
68HC11 evaluation board is shown in Listing 3. First, the
MC68HC11 is configured for SPI operation. Bits CPHA and
CPOL define the SPI mode wherein the serial clock (SCK) is
high at the beginning and end of transmission, and data is valid
on the rising edge of SCK. This mode matches the requirements
of the AD8802/AD8804. After the registers are saved on the
stack, the DAC value and address are transferred to RAM and
the AD8802/AD8804’s CS is driven low. Next, the DAC’s ad-
dress byte is transferred to the SPDR register, which automati-
cally initiates the SPI data transfer. The program tests the SPIF
bit and loops until the data transfer is complete. Then the DAC
value is sent to the SPI. When transmission of the second byte is
complete, CS is driven high to load the new data and address
into the AD8802/AD8804.
Like the 8051 µC, the MC68HC11 includes a dedicated serial
data port (labeled SPI). The SPI port provides an easy interface
to the AD8802/AD8804 (Figure 27). The interface uses three
lines of Port D for the serial data, and one or two lines from
Port C to control the SHDN and RS (AD8802 only) inputs.
AD8802/
AD8804*
MC68HC11*
MOSI
(PD3)
SDI
CLK
(PD4) SCK
CS
SS
PC0
PC1
(PD5)
SHDN
RS (AD8802 ONLY)
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 26. An AD8802/AD8804-to-MC68HC11 Interface
REV. 0
–11–
AD8802/AD8804
*
* AD8802/AD8804 to M68HC11 Interface Assembly Program
*
* M68HC11 Register definitions
*
PORTC
*
EQU
$1003
Port C control register
“0,0,0,0;0,0,RS/, SHDN/”
Port C data direction
Port D data register
“0,0,/CS,CLK;SDI,0,0,0”
Port D data direction
SPI control register
“SPIE,SPE,DWOM,MSTR;CPOL,CPHA,SPR1,SPR0”
SPI status register
“SPIF,WCOL,0,MODF;0,0,0,0”
SPI data register; Read-Buffer; Write-Shifter
DDRC
PORTD
*
DDRD
SPCR
*
SPSR
*
SPDR
*
EQU
EQU
$1007
$1008
EQU
EQU
$1009
$1028
EQU
EQU
$1029
$102A
* SDI RAM variables:
SDI1 is encoded from 0H to 7H
SDI2 is encoded from 00H to FFH
AD8802/AD8804 requires two 8-bit loads; upper 4 bits
of SDI1 are ignored. AD8802/AD8804 address bits in last
four LSBs of SDI1.
*
*
*
*
*
SDI1
SDI2
*
EQU
EQU
$00
$01
SDI packed byte 1 “0,0,0,0;A3,A2,A1,A0”
SDI packed byte 2 “DB7–DB4;DB3–DB0”
* Main Program
*
ORG
LDS
$C000
#$CFFF
Start of user’s RAM in EVB
Top of C page RAM
INIT
*
* Initialize Port C Outputs
*
LDAA
#$03
0,0,0,0;0,0,1,1
*
/RS-Hi, /SHDN-Hi
Initialize Port C Outputs
0,0,0,0;0,0,1,1
STAA
LDAA
PORTC
#$03
STAA
DDRC
/RS and /SHDN are now enabled as outputs
*
* Initialize Port D Outputs
*
LDAA
#$20
0,0,1,0;0,0,0,0
*
/CS-Hi,/CLK-Lo,SDI-Lo
Initialize Port D Outputs
0,0,1,1;1,0,0,0
STAA
LDAA
PORTD
#$38
STAA
DDRD
/CS,CLK, and SDI are now enabled as outputs
*
* Initialize SPI Interface
*
LDAA
#$53
STAA
SPCR
SPI is Master,CPHA=0,CPOL=0,Clk rate=E/32
*
* Call update subroutine
*
BSR
JMP
UPDATE
$E000
Xfer 2 8-bit words to AD8402
Restart BUFFALO
*
* Subroutine UPDATE
*
UPDATE
PSHX
PSHY
PSHA
Save registers X, Y, and A
*
* Enter Contents of SDI1 Data Register
–12–
REV. 0
AD8802/AD8804
*
*
LDAA
STAA
$0000
SDI1
Hi-byte data loaded from memory
SDI1 = data in location 0000H
* Enter Contents of SDI2 Data Register
*
LDAA
STAA
$0001
SDI2
Low-byte data loaded from memory
SDI2 = Data in location 0001H
*
*
LDX
LDY
#SDI1
#$1000
Stack pointer at 1st byte to send via SDI
Stack pointer at on-chip registers
* Reset AD8802 to one-half scale (AD8804 does not have a Reset input)
*
BCLR
BSET
PORTC,Y $02
PORTC,Y $02
Assert /RS
De-Assert /RS
*
* Get AD8802/04 ready for data input
*
BCLR
PORTD,Y $02
Assert /CS
*
TFRLP
LDAA
STAA
0,X
SPDR
Get a byte to transfer for SPI
Write SDI data reg to start xfer
*
WAIT
LDAA
BPL
SPSR
WAIT
Loop to wait for SPIF
SPIF is the MSB of SPSR
*
INX
CPX
BNE
Increment counter to next byte for xfer
Are we done yet ?
If not, xfer the second byte
#SDI2+1
TFRLP
*
* Update AD8802 output
*
BSET
PORTD,Y $20
Latch register & update AD8802
*
PULA
PULY
PULX
RTS
When done, restore registers X, Y & A
** Return to Main Program **
Listing 3. AD8802/AD8804 to MC68HC11 Interface Program Source Code
An Intelligent Temperature Control System—Interfacing the
8051 C with the AD8802/AD8804 and TMP14
interface lines, interrupts, and the serial port lines have been
assigned. The eight port pins may be used as chip selects, in
which case an array of eight AD8802/AD8804s controlling
twenty-four TMP14 sensors is possible.
Connecting the 80CL51 µC, or any modern microcontroller,
with the TMP14 and AD8802/AD8804 yields a powerful tem-
perature control tool, as shown in Figure 27. For example, the
80CL51 µC controls the TrimDACs allowing the user to auto-
matically set the temperature setpoints voltages of the TMP14
via computer or touch pad, while the TMP14 senses the tem-
perature and outputs four open-collector trip-points. Feeding
these trip-point outputs back to the 80CL51 µC allow it to sense
whether or not a setpoint has been exceeded. Additional
80CL51 µC port pins or TMP14 trip-point outputs may then
be used to change fan speed (i.e., high, medium, low, off), or
increase/decrease the power level to a heater. (Please refer to the
TMP14 data sheet for more applications information.)
The AD8802/AD8804 and TMP14 are also ideal choices for
low power applications. These devices have power shutdown
modes and operate on a single 5 Volt supply. When their shut-
down modes are activated current consumption is reduced to
less than 35 µA. However, at high operating frequencies
(12 MHz) the 80CL51 consumes far more energy (18 mA typ)
than the AD8802/AD8804 and TMP14 combined. Therefore,
to achieve a low power design the 80CL51 should operate at its
lowest possible frequency or be placed in its power-down mode
at the end of each instruction sequence.
To use the power-down mode of the 80CL51 µC set PCON.1
as the last instruction executed prior to going into the power-
down mode. If INT2 and INT9 are enabled, the 80CL51 µC
can be awakened from power-down mode with external inter-
rupts. As shown in Figure 28, the TLC555 outputs a pulse
every few seconds providing the interrupt to restart the 80CL51
µC which then samples the user input pins, the outputs of the
The CS (Chip Select) on the AD8802/AD8804 makes applica-
tions that call for large temperature sensor arrays possible. In
addition, the 12 channels of the AD8802/AD8804 allow inde-
pendent setpoint control for all four trip-point outputs on up to
three TMP14 temperature sensors. For example, assume that
the 80CL51 µC has eight free port pins available after all user
REV. 0
–13–
AD8802/AD8804
TMP14
V
REFH
AD8802/4
2.5 V
HYS
TRIP 1
TRIP 2
TRIP 3
TRIP 4
REF
P0.0
P3.2
P3.1
P3.0
CS
O1
O2
O3
O4
SET 1
CLK
SDI
SET 2
SET 3
SET 4
USER
INPUTS
P3.3
P0.7
4
4
+
+5V
0.1µF
V
TO 2nd TEMP SENSOR
IF NEEDED
3
05–8
TO 2nd AD8802/4
ARRAY IF NEEDED
SLEEP
80CL51 µC
GND
TO 3rd TEMP SENSOR
IF NEEDED
09–12
P2.0
P2.1
+5V
V
DD
P2.2
0.1µF
10µF
P2.3
GND
P1.0/INT2 P2.4
SHDN
+5V
0.01µF
V
RS
CC
DIS
TLC555
3
OUT
THR
TRIG
GND
Figure 27. Temperature Sensor Array with Programmable Setpoints
The gain of the SSM2018T is controlled by the voltage at Pin 11.
For maximum attenuation of –100 dB a control signal of 3.0 V
typ is necessary. The control signal has a scale of –30 mV/dB
centered around 0 dB gain for 0 V of control voltage, therefore,
for a maximum gain of 40 dB a control voltage of –1.2 volts is
necessary. Now notice that the normal +5 V to GND voltage
range of the AD8802/AD8804 does not cover the 3.0 V to
–1.2 V operational gain control range of the SSM2018T. To
cover the operating gain range fully and not exceed the maxi-
mum specified power supply rating requires the O1 output of
AD8802/AD8804 to be level shifted down. In Figure 28, the
level shifting is accomplished by a Zener diode and 1/4 of an
OP420 quad op amp. For applications that require only
TMP14, and makes the necessary adjustments to the AD8802/
AD8804 before shutting down again. The 80CL51 consumes
only 50 µA when operating at 32 kHz, in which case there
would be no need for the TLC555, which consumes 1 mW typ.
12 Channel Programmable Voltage Controlled Amplifier
The SSM2018T is a trimless Voltage Controlled Amplifier
(VCA) for volume control in audio systems. The SSM2018T is
the first professional quality audio VCA in the marketplace that
does not require an external trimming potentiometer to mini-
mize distortion. The TrimDAC shown in Figure 28 is not being
used to trim distortion, but rather to control the gain of the am-
plifier. In this configuration up to twelve SSM2018T can be
digitally controlled. (Please refer to the SSM2018T data sheet
for more specifications and applications information.)
18kΩ
50pF
OPTIONAL FOR
0 TO 40dB GAIN
V
OUT
+15V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
–15V
+15V
SSM2018T
50kΩ
1.2V
R
O
150kΩ
OP420A
+V
1µF
1µF
AD8802/4
18kΩ
V
O1
REFH
18kΩ
NC
V
REFL
47pF
(AD8804
ONLY)
O2–
O12
REF195
OUT
GND
O2
O3
CS
+15V
V+
IN
CLK
SDI
1µF
O4–O12
TO 8 MORE CHANNELS
GND
3
TO µC
Figure 28. 12-Channel Programmable Voltage Controlled Amplifier
–14–
REV. 0
AD8802/AD8804
+12V
R ∆GAIN
B ∆GAIN
G ∆GAIN
V
CC
9
–H SYNC
OUTPUT
13
43
15
24
CRT
CATHODE
RGB
VIDEO
INPUT
CRT
VIDEO
AMP
5
40, 35, 30
38, 28, 33
7, 11, 17
LM1204
RGB FEEDBACK
BLANK GATE
INPUT
22
21
+4V
20
V
CC
(+12V)
O1 O2 O3 04 O5 O6 O7
V
REFH
REF195
OUT IN
GND
CS
+12V
V
CC
AD8802/4
TO µC
CLK
0.1µF
10µF
10µF
0.1µF
SDI
O1 = 2V
O2 = CONTRAST
O3 = BP CLAMP WIDTH ADJUST
O4 = BLANK LEVEL ADJUST
(FOR BRIGHTNESS CONTROL)
O5 = R AGAIN
O6 = B AGAIN
O7 = G AGAIN
O8 – O12 = NOT USED
Figure 29. A Digitally Controlled LM1204—150 MHz RGB Amplifier System
attenuation the optional circuitry inside the dashed box may be
removed and replaced with a direct connection from O1 of
AD8802/AD8804 to Pin 11 of SSM2018T.
between Pins 5 and 7. The input referred noise spectral density
is only 1.3 nV√Hz and power consumption is 125 mW at the
recommended ±5 V supplies.
When high gain resolution is desired, VREFH and VREFL may be
decoupled from the power rails and shifted closer together.
This technique increases the gain resolution with the unfortu-
nate penalty of decreased gain range.
The decibel gain is “linear in dB,” accurately calibrated, and
stable over temperature and supply. The gain is controlled at a
high impedance (50 MΩ), low bias (200 nA) differential input;
the scaling is 25 mV/dB, requiring a gain-control voltage of only
1 V to span the central 40 dB of the gain range. An overrange
and underrange of 1 dB is provided whatever the selected
range. The gain-control response time is less than 1 µs for a 40
dB change. The settling time of the AD8802/AD8804 to within
a ±1/2 LSB band is 0.6 µs making it an excellent choice for con-
trol of the AD603.
A Digitally Controlled LM1204 150 MHz RGB Amplifier
System
The LM1204 is an industry standard video amplifier system.
Figure 29 illustrates a configuration that removes the usual
seven level setting potentiometers and replaces them with only
one IC. The AD8802/AD8804, in addition to being smaller
and more reliable than mechanical potentiometers, has the
added feature of digital control.
The differential gain-control interface allows the use of either
differential or single-ended positive or negative control voltages,
where the common-mode range is –1.2 V to 2.0 V. Once again
the AD8802/AD8804 is ideally suited to provide the differential
input range of 1 V within the common-mode range of 0 V to
2 V. To accomplish this, place VREFH at 2.0 V and VREFL at
1.0 V, then all 256 voltage levels of the AD8804 will fall within
the gain-control range of the AD603. Please refer to the AD603
data sheet for further information regarding gain control, layout,
and general operation.
The REF195 is a 5.0 V reference used to supply both the power
and reference voltages to the AD8802/AD8804. This is possible
because of the high reference output current available (30 mA
typical) together with the low power consumption of the
AD8802/AD8804.
A Low Noise 90 MHz Programmable Gain Amplifier
The AD603 is a low noise, voltage-controlled amplifier for use
in RF and IF AGC systems. It provides accurate, pin selectable
gains of –11 dB to +31 dB with a bandwidth of 90 MHz or
+9 dB to +51 dB with a bandwidth of 9 MHz. Any intermedi-
ate gain range may be arranged using one external resistor
The dual OP279 is a rail-to-rail op amp used in Figure 30 to
drive the inputs VREFH and VREFL because these reference inputs
are low impedance (2 kΩ typical).
REV. 0
–15–
AD8802/AD8804
+10V
8
0.1µF
+10V
8
0.1µF
0.1µF
6
3
4
0.1µF
5
6
3
4
AD603
1
7
0.1µF
100Ω
5
2
AD603
1
7
2
REF195
+5.0V
IN
+10V
OUT
GND
1µF
V
10µF
10µF
1/2 OP279
B
1/2 OP279
A
O1 O2 O3 O4
40kΩ
1.0V
30kΩ
DD
2.0V
AD8804
V
REFL
CS
V
20kΩ
REFH
10kΩ
GND SHDN SDI CLK
TO µC
Figure 30. A Low Noise 90 MHz PGA
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm)
20-Pin Plastic DIP Package
(N-20)
20-Lead SOIC Package
(R-20)
1.07 (27.18) MAX
0.512 (13.00)
0.496 (12.60)
20
1
11
0.255 (6.477)
0.245 (6.223)
10
20
11
0.32 (8.128)
0.135 (3.429)
0.125 (3.17)
0.060 (1.52)
0.015 (0.38)
0.30 (7.62)
PIN 1
0.145 (3.683)
MAX
1
10
0.125 (3.175)
MIN
0.011 (0.28)
0.009 (0.23)
SEATING
PLANE
0.021 (0.533) 0.11 (2.79) 0.065 (1.66)
0.015 (0.381) 0.09 (2.28) 0.045 (1.15)
PIN 1
15°
0
0.107 (2.72)
0.089 (2.26)
8°
0°
0.050
(1.27)
BSC
0.011 (0.275)
0.005 (0.125)
0.022 (0.56)
0.014 (0.36)
SEATING
PLANE
0.015 (0.38)
0.007 (0.18)
0.034 (0.86)
0.018 (0.46)
20-Lead Thin Surface Mount TSSOP Package
(RU-20)
0.260 (6.60)
0.252 (6.40)
20
11
10
1
0.006 (0.15)
0.002 (0.05)
PIN 1
0.0433
(1.10)
MAX
0.028 (0.70)
0.020 (0.50)
8°
0°
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
BSC
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
–16–
REV. 0
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