AD9057-PCB [ADI]
8-Bit 40 MSPS/50 MSPS/80 MSPS Converter; 8位40 MSPS / 50 MSPS / 80 MSPS转换器
| 型号： | AD9057-PCB |
| 厂家： | 
ADI |
| 描述： | 8-Bit 40 MSPS/50 MSPS/80 MSPS Converter |
| 文件： | 总12页 (文件大小：206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-Bit
a
40 MSPS/50 MSPS/80 MSPS Converter
AD9057
FEATURES
FUNCTIONAL BLOCK DIAGRAM
8-Bit, Low Power ADC: 200 mW Typical
120 MHz Analog Bandwidth
V
PWRDN
V
DD
D
On-Chip 2.5 V Reference and T/H
1 V p-p Analog Input Range
Single 5 V Supply Operation
5 V or 3 V Logic Interface
Power-Down Mode: < 10 mW
Three Performance Grades (40 MSPS, 60 MSPS, 80 MSPS)
AD9057
8
AIN
D7–D0
T/H
ADC
1k⍀
BIAS OUT
VREF IN
VREF OUT
+2.5V
APPLICATIONS
Digital Communications (QAM Demodulators)
RGB and YC/Composite Video Processing
Digital Data Storage Read Channels
Medical Imaging
GND
ENCODE
Digital Instrumentation
PRODUCT DESCRIPTION
Customers desiring multichannel digitization may consider the
AD9059, a dual 8-bit, 60 MSPS monolithic based on the
AD9057 ADC core. The AD9059 is available in a 28-lead sur-
face mount plastic package (28 SSOP) and is specified over the
industrial temperature range.
The AD9057 is an 8-bit monolithic analog-to-digital converter
optimized for low cost, low power, small size, and ease of use.
With a 40 MSPS, 60 MSPS, or 80 MSPS encode rates capabil-
ity and full-power analog bandwidth of 120 MHz, the component
is ideal for applications requiring excellent dynamic performance.
PIN CONFIGURATION
To minimize system cost and power dissipation, the AD9057
includes an internal 2.5 V reference and a track-and-hold
circuit. The user must provide only a 5 V power supply and an
encode clock. No external reference or driver components are
required for many applications.
1
2
20
PWRDN
D0 (LSB)
19 D1
18 D2
17 D3
VREF OUT
VREF IN
GND
3
The AD9057’s encode input is TTL/CMOS compatible and the
8-bit digital outputs can be operated from 5 V or 3 V supplies. A
power-down function may be exercised to bring total consump-
tion to < 10 mW. In power-down mode the digital outputs are
driven to a high impedance state.
4
AD9057
V
D
5
TOP VIEW 16 GND
(Not to Scale)
BIAS OUT
AIN
6
15
V
DD
14 D4
13
7
V
D
8
D5
12 D6
D7 (MSB)
Fabricated on an advanced BiCMOS process, the AD9057 is
available in a space saving 20-lead surface mount plastic pack-
age (20 SSOP) and is specified over the industrial (–40°C to
+85°C) temperature range.
9
GND
10
11
ENCODE
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2001
(V = 5 V, V = 3 V; external reference, unless otherwise noted.)
AD9057–SPECIFICATIONS
D
DD
Test
Level
AD9057BRS-40
AD9057BRS-60
AD9057BRS-80
Parameter
Temp
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
RESOLUTION
8
8
8
Bits
DC ACCURACY
Differential Nonlinearity
25°C
Full
25°C
Full
Full
25°C
Full
I
VI
I
VI
VI
I
0.75
0.75
1.9
2.0
1.9
2.0
0.75
0.75
1.9
2.0
1.9
2.0
0.75
0.75
1.9
2.0
1.9
2.0
LSB
LSB
LSB
LSB
Integral Nonlinearity
No Missing Codes
Gain Error1
GUARANTEED
GUARANTEED
GUARANTEED
–6
–8
–2.5
+6
+8
–6
–8
–2.5
+6
+8
–6
–8
–2.5
+6
+8
% FS
% FS
ppm/°C
VI
V
Gain Tempco1
Full
70
70
70
ANALOG INPUT
Input Voltage Range
(Centered at 2.5 V)
Input Offset Voltage
25°C
25°C
Full
25°C
25°C
25°C
Full
V
I
VI
V
V
I
1.0
0
1.0
0
1.0
0
V p-p
mV
mV
kΩ
–15
–25
+15
+25
–15
–25
+15
+25
–15
–25
+15
+25
Input Resistance
Input Capacitance
Input Bias Current
150
2
6
150
2
6
150
2
6
pF
16
25
16
25
16
25
µA
VI
V
µA
Analog Bandwidth
25°C
120
120
120
MHz
BANDGAP REFERENCE
Output Voltage
Temperature Coefficient
Full
Full
VI
V
2.4
40
2.5
10
2.6
2.4
60
2.5
10
2.6
2.4
80
2.5
10
2.6
V
ppm/°C
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Aperture Delay (tA)
Full
Full
25°C
25°C
Full
Full
VI
IV
V
V
IV
IV
MSPS
MSPS
ns
ps, rms
ns
5
5
5
2.7
5
6.6
11.5
2.7
5
6.6
9.5
2.7
5
6.6
8.0
Aperture Uncertainty (Jitter)
Output Valid Time (tV)2
4.0
4.0
4.0
2
Output Propagation Delay (tPD
)
18.0
14.2
11.3
ns
DYNAMIC PERFORMANCE3
Transient Response
Overvoltage Recovery Time
Signal-to-Noise Ratio (SINAD)
(With Harmonics)
fIN = 10.3 MHz
fIN = 76 MHz
Effective Number of Bits
fIN = 10.3 MHz
fIN = 76 MHz
25°C
25°C
V
V
9
9
9
9
9
9
ns
ns
25°C
25°C
I
V
42
45.5
44.0
42
45
43.5
41.5
6.6
45
43.5
dB
dB
25°C
25°C
I
V
6.7
7.2
7.0
6.7
7.2
6.9
7.2
6.9
Bits
Bits
Signal-to-Noise Ratio (SNR)
(Without Harmonics)
fIN = 10.3 MHz
fIN = 76 MHz
2nd Harmonic Distortion
fIN = 10.3 MHz
fIN = 76 MHz
3rd Harmonic Distortion
fIN = 10.3 MHz
fIN = 76 MHz
Two Tone Intermodulation
Distortion (IMD)
25°C
25°C
I
V
43
46.5
45.5
43
46
45
42.5
–50
–46
46
45
dB
dB
25°C
25°C
I
V
–50
–46
–62
–54
–50
–46
–62
–54
–62
–54
dBc
dBc
25°C
25°C
I
V
–60
–54
–60
–54
–60
–54
dBc
dBc
25°C
25°C
25°C
V
V
V
–52
0.8
1.0
–52
0.8
1.0
–52
0.8
1.0
dBc
Degrees
%
Differential Phase
Differential Gain
DIGITAL INPUTS
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Full
Full
Full
Full
25°C
25°C
25°C
VI
VI
VI
VI
V
IV
IV
2.0
2.0
2.0
V
V
0.8
1
1
0.8
1
1
0.8
1
1
µA
µA
pF
ns
ns
4.5
4.5
4.5
Encode Pulsewidth High (tEH
Encode Pulsewidth Low (tEL
)
)
9.0
9.0
166
166
6.7
6.7
166
166
5.5
5.5
166
166
–2–
REV. C
AD9057
Test
Temp Level
AD9057BRS-40
Min Typ Max
AD9057BRS-60
Min Typ Max
AD9057BRS-80
Min Typ Max
Parameter
Unit
DIGITAL OUTPUTS
Logic “1” Voltage (VDD = 3 V)
Logic “1” Voltage (VDD = 5 V)
Logic “0” Voltage
Full
Full
Full
VI
IV
VI
2.95
4.95
2.95
4.95
2.95
4.95
V
V
V
0.05
Offset Binary Code
0.05
Offset Binary Code
0.05
Offset Binary Code
Output Coding
POWER SUPPLY
V
D Supply Current (VD = 5 V)
Full
Full
Full
Full
VI
VI
VI
VI
36
4.0
192
6
48
38
5.5
205
6
48
40
7.4
220
6
51
mA
mA
mW
mW
VDD Supply Current (VDD = 3 V)4
Power Dissipation5, 6
6.5
260
10
6.5
260
10
8.8
281
10
Power-Down Dissipation
Power Supply Rejection Ratio
(PSRR)
25°C
I
15
15
15
mV/V
NOTES
1Gain error and gain temperature coefficient are based on the ADC only (with a fixed 2.5 V external reference).
2tV and tPD are measured from the 1.5 V level of the ENCODE to the 10%/90% levels of the digital output swing. The digital output load during test is not to exceed
an ac load of 10 pF or a dc current of 40 µA.
3SNR/harmonics based on an analog input voltage of –0.5 dBFS referenced to a 1.0 V full-scale input range.
4Digital supply current based on VDD = 3 V output drive with <10 pF loading under dynamic test conditions.
5Power dissipation is based on specified encode and 10.3 MHz analog input dynamic test conditions (VD = 5 V 5%, VDD = 3 V 5%).
6Typical thermal impedance for the RS style (SSOP) 20-lead package: θJC = 46°C/W, θCA = 80°C/W, θJA = 126°C/W.
Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
Test Level
Description
I
100% Production Tested
II
100% Production Tested at 25°C and Sample
Tested at Specified Temperatures
III
IV
Sample Tested Only
Parameter is Guaranteed by Design and Char-
acterization Testing
V
Parameter is a Typical Value Only
VI
100% Production Tested at 25°C; Guaran-
teed by Design and Characterization Testing
for Industrial Temperature Range
N
N + 5
N + 3
AIN
N + 1
N + 4
N + 2
tA
tEH
tEL
ENCODE
tV
DIGITAL
OUTPUTS
N – 3
N – 2
N – 1
N
N + 1
N + 2
tPD
MIN TYP MAX
2.7 ns
t
t
APERTURE DELAY
A
PULSEWIDTH HIGH
PULSEWIDTH LOW
OUTPUT VALID TIME
OUTPUT PROP DELAY
EH
166 ns
t
EL
166 ns
t
V
4.0 ns
6.6 ns
9.5 ns
t
PD
Figure 1. Timing Diagram
–3–
REV. C
AD9057
ABSOLUTE MAXIMUM RATINGS
PIN FUNCTION DESCRIPTIONS
VD, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . –0.5 V to VD + 0.5 V
Digital Inputs . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Pin No.
Mnemonic
Function
1
PWRDN
Power-Down Function Select;
Logic HIGH for Power-Down
Mode (Digital Outputs Go to
High Impedance State).
VREF Input . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VD + 0.5 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . . 150°C
2
3
VREF OUT
VREF IN
Internal Reference Output
(2.5 V typ); Bypass with 0.1 µF
to Ground.
Reference Input for ADC (2.5 V
typ, 10%)
ORDERING GUIDE
Temperature
4, 9, 16
5, 8
GND
Ground (Analog/Digital)
Analog 5 V Power Supply
Model
AD9057BRS–40, –60, –80 –40°C to +85°C RS-20
AD9057/PCB 25°C Evaluation Board
Range
Package Option*
VD
6
BIAS OUT
Bias Pin for AC Coupling
(1 kΩ to REF IN)
7
AIN
Analog Input for ADC
*RS = Shrink Small Outline (SSOP).
10
ENCODE
Encode Clock for ADC (ADC
Samples on Rising Edge of
ENCODE)
Table I. Digital Coding (VREF = 2.5 V)
Analog Input
Voltage Level
Digital Output
11–14, 17–20 D7–D4, D3–D0 Digital Outputs of ADC
3.0 V
Positive Full Scale
Midscale +1/2 LSB
Midscale –1/2 LSB
Negative Full Scale
1111 1111
1000 0000
0111 1111
0000 0000
15
VDD
Digital Output Power Supply;
Nominally 3 V to 5 V.
2.502 V
2.498 V
2.0 V
PIN CONFIGURATION
1
2
20
PWRDN
D0 (LSB)
19 D1
18 D2
17 D3
VREF OUT
VREF IN
GND
3
4
AD9057
V
D
5
TOP VIEW 16 GND
(Not to Scale)
BIAS OUT
AIN
6
15
V
DD
7
14 D4
13
V
D
8
D5
12 D6
9
GND
10
D7 (MSB)
11
ENCODE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9057 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. C
Typical Performance Characteristics–AD9057
0
–10
–20
–30
–30
ENCODE = 60MSPS
ANALOG IN = 10.3MHz, –0.5dBFS
SINAD = 46.1dB
ENCODE = 60MSPS
–35
AIN = –0.5dBFS
ENOB = 7.36 BITS
SNR = 46.5dB
–40
–45
ND
–40
–50
–60
–70
–80
–90
2
HARMONIC
–50
–55
–60
–65
–70
RD
3
HARMONIC
0
30
0
20
40
60
80
100
120
140
160
FREQUENCY – MHz
ANALOG INPUT FREQUENCY – MHz
TPC 1. Spectral Plot 60 MSPS, 10.3 MHz
TPC 4. Harmonic Distortion vs. AIN Frequency
0
0
ENCODE = 60MSPS
ENCODE = 60MSPS
ANALOG IN = 76MHz, –0.5dBFS
–10
–10
F1 IN = 9.5MHz @ –7.0dBFS
SINAD = 44.9dB
ENOB = 7.16 BITS
–20 SNR = 45.2dB
F2 IN = 9.9MHz @ –7.0dBFS
2F1 - F2 = –52.0dBc
2F2 - F1 = –53.0dBc
–20
–30
–40
–50
–60
–70
–30
–40
–50
–60
–70
–80
–80
–90
–90
0
30
0
10
20
30
FREQUENCY – MHz
FREQUENCY – MHz
TPC 2. Spectral Plot 60 MSPS, 76 MHz
TPC 5. Two-Tone Intermodulation Distortion
48
46
44
42
40
54
SNR
SNR
48
42
SINAD
SINAD
36
30
ENCODE = 60MSPS
AIN = –0.5dBFS
38
36
34
32
30
AIN = 10.3MHz, –0.5dBFS
24
18
12
0
0
20
40
60
80
100
120
140
160
5
10
20
30
40
50
60
70
80
90
ENCODE RATE – MSPS
ANALOG INPUT FREQUENCY – MHz
TPC 3. SINAD/SNR vs. AIN Frequency
TPC 6. SINAD/SNR vs. Encode Rate
–5–
REV. C
AD9057
12.0
350
11.0
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
300
250
200
150
100
50
V
= 3V
DD
V
= 5V
DD
V
= 3V
DD
V
= 5V
DD
AIN = 10.3MHz, –0.5dBFS
0
5
–45
0
25
TEMPERATURE –
70
90
10
20
30
40
50
60
70
80
90
C
ENCODE RATE – MSPS
TPC 7. Power Dissipation vs. Encode Rate
TPC 10. tPD vs. Temperature/Supply (VDD = 3 V/5 V)
46.5
46.0
46.5
46.0
SNR
SNR
45.5
45.0
45.5
45.0
44.5
44.0
SINAD
44.5
44.0
ENCODE = 60MSPS
43.5
AIN = 10.3MHz, –0.5dBFS
SINAD
43.0
42.5
42.0
41.5
43.5
ENCODE = 60MSPS
AIN = 10.3MHz, –05dBFS
43.0
42.5
5.8
6.7
7.5
8.35
9.2
10.0
10.9
–45
0
25
70
90
TEMPERATURE –
C
ENCODE HIGH PULSEWIDTH – ns
TPC 8. SINAD/SNR vs. Temperature
TPC 11. SINAD/SNR vs. Encode Pulsewidth
0
–1
–2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
–1.8
–3
ENCODE = 60MSPS
AIN = –0.5dBFS
–4
–5
–6
–7
–8
–9
–10
–45
0
25
70
90
1
2
5
10
20
50
100
200
500
TEMPERATURE –
C
ANALOG FREQUENCY – MHz
TPC 9. ADC Gain vs. Temperature (with External
2.5 V Reference)
TPC 12. ADC Frequency Response
–6–
REV. C
AD9057
5V
THEORY OF OPERATION
The AD9057 combines Analog Devices’ proprietary MagAmp
gray code conversion circuitry with flash converter technology
to provide a high performance, low cost ADC. The design
architecture ensures low power, high speed, and 8-bit accuracy.
A single-ended TTL/CMOS compatible ENCODE input controls
ADC timing for sampling the analog input pin and strobing the
digital outputs (D7–D0). An internal voltage reference (VREF
OUT) may be used to control ADC gain and offset or an exter-
nal reference may be applied.
REF OUT
10k⍀
AD9057
0.1F
10k⍀
REF IN
5V
AD8041
VIN
(–0.5V
TO +0.5V)
AIN
1k⍀
The analog input signal is buffered at the input of the ADC and
applied to a high speed track-and-hold. The T/H circuit holds the
analog input value during the conversion process (beginning with
the rising edge of the ENCODE command). The T/H’s output
signal passes through the gray code and flash conversion stages
to generate coarse and fine digital representations of the held
analog input level. Decode logic combines the multistage data
and aligns the 8-bit word for strobed outputs on the rising edge
of the ENCODE command. The MagAmp/Flash architecture of
the AD9057 results in three pipeline delays for the output data.
1k⍀
Figure 3. DC-Coupled AD9057 (Inverted VIN)
Voltage Reference
A stable and accurate 2.5 V voltage reference is built into the
AD9057 (VREF OUT). The reference output may be used to
set the ADC gain/offset by connecting VREF OUT to VREF IN.
The internal reference is capable of providing 300 µA of drive
current (for dc biasing the analog input or other user circuitry).
Some applications may require greater accuracy, improved
temperature performance, or gain adjustments that cannot be
obtained using the internal reference. An external voltage may
be applied to the VREF IN with VREF OUT disconnected for
gain adjustment of up to 10% (the VREF IN pin is internally
tied directly to the ADC circuitry). ADC gain and offset will
vary simultaneously with external reference adjustment with a
1:1 ratio (a 2% or 50 mV adjustment to the 2.5 V reference
varies ADC gain by 2% and ADC input range center offset by
50 mV). Theoretical input voltage range versus reference input
voltage may be calculated from the following equations:
USING THE AD9057
Analog Inputs
The AD9057 provides a single-ended analog input impedance
of 150 kΩ. The input requires a dc bias current of 6 µA (typical)
centered near 2.5 V ( 10%). The dc bias may be provided by
the user or may be derived from the ADC’s internal voltage
reference. Figure 2 shows a low cost dc bias implementation
allowing the user to capacitively couple ac signals directly into
the ADC without additional active circuitry. For best dynamic
performance, the VREF OUT pin should be decoupled to
ground with a 0.1 µF capacitor (to minimize modulation of
the reference voltage) and the bias resistor should be approxi-
mately 1 kΩ. A 1 kΩ bias resistor ( 20%) is included within
the AD9057 and may be used to reduce application board size
and complexity.
V
RANGE (p-p)
= VREF IN/2.5
= VREF IN
VMIDSCALE
VTOP-OF-RANGE
= VREF IN + VRANGE/2
VBOTTOM-OF-RANGE = VREF IN – VRANGE/2
Digital Logic (5 V/3 V Systems)
5V
The digital inputs and outputs of the AD9057 can easily be
configured to interface directly with 3 V or 5 V logic systems.
The ENCODE and power-down (PWRDN) inputs are CMOS
stages with TTL thresholds of 1.5 V, making the inputs compat-
ible with TTL, 5 V CMOS, and 3 V CMOS logic families. As
with all high-speed data converters, the encode signal should be
clean and jitter free to prevent degradation of ADC dynamic
performance.
REF OUT
REF IN
0.1F
1k⍀
BIAS OUT
0.1F
VIN
(1V p-p)
AIN
AD9057
The AD9057’s digital outputs will also interface directly with
5 V or 3 V CMOS logic systems. The voltage supply pin (VDD
for these CMOS stages is isolated from the analog VD voltage
supply. By varying the voltage on this supply pin the digital
output HIGH level will change for 5 V or 3 V systems. Optimum
SNR is obtained running the outputs at 3 V. Care should be
taken to isolate the VDD supply voltage from the 5 V analog
supply to minimize digital noise coupling into the ADC.
)
Figure 2. Capacitively Coupled AD9057
Figure 3 shows typical connections for high-performance dc
biasing using the ADC’s internal voltage reference. All compo-
nents may be powered from a single 5 V supply (in the example,
analog input signals are referenced to ground).
REV. C
–7–
AD9057
The AD9057 provides high impedance digital output operation
when the ADC is driven into power-down mode (PWRDN, logic
HIGH). A 200 ns (minimum) power-down time should be
provided before a high impedance characteristic is required at
the outputs. A 200 ns power-up period should be provided to
ensure accurate ADC output data after reactivation (valid out-
put data is available three clock cycles after the 200 ns delay).
full-power analog bandwidth of 2× the maximum sampling rate,
the ADC provides sufficient pixel to pixel transient settling time
to ensure accurate 60 MSPS video digitization. Figure 5 shows a
typical RGB video digitizer implementation for the AD9057.
8
AD9057
AD9057
AD9057
RED
Timing
8
8
GREEN
The AD9057 is guaranteed to operate with conversion rates from
5 MSPS to 80 MSPS depending on grade. The ADC is designed
to operate with an encode duty cycle of 50%, but performance
is insensitive to moderate variations. Pulsewidth variations of
up to 10% (allowing the encode signal to meet the minimum/
maximum HIGH/LOW specifications) will cause no degrada-
tion in ADC performance (see Figure 1 timing diagram).
BLUE
PIXEL CLOCK
H-SYNC
PLL
Power Dissipation
Figure 5. RGB Video Encoder
Evaluation Board
The power dissipation of the AD9057 is specified to reflect a
typical application setup under the following conditions: analog
input is –0.5 dBFS at 10.3 MHz, VD is 5 V, VDD is 3 V, and digital
outputs are loaded with 7 pF typical (10 pF maximum). The
actual dissipation will vary as these conditions are modified in
user applications. TPC 7 shows typical power consumption for the
AD9057 versus ADC encode frequency and VDD supply voltage.
The AD9057/PCB evaluation board provides an easy-to-use
analog/digital interface for the 8-bit, 60 MSPS ADC. The board
includes typical hardware configurations for a variety of high-
speed digitization evaluations. On-board components include
the AD9057 (in the 20-lead SSOP package), an optional analog
input buffer amplifier, a digital output latch, board timing driv-
ers, an analog reconstruction digital-to-analog converter, and
configurable jumpers for ac coupling, dc coupling, and power-
down function testing. The board is configured at shipment for
dc coupling using the AD9057’s internal voltage reference.
A power-down function allows users to reduce power dissipation
when ADC data is not required. A TTL/CMOS HIGH signal
(PWRDN) shuts down portions of the ADC and brings total
power dissipation to less than 10 mW. The internal bandgap
voltage reference remains active during power-down mode to
minimize ADC reactivation time. If the power-down function is
not desired, Pin 1 should be tied to ground.
For dc-coupled analog input applications, amplifier U2 is con-
figured to operate as a unity gain inverter with adjustable offset
for the analog input signal. For full-scale ADC drive, the analog
input signal should be 1 V p-p into 50 Ω (R1) referenced to
ground (0 V). The amplifier offsets the analog signal by +VREF
(2.5 V typical) to center the voltage for proper ADC input drive.
For dc-coupled operation, connect E1 to E2 (analog input to
R2) and E11 to E12 (amplifier output to analog input of AD9057)
using the board jumper connectors. DC offset of the analog
input signal can be modified by adjusting potentiometer R10.
APPLICATIONS
The wide analog bandwidth of the AD9057 makes it attractive for
a variety of high-performance receiver and encoder applications.
Figure 4 shows two ADCs in a typical low cost I and Q demodula-
tor implementation for cable, satellite, or wireless LAN modem
receivers. The excellent dynamic performance of the ADC at
higher analog input frequencies and encode rates empowers
users to employ direct IF sampling techniques (refer to TPC 2
spectral plot). IF sampling eliminates or simplifies analog mixer
and filter stages to reduce total system cost and power.
For ac-coupled analog input applications, amplifier U2 is
removed from the analog signal path. The analog signal is
coupled into the input of the AD9057 through capacitor C2.
The ADC pulls analog input bias current from the VREF IN
voltage through the 1 kΩ resistor internal to the AD9057 (BIAS
OUT). The analog input signal to the board should be 1 V p-p
into 50 Ω (R1) for full-scale ADC drive. For ac-coupled operation,
connect E1 to E3 (analog input A to C2 feedthrough capacitor)
and E10 to E12 (C2 to the analog input and internal bias resis-
tor) using the board jumper connectors.
BPF
BPF
AD9057
AD9057
IF IN
90
The on-board reference voltage may be used to drive the ADC
or an external reference may be applied. To use the internal
voltage reference, connect E6 to E5 (VREF OUT to VREF IN).
To apply an external voltage reference, connect E4 to E5
(external reference from the REF banana jack to VREF IN).
The external voltage reference should be 2.5 V 10%.
VCO
VCO
Figure 4. I and Q Digital Receiver
The high sampling rate and analog bandwidth of the AD9057
are ideal for computer RGB video digitizer applications. With a
–8–
REV. C
AD9057
The power-down function of the AD9057 can be exercised
through a board jumper connection. Connect E7 to E9 (5 V to
PWRDN) for power-down operation. For normal operation,
connect E8 to E9 (ground to PWRDN).
oscilloscope or spectrum analyzer. The DAC converts the
ADC’s digital outputs to an analog signal for examination at
the DAC OUT connector. The DAC is clocked at the ADC
ENCODE frequency. The AD9760 is a 10-bit/100 MSPS single
5 V supply DAC. The reconstruction signal facilitates quick
system troubleshooting or confirmation of ADC functionality
without requiring external digital memory, timing, or display
interfaces. The DAC can be used for limited dynamic testing,
but customers should note that test results will be based on the
combined performance of the ADC and DAC (the best ADC
performance will be recognized by evaluating the digital outputs
of the ADC directly).
The encode signal source should be TTL/CMOS compatible
and capable of driving a 50 Ω termination (R7). The digital
outputs of the AD9057 are buffered through latches on the
evaluation board (U3) and are available for the user at connec-
tor Pins 30–37. Latch timing is derived from the ADC ENCODE
clock and a digital clocking signal is provided for the board
user at connector Pins 2 and 21.
An on-board reconstruction digital-to-analog converter is
available for quick evaluations of ADC performance using an
V
D
V
D
ENCODE
PWRDN
500⍀
V
AIN
REFIN
Digital Inputs
Analog Input
V
, 3V TO 5V
DD
V
D
1k⍀
V
BIAS OUT
REFIN
D0–D7
Digital Outputs
Bias Output
V
D
V
D
3k⍀
V
V
REFIN
REFOUT
2.5k⍀
V
Output
V
Input
REF
REF
Figure 6. Equivalent Circuits
REV. C
–9–
AD9057
E7
5V
PWRDN
E9
E8
J6, REF
GND
C17
0.1F
ANALOG IN
C37DRPF
P2
U2
E4
E5
E6
AD8041Q
1
2
3
4
5
R2
1k⍀
1
2
3
4
5
20
19
18
17
16
1
2
3
4
8
7
6
5
PWRDN
REF OUT
REF IN
GND
D0
D1
D2
D3
DIS
+V
NC
(LSB) D0
D1
U3
E2
R5
BNC
J1
74ACQ574
S
2k⍀
E1
9
8
7
6
5
12
13
14
15
16
D2
D3
GND
D7
D6
D5
D4
D3
D2
D1
D0
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
8D 8Q
7D 7Q
6D 6Q
5D 5Q
4D 4Q
3D 3Q
2D 2Q
C1
0.1F
R10
500
E3
NC
GND
5V
–V
S
GND
V
D
6
7
6
7
15
14
13
12
11
V
R3
1k⍀
DD
BIAS OUT
AIN
R1
50⍀
R4
2k⍀
V
DD
D4
D5
D6
D7
8
9
10
11
12
D4
D5
D6
8
9
R6
10⍀
5V
GND
4
3
2
17
18
19
V
D
E11
GND
ENC
10
E12
E10
(MSB) D7
1D 1Q
CK
OE
13
14
15
16
17
18
19
11
1
C2
0.1F
20
21
22
23
24
25
26
U4
BNC
J3
74AC00
DAC
1
2
AD9760AR
3
28
ENCODE
5V
C18
CLK
(MSB)
DB9
27
DVDD
24
R7
50⍀
U4
74AC00
5V
5V
1
2
3
0.1F
DA7
DA6
DA5
AVDD
4
5
27
28
29
6
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
23
19
COMP2
COMP1
4
DA4
5
C19
0.1F
U4
74AC00
30
31
32
33
34
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA3
DA2
DA1
DA0
GND
GND
18
12
13
6
7
FSADJ
11
8
17
REFIO
16
R9
2k⍀
8
9
U4
74AC00
REFLO
35
36
37
10
15
9
SLEEP
10
C13
0.1F
(LSB)
IOUT
A
B
21
BNC
J2
22
ANALOG
RECONSTRUCT
DAC OUT
PWRDN
V
J7, V
DD
DD
R8
50⍀
R11
50⍀
+
C11
10F
C10
0.1F
J4, GND
J5, 5V
C7
0.1F
C8
0.1F
C14
0.1F
+
C5
0.1F
C9
0.1F
C12
10F
C3
0.1F
C4
0.1F
DECOUPLING CAPS
Figure 7. Evaluation Board Schematic
–10–
REV. C
AD9057
Figure 8. Evaluation Board Layout
REV. C
–11–
AD9057
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead SSOP
(RS-20)
0.295 (7.50)
0.271 (6.90)
20
11
1
10
0.07 (1.78)
0.066 (1.67)
0.078 (1.98)
0.068 (1.73)
PIN 1
0.037 (0.94)
0.022 (0.559)
8؇
0؇
0.0256
(0.65)
BSC
0.008 (0.203)
0.002 (0.050)
SEATING
PLANE
0.009 (0.229)
0.005 (0.127)
Revision History
Location
Page
Data Sheet changed from REV. B to REV. C.
Edit to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
–12–
REV. C
相关型号：
AD9057BRS-RL40
IC 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO20, PLASTIC, SSOP-20, Analog to Digital Converter
ADI
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