ADA4084-4ARUZ-RL
更新时间：2024-09-18 16:53:17
品牌：ADI
描述：30 V, Low Noise, Rail-to-Rail Input/Output, Low Power Operational Quad Amplifier
概述
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替代型号ADA4084-4ARUZ-RL 概述
30 V, Low Noise, Rail-to-Rail Input/Output, Low Power Operational Quad Amplifier 运算放大器
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PDF下载30 V, Low Noise, Rail-to-Rail Input/Output,
Low Power Operational Amplifiers
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
FEATURES
PIN CONNECTION DIAGRAM
ADA4084-2
Rail-to-rail input/output
OUT A 1
–IN A 2
+IN A 3
V– 4
8 V+
Low power: 0.625 mA typical per amplifier at 15 V
Gain bandwidth product: 15.9 MHz at AV = 100 typical
Unity-gain crossover: 9.9 MHz typical
−3 dB closed-loop bandwidth: 13.9 MHz typical at 15 V
Low offset voltage: 100 µV maximum (SOIC)
Unity-gain stable
7 OUT B
6 –IN B
5 +IN B
NOTES
1. FOR THE LFCSP PACKAGE,
THE EXPOSED PAD MUST BE
CONNECTED TO V–.
High slew rate: 4.6 V/µs typical
Figure 1. ADA4084-2, 8-Lead LFCSP (CP); for Additional Packages and
Models, See the Pin Configurations and Function Descriptions Section
Low noise: 3.9 nV/√Hz typical at 1 kHz
Long-term offset voltage drift (10,000 hours): 3 µV typical
Temperature hysteresis: 4 µV typical
APPLICATIONS
Battery-powered instrumentation
High-side and low-side sensing
Power supply control and protection
Telecommunications
Digital-to-analog converter (DAC) output amplifiers
Analog-to-digital converter (ADC) input buffers
GENERAL DESCRIPTION
The ADA4084-1 (single), ADA4084-2 (dual), and ADA4084-4
(quad) are single-supply, 10 MHz bandwidth amplifiers featuring
rail-to-rail inputs and outputs. They are guaranteed to operate
from +3 V to +30 V (or 1.5 V to 15 V).
The single ADA4084-1 is available in the 5-lead SOT-23 and
8-lead SOIC; the dual ADA4084-2 is available in the 8-lead
SOIC, 8-lead MSOP, and 8-lead LFCSP surface-mount
packages; and the ADA4084-4 is offered in the 14-lead TSSOP
and 16-lead LFCSP.
These amplifiers are well suited for single-supply applications
requiring both ac and precision dc performance. The combination
of wide bandwidth, low noise, and precision makes the
ADA4084-1/ADA4084-2/ADA4084-4 useful in a wide variety of
applications, including filters and instrumentation.
The ADA4084-1/ADA4084-2/ADA4084-4 are members of a
growing series of high voltage, low noise op amps offered by
Analog Devices, Inc. (see Table 1).
Table 1. Low Noise Op Amps
Other applications for these amplifiers include portable telecom-
munications equipment, power supply control and protection, and
use as amplifiers or buffers for transducers with wide output
ranges. Sensors requiring a rail-to-rail input amplifier include
Hall effect, piezoelectric, and resistive transducers.
Single
Dual
Quad
Voltage Noise
AD8597
AD8599
1.1 nV/Hz
ADA4004-1 ADA4004-2 ADA4004-4 1.8 nV/Hz
AD8675
AD8671
AD8676
AD8672
2.8 nV/Hz rail-to-rail output
2.8 nV/Hz
AD8674
OP27, OP37
3.2 nV/Hz
The ability to swing rail to rail at both the input and output
enables designers to build multistage filters in single-supply
systems and to maintain high signal-to-noise ratios.
ADA4084-1 ADA4084-2 ADA4084-4 3.9 nV/Hz rail-to-rail
input/output
The ADA4084-1/ADA4084-2/ADA4084-4 are specified over
the industrial temperature range of −40°C to +125°C.
Rev. I
Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
5 V Characteristics................................................................... 17
15 V Characteristics ................................................................ 23
Applications Information .............................................................. 29
Functional Description.............................................................. 29
Start-Up Characteristics............................................................ 30
Input Protection ......................................................................... 30
Output Phase Reversal............................................................... 30
Designing Low Noise Circuits in Single-Supply Applications .. 31
Comparator Operation.............................................................. 31
Long-Term Drift......................................................................... 32
Temperature Hysteresis ............................................................. 32
Outline Dimensions....................................................................... 33
Ordering Guide .......................................................................... 36
Applications....................................................................................... 1
Pin Connection Diagram ................................................................ 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 4
Electrical Characteristics............................................................. 4
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ........................................... 11
1.5 V Characteristics................................................................ 11
REVISION HISTORY
5/2017—Rev. H to Rev. I
6/2015—Rev. F to Rev. G
Changed CP-8-12 to CP-8-11 ...................................... Throughout
Changed CP-16-26 to CP-16-17.................................. Throughout
Changes to Features Section............................................................ 1
Added Long-Term Drift Section, Temperature Hysteresis
Section, Figure 112, Figure 113, and Figure 114; Renumbered
Sequentially ..................................................................................... 32
Updated Outline Dimensions ....................................................... 34
Changes to Ordering Guide .......................................................... 36
Changes to Figure 96 and Figure 97............................................. 24
1/2015—Rev. E to Rev. F
Moved Revision History...................................................................3
Changes to Table 5.............................................................................7
Changes to Ordering Guide.......................................................... 29
7/2014—Rev. D to Rev. E
Added ADA4084-1.............................................................Universal
Added Figure 1; Renumbered Sequentially ...................................1
Changes to Output Voltage High Parameter, Table 2...................3
Changes to Current Noise Density Parameter, Table 3 ................4
Changes to Current Noise Density Parameter, Table 4 ................5
Changes to Figure 8 Caption, and Figure 9 to Figure 11 .............7
Changes to Figure 13.........................................................................8
Changes to Figure 21.........................................................................9
Added Figure 31; Renumbered Sequentially .............................. 11
Changes to Figure 30 Caption, and Figure 32 to Figure 34 ...... 11
Changes to Figure 36 Caption to Figure 39 Caption ................. 12
Changes to Figure 50...................................................................... 14
Added Figure 60 ............................................................................. 16
Changes to Figure 59 Caption, Figure 62, and Figure 63.......... 16
Changes to Figure 65 Caption to Figure 68 Caption ................. 17
Changes to Figure 79...................................................................... 19
Added Figure 89 ............................................................................. 21
Changes to Figure 88 Caption, Figure 91 Caption, and
8/2015—Rev. G to Rev. H
Added 5-Lead SOT-23 .......................................................Universal
Changes to Pin Connection Diagram Section, Figure 1, and
General Description Section........................................................... 1
Deleted Figure 3; Renumbered Sequentially................................. 1
Changes to Large Signal Voltage Gain Parameter, Table 2.......... 4
Changes to Large Signal Voltage Gain Parameter, Table 3.......... 5
Changes to Large Signal Voltage Gain Parameter, Table 4.......... 6
Changes to Table 6............................................................................ 7
Moved Figure 3 ................................................................................. 8
Added Pin Configurations and Function Descriptions Section,
Figure 4, Figure 5, Table 7, Table 8, and Table 9; Renumbered
Sequentially ....................................................................................... 8
Added Figure 6, Figure 7, Figure 8, Table 10, and Table 11 ........ 9
Moved Figure 9 ............................................................................... 10
Added Table 12 ............................................................................... 10
Added Figure 11 and Figure 15..................................................... 11
Added Figure 42 and Figure 46..................................................... 17
Added Figure 73 and Figure 77..................................................... 23
Updated Outline Dimensions ....................................................... 32
Changes to Ordering Guide .......................................................... 35
Figure 92 Caption........................................................................... 21
Changes to Ordering Guide.......................................................... 28
Rev. I | Page 2 of 36
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
11/2013—Rev. C to Rev. D
Added Figure 55 and Figure 57.....................................................17
Added Startup Characteristics Section ........................................23
Moved Figure 78..............................................................................23
Changes to Output Phase Reversal Section and Comparator
Operation Section ...........................................................................24
Updated Outline Dimensions........................................................25
Changes to Ordering Guide...........................................................26
Added 14-Lead TSSOP and 16-Lead LFCSP Packages.......Universal
Added ADA4084-4.....................................................................Universal
Change to Features Section and Applications Section.................1
Added Figure 2 and Figure 3; Renumbered Sequentially ............1
Changes to Table 2 ............................................................................3
Changes to Table 3 ............................................................................4
Changes to Table 4 ............................................................................5
Changes to Table 5 and Table 6 .......................................................6
Changes to Typical Performance Characteristics Section ...........7
Updated Outline Dimensions........................................................27
Changes to Ordering Guide...........................................................28
2/2012—Rev. 0 to Rev. A
Changes to Data Sheet Title.............................................................1
Changes to Voltage Range in General Description ......................1
Changes to Supply Current/Amplifier Parameter, Table 2..........3
Changes to Common-Mode Rejection Ratio Parameter, Table 3..4
Changes to Common-Mode Rejection Ratio Parameter, Table 4..5
Changes to Figure 2 ..........................................................................6
Changes to Figure 24 ......................................................................10
Changes to Figure 32 ......................................................................12
Changes to Figure 47 ......................................................................14
Changes to Figure 55 ......................................................................16
Changes to Figure 62 ......................................................................17
Changes to Figure 73 ......................................................................20
4/2013—Rev. B to Rev. C
Changes to Figure 48 Caption .......................................................15
Updated Outline Dimensions........................................................25
6/2012—Rev. A to Rev. B
Added LFCSP Package.......................................................Universal
Changes to Figure 1...........................................................................1
Changes to Output Voltage High Parameter, Table 4...................5
Added Figure 5 and Figure 7, Renumbered Sequentially ............7
Added Figure 30 and Figure 32 .....................................................12
10/2011—Revision 0: Initial Version
Rev. I | Page 3 of 36
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VSY = 3 V, V CM = 1.5 V, T A = 25°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
20
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
SOIC package
100
200
130
250
200
300
1.75
150
200
250
400
25
µV
µV
µV
µV
µV
µV
µV/°C
µV
µV
nA
nA
nA
nA
V
−40°C ≤ TA ≤ +125°C
SOT-23, MSOP, TSSOP packages
−40°C ≤ TA ≤ +125°C
ADA4084-2 LFCSP package
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
TA = 25°C
50
80
Offset Voltage Drift
Offset Voltage Matching
Δt/ΔT
0.5
ADA4084-4 LFCSP package
Input Bias Current
IB
140
5
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
50
3
Input Voltage Range
0
Common-Mode Rejection Ratio
CMRR
AVO
VCM = 0 V to 3 V
64
60
100
97
88
dB
dB
dB
dB
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ, 0.5 V ≤ VOUT ≤ 2.5 V
−40°C ≤ TA ≤ +125°C
Large Signal Voltage Gain
104
Input Impedance
Differential
Common Mode
100||1.1
80||2.9
kΩ||pF
MΩ||pF
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ to VCM
2.90
2.80
2.85
2.70
2.95
2.9
10
V
V
V
V
mV
mV
mV
mV
mA
Ω
Output Voltage Low
VOL
20
40
30
50
20
−40°C ≤ TA ≤ +125°C
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
ISC
ZOUT
−17/+10
0.1
f = 1 kHz, AV = 1
Power Supply Rejection Ratio
PSRR
ISY
VSY
=
1.25 V to 1.75 V
100
90
110
dB
dB
mA
mA
−40°C ≤ TA ≤ +125°C
IOUT = 0 mA
−40°C ≤ TA ≤ +125°C
Supply Current per Amplifier
0.565
0.650
0.950
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Unity-Gain Crossover
Phase Margin
−3 dB Closed-Loop Bandwidth
Settling Time
Total Harmonic Distortion Plus Noise
NOISE PERFORMANCE
Voltage Noise
SR
RL = 2 kΩ
VIN = 5 mV p-p, RL = 10 kΩ, AV = 100
VIN = 5 mV p-p, RL = 10 kΩ, AV = 1
2.0
2.6
V/µs
MHz
MHz
Degrees
MHz
µs
GBP
UGC
ΦM
−3 dB
tS
15.4
8.08
86
12.3
4
AV = 1, VIN = 5 mV p-p
AV = 10, VIN = 2 V p-p, 0.1%
VIN = 300 mV rms, RL = 2 kΩ, f = 1 kHz
THD + N
0.009
%
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
0.14
3.9
0.55
µV p-p
nV/√Hz
pA/√Hz
Voltage Noise Density
Current Noise Density
Rev. I | Page 4 of 36
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
VSY
= 5.0 V, VCM = 0 V, T A = 25°C, unless otherwise noted.
Table 3.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
30
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
SOIC package
100
200
130
250
200
300
1.75
150
200
250
400
25
µV
µV
µV
µV
µV
µV
µV/°C
µV
µV
nA
nA
nA
nA
V
−40°C ≤ TA ≤ +125°C
SOT-23, MSOP, TSSOP packages
−40°C ≤ TA ≤ +125°C
ADA4084-2 LFCSP package
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
TA = 25°C
60
90
Offset Voltage Drift
Offset Voltage Matching
ΔVOS/ΔT
0.5
ADA4084-4 LFCSP package
Input Bias Current
IB
140
5
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
50
+5
Input Voltage Range
−5
Common-Mode Rejection Ratio
CMRR
AVO
VCM
VCM
VCM
=
=
=
4 V, −40°C ≤ TA ≤ +125°C
5 V
5 V, −40°C ≤ TA ≤ +125°C
106
76
70
108
103
124
112
dB
dB
dB
dB
dB
Large Signal Voltage Gain
RL = 2 kΩ, −4 V ≤ VOUT ≤ 4 V
−40°C ≤ TA ≤ +125°C
Input Impedance
Differential
Common Mode
100||1.1
200||2.5
kΩ||pF
MΩ||pF
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ to VCM
4.9
4.8
4.8
4.7
4.95
V
V
V
V
V
V
V
V
4.85
Output Voltage Low
VOL
−4.95
−4.95
−4.9
−4.8
−4.8
−4.7
−40°C ≤ TA ≤ +125°C
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
ISC
ZOUT
−24/+17
0.1
mA
Ω
f = 1 kHz, AV = 1
Power Supply Rejection Ratio
PSRR
ISY
VSY
=
2 V to 18 V
110
105
120
dB
dB
mA
mA
−40°C ≤ TA ≤ +125°C
IOUT = 0 mA
−40°C ≤ TA ≤ +125°C
Supply Current per Amplifier
0.595
0.700
1.00
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Unity-Gain Crossover
Phase Margin
−3 dB Closed-Loop Bandwidth
Settling Time
Total Harmonic Distortion Plus Noise
NOISE PERFORMANCE
Voltage Noise
SR
RL = 2 kΩ to VCM
VIN = 5 mV p-p, RL = 10 kΩ, AV = 100
VIN = 5 mV p-p, RL = 10 kΩ, AV = 1
2.4
3.7
15.9
9.6
85
13.9
4
V/µs
MHz
MHz
Degrees
MHz
µs
GBP
UGC
ΦM
−3 dB
tS
AV = 1, VIN = 5 mV p-p
AV = 10, VIN = 8 V p-p, 0.1%
VIN = 2 V rms, RL = 2 kΩ, f = 1 kHz
THD + N
0.003
%
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
0.14
3.9
0.55
µV p-p
nV/√Hz
pA/√Hz
Voltage Noise Density
Current Noise Density
Rev. I | Page 5 of 36
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
VSY
= 15.0 V, VCM = 0 V, T A = 25°C, unless otherwise noted.
Table 4.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
40
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
SOIC package
100
200
130
250
200
300
1.75
150
200
250
400
25
µV
µV
µV
µV
µV
µV
µV/°C
µV
µV
nA
nA
nA
nA
V
−40°C ≤ TA ≤ +125°C
SOT-23, MSOP, TSSOP packages
−40°C ≤ TA ≤ +125°C
ADA4084-2 LFCSP package
−40°C ≤ TA ≤ +125°C
70
100
0.5
Offset Voltage Drift
Offset Voltage Matching
ΔVOS/ΔT
TA = 25°C
ADA4084-4 LFCSP package
Input Bias Current
IB
140
5
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
50
+15
Input Voltage Range
Common-Mode Rejection Ratio
−15
106
85
80
110
105
CMRR
AVO
VCM
VCM
VCM
=
=
=
14 V, −40°C ≤ TA ≤ +125°C
15 V
15 V, −40°C ≤ TA ≤ +125°C
124
117
dB
dB
dB
dB
dB
Large Signal Voltage Gain
RL = 2 kΩ, −13.5 V ≤ VOUT ≤ +13.5 V
−40°C ≤ TA ≤ +125°C
Input Impedance
Differential
Common Mode
100||1.1
200||2.5
kΩ||pF
MΩ||pF
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ to VCM
14.85 14.9
14.8
V
V
V
V
V
V
V
V
14.5
14.0
14.6
Output Voltage Low
VOL
−14.95
−14.9
−14.9
−14.8
−14.8
−14.7
−40°C ≤ TA ≤ +125°C
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
ISC
ZOUT
30
0.1
mA
Ω
f = 1 kHz, AV = +1
Power Supply Rejection Ratio
PSRR
ISY
VSY
=
2 V to 18 V
110
105
120
dB
dB
mA
mA
−40°C ≤ TA ≤ +125°C
IOUT = 0 mA
−40°C ≤ TA ≤ +125°C
Supply Current per Amplifier
0.625
0.750
1.050
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Unity-Gain Crossover
Phase Margin
−3 dB Closed-Loop Bandwidth
Settling Time
Total Harmonic Distortion Plus Noise
NOISE PERFORMANCE
Voltage Noise
SR
RL = 2 kΩ
VIN = 5 mV p-p, RL = 10 kΩ, AV = 100
VIN = 5 mV p-p, RL = 10 kΩ, AV = 1
2.4
4.6
15.9
9.9
86
13.9
4
V/µs
MHz
MHz
Degrees
MHz
µs
GBP
UGC
ΦM
−3 dB
tS
AV = 1, VIN = 5 mV p-p
AV = 10, VIN = 10 V p-p, 0.1%
VIN = 5 V rms, RL = 2 kΩ, f = 1 kHz
THD + N
0.003
%
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
0.1
3.9
0.55
µV p-p
nV/√Hz
pA/√Hz
Voltage Noise Density
Current Noise Density
Rev. I | Page 6 of 36
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 5.
θJA is specified for the device soldered on a 4-layer JEDEC
standard printed circuit board (PCB) with zero airflow.
Parameter
Rating
Supply Voltage
18 V
Input Voltage
V− ≤ VIN ≤ V+
0.6 V
Indefinite
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
Table 6. Thermal Resistance
Package Type
Differential Input Voltage1
Output Short-Circuit Duration to GND
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering 60 sec)
ESD
θJA
θJC
155.6
43
45
40
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
5-Lead SOT-23 (RJ-5)
8-Lead SOIC_N (R-8)
8-Lead MSOP (RM-8)
8-Lead LFCSP (CP-8-11)1, 3
14-Lead TSSOP (RU-14)
16-Lead LFCSP (CP-16-17)2, 3
219.4
121
142
84
112
55
43
30
Human Body Model2
Machine Model3
Field-Induced Charged-Device Model
(FICDM)4
4.5 kV
200 V
1.25 kV
1 Values are based on 4-layer (2S2P) JEDEC standard PCB, with four thermal
vias. Exposed pad soldered to PCB.
2 Values are based on 4-layer (2S2P) JEDEC standard PCB, with nine thermal
vias. Exposed pad soldered to PCB.
3 θJC measured on top of package.
1 For input differential voltages greater than 0.6 V, limit the input current to
less than 5 mA to prevent degradation or destruction of the input devices.
2 Applicable standard: MIL-STD-883, Method 3015.7.
3 Applicable standard: JESD22-A115-A (ESD machine model standard of
JEDEC).
ESD CAUTION
4 Applicable standard: JESD22-C101-C (ESD FICDM standard of JEDEC).
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
V
CC
R4
R3
R6
Q24
Q23
D1
D2
Q1
Q2
MIRROR
D100
D101
FOLDED
CASCADE
V
Q4
Q3
OUT
C2
Q13
R7
V
BIAS
D5
D4
Q18
R5
C1
Q19
R1
R2
Q21
V
D20
EE
Figure 2. Simplified Schematic
Rev. I | Page 7 of 36
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NIC
–IN
+IN
V–
1
2
3
4
8
7
6
5
NIC
ADA4084-1
TOP VIEW
(Not to Scale)
V+
OUT
NIC
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
Figure 3. ADA4084-1, 8-Lead SOIC (R)
Table 7. 8-Lead SOIC, ADA4084-1 Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
3
4
5
6
7
8
NIC
−IN
+IN
V−
NIC
OUT
V+
Not Internally Connected
Negative Input
Positive Input
Negative Supply
Not Internally Connected
Output
Positive Supply
Not Internally Connected
NIC
ADA4084-1
OUT
V–
1
2
3
5
4
V+
+IN
–IN
Figure 4. ADA4084-1, 5-Lead SOT-23 (RJ)
Table 8. 5-Lead SOT-23, ADA4084-1 Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
3
4
5
OUT
V−
+IN
−IN
V+
Output
Negative Supply
Positive Input
Negative Input
Positive Supply
OUT A
–IN A
+IN A
V–
V+
1
2
3
4
8
7
6
5
OUT B
–IN B
+IN B
ADA4084-2
TOP VIEW
(Not to Scale)
NOTES
1. FOR THE LFCSP PACKAGE,
THE EXPOSED PAD MUST BE
CONNECTED TO V–.
Figure 5. ADA4084-2, 8-Lead LFCSP (CP)
Table 9. 8-Lead LFCSP, ADA4084-2 Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
3
4
5
6
7
8
OUT A
−IN A
+IN A
V−
+IN B
−IN B
OUT B
V+
Output, Channel A
Negative Input, Channel A
Positive Input, Channel A
Negative Supply
Positive Input, Channel B
Negative Input, Channel B
Output, Channel B
Positive Supply
EPAD
Exposed Pad. For the LFCSP package, the exposed pad must be connected to V−.
Rev. I | Page 8 of 36
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
ADA4084-2
1
2
3
4
OUT A
8
7
6
5
V+
OUT A
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
V+
–IN A
+IN A
V–
OUT B
–IN B
+IN B
OUT B
–IN B
+IN B
TOP VIEW
(Not to Scale)
ADA4084-2
TOP VIEW
(Not to Scale)
Figure 7. ADA4084-2, 8-Lead SOIC (R)
Figure 6. ADA4084-2, 8-Lead MSOP (RM)
Table 10. 8-Lead MSOP, 8-Lead SOIC, ADA4084-2 Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
3
4
5
6
7
8
OUT A
−IN A
+IN A
V−
+IN B
−IN B
OUT B
V+
Output, Channel A
Negative Input, Channel A
Positive Input, Channel A
Negative Supply
Positive Input, Channel B
Negative Input, Channel B
Output, Channel B
Positive Supply B
1
2
3
4
5
6
7
OUT A
14
13
12
11
10
9
OUT D
–IN D
+IN D
V–
–IN A
+IN A
V+
ADA4084-4
TOP VIEW
(Not to Scale)
+IN B
–IN B
OUT B
+IN C
–IN C
OUT C
8
Figure 8. ADA4084-4, 14-Lead TSSOP (RU)
Table 11. 14-Lead TSSOP, ADA4804-4 Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
3
4
OUT A
−IN A
+IN A
V+
Output, Channel A
Negative Input, Channel A
Positive Input, Channel A
Positive Supply
5
6
7
8
+IN B
−IN B
OUT B
OUT C
−IN C
+IN C
V−
+IN D
−IN D
OUT D
Positive Input, Channel B
Negative Input, Channel B
Output, Channel B
Output, Channel C
9
Negative Input, Channel C
Positive Input, Channel C
Negative Supply
Positive Input, Channel D
Negative Input, Channel D
Output, Channel D
10
11
12
13
14
Rev. I | Page 9 of 36
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
–IN A
1
2
3
4
12 –IN D
11 +IN D
10 V–
+IN A
V+
ADA4084-4
TOP
VIEW
9
+IN C
+IN B
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
2. FOR THE LFCSP PACKAGE, THE EXPOSED PAD
MUST BE CONNECTED TO V–.
Figure 9. ADA4084-4, 16-Lead LFCSP (CP)
Table 12. 16-Lead LFCSP, ADA4084-4 Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
3
−IN A
+IN A
V+
Negative Input Channel A
Positive Input, Channel A
Positive Supply
4
5
6
7
8
9
10
11
12
13
14
15
16
+IN B
−IN B
OUT B
OUT C
−IN C
+IN C
V−
+IN D
−IN D
NIC
Positive Input, Channel B
Negative Input, Channel B
Output, Channel B
Output, Channel C
Negative Input, Channel C
Positive Input, Channel C
Negative Supply
Positive Input, Channel D
Negative Input, Channel D
Not Internally Connected
Output, Channel D
OUT D
OUT A
NIC
Output, Channel A
Not Internally Connected
Rev. I | Page 10 of 36
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
1.5 V CHARACTERISTICS
200
150
100
50
120
V
T
= ±1.5V
= 25°C
V
T
R
= ±1.5V
= 25°C
= ∞
SY
SY
A
A
R
= ∞
L
L
100
80
60
40
20
0
0
–200
–150
–100
–50
(µV)
0
50
100
–100
–75
–50
–25
0
25
50
75
100
V
(µV)
V
OS
OS
Figure 10. Input Offset Voltage (VOS) Distribution, SOIC
Figure 13. Input Offset Voltage (VOS) Distribution, LFCSP
100
60
V
A
R
= ±1.5V
SY
T
= 25°C
90
80
70
60
50
40
30
20
10
0
= ∞
L
50
40
30
20
10
0
V
= ±1.5V
SY
R
= ∞
L
–40°C ≤ T ≤ +125°C
A
–100
–75
–50
–25
0
25
50
75
100
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
V
(µV)
TCV (µV/°C)
OS
OS
Figure 11. Input Offset Voltage (VOS) Distribution, SOT-23
Figure 14. TCVOS Distribution, SOIC, MSOP, and TSSOP
20
50
V
T
R
= ±1.5V
= 25°C
= ∞
V
= ±1.5V
SY
SY
= ∞
R
L
45
40
35
30
25
20
15
10
5
A
18
16
14
12
10
8
–40°C ≤ T ≤ +125°C
A
L
6
4
2
0
0
–100
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
–75
–50
–25
0
25
50
75
100
TCV (µV/°C)
V
(µV)
OS
OS
Figure 12. Input Offset Voltage (VOS) Distribution, MSOP and TSSOP
Figure 15. TCVOS Distribution, SOT-23
Rev. I | Page 11 of 36
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
50
–100
–150
–200
–250
30
V
R
= ±1.5V
= ∞
V
V
R
= ±1.5V
= 0V
= ∞
SY
SY
L
CM
–40°C ≤ T ≤ +125°C
L
A
25
20
15
10
5
I
+
B
I
–
B
0
–50
–25
0
25
50
75
100
125
150
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
TEMPERATURE (°C)
TCV (µV/°C)
OS
Figure 19. Input Bias Current vs. Temperature
Figure 16. TCVOS Distribution, LFCSP
600
400
500
400
V
= ±1.5V
SY
300
200
200
0
100
T
= +125°C
0
A
T
= +85°C
A
–100
–200
–300
–400
–200
–400
–600
T
= +25°C
A
T
= –40°C
A
V
= ±1.5V
= 25°C
= ∞
SY
T
A
R
L
–500
–1.50
–1.00
–0.50
0
0.50
1.00
1.50
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
COMMON-MODE VOLTAGE (V)
V
(V)
CM
Figure 17. Input Offset Voltage vs. Common-Mode Voltage
Figure 20. Input Bias Current vs. VCM for Various Temperatures
100
75
V
= ±1.5V
SY
V
= ±1.5V
= 25°C
SY
T
A
1000
100
10
50
25
0
–25
–50
–75
–100
(V+) – V
OH
1
–50
–25
0
25
50
75
100
125
150
0.001
0.01
0.1
1
10
TEMPERATURE (°C)
SOURCE CURRENT (mA)
Figure 18. Input Offset Voltage vs. Temperature
Figure 21. Dropout Voltage (VDO) vs. Source Current
Rev. I | Page 12 of 36
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
1000
100
V = ±1.5V
SY
V
= ±1.5V
= 25°C
SY
T
= 25°C
A
T
A
1000
100
10
A
= +10
V
10
1
A
= +100
V
A
= +1
V
V
– (V–)
OL
0.10
0.01
1
10
100
1k
10k
100k
1M
10M
100M
0.001
0.01
0.1
1
10
FREQUENCY (Hz)
SINK CURRENT (mA)
Figure 25. Output Impedance (ZOUT) vs. Frequency
Figure 22. Dropout Voltage (VDO) vs. Sink Current
140
120
100
80
120
100
80
270
225
V
T
= ±1.5V
= 25°C
V
T
R
= ±1.5V
= 25°C
= 10kΩ
SY
SY
A
A
L
180
135
90
60
60
40
PSRR–
40
45
20
20
0
0
PSRR+
0
–45
–20
–40
–20
–90
10
100
1k
10k
100k
1M
10M
100M
0.1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (kHz)
Figure 26. PSRR vs. Frequency
Figure 23. Open-Loop Gain and Phase vs. Frequency
140
120
100
80
60
50
V
T
= ±1.5V
= 25°C
V
T
= ±1.5V
= 25°C
SY
SY
A
A
A
A
A
= +100
= +10
= +1
V
V
V
40
30
20
60
10
40
0
20
–10
0
10
–20
10
100
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 27. CMRR vs. Frequency
Figure 24. Closed-Loop Gain vs. Frequency
Rev. I | Page 13 of 36
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
1.5
10
1.0
0.5
0
4
–0.5
V
= ±1.5V
= 25°C
= 2kΩ
= 100pF
SY
–1.0
–1.5
T
A
V
T
= ±1.5V
= 25°C
R
C
SY
L
L
A
1
0
2
4
6
8
10
12
14
16
18
1
10
100
1k
10k
100k
TIME (µs)
FREQUENCY (Hz)
Figure 28. Large Signal Transient Response
Figure 31. Voltage Noise Density vs. Frequency
80
60
60
V
V
R
= ±1.5V
= 100mV p-p
= 2kΩ
SY
IN
L
50
40
30
20
10
0
OS+
T
= 25°C
A
40
20
0
–20
–40
–60
–80
OS–
V
= ±1.5V
= 25°C
= 2kΩ
= 100pF
SY
T
A
R
C
L
L
0
2
4
6
8
10
12
14
16
18
1
10
100
1000
TIME (µs)
LOAD CAPACITANCE (pF)
Figure 29. Small Signal Transient Response
Figure 32. Overshoot vs. Load Capacitance
2
0.08
0.06
80
60
INPUT
0
–2
40
0.04
0.02
0
20
–4
0
OUTPUT
–20
–40
–60
–80
–6
–8
–0.02
–0.04
V
= ±1.5V
SY
V
= ±1.5V
SY
T
= 25°C
A
T
= 25°C
A
–10
–1
3
4
0
1
2
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9 10
TIME (µs)
TIME (Seconds)
Figure 30. Settling Time
Figure 33. Voltage Noise, 0.1 Hz to 10 Hz
Rev. I | Page 14 of 36
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
0
0.1
0.01
10kΩ
V
T
V
= ±1.5V
V
T
= ±1.5V
SY
= 25°C
SY
= 25°C
A
V
V
V
V
CC
CC
–
A
1kΩ
–20
–40
V
= 300mV rms
–
+
IN
= 1V p-p
IN
80kHz FILTER
+
EE
EE
10V p-p
2kΩ 2kΩ
CH B,
CH C,
CH D
CH A
–60
–80
R
= 2kΩ
L
–100
–120
–140
–160
0.001
0.0001
R
= 10kΩ
L
100
1k
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 34. Channel Separation vs. Frequency
Figure 37. THD + N vs. Frequency, 80 kHz Filter
2.0
1.5
1
0.1
V
= ±1.5V
SY
V
T
= ±1.5V
SY
T = 25°C
A
= 25°C
A
R
= 10kΩ
AT 1kHz
L
V
IN
1.0
0.5
OUTPUT
0
0.01
–0.5
–1.0
–1.5
–2.0
INPUT
0.001
0
100 200 300 400 500 600 700 800 900 1000
TIME (µs)
0.0001
0.001
0.01
AMPLITUDE (V
0.1
)
1
RMS
Figure 35. THD + N vs. Amplitude
Figure 38. No Phase Reversal
0.5
0
4
0.01
V
A
V
= ±1.5V
SY
T
= 25°C
= 300mV rms
IN
R = 2kΩ
L
500kHz FILTER
3
INPUT
–0.5
–1.0
–1.5
–2.0
2
1
R
= 10kΩ
L
OUTPUT
0
V
= ±1.5V
= 25°C
SY
T
A
–1
0.001
6
8
–2
0
2
4
10
12
14
16
18
0.01
0.1
1
10
100
TIME (µs)
FREQUENCY (kHz)
Figure 36. THD + N vs. Frequency, 500 kHz Filter
Figure 39. Positive 50% Overload Recovery
Rev. I | Page 15 of 36
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
0.5
3
0
2
INPUT
–0.5
1
OUTPUT
–1.0
0
–1.5
–1
–2
V
= ±1.5V
= 25°C
SY
T
A
–2.0
–2
6
8
0
2
4
10
12
14
16
18
TIME (µs)
Figure 40. Negative 50% Overload Recovery
Rev. I | Page 16 of 36
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
5 V CHARACTERISTICS
250
200
150
100
50
120
V
T
= ±5V
= 25°C
V
T
R
= ±5V
= 25°C
= ∞
SY
SY
A
A
R
= ∞
L
L
100
80
60
40
20
0
0
–200
–150
–100
–50
(µV)
0
50
100
–100
–75
–50
–25
0
25
50
75
100
V
(µV)
V
OS
OS
Figure 41. Input Offset Voltage (VOS) Distribution, SOIC
Figure 44. Input Offset Voltage (VOS) Distribution, LFCSP
120
50
V
T
= ±5V
V
R
= ±5V
= ∞
L
SY
SY
= 25°C
A
45
40
35
30
25
20
15
10
5
R
= ∞
L
–40°C ≤ T ≤ +125°C
A
100
80
60
40
20
0
0
–100
–75
–50
–25
0
25
50
75
100
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
TCV (µV/°C)
V
(µV)
OS
OS
Figure 42. Input Offset Voltage (VOS) Distribution, SOT-23
Figure 45. TCVOS Distribution, SOIC, MSOP, and TSSOP
60
20
V
T
R
= ±5V
= 25°C
= ∞
SY
V
= ±5V
SY
L
R
= ∞
A
18
16
14
12
10
8
–40°C ≤ T ≤ +125°C
L
A
50
40
30
20
10
0
6
4
2
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
–100
–75
–50
–25
0
25
50
75
100
V
(µV)
TCV (µV/°C)
OS
OS
Figure 43. Input Offset Voltage (VOS) Distribution, MSOP and TSSOP
Figure 46. TCVOS Distribution for SOT-23
Rev. I | Page 17 of 36
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
35
–50
–100
–150
–200
V
V
R
= ±5V
= 0V
= ∞
V
R
= ±5V
= ∞
SY
SY
CM
L
–40°C ≤ T ≤ +125°C
L
30
25
20
15
10
5
A
I
+
B
I
–
B
–250
0
–40 –25 –10
5
20
35
50
65
80
95 110 125
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
TEMPERATURE (°C)
TCV (µV/°C)
OS
Figure 47. TCVOS Distribution, LFCSP
Figure 50. Input Bias Current vs. Temperature
600
500
800
600
V
= ±5V
= 25°C
= ∞
V
= ±5V
SY
SY
T
A
R
L
400
300
400
200
200
100
T
= +125°C
A
T
= +85°C
A
0
0
–100
–200
–300
–400
–500
–600
–200
–400
–600
–800
T
= +25°C
A
T
= –40°C
A
–5
–4
–3
–2
–1
0
1
2
3
4
5
–5
–4
–3
–2
–1
0
1
2
3
4
5
COMMON-MODE VOLTAGE (V)
V
(V)
CM
Figure 48. Input Offset Voltage vs. Common-Mode Voltage
Figure 51. Input Bias Current vs. VCM for Various Temperatures
100
75
V
= ±5V
SY
V
T
= ±5V
= 25°C
SY
1000
100
10
A
50
25
0
–25
–50
–75
–100
(V+) – V
OH
1
–50
–25
0
25
50
75
100
125
150
0.001
0.01
0.1
1
10
TEMPERATURE (°C)
SOURCE CURRENT (mA)
Figure 49. Input Offset Voltage vs. Temperature
Figure 52. Dropout Voltage (VDO) vs. Source Current
Rev. I | Page 18 of 36
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
1000
100
V
= ±5V
= 25°C
SY
V
T
= ±5V
= 25°C
SY
T
A
1000
100
10
A
A
= +10
V
10
1
A = +1
V
A
= +100
V
V
– (V–)
OL
0.10
0.01
1
10
100
1k
10k
100k
1M
10M
100M
0.001
0.01
0.1
1
10
FREQUENCY (Hz)
SINK CURRENT (mA)
Figure 56. Output Impedance (ZOUT) vs. Frequency
Figure 53. Dropout Voltage (VDO) vs. Sink Current
140
120
100
80
120
100
80
270
225
V
T
= ±5V
= 25°C
V
T
R
= ±5V
= 25°C
= 10kΩ
SY
SY
A
A
L
180
135
90
60
60
40
PSRR–
40
45
20
20
0
0
PSRR+
0
–45
–20
–40
–20
–90
10
100
1k
10k
100k
1M
10M
100M
0.1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (kHz)
Figure 57. PSRR vs. Frequency
Figure 54. Open-Loop Gain and Phase vs. Frequency
140
120
100
80
60
50
V
T
= ±5V
= 25°C
V
= ±5V
= 25°C
SY
SY
T
A
A
A
A
A
= +100
= +10
= +1
V
V
V
40
30
20
60
10
40
0
20
–10
0
10
–20
10
100
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 58. CMRR vs. Frequency
Figure 55. Closed-Loop Gain vs. Frequency
Rev. I | Page 19 of 36
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
5
4
10
3
2
4
1
0
–1
–2
–3
–4
–5
V
= ±5V
= 25°C
= 2kΩ
= 100pF
SY
T
A
R
C
V
T
= ±5V
= 25°C
L
L
SY
A
1
0
2
4
6
8
10
12
14
16
18
1
10
100
1k
10k
100k
TIME (µs)
FREQUENCY (Hz)
Figure 59. Large Signal Transient Response
Figure 62. Voltage Noise Density vs. Frequency
80
60
60
V
V
R
= ±5V
= 100mV p-p
= 2kΩ
SY
IN
L
50
40
30
20
10
0
OS+
T
= 25°C
A
40
20
0
–20
–40
–60
–80
OS–
V
= ±5V
= 25°C
= 2kΩ
= 100pF
SY
T
A
R
C
L
L
0
1
2
3
4
5
6
7
8
9
10
1
10
100
1000
TIME (µs)
LOAD CAPACITANCE (pF)
Figure 60. Small Signal Transient Response
Figure 63. Overshoot vs. Load Capacitance
10
5
0.16
0.12
80
60
V
= ±5V
SY
= 25°C
V
= ±5V
= 25°C
SY
T
A
T
A
INPUT
40
0.08
0.04
0
0
20
–5
OUTPUT
0
–10
–15
–20
–20
–40
–60
–80
–0.04
–0.08
–0.12
–25
–2
4
0
2
6
8
10
12
14
16
18
0
1
2
3
4
5
6
7
8
9
10
TIME (µs)
TIME (Seconds)
Figure 61. Settling Time
Figure 64. Voltage Noise, 0.1 Hz to 10 Hz
Rev. I | Page 20 of 36
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
0
0.1
0.01
10kΩ
V
T
V
= ±5V
= 25°C
= 5V p-p
V
T
= ±5V
SY
SY
= 25°C
A
V
V
V
V
CC
A
CC
–
1kΩ
–20
–40
V
= 300mV rms
–
+
IN
IN
80kHz FILTER
+
R
= 2kΩ
EE
EE
L
10V p-p
2kΩ 2kΩ
CH B,
CH C,
CH D
CH A
–60
–80
0.001
–100
–120
–140
–160
0.0001
R
= 10kΩ
L
0.00001
100
1k
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 65. Channel Separation vs. Frequency
Figure 68. THD + N vs. Frequency, 80 kHz Filter
6
4
1
0.1
V
= ±5V
= 25°C
V
= ±5V
SY
SY
T
= 25°C
T
A
R
V
A
= 10kΩ
AT 1kHz
L
IN
2
0
0.01
OUTPUT
–2
–4
–6
INPUT
0.001
0.0001
0
100 200 300 400 500 600 700 800 900 1000
TIME (µs)
0.001
0.01
0.1
AMPLITUDE (V
1
)
RMS
Figure 69. No Phase Reversal
Figure 66. THD + N vs. Amplitude
1
0
10
1
0.1
V
= ±5V
SY
= 25°C
T
A
V
= 2V rms
IN
500kHz FILTER
8
INPUT
–1
–2
–3
–4
–5
6
4
2
R
= 2kΩ
L
0.01
R
= 10kΩ
L
OUTPUT
0.001
0
V
= ±5V
= 25°C
SY
T
A
–2
6
8
–2
0
2
4
10
12
14
16
18
0.0001
0.01
0.1
1
10
100
TIME (µs)
FREQUENCY (kHz)
Figure 70. Positive 50% Overload Recovery
Figure 67. THD + N vs. Frequency, 500 kHz Filter
Rev. I | Page 21 of 36
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
1
6
0
4
INPUT
–1
2
OUTPUT
–2
0
–3
–4
–2
–4
–6
V
= ±5V
= 25°C
SY
T
A
–5
–2
6
8
0
2
4
10
12
14
16
18
TIME (µs)
Figure 71. Negative 50% Overload Recovery
Rev. I | Page 22 of 36
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
15 V CHARACTERISTICS
100
200
150
100
50
V
= ±15V
V
= ±15V
SY
SY
T
R
= 25°C
= ∞
T = 25°C
90
80
70
60
50
40
30
20
10
0
A
A
R
= ∞
L
L
0
–200
–150
–100
–50
(µV)
0
50
100
–100
–75
–50
–25
0
25
50
75
100
V
(µV)
V
OS
OS
Figure 72. Input Offset Voltage (VOS) Distribution, SOIC
Figure 75. Input Offset Voltage (VOS) Distribution, LFCSP
100
60
V
R
= ±15V
= ∞
V
T
= ±1.5V
SY
SY
= 25°C
A
L
90
80
70
60
50
40
30
20
10
0
R
= ∞
L
–40°C ≤ T ≤ +125°C
A
50
40
30
20
10
0
–100
–75
–50
–25
0
25
50
75
100
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
TCV (µV/°C)
V
(µV)
OS
OS
Figure 73. Input Offset Voltage (VOS) Distribution, SOT-23
Figure 76. TCVOS Distribution, SOIC, MSOP, and TSSOP
25
60
50
40
30
20
10
0
V
= ±15V
= 25°C
= ∞
V
= ±15V
SY
SY
R = ∞
L
T
A
–40°C ≤ T ≤ +125°C
R
A
L
20
15
10
5
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
–100
–75
–50
–25
0
25
50
75
100
V
(µV)
TCV (µV)
OS
OS
Figure 74. Input Offset Voltage (VOS) Distribution, MSOP and TSSOP
Figure 77. TCVOS Distribution, SOT-23
Rev. I | Page 23 of 36
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
–50
–100
–150
–200
30
V
R
= ±15V
= ∞
SY
L
–40°C ≤ T ≤ +125°C
A
25
20
15
10
5
I
+
B
I
–
B
V
V
= ±15V
= 0V
SY
CM
R
= ∞
L
–250
0
–40 –25 –10
5
20
35
50
65
80
95 110 125
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
TEMPERATURE (°C)
TCV (µV/°C)
OS
Figure 81. Input Bias Current vs. Temperature
Figure 78. TCVOS Distribution, LFCSP
1200
800
400
0
600
500
V
= ±15V
V
= ±15V
= 25°C
= ∞
SY
SY
T
A
R
L
400
300
200
T
= +125°C
A
100
T
= +85°C
A
0
–100
–200
–300
–400
–500
–600
T
= +25°C
–400
A
T
= –40°C
A
–800
–1200
–15
–10
–5
0
5
10
15
–15
–10
–5
0
5
10
15
COMMON-MODE VOLTAGE (V)
V
(V)
CM
Figure 79. Input Offset Voltage vs. Common-Mode Voltage
Figure 82. Input Bias Current vs. VCM for Various Temperatures
100
75
V
= ±15V
SY
10000
50
1000
100
10
25
0
–25
–50
–75
–100
(V+) – V
OH
V
= ±15V
SY
T
= 25°C
A
1
–50
–25
0
25
50
75
100
125
150
0.001
0.01
0.1
1
10
SOURCE CURRENT (mA)
TEMPERATURE (°C)
Figure 80. Input Offset Voltage vs. Temperature
Figure 83. Dropout Voltage (VDO) vs. Source Current
Rev. I | Page 24 of 36
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
1000
100
V
= ±15V
= 25°C
SY
10000
1000
100
10
T
A
A
= +10
V
10
1
A
= +100
V
A
= +1
V
V
– (V–)
OL
0.1
V
= ±15V
SY
T
= 25°C
A
0.01
1
10
100
1k
10k
100k
1M
10M
100M
0.001
0.01
0.1
1
10
FREQUENCY (Hz)
SINK CURRENT (mA)
Figure 84. Dropout Voltage (VDO) vs. Sink Current
Figure 87. Output Impedance (ZOUT) vs. Frequency
120
100
80
270
225
140
120
100
80
V
= ±15V
= 25°C
= 10kΩ
V
= ±15V
SY
SY
T
T = 25°C
A
A
R
L
180
135
90
60
40
60
PSRR–
45
20
40
0
0
20
PSRR+
–45
–20
–40
0
–90
–20
100
1k
10k
100k
1M
10M
100M
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 85. Open-Loop Gain and Phase vs. Frequency
Figure 88. PSRR vs. Frequency
60
50
140
120
100
80
V
= ±15V
= 25°C
SY
V
= ±15V
SY
T
A
T = 25°C
A
A
A
A
= +100
= +10
= +1
V
V
V
40
30
20
60
10
40
0
20
–10
–20
10
0
10
100
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 86. Closed-Loop Gain vs. Frequency
Figure 89. CMRR vs. Frequency
Rev. I | Page 25 of 36
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
15
10
5
10
4
0
–5
V
= ±15V
= 25°C
= 2kΩ
= 100pF
SY
–10
–15
T
A
V
T
= ±15V
= 25°C
R
C
SY
L
L
A
1
0
4
8
12
16
20
24
28
32
36
1
10
100
1k
10k
100k
TIME (µs)
FREQUENCY (Hz)
Figure 90. Large Signal Transient Response
Figure 93. Voltage Noise Density vs. Frequency
80
60
70
V
V
R
= ±15V
= 100mV p-p
= 2kΩ
SY
IN
60
50
40
30
20
10
0
L
OS+
T
= 25°C
A
40
20
0
–20
–40
–60
–80
OS–
V
T
R
= ±15V
= 25°C
= 2kΩ
= 100pF
SY
A
L
L
C
3
4
0
1
2
5
6
7
8
9
10
1
10
100
1000
TIME (µs)
LOAD CAPACITANCE (pF)
Figure 91. Small Signal Transient Response
Figure 94. Overshoot vs. Load Capacitance
10
0.20
0.15
60
40
5
0
INPUT
0.10
0.05
0
20
–5
0
OUTPUT
–10
–15
–20
–25
–20
–40
–60
–0.05
–0.10
–0.15
V
= ±15V
V
T
= ±15V
= 25°C
SY
SY
T
= 25°C
A
A
4
–2
0
2
6
8
10
12
14
16
18
0
2
4
6
8
10
TIME (µs)
TIME (Seconds)
Figure 92. Settling Time
Figure 95. Voltage Noise 0.1 Hz to 10 Hz
Rev. I | Page 26 of 36
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
0
0.1
0.01
10kΩ
V
T
= ±15V
= 25°C
= 10V p-p
V
T
= ±15V
SY
SY
A
IN
= 25°C
V
V
V
V
A
CC
CC
–
–20
–40
1kΩ
V
= 300mV rms
V
–
+
IN
80kHz FILTER
+
R
= 2kΩ
EE
EE
L
10V p-p
2kΩ 2kΩ
CH B,
CH C,
CH D
CH A
–60
–80
0.001
–100
–120
–140
–160
–180
0.0001
0.00001
R
= 10kΩ
L
100
1k
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 96. Channel Separation vs. Frequency
Figure 99. THD + N vs. Frequency, 80 kHz Filter
20
15
1
0.1
V
= ±15V
= 25°C
SY
V
= ±15V
= 10kΩ
SY
L
IN
T
A
R
V
AT 1kHz
10
5
0
OUTPUT
0.01
–5
INPUT
–10
–15
–20
0.001
0
100 200 300 400 500 600 700 800 900 1000
TIME (µs)
0.0001
0.001
0.01
0.1
1
10
AMPLITUDE (V
)
RMS
Figure 97. THD + N vs. Amplitude
Figure 100. No Phase Reversal
1
0.1
V
A
V
= ±15V
V
SY
IN
T
= 25°C
1
= 5V rms
IN
500kHz FILTER
CH1 AMPL
202mV
V
OUT
R
= 2kΩ
L
0.01
R
= 10kΩ
L
0.001
2
V
= ±15V
–84mV
SY
0.0001
CH1 100mV
CH2 5V
M1µs
10.2%
A CH1
0.01
0.1
1
10
100
T
FREQUENCY (kHz)
Figure 101. Positive 50% Overload Recovery
Figure 98. THD + N vs. Frequency, 500 kHz Filter
Rev. I | Page 27 of 36
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
140
120
100
80
V
= ±15V
SY
V
= ±14V
CM
CH1 AMPL
200mV
V
V
= ±4V
CM
IN
1
2
V
= ±1.5V
CM
60
40
V
OUT
20
0
–50
CH1 100mV
CH2 5V
M2µs
10.4%
A CH1
44mV
–25
0
25
50
75
100
125
150
T
TEMPERATURE (°C)
Figure 104. CMRR vs. Temperature
Figure 102. Negative 50% Overload Recovery
150
140
130
120
110
100
90
1000
900
+125°C
+85°C
800
700
600
500
400
300
200
100
0
V
= ±2V TO ±18V, V
= 0V
SY
CM
+25°C
–40°C
V
= ±1.25V TO ±1.75V, V
= 0V
SY
CM
80
70
60
T
R
= 25°C
= ∞
A
50
–50
L
–25
0
25
50
75
100
125
150
0
4
8
12
16
20
(V)
24
28
32
36
TEMPERATURE (°C)
V
SY
Figure 103. Supply Current (ISY) per Amplifier vs. Supply Voltage (VSY) for
Various Temperatures
Figure 105. PSRR vs. Temperature
Rev. I | Page 28 of 36
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
APPLICATIONS INFORMATION
A key issue in the input stage is the behavior of the input bias
currents over the input common-mode voltage range. Input bias
currents in the ADA4084-1/ADA4084-2/ADA4084-4 are the
arithmetic sum of the base currents in Q1 and Q4 and in Q2 and
Q3. As a result of this design approach, the input bias currents in
the ADA4084-1/ADA4084-2/ADA4084-4 not only exhibit
different amplitudes, but they also exhibit different polarities. This
effect is best shown in Figure 19, Figure 20, Figure 50, Figure 51,
Figure 81, and Figure 82. It is, therefore, important that the
effective source impedances that are connected to the ADA4084-1/
ADA4084-2/ADA4084-4 inputs be balanced for optimum dc
and ac performance.
FUNCTIONAL DESCRIPTION
The ADA4084-1/ADA4084-2/ADA4084-4 devices are precision
single-supply, rail-to-rail operational amplifiers. Intended for
portable instrumentation, the ADA4084-1/ADA4084-2/
ADA4084-4 devices combine the attributes of precision, wide
bandwidth, and low noise, making them an ideal choice in
single-supply applications that require both ac and precision dc
performance. Other low supply voltage applications for which
the ADA4084-1/ADA4084-2/ADA4084-4 devices are well suited
include active filters, audio microphone preamplifiers, power
supply control, and telecommunications. To combine all of
these attributes with rail-to-rail input/output operation, novel
circuit design techniques are used.
To achieve rail-to-rail output, the ADA4084-1/ADA4084-2/
ADA4084-4 output stage design employs a unique topology for
both sourcing and sinking current. This circuit topology is shown
in Figure 107. The output stage is voltage driven from the second
gain stage. The signal path through the output stage is inverting;
that is, for positive input signals, Q13 provides the base current
drive to Q19 so that it conducts (sinks) current. For negative input
signals, the signal path via Q18 to the mirror to Q24 provides
the base current drive for Q23 to conduct (source) current. Both
transistors provide output current until they are forced into
saturation.
R4
R3
D1
D2
Q1
Q2
D100
D101
Q4
Q3
V
CC
D5
D4
R6
Q24
Q23
R1
R2
MIRROR
Figure 106. Equivalent Input Circuit
V
OUT
For example, Figure 106 illustrates a simplified equivalent
circuit for the input stage of the ADA4084-1/ADA4084-2/
ADA4084-4. It comprises a PNP differential pair, Q1 and Q2,
and an NPN differential pair, Q3 and Q4, operating concurrently.
Diode D100 and Diode D101 serve to clamp the applied
differential input voltage to the ADA4084-1/ADA4084-2/
ADA4084-4, thereby protecting the input transistors against Zener
breakdown of the emitter-base junctions. Input stage voltage
gains are kept low for input rail-to-rail operation. The two pairs of
differential output voltages are connected to the second stage of
the ADA4084-1/ADA4084-2/ADA4084-4, which is a modified
compound folded cascade gain stage. It is also in the second
gain stage that the two pairs of differential output voltages are
combined into a single-ended output signal voltage used to
drive the output stage.
C2
Q13
R7
V
BIAS
Q18
R5
C1
Q19
Q21
V
D20
EE
Figure 107. Equivalent Output Circuit
Thus, the saturation voltage of the output transistors sets the
limit on the ADA4084-1/ADA4084-2/ADA4084-4 maximum
output voltage swing. Output short-circuit current limiting is
determined by the maximum signal current into the base of
Q13 from the second gain stage. The output stage also exhibits
voltage gain. This is accomplished by the use of common-emitter
amplifiers, and, as a result, the voltage gain of the output stage
(thus, the open-loop gain of the device) exhibits a dependence
on the total load resistance at the output of the ADA4084-1/
ADA4084-2/ADA4084-4.
Rev. I | Page 29 of 36
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
R2
START-UP CHARACTERISTICS
The ADA4084-1/ADA4084-2/ADA4084-4 are specified to operate
from 3 V to 30 V ( 1.5 V to 15 V) under nominal power
supplies. During power-up as the supply voltage increases from
0 V to the nominal power supply voltage, the supply current (ISY)
increases as well, to the point at which it stabilizes and the amplifier
is ready to operate. The stabilization varies with temperature, as
shown in Figure 103. For example, at −40°C, it requires a higher
voltage and stabilizes at a lower supply current than at hot
temperatures. At hot temperatures, it requires a lower voltage but
stabilizes at a higher current. In all cases, the ADA4084-1/
ADA4084-2/ADA4084-4 are specified to start up and operate at
a minimum of 3 V under all temperature conditions.
1/2
ADA4084-1/
ADA4084-2/
ADA4084-4
V
OUT
R1
V
IN
Figure 108. Resistance in Series with the Input
Limits Overvoltage Currents to Safe Values
To protect the Q1/Q2 and Q3/Q4 pairs from large differential
voltages that may result in Zener breakdown of the emitter-base
junction, D100 and D101 are connected between the two inputs.
This precludes operation as a comparator. For a more complete
description, see the MT-035 Tutorial, Op Amp Inputs, Outputs,
Single-Supply, and Rail-to-Rail Issues; the MT-083 Tutorial,
Comparators; the MT-084 Tutorial, Using Op Amps as
Comparators; and the AN-849 Application Note, Using Op
Amps as Comparators.
INPUT PROTECTION
As with any semiconductor device, if conditions exist where the
applied input voltages to the device exceed either supply voltage,
the input overvoltage I-to-V characteristic of the device must be
considered. When an overvoltage occurs, the amplifier may be
damaged, depending on the magnitude of the applied voltage
and the magnitude of the fault current.
OUTPUT PHASE REVERSAL
Some operational amplifiers designed for single-supply operation
exhibit an output voltage phase reversal when their inputs are
driven beyond their useful common-mode range. Typically, for
single-supply bipolar op amps, the negative supply determines
the lower limit of their common-mode range. With these devices,
external clamping diodes, with the anode connected to ground
and the cathode to the inputs, prevent input signal excursions
from exceeding the negative supply of the device (that is, GND),
preventing a condition that causes the output voltage to change
phase. JFET input amplifiers can also exhibit phase reversal, and, if
so, a series input resistor is usually required to prevent it.
The D1, D2, D4, and D5 diodes conduct when the input common-
mode voltage exceeds either supply pin by a diode drop. This
diode drop voltage varies with temperature and is in the range
of 0.3 V to 0.8 V. As shown in the simplified equivalent input
circuit of Figure 106, the ADA4084-1/ADA4084-2/ADA4084-4
do not have any internal current limiting resistors; thus, fault
currents can quickly rise to damaging levels.
This input current is not inherently damaging to the device,
provided that it is limited to 5 mA or less. If a fault condition
causes more than 5 mA to flow, add an external series resistor at
the expense of additional thermal noise. Figure 108 shows a
typical noninverting configuration for an overvoltage protected
amplifier, where the series resistance (R1) is chosen, such that
The ADA4084-1/ADA4084-2/ADA4084-4 are free from
reasonable input voltage range restrictions, provided that input
voltages no greater than the supply voltages are applied (see
Figure 38, Figure 69, and Figure 100).
VIN
) −VSUPPLY
MAX
(
R1 =
Although device output does not change phase, large currents can
flow through the input protection diodes. Therefore, apply the
technique recommended in the Input Protection section to
those applications where the likelihood of input voltages
exceeding the supply voltages is high.
5 mA
For example, a 1 kΩ resistor protects the ADA4084-1/ADA4084-2/
ADA4084-4 against input signals up to 5 V above and below the
supplies. Note that the thermal noise of a 1 kΩ resistor at room
temperature is 4 nV/√Hz, which exceeds the voltage noise of the
ADA4084-1/ADA4084-2/ADA4084-4. For other configurations
in which both inputs are used, add a series resistor to limit the
input current. To ensure optimum dc and ac performance,
balance the source impedance levels.
Rev. I | Page 30 of 36
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
Because circuit SNR is the critical parameter in the final analysis,
the noise behavior of a circuit is sometimes expressed in terms
of its noise figure (NF). The noise figure is defined as the ratio
of the signal-to-noise output of a circuit to its signal-to-noise input.
DESIGNING LOW NOISE CIRCUITS IN SINGLE-
SUPPLY APPLICATIONS
In single-supply applications, devices like the ADA4084-1/
ADA4084-2/ADA4084-4 extend the dynamic range of the
application through the use of rail-to-rail operation. Referring to
the op amp noise model circuit configuration illustrated in
Figure 109, the expression for the total equivalent input noise
voltage of an amplifier for a source resistance level, RS, is given by
Noise figure is generally used for RF and microwave circuit analysis
in a 50 Ω system. This is not very useful for op amp circuits where
the input and output impedances can vary greatly. For a more
complete description of noise figure, see the MT-052 Tutorial,
Op Amp Noise Figure: Don’t be Misled.
V
2
2
enT = 2
[
(enR )2 + (
×
)
+ (enOA
)
, units in
inOA RS
Signal levels in the application invariably increase to maximize
circuit SNR, which is not an option in low voltage, single-supply
applications.
where:
(enR)2 is the source resistance thermal noise voltage power (4kTR).
k is the Boltzmann’s constant, 1.38 × 10–23 J/K.
T is the ambient temperature in Kelvin of the circuit, 273.15 +
TA (°C).
Therefore, to achieve optimum circuit SNR in single-supply
applications, choose an operational amplifier with the lowest
equivalent input noise voltage, along with source resistance
levels that are consistent with maintaining low total circuit noise.
(inOA)2 is the op amp equivalent input noise current spectral
power (1 Hz bandwidth).
COMPARATOR OPERATION
RS = 2R, the effective, or equivalent, circuit source resistance.
(enOA)2 is the op amp equivalent input noise voltage spectral
power (1 Hz bandwidth).
Although op amps are quite different from comparators,
occasionally an unused section of a dual or a quad op amp can
be used as a comparator; however, this is not recommended for
any rail-to-rail output op amps. For rail-to-rail output op amps,
the output stage is generally a ratioed current mirror with bipolar
or MOSFET transistors. With the device operating open-loop,
the second stage increases the current drive to the ratioed mirror
to close the loop. However, the loop cannot close, which results in
an increase in supply current. With the op amp configured as a
comparator, the supply current can be significantly higher (see
Figure 111). Configure an unused section as a voltage follower
with the noninverting input connected to a voltage within the
input voltage range. The ADA4084-1/ADA4084-2/ADA4084-4
have unique second stage and output stage designs that greatly
reduce the excess supply current when the op amp is operating
open-loop.
enR
enOA
R
NOISELESS
inOA
IDEAL
NOISELESS
OP AMP
enR
R
NOISELESS
R
= 2R
S
inOA
Figure 109. Op Amp Noise Circuit Model Used to Determine Total Circuit
Equivalent Input Noise Voltage and Noise Figure
As a design aid, Figure 110 shows the equivalent thermal noise
of the ADA4084-1/ADA4084-2/ADA4084-4 vs. the total source
resistance. Note that for source resistance less than 1 kΩ, the
equivalent input noise voltage of the ADA4084-1/ADA4084-2/
ADA4084-4 is dominant.
800
COMPARATOR
OUTPUT LOW
100
700
FREQUENCY = 1kHz
T
= 25°C
A
600
BUFFER
500
400
300
200
100
0
COMPARATOR
OUTPUT HIGH
ADA4084-1/ADA4084-2/ADA4084-4
TOTAL EQUIVALENT NOISE
10
RESISTOR THERMAL
NOISE ONLY
T
= 25°C
A
R
= ∞
L
0
4
8
12
16
20
(V)
24
28
32
36
V
1
100
SY
1k
10k
100k
Figure 111. Supply Current vs. Supply Voltage (VSY
)
TOTAL SOURCE RESISTANCE, R (Ω)
S
Figure 110. Equivalent Thermal Noise vs. Total Source Resistance
Rev. I | Page 31 of 36
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
LONG-TERM DRIFT
TEMPERATURE HYSTERESIS
The stability of a precision signal path over its lifetime or
between calibration procedures is dependent on the long-term
stability of the analog components in the path, such as op amps,
references, and data converters. To help system designers
predict the long-term drift of circuits that use the ADA4084-1/
ADA4084-2/ADA4084-4, Analog Devices measured the offset
voltage of multiple units for 10,000 hours (more than 13 months)
using a high precision measurement system, including an
ultrastable oil bath. To replicate real-world system performance,
the devices under test (DUTs) were soldered onto an FR4 PCB
using a standard reflow profile (as defined in the JEDEC J-STD-
020D standard), as opposed to testing them in sockets. This
manner of testing is important because expansion and
In addition to stability over time as described in the Long-Term
Drift section, it is useful to know the temperature hysteresis,
that is, the stability vs. cycling of temperature. Hysteresis is an
important parameter because it tells the system designer how
closely the signal returns to its starting amplitude after the
ambient temperature changes and subsequent return to room
temperature. Figure 113 shows the change in input offset
voltage as the temperature cycles three times from room
temperature to +125°C to −40°C and back to room temperature.
The dotted line is an initial preconditioning cycle to eliminate
the original temperature-induced offset shift from exposure to
production solder reflow temperatures. In the three full cycles,
the offset hysteresis is typically only 4 μV, or 2% of its 200 µV
maximum offset voltage over the full operating temperature
range. The histogram in Figure 114 shows that the hysteresis is
larger when the device is cycled through only a half cycle, from
room temperature to 125°C and back to room temperature.
100
contraction of the PCB can apply stress to the integrated circuit
(IC) package and contribute to shifts in the offset voltage.
The ADA4084-1/ADA4084-2/ADA4084-4 have extremely low
long-term drift, as shown in Figure 112. The red, blue, and
green traces show sample units. Note that the mean drift of the
ADA4084-1/ADA4084-2/ADA4084-4 over 10,000 hours is less
than 3 μV, or less than 3% of their maximum specified offset
voltage of 100 µV at room temperature.
PRECONDITION
CYCLE 1
V
= 10V
SY
80
60
CYCLE 2
CYCLE 3
40
15
20
0
10
–20
–40
–60
–80
–100
5
0
–40
–20
0
20
40
60
80
100
120
–5
TEMPERATURE (°C)
Figure 113. Change in Offset Voltage over Three Full Temperature Cycles
–10
40
V
= 10V
HALF CYCLE
FULL CYCLE
SY
35
30
25
20
15
10
27 UNITS × 3 CYCLES
HALF CYCLE = +26°C, +125°C, +26°C
FULL CYCLE = +26°C, +125°C, +26°C, –40°C, +26°C
–15
TIME (Hours)
Figure 112. Measured Long-Term Drift of the ADA4084-1/ADA4084-2/
ADA4084-4 Offset Voltage over 10,000 Hours
5
0
40
35
30
25
20
15
10
5
0
–40 –32 –24 –18
–8
0
8
18
24
32
40
OFFSET VOLTAGE HYSTERESIS (µV)
Figure 114. Histogram Showing the Temperature Hysteresis of the Offset
Voltage over Three Full Cycles and over Three Half Cycles
Rev. I | Page 32 of 36
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
45°
1.27 (0.0500)
BSC
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0099)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 115. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
3.00
2.90
2.80
5
1
4
3
3.00
2.80
2.60
1.70
1.60
1.50
2
0.95 BSC
1.90
BSC
1.30
1.15
0.90
0.20 MAX
0.08 MIN
1.45 MAX
0.95 MIN
0.55
0.45
0.35
0.15 MAX
0.05 MIN
10°
5°
0°
SEATING
PLANE
0.60
BSC
0.50 MAX
0.35 MIN
COMPLIANT TO JEDEC STANDARDS MO-178-AA
Figure 116. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
Rev. I | Page 33 of 36
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
3.20
3.00
2.80
8
5
4
5.15
4.90
4.65
3.20
3.00
2.80
1
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.15
0.05
0.23
0.09
6°
0°
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 117. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
DETAIL A
(JEDEC 95)
2.44
2.34
2.24
3.10
3.00 SQ
0.50 BSC
2.90
8
5
PIN 1 INDEX
AREA
1.70
1.60
1.50
EXPOSED
PAD
0.50
0.40
0.30
4
1
0.20 MIN
TOP VIEW
SIDE VIEW
BOTTOM VIEW
PIN
1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET
0.30
0.25
0.20
SEATING
PLANE
0.203 REF
COMPLIANT TO JEDEC STANDARDS MO-229-W3030D-4
Figure 118. 8-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-8-11)
Dimensions shown in millimeters
Rev. I | Page 34 of 36
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
DETAIL A
(JEDEC 95)
4.10
4.00 SQ
3.90
0.35
0.30
0.25
PIN 1
INDICATOR
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
13
16
0.65
BSC
12
1
2.70
2.60 SQ
EXPOSED
PAD
2.50
4
9
8
5
0.45
0.40
0.35
0.20 MIN
BOTTOM VIEW
TOP VIEW
SIDE VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
Figure 119. 16-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 075 mm Package Height
(CP-16-17)
Dimensions shown in millimeters
5.10
5.00
4.90
14
8
7
4.50
4.40
4.30
6.40
BSC
1
PIN 1
0.65 BSC
1.05
1.00
0.80
1.20
MAX
0.20
0.09
0.75
0.60
0.45
8°
0°
0.15
0.05
COPLANARITY
0.10
SEATING
PLANE
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 120. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
Rev. I | Page 35 of 36
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
ORDERING GUIDE
Model1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
Branding
ADA4084-1ARZ
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
5-Lead Small Outline Transistor Package [SOT-23]
5-Lead Small Outline Transistor Package [SOT-23]
5-Lead Small Outline Transistor Package [SOT-23]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Lead Frame Chip Scale Package [LFCSP]
8-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
14-Lead Thin Shrink Small Outline Package [TSSOP]
14-Lead Thin Shrink Small Outline Package [TSSOP]
R-8
R-8
R-8
RJ-5
RJ-5
RJ-5
ADA4084-1ARZ-R7
ADA4084-1ARZ-RL
ADA4084-1ARJZ-R2
ADA4084-1ARJZ-R7
ADA4084-1ARJZ-RL
ADA4084-2ARMZ
ADA4084-2ARMZ-R7
ADA4084-2ARMZ-RL
ADA4084-2ARZ
ADA4084-2ARZ-R7
ADA4084-2ARZ-RL
ADA4084-2ACPZ-R7
ADA4084-2ACPZ-RL
ADA4084-4ACPZ-R7
ADA4084-4ACPZ-RL
ADA4084-4ARUZ
ADA4084-4ARUZ-RL
A38
A38
A38
A2Q
A2Q
A2Q
RM-8
RM-8
RM-8
R-8
R-8
R-8
CP-8-11
CP-8-11
CP-16-17
CP-16-17
RU-14
RU-14
A2Q
A2Q
1 Z = RoHS Compliant Part.
©2011–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08237-0-5/17(I)
Rev. I | Page 36 of 36
ADA4084-4ARUZ-RL CAD模型
引脚图
封装焊盘图
ADA4084-4ARUZ-RL 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| ADA4084-4ACPZ-R7 | ADI | 30 V, Low Noise, Rail-to-Rail Input/Output, Low Power Operational Quad Amplifier | 功能相似 |
|
| ADA4084-4ACPZ-RL | ADI | 30 V, Low Noise, Rail-to-Rail Input/Output, Low Power Operational Quad Amplifier | 功能相似 |
|
ADA4084-4ARUZ-RL 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| ADA4091-2 | ADI | Precision Micropower, OVP, RRIO Operational Amplifier | 获取价格 |
|
| ADA4091-2ACPZ-R2 | ADI | Precision Micropower, OVP, RRIO Operational Amplifier | 获取价格 |
|
| ADA4091-2ACPZ-R7 | ADI | Precision Micropower, OVP, RRIO Operational Amplifier | 获取价格 |
|
| ADA4091-2ACPZ-RL | ADI | Precision Micropower, OVP, RRIO Operational Amplifier | 获取价格 |
|
| ADA4091-2ARZ | ADI | Precision Micropower, OVP, RRIO Operational Amplifier | 获取价格 |
|
| ADA4091-2ARZ-R2 | ADI | IC OP-AMP, 600 uV OFFSET-MAX, 1.22 MHz BAND WIDTH, PDSO8, ROHS COMPLIANT, MS-012AA, SOIC-8, Operational Amplifier | 获取价格 |
|
| ADA4091-2ARZ-R7 | ADI | Precision Micropower, OVP, RRIO Operational Amplifier | 获取价格 |
|
| ADA4091-2ARZ-RL | ADI | Precision Micropower, OVP, RRIO Operational Amplifier | 获取价格 |
|
| ADA4091-4 | ADI | Precision Micropower, OVP, RRIO Operational Amplifier | 获取价格 |
|
| ADA4091-4ACPZ-R2 | ADI | Precision Micropower, OVP, RRIO Operational Amplifier | 获取价格 |
|
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