ADG1412YCPZ-REEL [ADI]
1.5 Ω On Resistance, ±15 V/+12 V/±5 V, iCMOS®, Quad SPST Switch;
| 型号： | ADG1412YCPZ-REEL |
| 厂家： | 
ADI |
| 描述： | 1.5 Ω On Resistance, ±15 V/+12 V/±5 V, iCMOS®, Quad SPST Switch 输出元件 |
| 文件： | 总16页 (文件大小：427K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1.5 Ω On Resistance, 15 ꢀV/1ꢁ ꢀV 5 ꢀ,
iCMOS, Quad SPST Switches
Data Sheet
ADG1411VADG141ꢁVADG1413
FEATURES
FUNCTIONAL BLOCK DIAGRAM
1.5 Ω on resistance
S1
S1
S1
0.3 Ω on-resistance flatness
0.1 Ω on-resistance match between channels
Continuous current per channel
LFCSP: 250 mA
TSSOP: 190 mA
Fully specified at +12 V, 15 V, and 5 V
No VL supply required
3 V logic-compatible inputs
Rail-to-rail operation
16-lead TSSOP and 16-lead, 4 mm × 4 mm LFCSP
Qualified for automotive applications
IN1
IN2
IN3
IN4
IN1
IN2
IN3
IN4
IN1
IN2
IN3
IN4
D1
S2
D1
S2
D1
S2
D2
S3
D2
S3
D2
S3
ADG1411
ADG1412
ADG1413
D3
S4
D3
S4
D3
S4
D4
D4
D4
APPLICATIONS
SWITCHES SHOWN FOR A LOGIC 1 INPUT.
Figure 1.
Automated test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Video signal routing
Communications systems
Relay replacement
GENERAL DESCRIPTION
The ADG1411/ADG1412/ADG1413 are monolithic complemen-
tary metal-oxide semiconductor (CMOS) devices containing
four independently selectable switches designed on an iCMOS®
process. iCMOS (industrial CMOS) is a modular manufacturing
process combining high voltage CMOS and bipolar technologies.
It enables the development of a wide range of high performance
analog ICs capable of 33 V operation in a footprint that no previous
generation of high voltage devices has been able to achieve.
Unlike analog ICs using conventional CMOS processes, iCMOS
components can tolerate high supply voltages while providing
increased performance, dramatically lower power consumption,
and reduced package size.
ADG1412 differ only in that the digital control logic is inverted.
The ADG1411 switches are turned on with Logic 0 on the
appropriate control input, whereas the ADG1412 switches are
turned on with Logic 1. The ADG1413 has two switches with
digital control logic similar to that of the ADG1411; the logic is
inverted on the other two switches. Each switch conducts equally
well in both directions when on and has an input signal range
that extends to the supplies. In the off condition, signal levels up
to the supplies are blocked.
The ADG1413 exhibits break-before-make switching action for
use in multiplexer applications. Inherent in the design is low
charge injection, which results in minimum transients when the
digital inputs are switched.
The on-resistance profile is very flat over the full analog input
range, ensuring excellent linearity and low distortion when
switching signals.
PRODUCT HIGHLIGHTS
1. 2.6 Ω maximum on resistance over temperature.
2. Minimum distortion.
3. Ultralow power dissipation: <0.03 μW.
iCMOS construction ensures ultralow power dissipation,
making the devices ideally suited for portable and battery-
powered instruments.
4. 16-lead TSSOP and 16-lead, 4 mm × 4 mm LFCSP.
The ADG1411/ADG1412/ADG1413 contain four independent
single-pole/single-throw (SPST) switches. The ADG1411 and
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2008–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADG1411/ADG1412/ADG1413
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................6
ESD Caution...................................................................................6
Pin Configurations and Function Descriptions............................7
Typical Performance Characteristics ..............................................8
Terminology.................................................................................... 12
Test Circuits..................................................................................... 13
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 16
Automotive Products................................................................. 16
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
15 V Dual Supply ....................................................................... 3
+12 V Single Supply ..................................................................... 4
5 V Dual Supply ......................................................................... 5
REVISION HISTORY
3/09—Rev. 0 to Rev. A
3/16—Rev. B to Rev. C
Changed CP-16-13 to CP-16-26.................................. Throughout
Changes to Figure 2, Figure 3, and Table 5 ................................... 7
Updated Outline Dimensions....................................................... 15
Changes to Ordering Guide .......................................................... 16
Changes to Power Requirements, IDD, Digital Inputs = 5 V
Parameter, Table 1 .............................................................................3
Changes to Power Requirements, IDD, Digital Inputs = 5 V
Parameter Table 2 ..............................................................................4
3/11—Rev. A to Rev. B
5/08—Revision 0: Initial Version
Changes to Features Section............................................................ 1
Changes to Table 5, Added Exposed Pad Notation...................... 3
Updated Outline Dimensions....................................................... 15
Changes to Ordering Guide .......................................................... 40
Added Automotive Products Section........................................... 40
Rev. C | Page 2 of 16
Data Sheet
ADG1411/ADG1412/ADG1413
SPECIFICATIONS
15 V DUAL SUPPLY
VDD = 15 V 10%, VSS = −15 V 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
25°C
−40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VDD to VSS
2.6
V
1.5
1.8
0.1
Ω typ
Ω max
Ω typ
VS = 10 V, IS = −10 mA; see Figure 23
VDD = +13.5 V, VSS = −13.5 V
VS = 10 V , IS = −10 mA
2.3
On-Resistance Match
Between Channels, ∆RON
0.18
0.3
0.36
0.19
0.4
0.21
0.45
Ω max
Ω typ
Ω max
On-Resistance Flatness, RFLAT(ON)
VS = 10 V, IS = −10 mA
LEAKAGE CURRENTS
VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage, IS (Off)
0.03
0.55
0.03
nA typ
nA max
nA typ
VS = 10 V, VD = ∓10 V; see Figure 24
2
2
4
12.5
12.5
30
Drain Off Leakage, ID (Off)
VS = 10 V, VD = ∓10 V; see Figure 24
0.55
0.15
nA max
nA typ
Channel On Leakage, ID, IS (On)
VS = VD = 10 V; see Figure 25
2
nA max
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
µA typ
µA max
pF typ
0.005
3.5
VIN = VGND or VDD
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
tON
100
150
90
120
25
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 30
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 30
RL = 300 Ω, CL = 35 pF
170
140
190
160
tOFF
Break-Before-Make Time Delay, tD
(ADG1413 Only)
10
ns min
pC typ
dB typ
dB typ
% typ
VS1 = VS2 = 10 V; see Figure 31
Charge Injection, QINJ
−20
VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 32
RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 26
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27
RL = 110 Ω, 15 V p-p, f = 20 Hz to 20 kHz;
see Figure 29
Off Isolation
−80
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
−100
0.014
−3 dB Bandwidth
Insertion Loss
CS (Off)
CD (Off)
CD, CS (On)
170
−0.35
23
23
116
MHz typ
dB typ
pF typ
pF typ
pF typ
RL = 50 Ω, CL = 5 pF; see Figure 28
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
POWER REQUIREMENTS
IDD
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
0.001
220
µA typ
µA max
µA typ
µA max
µA typ
µA max
1
IDD
Digital inputs = 5 V
380
ISS
0.001
Digital inputs = 0 V or VDD
1
VDD/VSS
4.5/ 16.5
V min/V max GND = 0 V
1 Guaranteed by design; not subject to production test.
Rev. C | Page 3 of 16
ADG1411/ADG1412/ADG1413
Data Sheet
+12 V SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
25°C
−40°C to +85°C
−40°C to +125°C
0 V to VDD
4.8
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
V
2.8
3.5
0.13
Ω typ
Ω max
Ω typ
VS = 0 V to 10 V, IS = −10 mA; see Figure 23
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −10 mA
4.3
On-Resistance Match
Between Channels, ∆RON
0.21
0.6
1.1
0.23
1.2
0.25
1.3
Ω max
Ω typ
Ω max
On-Resistance Flatness, RFLAT(ON)
VS = 0 V to 10 V, IS = −10 mA
LEAKAGE CURRENTS
VDD = 10.8 V, VSS = 0 V
Source Off Leakage, IS (Off)
0.02
0.55
0.02
nA typ
nA max
nA typ
VS = 1 V/10 V, VD = 10 V/0 V; see Figure 24
2
2
4
12.5
12.5
30
Drain Off Leakage, ID (Off)
VS = 1 V/10 V, VD = 10 V/0 V; see Figure 24
VS = VD = 1 V/10 V; see Figure 25
0.55
0.15
1.5
nA max
nA typ
nA max
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
µA typ
µA max
pF typ
0.001
3.5
VIN = VGND or VDD
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
tON
170
250
75
135
100
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 30
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 30
RL = 300 Ω, CL = 35 pF
295
165
330
190
tOFF
Break-Before-Make Time Delay, tD
(ADG1413 Only)
40
ns min
pC typ
dB typ
dB typ
MHz typ
dB typ
pF typ
pF typ
pF typ
VS1 = VS2 = 8 V; see Figure 31
VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 32
RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 26
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27
RL = 50 Ω, CL = 5 pF; see Figure 28
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
VS = 6 V, f = 1 MHz
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
Insertion Loss
CS (Off)
30
−80
−100
130
−0.5
38
CD (Off)
40
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
CD, CS (On)
104
POWER REQUIREMENTS
IDD
VDD = 13.2 V
Digital inputs = 0 V or VDD
0.001
220
µA typ
µA max
µA typ
µA max
V min/V max
1
Digital inputs = 5 V
GND = 0 V, VSS = 0 V
380
5/16.5
VDD
1 Guaranteed by design; not subject to production test.
Rev. C | Page 4 of 16
Data Sheet
ADG1411/ADG1412/ADG1413
5 V DUAL SUPPLY
VDD = 5 V 10%, VSS = −5 V 10%, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
25°C
−40°C to +85°C
−40°C to +125°C
VDD to VSS
5.4
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
V
3.3
4
0.13
Ω typ
Ω max
Ω typ
VS = 4.5 V, IS = −10 mA; see Figure 23
VDD = +4.5 V, VSS = −4.5 V
VS = 4.5 V, IS = −10 mA
4.9
On-Resistance Match
Between Channels, ∆RON
0.22
0.9
1.1
0.23
1.24
0.25
1.31
Ω max
Ω typ
Ω max
On-Resistance Flatness, RFLAT(ON)
VS = 4.5 V; IS = −10 mA
LEAKAGE CURRENTS
VDD = +5.5 V, VSS = −5.5 V
Source Off Leakage, IS (Off)
0.03
0.55
0.03
0.55
0.05
1.0
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 4.5 V, VD = ∓4.5 V; see Figure 24
2
2
4
12.5
12.5
30
Drain Off Leakage, ID (Off)
VS = 4.5 V, VD = ∓4.5 V; see Figure 24
Channel On Leakage, ID, IS (On)
VS = VD = 4.5 V; see Figure 25
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
µA typ
µA max
pF typ
0.001
3.5
VIN = VGND or VDD
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
tON
275
400
175
290
100
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF
VS = 3 V; see Figure 30
RL = 300 Ω, CL = 35 pF
VS = 3 V; see Figure 30
RL = 300 Ω, CL = 35 pF
465
320
510
380
tOFF
Break-Before-Make Time Delay,
tD (ADG1413 Only)
50
ns min
pC typ
dB typ
dB typ
% typ
VS1 = VS2 = 3 V; see Figure 31
Charge Injection, QINJ
30
VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 32
RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 26
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27
RL = 110 Ω, 5 V p-p, f = 20 Hz to 20 kHz;
see Figure 29
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
−80
−100
0.03
−3 dB Bandwidth
Insertion Loss
CS (Off)
CD (Off)
CD, CS (On)
130
−0.5
32
33
116
MHz typ
dB typ
pF typ
pF typ
pF typ
RL = 50 Ω, CL = 5 pF; see Figure 28
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
POWER REQUIREMENTS
IDD
VDD = +5.5 V, VSS = −5.5 V
Digital inputs = 0 V or VDD
0.001
0.001
µA typ
µA max
µA typ
µA max
1.0
ISS
Digital inputs = 0 V or VDD
1.0
VDD/VSS
4.5/ 16.5
V min/V max GND = 0 V
1 Guaranteed by design; not subject to production test.
Rev. C | Page 5 of 16
ADG1411/ADG1412/ADG1413
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Parameter
Rating
VDD to VSS
35 V
−0.3 V to +25 V
+0.3 V to −25 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
GND − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
500 mA (pulsed at 1 ms,
VDD to GND
VSS to GND
Analog Inputs1
Digital Inputs1
Only one absolute maximum rating may be applied at any
one time.
Peak Current, Sx or Dx Pins
10% duty cycle maximum)
ESD CAUTION
Continuous Current per
Channel at 25°C
16-Lead TSSOP
16-Lead LFCSP
190 mA
250 mA
Continuous Current per
Channel at 125°C
16-Lead TSSOP
90 mA
16-Lead LFCSP
100 mA
Operating Temperature Range
Automotive (Y Version)
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
−40°C to +125°C
−65°C to +150°C
150°C
16-Lead TSSOP (4-Layer Board) 112°C/W
16-Lead LFCSP
30.4°C/W
Reflow Soldering Peak
Temperature, Pb Free
260(+0/−5)°C
1 Overvoltages at the INx, Sx, and Dx pins are clamped by internal diodes.
Current should be limited to the maximum ratings given.
Rev. C | Page 6 of 16
Data Sheet
ADG1411/ADG1412/ADG1413
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
IN1
D1
S1
1
2
3
4
5
6
7
8
16 IN2
15 D2
14 S2
S1 1
12 S2
ADG1411/
ADG1412/
ADG1413
V
2
11 V
DD
SS
ADG1411/
ADG1412/
ADG1413
10
9
GND 3
NIC
V
13
V
SS
DD
4
S4
S3
GND
12 NIC
TOP VIEW
S4
D4
(Not to Scale) 11 S3
10 D3
TOP VIEW
(Not to Scale)
IN4
9 IN3
NOTES
NOTES
1. NIC = NO INTERNAL CONNECTION.
2. TIE THE EXPOSED PAD TO THE SUBSTRATE, V
1. NIC = NO INTERNAL CONNECTION.
.
SS
Figure 2. TSSOP Pin Configuration
Figure 3. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
LFCSP
TSSOP
Mnemonic
IN1
D1
Description
1
2
3
15
16
1
Logic Control Input.
Drain Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
Most Negative Power Supply Potential.
Ground (0 V) Reference.
Source Terminal. This pin can be an input or output.
Drain Terminal. This pin can be an input or output.
Logic Control Input.
S1
4
2
VSS
5
6
3
4
GND
S4
7
5
D4
8
9
6
7
8
9
10
11
12
13
14
0
IN4
IN3
D3
S3
NIC
VDD
S2
D2
IN2
EPAD
Logic Control Input.
10
11
12
13
14
15
16
N/A1
Drain Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
No Internal Connection.
Most Positive Power Supply Potential.
Source Terminal. This pin can be an input or output.
Drain Terminal. This pin can be an input or output.
Logic Control Input.
Exposed Pad. Tie the exposed pad to the substrate, VSS.
1 N/A means not applicable.
Table 6. ADG1411/ADG1412 Truth Table
ADG1411 INx
ADG1412 INx
Switch Condition
0
1
1
0
On
Off
Table 7. ADG1413 Truth Table
ADG1413 INx
S1, S4
Off
On
S2, S3
On
Off
0
1
Rev. C | Page 7 of 16
ADG1411/ADG1412/ADG1413
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
2.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
V
= +10V,
= –10V
DD
SS
2.0
1.5
1.0
0.5
0
V
V
= +12V,
= –12V
DD
SS
T
= +125°C
= +85°C
A
T
A
T
T
= +25°C
= –40°C
A
V
V
= +16.5V,
= –16.5V
DD
SS
V
V
= +13.5V,
= –13.5V
DD
SS
V
= +15V,
DD
SS
A
V
= –15V
V
V
I
= +15V
= –15V
= –10mA
DD
SS
T
I
= 25°C
= –10mA
A
S
S
–16.5 –12.5 –8.5
–4.5
–0.5
3.5
7.5
11.5
15.5
–15
–10
–5
0
5
10
15
V
OR V (V)
V OR V (V)
S D
S
D
Figure 4. On Resistance vs. VD or VS,
Dual Supply
Figure 7. On Resistance vs. VD or VS for Different Temperatures,
15 V Dual Supply
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5.0
4.5
4.0
V
V
= +4.5V,
= –4.5V
DD
SS
V
V
= +5V,
= –5V
DD
SS
T
= +125°C
= +85°C
A
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
T
A
T
T
= +25°C
= –40°C
A
V
V
= +7V,
= –7V
DD
SS
V
= +5.5V,
DD
SS
V
= –5.5V
A
V
V
= +5V
= –5V
= –10mA
DD
T
= 25°C
= –10mA
A
SS
I
S
I
S
–7 –6 –5 –4 –3 –2 –1
0
1
2
3
4
5
6
7
–5
–4
–3
–2
–1
V
0
1
2
3
4
5
V
OR V (V)
OR V (V)
S D
S
D
Figure 5. On Resistance vs. VD or VS,
Dual Supply
Figure 8. On Resistance vs. VD or VS for Different Temperatures,
5 V Dual Supply
4.5
4.0
7
6
5
4
3
2
1
0
V
V
= 5V,
= 0V
DD
SS
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
T
= +125°C
= +85°C
A
T
A
V
V
= 10.8V,
= 0V
DD
SS
V
V
= 8V,
= 0V
DD
SS
V
V
= 12V,
= 0V
DD
SS
T
= +25°C
= –40°C
A
T
A
V
V
= 15V,
V
V
= 13.2V,
= 0V
DD
DD
SS
= 0V
V
V
I
= 12V
= 0V
= –10mA
SS
DD
T
I
= 25°C
= –10mA
A
SS
S
S
0
2
4
6
8
10
12
0
2
4
6
8
10
12
14
V
OR V (V)
D
V
OR V (V)
D
S
S
Figure 9. On Resistance vs. VD or VS for Different Temperatures,
+12 V Single Supply
Figure 6. On Resistance vs. VD or VS,
Single Supply
Rev. C | Page 8 of 16
Data Sheet
ADG1411/ADG1412/ADG1413
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
9
8
V
V
V
= 12V
= 0V
I
I
I
I
I
I
(OFF) + –
(OFF) + –
(OFF) – +
(OFF) – +
DD
SS
S
D
S
D
D
D
= 1V/10V
BIAS
T
I
= 125°C
= 100mA
A
7
S
, I (ON) ++
S
6
, I (ON) – –
S
5
4
T
S
= 25°C
= 190mA
A
I
3
2
1
0
V
V
= +5V
= –5V
DD
SS
0
–1
–5
–4
–3
–2
–1
0
1
2
3
4
5
0
20
40
60
80
100
120
V
OR V (V)
TEMPERATURE (°C)
S
D
Figure 10. On Resistance vs. VD or VS for Different Current Levels,
5 V Dual Supply
Figure 13. Leakage Currents vs. Temperature,
+12 V Single Supply
80
70
60
50
40
30
20
10
0
1.5
T
= 25°C
PER LOGIC INPUT
A
I
, I (ON) + +
S
D
I
DD
1.0
0.5
I
(OFF) + –
I
(OFF) – +
S
D
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
V
V
= +15V
= –15V
I
, I (ON) – –
S
DD
SS
D
V
V
= +12V
= 0V
DD
SS
I
(OFF) + –
D
I
(OFF) – +
V
V
V
= +15V
= –15V
= +10V/–10V
S
DD
V
V
= +5V
= –5V
DD
SS
SS
BIAS
0
2
4
6
8
10
12
14
0
20
40
60
80
100
120
LOGIC, INx (V)
TEMPERATURE (°C)
Figure 11. Leakage Currents vs. Temperature,
15 V Dual Supply
Figure 14. IDD vs. Logic Level
600
1.5
1.0
V
V
V
= +5V
T
= 25°C
DD
A
= –5V
SS
BIAS
= +4.5V/–4.5V
400
200
V
= +15V, V = –15V
SS
DD
0.5
V
= +5V, V = –5V
SS
DD
0
0
V
= +12V, V = 0V
SS
DD
–200
–400
–600
–0.5
–1.0
–1.5
I
I
I
I
I
I
(OFF) + –
(OFF) + –
(OFF) – +
(OFF) – +
S
D
S
D
D
D
, I (ON) ++
S
, I (ON) – –
S
–15
–10
–5
0
5
10
15
0
20
40
60
80
100
120
V
(V)
TEMPERATURE (°C)
S
Figure 15. Charge Injection vs. Source Voltage
Figure 12. Leakage Currents vs. Temperature,
5 V Dual Supply
Rev. C | Page 9 of 16
ADG1411/ADG1412/ADG1413
Data Sheet
300
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
V
V
= +15V
= –15V
DD
SS
T
= 25°C
A
250
12V SS tON
200
15V DS tON
150
100
15V DS tOFF
12V SS tOFF
50
0
–40
–20
0
20
40
60
80
100
120
10k
100k
1M
10M
100M
1G
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 16. tON/tOFF Times vs. Temperature for
Single Supply (SS) and Dual Supply (DS)
Figure 19. On Response vs. Frequency,
15 V Dual Supply
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
V
V
= +15V
= –15V
= 25°C
V
V
= +15V
= –15V
DD
SS
DD
SS
T
V p-p = 0.62V
= 25°C
A
T
A
NO DECOUPLING
CAPACITORS
DECOUPLING
CAPACITORS
ON SUPPLIES
1k
10k
100k
1M
10M
100M
1G
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 17. Off Isolation vs. Frequency,
15 V Dual Supply
Figure 20. ACPSRR vs. Frequency,
15 V Dual Supply
0.028
0.026
0.024
0.022
0.020
0.018
0.016
0.014
0.012
0.010
0.008
0.006
0.004
0.002
0
–10
V
V
T
= +15V
= –15V
= 25°C
DD
SS
V
= 20V p-p
S
A
V
V
= +15V
= –15V
= 25°C
DD
SS
–20
–30
T
A
–40
–50
–60
V
V
= 15V p-p
S
–70
–80
–90
= 10V p-p
S
–100
–110
–120
10
100
1k
FREQUENCY (Hz)
10k
100k
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 21. THD + N vs. Frequency,
15 V Dual Supply
Figure 18. Crosstalk vs. Frequency,
15 V Dual Supply
Rev. C | Page 10 of 16
Data Sheet
ADG1411/ADG1412/ADG1413
1
V
V
= +5V
= –5V
DD
SS
T
= 25°C
A
V
= 10V p-p
= 5V p-p
S
0.1
0.01
V
S
V
= 2.5V p-p
S
0.001
10
100
1k
FREQUENCY (Hz)
10k
100k
Figure 22. THD + N vs. Frequency,
5 V Dual Supply
Rev. C | Page 11 of 16
ADG1411/ADG1412/ADG1413
Data Sheet
TERMINOLOGY
IDD
CIN
The positive supply current.
The digital input capacitance.
ISS
tON
The negative supply current.
The delay between applying the digital control input and the
output switching on. See Figure 30.
VD, VS
The analog voltage on Terminal D and Terminal S.
tOFF
The delay between applying the digital control input and the
output switching off.
RON
The ohmic resistance between Terminal D and Terminal S.
Charge Injection
RFLAT(ON)
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
Flatness is defined as the difference between the maximum and
minimum value of on resistance measured over the specified
analog signal range.
Off Isolation
A measure of unwanted signal coupling through an off switch.
IS (Off)
The source leakage current with the switch off.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
ID (Off)
The drain leakage current with the switch off.
Bandwidth
ID, IS (On)
The frequency at which the output is attenuated by 3 dB.
The channel leakage current with the switch on.
On Response
The frequency response of the on switch.
VINL
The maximum input voltage for Logic 0.
Insertion Loss
The loss due to the on resistance of the switch.
VINH
The minimum input voltage for Logic 1.
Total Harmonic Distortion + Noise (THD + N)
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
I
INL, IINH
The input current of the digital input when high or when low.
CS (Off)
AC Power Supply Rejection Ratio (ACPSRR)
A measure of the ability of the device to avoid coupling noise and
spurious signals that appear on the supply voltage pin to the
output of the switch. The dc voltage on the device is modulated
by a sine wave of 0.62 V p-p. The ratio of the amplitude of the
signal on the output to the amplitude of the modulation is the
ACPSRR.
The off switch source capacitance, which is measured with
reference to ground.
CD (Off)
The off switch drain capacitance, which is measured with
reference to ground.
CD, CS (On)
The on switch capacitance, which is measured with reference
to ground.
Rev. C | Page 12 of 16
Data Sheet
ADG1411/ADG1412/ADG1413
TEST CIRCUITS
V
V
DD
SS
0.1µF
0.1µF
NETWORK
ANALYZER
V
V
DD
SS
I
S
Sx
Dx
50Ω
50Ω
INx
IN
V
S
V1
V
OUT
V
R
L
50Ω
GND
Sx
R
Dx
V
OUT
V
S
= V1/I
ON
S
OFF ISOLATION = 20 log
V
S
Figure 23. On Resistance
Figure 26. Off Isolation
V
V
DD
SS
0.1µF
0.1µF
NETWORK
ANALYZER
V
V
DD
SS
V
OUT
S1
R
L
50Ω
Dx
R
L
50Ω
S2
V
S
GND
I
(OFF)
A
I
(OFF)
A
S
D
Sx
Dx
V
OUT
V
V
D
S
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
V
S
Figure 24. Off Leakage
Figure 27. Channel-to-Channel Crosstalk
V
V
DD
SS
0.1µF
0.1µF
NETWORK
ANALYZER
V
V
DD
SS
Sx
Dx
50Ω
INx
V
S
V
OUT
I
(ON)
A
V
D
IN
R
L
Sx
Dx
50Ω
GND
NIC
V
D
V
WITH SWITCH
OUT
INSERTION LOSS = 20 log
NIC = NO INTERNAL CONNECTION.
V
WITHOUT SWITCH
OUT
Figure 25. On Leakage
Figure 28. Bandwidth
Rev. C | Page 13 of 16
ADG1411/ADG1412/ADG1413
Data Sheet
V
V
DD
SS
0.1µF
0.1µF
AUDIO PRECISION
V
V
DD
SS
R
S
Sx
INx
IN
V
V p-p
S
Dx
V
OUT
V
R
L
110Ω
GND
Figure 29. THD + Noise
V
V
DD
SS
0.1µF
0.1µF
ADG1412
ADG1411
V
V
50%
50%
50%
50%
IN
IN
V
V
SS
DD
V
L
OUT
Sx
Dx
R
C
L
V
S
300Ω
35pF
INx
90%
90%
V
OUT
GND
tOFF
tON
Figure 30. Switching Times
V
V
DD
SS
V
0.1µF
0.1µF
IN
50%
50%
0V
0V
V
S1
V
SS
D1
90%
DD
90%
V
V
OUT1
OUT2
V
V
V
S1
OUT1
C
35pF
R
300Ω
L
L
S2
D2
V
S2
OUT2
C
35pF
R
300Ω
L
L
90%
90%
IN1,
IN2
0V
ADG1413
GND
tD
tD
Figure 31. Break-Before-Make Time Delay
V
V
V
DD
SS
V
V
ADG1412
DD
SS
IN
ON
OFF
V
R
S
OUT
Sx
Dx
C
1nF
L
V
V
S
IN
ADG1411
INx
V
OUT
ΔV
GND
OUT
Q
= C × ΔV
L
OUT
INJ
Figure 32. Charge Injection
Rev. C | Page 14 of 16
Data Sheet
ADG1411/ADG1412/ADG1413
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 33. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
4.10
4.00 SQ
3.90
0.35
0.30
0.25
PIN 1
INDICATOR
PIN 1
INDICATOR
13
16
0.65
BSC
1
4
12
EXPOSED
PAD
2.60
2.50 SQ
2.40
9
8
5
0.50
0.40
0.30
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
Figure 34. 16-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-16-26)
Dimensions shown in millimeters
Rev. C | Page 15 of 16
ADG1411/ADG1412/ADG1413
Data Sheet
ORDERING GUIDE
Model1, 2
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
RU-16
RU-16
CP-16-26
CP-16-26
CP-16-26
RU-16
ADG1411YRUZ
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
ADG1411YRUZ-REEL7
ADG1411YCPZ-REEL
ADG1411YCPZ-REEL7
ADG1411WBCPZ-REEL
ADG1412YRUZ
ADG1412YRUZ-REEL7
ADG1412YCPZ-REEL
ADG1412YCPZ-REEL7
ADG1413YRUZ
RU-16
CP-16-26
CP-16-26
RU-16
RU-16
CP-16-26
CP-16-26
ADG1413YRUZ-REEL7
ADG1413YCPZ-REEL
ADG1413YCPZ-REEL7
1 Z = RoHS Compliant Part.
2 W = qualified for automotive applications.
AUTOMOTIVE PRODUCTS
The ADG1411W model is available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for this model.
©2008–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06815-0-3/16(C)
Rev. C | Page 16 of 16
相关型号：
©2020 ICPDF网 联系我们和版权申明