ADG5436_11 [ADI]
High Voltage Latch-Up Proof, Dual SPDT Switches; 高电压闩锁防，双SPDT开关
| 型号： | ADG5436_11 |
| 厂家： | 
ADI |
| 描述： | High Voltage Latch-Up Proof, Dual SPDT Switches |
| 文件： | 总20页 (文件大小：394K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Voltage Latch-Up Proof,
Dual SPDT Switches
ADG5436
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
Latch-up proof
8 kV HBM ESD rating
ADG5436
S1A
D1
Low on resistance (<10 Ω)
S1B
9 V to 22 V dual-supply operation
9 V to 40 V single-supply operation
48 V supply maximum ratings
Fully specified at 1ꢀ V, 20 V, +12 V, and +36 V
IN1
IN2
VSS to VDD analog signal range
S2A
D2
APPLICATIONS
S2B
Relay replacement
Automatic test equipment
Data acquisition
SWITCHES SHOWN FOR A LOGIC 1 INPUT.
Figure 1. TSSOP Package
Instrumentation
Avionics
Audio and video switching
Communication systems
ADG5436
S1A
D1
S2A
D2
S1B
S2B
LOGIC
IN2
IN1
EN
SWITCHES SHOWN FOR A LOGIC 1 INPUT.
Figure 2. LFCSP Package
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
1. Trench isolation guards against latch-up. A dielectric trench
separates the P and N channel transistors thereby preventing
latch-up even under severe overvoltage conditions.
The ADG5436 is a monolithic CMOS device containing two
independently selectable single-pole/single-throw (SPDT)
switches. An EN input on the LFCSP package enables or
disables the device. When disabled, all channels switch off. Each
switch conducts equally well in both directions when on and
has an input signal range that extends to the supplies. In the off
condition, signal levels up to the supplies are blocked. Both
switches exhibit break-before-make switching action for use in
multiplexer applications.
2. Low RON
.
3. Dual-supply operation. For applications where the analog
signal is bipolar, the ADG5436 can be operated from dual
supplies up to 22 V.
4. Single-supply operation. For applications where the analog
signal is unipolar, the ADG5436 can be operated from a
single-rail power supply up to 40 V.
The on-resistance profile is very flat over the full analog input
range, ensuring excellent linearity and low distortion when
switching audio signals.
5. 3 V logic compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V.
6. No VL logic power supply required.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2010–2011 Analog Devices, Inc. All rights reserved.
ADG5436
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................8
ESD Caution...................................................................................8
Pin Configurations and Function Descriptions............................9
Truth Table For Switches..............................................................9
Typical Performance Characteristics ........................................... 10
Test Circuits..................................................................................... 14
Terminology.................................................................................... 16
Trench Isolation.............................................................................. 17
Applications Information .............................................................. 18
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 19
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
15 V Dual Supply ....................................................................... 3
20 V Dual Supply ....................................................................... 4
12 V Single Supply........................................................................ 5
36 V Single Supply........................................................................ 6
Continuous Current per Channel, Sx or Dx............................. 7
REVISION HISTORY
6/11—Rev. 0 to Rev. A
Added ISS −40°C to +125°C Parameter.......................................... 5
Updated Outline Dimensions....................................................... 19
Changes to Ordering Guide .......................................................... 19
7/10—Revision 0: Initial Version
Rev. A | Page 2 of 20
ADG5436
SPECIFICATIONS
15 V DUAL SUPPLY
VDD = +15 V 10%, VSS = −15 V 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
25°C
−40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VDD to VSS
16
V
9.8
11
0.35
Ω typ
Ω max
Ω typ
VS = 10 V, IS = −10 mA; see Figure 25
VDD = +13.5 V, VSS = −13.5 V
VS = 10 V , IS = −10 mA
14
On-Resistance Match
Between Channels, ∆RON
0.7
1.2
1.6
0.9
2
1.1
2.2
Ω max
Ω typ
Ω max
On-Resistance Flatness, RFLAT (ON)
VS = 10 V, IS = −10 mA
LEAKAGE CURRENTS
VDD = +16.5 V, VSS = −16.5 V
0.05
0.25
0.1
Source Off Leakage, IS (Off)
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 10 V, VD = 10 V; see Figure 28
0.75
3.5
12
12
Drain Off Leakage, ID (Off)
Channel On Leakage, ID (On), IS (On)
DIGITAL INPUTS
VS = 10 V, VD = 10 V; see Figure 28
0.4
2
2
0.1
VS = VD = 10 V; see Figure 24
0.4
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
µA typ
µA max
pF typ
0.002
5
VIN = VGND or VDD
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
170
235
173
230
124
160
55
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 31
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; see Figure 32
285
280
193
316
351
218
18
tON
tOFF
Break-Before-Make Time Delay, tD
Charge Injection, QINJ
200
VS = 0 V, RS = 0 Ω, CL = 1 nF;
see Figure 34
Off Isolation
−78
−58
0.009
dB typ
dB typ
% typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 26
RL = 1 kΩ, 15 V p-p, f = 20 Hz to 20 kHz;
see Figure 29
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
−3 dB Bandwidth
Insertion Loss
102
−0.7
MHz typ
dB typ
RL = 50 Ω, CL = 5 pF; see Figure 30
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 30
CS (Off)
CD (Off)
CD (On), CS (On)
18
62
83
pF typ
pF typ
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
Rev. A | Page 3 of 20
ADG5436
Parameter
25°C
−40°C to +85°C −40°C to +125°C Unit
µA typ
Test Conditions/Comments
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
POWER REQUIREMENTS
IDD
45
55
70
µA max
µA typ
µA max
0.001
ISS
Digital inputs = 0 V or VDD
1
VDD/VSS
9/ 22
V min/V max GND = 0 V
1 Guaranteed by design; not subject to production test.
20 V DUAL SUPPLY
VDD = +20 V 10%, VSS = −20 V 10%, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
25°C −40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VDD to VSS
15
V
9
Ω typ
Ω max
Ω typ
VS = 15 V, IS = −10 mA; see Figure 25
VDD = +18 V, VSS = −18 V
VS = 15 V , IS = −10 mA
10
0.35
13
On-Resistance Match
Between Channels, ∆RON
0.7
1.5
1.8
0.9
2.2
1.1
2.5
Ω max
Ω typ
Ω max
On-Resistance Flatness, RFLAT (ON)
VS = 15 V, IS = −10 mA
VDD = +22 V, VSS = −22 V
LEAKAGE CURRENTS
0.05
Source Off Leakage, IS (Off)
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 15 V, VD = 15 V; see Figure 28
0.25
0.1
0.4
0.1
0.4
0.75
3.5
12
12
Drain Off Leakage, ID (Off)
VS = 15 V, VD = 15 V; see Figure 28
2
2
Channel On Leakage, ID (On), IS (On)
VS = VD = 15 V; see Figure 24
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
µA typ
µA max
pF typ
0.002
5
VIN = VGND or VDD
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
158
217
164
213
110
152
50
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 31
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; see Figure 32
VS = 0 V, RS = 0 Ω, CL = 1 nF; see
Figure 34
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 27
260
256
173
293
287
194
15
tON
tOFF
Break-Before-Make Time Delay, tD
Charge Injection, QINJ
Off Isolation
250
−78
−58
0.007
100
dB typ
dB typ
% typ
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
−3 dB Bandwidth
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 26
RL = 1 kΩ, 20 V p-p, f = 20 Hz to 20 kHz;
see Figure 29
MHz typ
RL = 50 Ω, CL = 5 pF; see Figure 30
Rev. A | Page 4 of 20
ADG5436
Parameter
25°C −40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
Insertion Loss
−0.6
dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 30
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
IDD
18
63
82
pF typ
pF typ
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = +22 V, VSS = −22 V
Digital inputs = 0 V or VDD
50
μA typ
μA max
μA typ
μA max
70
110
0.001
ISS
Digital inputs = 0 V or VDD
1
VDD/VSS
±±/±22
V min/V max GND = 0 V
1 Guaranteed by design; not subject to production test.
12 V SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
25°C −40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
0 V to VDD
31
V
1±
Ω typ
VS = 0 V to 10 V, IS = −10 mA; see
Figure 25
VDD = 10.8 V, VSS = 0 V
22
27
Ω max
Ω typ
0.4
On-Resistance Match
VS = 0 V to 10 V, IS = −10 mA
Between Channels, ∆RON
0.8
4.4
5.5
1
1.2
7.5
Ω max
Ω typ
Ω max
On-Resistance Flatness, RFLAT (ON)
VS = 0 V to 10 V, IS = −10 mA
VDD = 13.2 V, VSS = 0 V
6.5
LEAKAGE CURRENTS
±0.05
Source Off Leakage, IS (Off)
nA typ
VS = 1 V/10 V, VD = 10 V/1 V;
see Figure 28
±0.25 ±0.75
±0.1
±3.5
nA max
nA typ
Drain Off Leakage, ID (Off)
VS = 1 V/10 V, VD = 10 V/1 V;
see Figure 28
±0.4
±0.1
±0.4
±2
±2
±12
±12
nA max
nA typ
nA max
Channel On Leakage, ID (On), IS (On)
VS = VD = 1 V/10 V; see Figure 24
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
μA typ
μA max
pF typ
0.002
5
VIN = VGND or VDD
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
250
346
250
358
135
178
125
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 31
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V; see Figure 32
437
445
212
501
512
237
50
tON
tOFF
Break-Before-Make Time Delay, tD
Charge Injection, QINJ
80
VS = 6 V, RS = 0 Ω, CL = 1 nF; see
Figure 34
Rev. A | Page 5 of 20
ADG5436
Parameter
25°C −40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
Off Isolation
−78
dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 27
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
−58
dB typ
% typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 26
RL = 1 kΩ, 6 V p-p, f = 20 Hz to 20 kHz;
see Figure 2±
0.075
−3 dB Bandwidth
Insertion Loss
106
−1.3
MHz typ
dB typ
RL = 50 Ω, CL = 5 pF; see Figure 30
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 30
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
IDD
22
67
85
pF typ
pF typ
pF typ
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VDD = 13.2 V
40
50
μA typ
μA max
Digital inputs = 0 V or VDD
65
VDD
±/40
V min/V max GND = 0 V, VSS = 0 V
1 Guaranteed by design; not subject to production test.
36 V SINGLE SUPPLY
VDD = 36 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 4.
Parameter
25°C −40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
0 V to VDD
17
V
10.6
Ω typ
VS = 0 V to 30 V, IS = −10 mA;
see Figure 25
VDD = 32.4 V, VSS = 0 V
12
15
Ω max
Ω typ
0.35
On-Resistance Match
VS = 0 V to 30 V, IS = −10 mA
Between Channels, ∆RON
0.7
2.7
3.2
0.±
3.8
1.1
4.5
Ω max
Ω typ
Ω max
On-Resistance Flatness, RFLAT(ON)
VS = 0 V to 30 V, IS = −10 mA
VDD = 3±.6 V, VSS = 0 V
LEAKAGE CURRENTS
±0.05
Source Off Leakage, IS (Off)
nA typ
VS = 1 V/30 V, VD = 30 V/1 V;
see Figure 28
±0.25 ±0.75
±0.1
±3.5
nA max
nA typ
Drain Off Leakage, ID (Off)
VS = 1 V/30 V, VD = 30 V/1 V;
see Figure 28
±0.4
±0.1
±0.4
±2
±2
±12
±12
nA max
nA typ
nA max
Channel On Leakage, ID (On), IS (On)
VS = VD = 1 V/30 V; see Figure 24
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
μA typ
μA max
pF typ
0.002
5
VIN = VGND or VDD
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
174
246
180
247
ns typ
ns max
ns typ
ns max
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 31
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 33
270
270
303
301
tON
Rev. A | Page 6 of 20
ADG5436
Parameter
25°C −40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
tOFF
127
179
55
ns typ
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 18 V; see Figure 32
VS = 18 V, RS = 0 Ω, CL = 1 nF;
see Figure 34
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 26
RL = 1 kΩ, 18 V p-p, f = 20 Hz to
20 kHz; see Figure 29
193
215
18
ns max
ns typ
ns min
pC typ
Break-Before-Make Time Delay, tD
Charge Injection, QINJ
250
−78
−58
0.03
Off Isolation
dB typ
dB typ
% typ
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
−3 dB Bandwidth
Insertion Loss
98
−0.8
MHz typ
dB typ
RL = 50 Ω, CL = 5 pF; see Figure 30
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 30
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
IDD
19
40
78
pF typ
pF typ
pF typ
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VDD = 39.6 V
80
µA typ
Digital inputs = 0 V or VDD
100
130
µA max
VDD
9/40
V min/V max GND = 0 V, VSS = 0 V
1 Guaranteed by design; not subject to production test.
CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx
Table 5.
Parameter
25°C
85°C
125°C
Unit
CONTINUOUS CURRENT, Sx OR Dx
VDD = +15 V, VSS = −15 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = +20 V, VSS = −20 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = 12 V, VSS = 0 V
122
217
77
116
44
53
mA maximum
mA maximum
130
229
80
121
45
54
mA maximum
mA maximum
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = 36 V, VSS = 0 V
84
150
56
90
36
48
mA maximum
mA maximum
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
110
196
70
109
42
52
mA maximum
mA maximum
Rev. A | Page 7 of 20
ADG5436
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
VDD to VSS
48 V
−0.3 V to +48 V
+0.3 V to −48 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
375 mA (pulsed at 1 ms,
VDD to GND
VSS to GND
Analog Inputs1
Digital Inputs1
Only one absolute maximum rating can be applied at any
one time.
Peak Current, Sx or Dx Pins
10% duty cycle maximum)
ESD CAUTION
Continuous Current, Sx or Dx2 Data + 15%
Temperature Range
Operating
−40°C to +125°C
Storage
Junction Temperature
Thermal Impedance, θJA
−65°C to +150°C
150°C
16-Lead TSSOP (4-Layer
Board)
112°C/W
16-Lead LFCSP
30.4°C/W
Reflow Soldering Peak
Temperature, Pb Free
260(+0/−5)°C
1 Overvoltages at the INx, Sx, and Dx pins are clamped by internal diodes.
Current should be limited to the maximum ratings given.
2 See Table 5.
Rev. A | Page 8 of 20
ADG5436
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
IN1
S1A
D1
1
2
3
4
5
6
7
8
16 NC
15 NC
14 NC
PIN 1
INDICATOR
ADG5436
12 EN
11 V
S1B
13
V
D1
1
2
3
4
DD
TOP VIEW
S1B
DD
V
12 S2B
11 D2
ADG5436
TOP VIEW
(Not to Scale)
SS
(Not to Scale)
V
10 S2B
9 D2
SS
GND
NC
GND
10 S2A
NC
9 IN2
NC = NO CONNECT
NOTES
1. EXPOSED PAD TIED TO SUBSTRATE, V
.
SS
2. NC = NO CONNECT.
Figure 3. TSSOP Pin Configuration
Figure 4. LFCSP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
LFCSP
TSSOP
Mnemonic
IN1
Function
1
2
3
4
5
6
15
16
1
2
3
Logic Control Input 1.
S1A
D1
S1B
VSS
GND
NC
Source Terminal 1A. This pin can be an input or output.
Drain Terminal 1. This pin can be an input or output.
Source Terminal 1B. This pin can be an input or output.
Most Negative Power Supply Potential.
Ground (0 V) Reference.
4
7, 8, 14 to 16 5, 7, 13, 14
No Connect.
9
6
IN2
Logic Control Input 2.
10
11
12
13
N/A
8
9
10
11
12
S2A
D2
S2B
VDD
Source Terminal 2A. This pin can be an input or output.
Drain Terminal 2. This pin can be an input or output.
Source Terminal 2B. This pin can be an input or output.
Most Positive Power Supply Potential.
Active High Digital Input. When this pin is low, the device is disabled and all switches are
off. When this pin is high, INx logic inputs determine the on switches.
EN
EP
Exposed Pad The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
TRUTH TABLE FOR SWITCHES
Table 8. ADG5436 TSSOP Truth Table
INx
SxA
Off
On
SxB
On
Off
0
1
Table 9. ADG5436 LFCSP Truth Table
EN
INx
SxA
Off
Off
On
SxB
Off
On
0
1
1
X
0
1
Off
Rev. A | Page 9 of 20
ADG5436
TYPICAL PERFORMANCE CHARACTERISTICS
16
12
10
8
T
= 25°C
V
V
= +10V
= –10V
T = 25°C
A
A
DD
SS
V
V
= +9V
= –9V
DD
SS
14
12
10
8
V
V
= 32.4V
= 0V
DD
SS
V
V
= 36V
= 0V
DD
SS
V
V
= +11V
= –11V
DD
SS
6
V
V
= 39.6V
= 0V
DD
SS
V
V
=
+13.5V
DD
SS
= –13.5V
V
V
= +16.5V
= –16.5V
DD
SS
V
V
= +15V
= –15V
6
DD
SS
4
4
2
2
0
0
–20
–15
–10
–5
0
V , V (V)
5
10
15
20
0
5
10
15
20
25
30
35
40
45
V , V (V)
S
D
S
D
Figure 8. On Resistance vs. VS, VD (Single Supply)
Figure 5. On Resistance vs. VS, VD (Dual Supply)
12
10
8
18
16
14
12
10
8
V
V
= +18V
= –18V
DD
SS
T
= +125°C
= +85°C
A
T
V
V
= +22V
= –22V
A
DD
SS
V
= +20V
= –20V
DD
SS
V
6
T
= +25°C
= –40°C
A
T
A
4
6
4
2
2
V
= +15V
= –15V
DD
SS
V
T
= 25°C
A
0
0
–15
–25 –20 –15 –10
–5
0
5
10
15
20
25
–10
–5
0
5
10
15
V , V (V)
V , V (V)
S D
S
D
Figure 6. On Resistance vs. VS, VD (Dual Supply) Included
Figure 9. On Resistance vs. VD or VS for Different Temperatures, ±15 V Dual Supply
16
14
12
25
20
15
10
5
T
= 25°C
A
V
V
= +10V
= 0V
DD
SS
V
V
= 10.8V
= 0V
DD
SS
V
V
= +9V
= 0V
DD
SS
T
= +125°C
= +85°C
A
10
8
T
A
T
= +25°C
= –40°C
A
V
V
= 11V
= 0V
DD
SS
V
V
= 12V
= 0V
6
T
DD
SS
A
V
V
= 13.2V
= 0V
DD
SS
4
2
V
V
= +20V
= –20V
DD
SS
0
–20
0
–15
–10
–5
0
5
10
15
20
0
2
4
6
8
10
12
14
V , V (V)
V , V (V)
S
D
S
D
Figure 10. On Resistance vs. VD or VS for Different Temperatures, ±±0 V Dual Supply
Figure 7. On Resistance vs. VS, VD (Single Supply)
Rev. A | Page 10 of 20
ADG5436
30
25
20
15
10
5
0.8
0.6
V
V
= 12V
= 0V
V
V
V
= +20V
= –20V
BIAS
DD
SS
DD
SS
= +15V/–15V
I
, I (ON) + +
D
S
I
(OFF) – +
D
T
= +125°C
0.4
A
I
(OFF) + –
S
T
= +85°C
A
0.2
T
= +25°C
= –40°C
A
0
T
A
I
, I (ON) – –
S
D
–0.2
–0.4
–0.6
I
(OFF) – +
S
I
(OFF) + –
D
0
0
2
4
6
8
10
12
0
25
50
75
100
125
V , V (V)
TEMPERATURE (°C)
S
D
Figure 11. On Resistance vs. VD or VS for Different Temperatures, 12 V Single Supply
Figure 14. Leakage Currents vs. Temperature, 2ꢀ V Single Supply
0.6
16
14
12
V
V
V
= 12V
= 0V
BIAS
DD
SS
I
, I (ON) + +
S
D
= 1V/10V
0.4
0.2
0
T
= +125°C
A
T
= +85°C
A
10
8
I
(OFF) – +
T
= +25°C
= –40°C
D
A
I
(OFF) + –
S
T
6
A
4
I
, I (ON) – –
S
2
D
I
(OFF) – +
75
S
I
(OFF) + –
50
D
V
V
= 36V
= 0V
DD
SS
–0.2
0
0
25
100
125
0
5
10
15
20
25
30
35
40
TEMPERATURE (°C)
V , V (V)
S
D
Figure 15. Leakage Currents vs. Temperature, 12 V Single Supply
Figure 12. On Resistance vs. VS (VD) for Different Temperatures, 36 V Single Supply
0.8
0.6
V
V
V
= 36V
= 0V
BIAS
V
V
V
= +15V
= –15V
BIAS
DD
SS
DD
SS
I
, I (ON) + +
S
D
I
, I (ON) + +
S
D
= 1V/30V
= +10V/–10V
0.6
0.4
0.4
0.2
I
(OFF) – +
D
I
(OFF) – +
D
I
(OFF) + –
S
I
(OFF) + –
S
0.2
0
0
–0.2
–0.4
–0.6
I
, I (ON) – –
S
D
–0.2
–0.4
–0.6
I
(OFF) + –
D
I
, I (ON) – –
S
D
I
(OFF) – +
I
(OFF) – +
S
S
I
(OFF) + –
100
D
0
25
50
75
125
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. Leakage Currents vs. Temperature, 36 V Single Supply
Figure 13. Leakage Currents vs. Temperature, 15 V Dual Supply
Rev. A | Page 11 of 20
ADG5436
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
T
V
V
= 25°C
= +15V
T
V
V
= 25°C
A
A
= +15V
= –15V
DD
DD
SS
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
= –15V
SS
NO DECOUPLING
CAPACITORS
DECOUPLING
CAPACITORS
1k
10k
100k
1M
10M
100M
1G
1G
40
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 17. Off Isolation vs. Frequency
Figure ±0. ACPSRR vs. Frequency
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
T
V
V
= 25°C
LOAD = 1kΩ
T = 25°C
A
A
= +15V
= –15V
DD
SS
V
= 12V, V = 0V, V = 6V p-p
SS
DD
S
V
= 36V, V = 0V, V = 18V p-p
SS
DD
S
V
V
= 15V, V = 15V, V = 15V p-p
SS
DD
S
= 20V, V = 20V, V = 20V p-p
SS
DD
S
10k
100k
1M
10M
100M
0
5k
10k
FREQUENCY (Hz)
15k
20k
FREQUENCY (Hz)
Figure 18. Crosstalk vs. Frequency
Figure ±1. THD + N vs. Frequency
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
450
400
350
300
250
200
150
100
50
T
V
V
= 25°C
= +15V
= –15V
A
T
= 25°C
A
DD
SS
V
V
= +20V
= –20V
DD
SS
V
V
= +36V
= 0V
DD
SS
V
V
= +15V
= –15V
DD
SS
V
V
= +12V
= 0V
DD
SS
0
–20
1k
10k
100k
1M
10M
100M
1G
–10
0
10
20
30
FREQUENCY (Hz)
V
(V)
S
Figure ±±. Bandwidth
Figure 19. Charge Injection vs. Source Voltage
Rev. A | Page 12 of 20
ADG5436
400
350
300
250
200
150
100
50
V
V
= 12V
= 0V
DD
SS
V
V
= 36V
= 0V
DD
SS
V
V
= +20V
= –20V
DD
SS
V
V
= +15V
= –15V
DD
SS
0
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure ±3. tTRANSITION Time vs. Temperature
Rev. A | Page 13 of 20
ADG5436
TEST CIRCUITS
I
(ON)
A
I
(OFF)
A
I
(OFF)
A
D
S
D
SxA/SxB
Dx
SxA/SxB
Dx
NC
V
V
D
V
D
S
NC = NO CONNECT
Figure 24. On Leakage
Figure 28. Off Leakage
V
V
DD
SS
0.1µF
0.1µF
AUDIO PRECISION
V
V
DD
SS
R
S
SxA/SxB
V
INx
V
S
V p-p
Dx
SxA/SxB
Dx
V
OUT
V
IN
R
L
1kΩ
I
DS
GND
V
S
Figure 25. On Resistance
Figure 29. THD + Noise
V
V
DD
SS
0.1µF
0.1µF
V
V
DD
SS
0.1µF
0.1µF
NETWORK
ANALYZER
V
V
NETWORK
ANALYZER
DD
SS
SxA
V
V
DD
V
SS
OUT
NC
R
50Ω
L
50Ω
SxA
SxB
SxB
50Ω
Dx
R
50Ω
INx
IN
L
V
S
Dx
INx
V
V
OUT
S
V
R
L
GND
50Ω
GND
V
OUT
V
WITH SWITCH
OUT
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
V
INSERTION LOSS = 20 log
S
V
WITHOUT SWITCH
OUT
Figure 30. Bandwidth
Figure 26. Channel-to-Channel Crosstalk
V
V
DD
SS
0.1µF
0.1µF
NETWORK
ANALYZER
V
V
DD
SS
NC
50Ω
SxA
SxB
50Ω
INx
V
S
Dx
V
OUT
V
IN
R
L
50Ω
GND
V
OUT
OFF ISOLATION = 20 log
V
S
Figure 27. Off Isolation
Rev. A | Page 14 of 20
ADG5436
V
V
DD
SS
0.1µF
0.1µF
V
V
IN
IN
50%
50%
50%
50%
V
V
SS
DD
SxB
SxA
V
Dx
S
V
OUT
R
300Ω
C
35pF
L
L
90%
90%
INx
V
OUT
GND
V
IN
tON
tOFF
Figure 31. Switching Times
V
DD
V
SS
0.1µF
0.1µF
V
IN
V
V
SS
DD
SxB
SxA
V
S
Dx
V
OUT
80%
V
R
C
OUT
L
L
35pF
300Ω
INx
tD
tD
GND
V
IN
Figure 32. Break-Before-Make Time Delay tD
V
V
V
V
DD
DD
SS
3V
SS
ENABLE
DRIVE (V
50%
50%
)
INx
SxA
V
IN
S
SxB
Dx
0V
tON (EN)
tOFF (EN)
OUTPUT
0.9V
0.9V
OUT
EN
OUT
OUTPUT
V
35pF
IN
50ꢀ
300ꢀ
GND
Figure 33. Enable Delay, tON (EN), tOFF (EN)
V
V
DD
SS
0.1µF
0.1µF
V
(NORMALLY
IN
CLOSED SWITCH)
V
V
SS
DD
ON
OFF
SxB
NC
V
Dx
V
S
V
(NORMALLY
IN
OPEN SWITCH)
OUT
SxA
C
INx
L
1nF
V
∆V
OUT
OUT
V
GND
IN
Q
= C × ∆V
L
OUT
INJ
Figure 34. Charge Injection
Rev. A | Page 15 of 20
ADG5436
TERMINOLOGY
IDD
CIN
I
DD represents the positive supply current.
C
IN is the digital input capacitance.
ISS
tON
I
SS represents the negative supply current.
tON represents the delay between applying the digital control
input and the output switching on.
VD, VS
VD and VS represent the analog voltage on Terminal D and
Terminal S, respectively.
tOFF
tOFF represents the delay between applying the digital control
input and the output switching off.
RON
RON represents the ohmic resistance between Terminal D and
tD
Terminal S.
tD represents the off time measured between the 80% point of
both switches when switching from one address state to
another.
∆RON
∆RON represents the difference between the RON of any two
channels.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off switch.
RFLAT (ON)
Flatness that is defined as the difference between the maximum
and minimum value of on resistance measured over the specified
Charge Injection
analog signal range is represented by RFLAT (ON)
.
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
IS (Off)
IS (Off) is the source leakage current with the switch off.
Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
ID (Off)
ID (Off) is the drain leakage current with the switch off.
ID (On), IS (On)
ID (On) and IS (On) represent the channel leakage currents with
the switch on.
Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
VINL
On Response
V
INL is the maximum input voltage for Logic 0.
VINH
INH is the minimum input voltage for Logic 1.
INL, IINH
INL and IINH represent the low and high input currents of the
On response is the frequency response of the on switch.
Insertion Loss
V
Insertion loss is the loss due to the on resistance of the switch.
I
I
Total Harmonic Distortion + Noise (THD + N)
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental is represented by THD + N.
digital inputs.
CD (Off)
AC Power Supply Rejection Ratio (ACPSRR)
CD (Off) represents the off switch drain capacitance, which is
measured with reference to ground.
ACPSRR is the ratio of the amplitude of signal on the output to the
amplitude of the modulation. This is a measure of the ability of
the part to avoid coupling noise and spurious signals that appear
on the supply voltage pin to the output of the switch. The dc voltage
on the device is modulated by a sine wave of 0.62 V p-p.
CS (Off)
CS (Off) represents the off switch source capacitance, which is
measured with reference to ground.
CD (On), CS (On)
CD (On) and CS (On) represent on switch capacitances, which
are measured with reference to ground.
Rev. A | Page 16 of 20
ADG5436
NMOS
PMOS
TRENCH ISOLATION
In the ADG5436, an insulating oxide layer (trench) is placed
between the NMOS and the PMOS transistors of each CMOS
switch. Parasitic junctions, which occur between the transistors
in junction isolated switches, are eliminated, and the result is a
completely latch-up proof switch.
P-WELL
N-WELL
In junction isolation, the N and P wells of the PMOS and
NMOS transistors form a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode can become forward-biased. A silicon controlled rectifier
(SCR) type circuit is formed by the two transistors causing a
significant amplification of the current that, in turn, leads to
latch-up. With trench isolation, this diode is removed, and the
result is a latch-up proof switch.
TRENCH
BURIED OXIDE LAYER
HANDLE WAFER
Figure 35. Trench Isolation
Rev. A | Page 17 of 20
ADG5436
APPLICATIONS INFORMATION
The ADG54xx family of switches and multiplexers provide a
robust solution for instrumentation, industrial, automotive,
aerospace and other harsh environments that are prone to latch-
up, which is an undesirable high current state that can lead to
device failure and persist until the power supply is turned off.
The ADG5436 high voltage switches allow single-supply
operation from 9 V to 40 V and dual supply operation from
9 V to 22 V. The ADG5436 (as well as other select devices
within this family) achieves an 8 kV human body model ESD
rating, which provides a robust solution eliminating the need
for separate protect circuitry designs in some applications.
Rev. A | Page 18 of 20
ADG5436
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 36. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
4.10
4.00 SQ
3.90
0.35
0.30
0.25
PIN 1
INDICATOR
PIN 1
INDICATOR
13
16
0.65
BSC
12
1
EXPOSED
PAD
2.70
2.60 SQ
2.50
4
9
8
5
0.45
0.40
0.35
0.20 MIN
TOP VIEW
BOTTOM VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
Figure 37. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-16-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
ADG5436BRUZ
ADG5436BRUZ-REEL7
ADG5436BCPZ-REEL7
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-17
RU-16
RU-16
1 Z = RoHS Compliant Part.
Rev. A | Page 19 of 20
ADG5436
NOTES
©2010–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09204-0-6/11(A)
Rev. A | Page 20 of 20
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