ADG608BRUZ-REEL7 [ADI]
LC2MOS ± 5V 8-Channel High Performance Analog Multiplexer;
| 型号： | ADG608BRUZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | LC2MOS ± 5V 8-Channel High Performance Analog Multiplexer 信息通信管理 光电二极管 |
| 文件： | 总12页 (文件大小：182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3 V/5 V, 4/8 Channel High
Performance Analog Multiplexers
a
ADG608/ADG609
FUNCTIO NAL BLO CK D IAGRAMS
FEATURES
+3 V, +5 V, ؎5 V Pow er Supplies
VSS to VDD Analog Signal Range
Low On Resistance (30 ⍀ m ax)
Fast Sw itching Tim es
tON 75 ns m ax
tOFF 45 ns m ax
Low Pow er Dissipation (1.5 W m ax)
Break-Before-Make Construction
ESD > 5000 V as per Military Standard 3015.7
TTL and CMOS Com patible Inputs
ADG608
ADG609
S1
S1A
S4A
DA
DB
D
S1B
S4B
S8
1 OF 4
DECODER
1 OF 8
DECODER
APPLICATIONS
Autom atic Test Equipm ent
Data Acquisition System s
A0 A1 A2 EN
A0
A1
EN
Com m unication System s
Avionics and Military System s
Microprocessor Controlled Analog System s
Medical Instrum entation
Battery Pow ered Instrum ents
Rem ote Pow ered Equipm ent
Com patible w ith ؎5 V DACs and ADCs such as
AD7840/ 8, AD7870/ 1/ 2/ 4/ 5/ 6/ 8
T he ability to operate from single +3 V, +5 V or ±5 V bipolar
supplies makes the ADG608 and ADG609 perfect for use in
battery operated instruments and with the new generation of
DACs and ADCs from Analog Devices. T he use of 5 V sup-
plies and reduced operating currents gives much lower power
dissipation than devices operating from ±15 V supplies.
GENERAL D ESCRIP TIO N
T he ADG608 and ADG609 are monolithic CMOS analog mul-
tiplexers comprising eight single channels and four differential
channels respectively, fully specified for ±5 V, +5 V and +3 V
power supplies. T he ADG608 switches one of eight inputs to a
common output as determined by the 3-bit binary address lines
A0, A1 and A2. T he ADG609 switches one of four differential
inputs to a common differential output as determined by the
2-bit binary address lines A0 and A1. An EN input on both de-
vices is used to enable or disable the device. When disabled, all
channels are switched OFF. All the address and enable inputs
are T T L compatible over the full specified operating tempera-
ture range, making the parts suitable for bus-controlled systems
such as data acquisition systems, process controls, avionics and
ATEs since the TTL compatible address inputs simplify the digital
interface design and reduce the board space requirements.
P RO D UCT H IGH LIGH TS
1. Extended Signal Range
T he ADG608/ADG609 are fabricated on an enhanced
LC2MOS process giving an increased signal range which
extends to the supplies.
2. Low Power Dissipation
3. Low RON
4. Fast Switching T imes
5. Break-Before-Make Switching
Switches are guaranteed break-before-make so that input
signals are protected against momentary shorting.
6. Single/Dual Supply Operation
T he ADG608/ADG609 are designed on an enhanced LC2MOS
process that provides low power dissipation yet gives high
switching speed and low on resistance. Each channel conducts
equally well in both directions when ON and has an input signal
range which extends to the supplies. In the OFF condition, sig-
nal levels up to the supplies are blocked. All channels exhibit
break-before-make switching action preventing momentary
shorting when switching channels. Inherent in the design is low
charge injection for minimum transients when switching the
digital inputs.
O RD ERING GUID E
Model
Tem perature Range P ackage O ption*
ADG608BN
ADG608BR
ADG608BRU
ADG608T RU
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
N-16
R-16A
RU-16
RU-16
ADG609BN
ADG609BR
ADG609BRU
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
N-16
R-16A
RU-16
*N = Plastic DIP; RU = T hin Shrink Small Outline Package (T SSOP);
R = 0.15" Small Outline IC (SOIC).
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700 Fax: 617/ 326-8703
ADG608/ADG609–SPECIFICATIONS
1
(V = +5 V ؎ 10%, V = –5 V ؎ 10%, GND = 0 V, unless otherwise noted)
DUAL SUPPLY
P aram eter
DD
SS
B Version
T Version
+25؇C –55؇C to
+125؇C
+25؇C
–40°C to
Test Conditions/
Com m ents
+85؇C
Units
ANALOG SWIT CH
Analog Signal Range
RON
VSS to VDD
VSS to VDD
V
22
30
22
30
Ω typ
Ω max
–3.5 V < VS < +3.5 V, IS = –1 mA;
VDD = +4.5 V, VSS = –4.5 V;
T est Circuit 1
–3 V < VS < +3 V, IDS = –1 mA;
VDD = +5 V, VSS = –5 V
VS = 0 V, IDS = –1 mA;
35
6
40
6
∆RON
5
2
5
Ω max
Ω max
RON Match
3
2
3
VDD = +5 V, VSS = –5 V
LEAKAGE CURRENT S
Source OFF Leakage IS (OFF)
VDD = +5.5 V, VSS = –5.5 V
VD = ±4.5 V, VS = ϯ4.5 V;
T est Circuit 2
VD = ±4.5 V, VS = ϯ4.5 V;
T est Circuit 3
±0.05
±0.5
±0.05
±0.5
±0.5
±0.05
±0.5
±0.05
±0.5
±0.05
±0.5
±0.5
±0.05
±0.5
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
±2
±10
Drain OFF Leakage ID (OFF)
ADG608
ADG609
Channel ON Leakage ID, IS (ON)
ADG608
ADG609
±2
±1
±10
±5
VS = VD = ±4.5 V;
T est Circuit 4
±3
±1.5
±20
±10
±0.5
±0.5
DIGIT AL INPUT S
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
2.4
0.8
V min
V max
IINL or IINH
±1
±1
µA max
VIN = 0 or VDD
CIN, Digital Input Capacitance
5
5
pF typ
DYNAMIC CHARACT ERIST ICS2
tT RANSIT ION
50
75
50
75
ns typ
ns max
RL = 300 Ω, CL = 35 pF;
VS1 = ±3.5 V, VS8 = ϯ3.5 V;
T est Circuit 5
90
100
tOPEN
10
10
ns min
RL = 300 Ω, CL = 35 pF;
VS = +3.5 V; T est Circuit 6
RL = 300 Ω, CL = 35 pF;
VS = +3.5 V; T est Circuit 7
RL = 300 Ω, CL = 35 pF;
VS = +3.5 V; T est Circuit 7
VS = 0 V, RS = 0 Ω, CL = 1 nF;
T est Circuit 8
RL = 1 kΩ, CL = 15 pF, f = 100 kHz;
VS = 3 V rms; T est Circuit 9
RL = 1 kΩ, CL = 15 pF, f = 100 kHz;
T est Circuit 10
tON (EN)
50
75
30
45
6
50
75
30
45
6
ns typ
ns max
ns typ
ns max
pC typ
90
60
100
75
tOFF (EN)
Charge Injection
OFF Isolation
Channel-to-Channel Crosstalk
85
85
9
85
85
9
dB typ
dB typ
pF typ
CS (OFF)
CD (OFF)
ADG608
ADG609
CD (ON)
ADG608
ADG609
40
20
40
20
pF typ
pF typ
54
34
54
34
pF typ
pF typ
POWER REQUIREMENT S
IDD
0.05
0.2
0.01
0.2
2
0.1
0.05
0.2
0.01
0.2
2
0.1
µA typ
µA max
µA typ
VIN = 0 V or VDD
ISS
0.1
1
0.1
1
µA max
NOT ES
1T emperature ranges are as follows: B Version: –40°C to +85°C; T Version: –55°C to +125°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. A
ADG608/ADG609
1
(V = +5 V
؎ 10%, V = 0 V, GND = 0 V, unless otherwise noted)
SINGLE SUPPLY
P aram eter
DD
SS
B Version
T Version
+25؇C –55؇C to
+125؇C
+25؇C
–40؇C to
Test Conditions/
+85؇C
Units
Com m ents
ANALOG SWIT CH
Analog Signal Range
RON
0 to VDD
0 to VDD
V
40
50
40
50
Ω typ
Ω max
VS = +3.5 V, IS = –1 mA;
VDD = +4.5 V;
T est Circuit 1
+1 V < VS < +3 V, IDS = –1 mA;
VDD = +5 V
VS = 0 V, IDS = –1 mA;
VDD = +5 V
60
6
70
6
∆RON
5
2
5
Ω max
Ω max
RON Match
3
2
3
LEAKAGE CURRENT S
VDD = +5.5 V
Source OFF Leakage IS (OFF)
±0.05
±0.5
±0.05
±0.5
±0.5
±0.05
±0.5
±0.05
±0.5
±0.05
±0.5
±0.5
±0.05
±0.5
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
VD = 4.5 V/0.1 V, VS = 0.1 V/4.5 V;
T est Circuit 2
VD = 4.5 V/0.1 V, VS = 0.1 V/4.5 V;
T est Circuit 3
±2
±10
Drain OFF Leakage ID (OFF)
ADG608
ADG609
Channel ON Leakage ID, IS (ON)
ADG608
ADG609
±2
±1
±10
±5
VS = VD = 4.5 V/0.1 V;
T est Circuit 4
±3
±1.5
±20
±10
±0.5
±0.5
DIGIT AL INPUT S
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
2.4
0.8
V min
V max
IINL or IINH
±1
±1
µA max
VIN = 0 or VDD
CIN, Digital Input Capacitance
5
5
pF typ
DYNAMIC CHARACT ERIST ICS2
tT RANSIT ION
80
100
80
100
ns typ
ns max
RL = 300 Ω, CL = 35 pF;
VS1 = 3.5 V/0 V, VS8 = 0 V/3.5 V;
T est Circuit 5
130
150
tOPEN
10
10
ns min
RL = 300 Ω, CL = 35 pF;
VS = +3.5 V; T est Circuit 6
RL = 300 Ω, CL = 35 pF;
VS = +3.5 V; T est Circuit 7
RL = 300 Ω, CL = 35 pF;
VS = +3.5 V; T est Circuit 7
VS = 0 V, RS = 0 Ω, CL = 1 nF;
T est Circuit 8
RL = 1 kΩ, CL = 15 pF, f = 100 kHz;
VS = 1.5 V rms; T est Circuit 9
RL = 1 kΩ, CL = 15 pF, f = 100 kHz;
T est Circuit 10
tON (EN)
80
100
40
50
0.5
3
80
100
40
50
0.5
3
ns typ
ns max
ns typ
ns max
pC typ
pC max
dB typ
130
60
150
75
tOFF (EN)
Charge Injection
OFF Isolation
Channel-to-Channel Crosstalk
85
85
85
9
85
9
dB typ
pF typ
CS (OFF)
CD (OFF)
ADG608
ADG609
CD (ON)
ADG608
ADG609
40
20
40
20
pF typ
pF typ
54
34
54
34
pF typ
pF typ
POWER REQUIREMENT S
IDD
0.05
0.2
0.2
2
0.05
0.2
0.2
2
µA typ
µA max
VIN = 0 V or VDD
NOT ES
1T emperature ranges are as follows: B Version: –40°C to +85°C; T Version: –55°C to +125°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. A
–3–
ADG608/ADG609–SPECIFICATIONS
1
(V = +3.3 V ؎ 10%, V = 0 V, GND = 0 V, unless otherwise noted)
DD
SS
SINGLE SUPPLY
P aram eter
B Version
T Version
+25؇C –55؇C to
+125؇C
+25؇C
–40؇C to
+85؇C
Test Conditions/
Com m ents
Units
ANALOG SWIT CH
Analog Signal Range
RON
0 to VDD
0 to VDD
V
60
90
3
60
90
3
Ω typ
Ω max
Ω max
VS = +1.5 V, IS = –1 mA;
VDD = +3 V; T est Circuit 1
VS = 0 V, IDS = –1 mA, VDD = +3.3 V
100
3
120
3
RON Match
LEAKAGE CURRENT S
VDD = +3.6 V
Source OFF Leakage IS (OFF)
±0.05
±0.5
±0.05
±0.5
±0.5
±0.05
±0.5
±0.05
±0.5
±0.05
±0.5
±0.5
±0.05
±0.5
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
VD = 2.6 V/0.1 V, VS = 0.1 V/2.6 V;
T est Circuit 2
VD = 2.6 V/0.1 V, VS = 0.1 V/2.6 V;
T est Circuit 3
±2
±10
Drain OFF Leakage ID (OFF)
ADG608
ADG609
Channel ON Leakage ID, IS (ON)
ADG608
ADG609
±2
±1
±10
±5
VS = VD = 2.6 V/0.1 V;
T est Circuit 4
±3
±1.5
±20
±10
±0.5
±0.5
DIGIT AL INPUT S
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
2.4
0.8
V min
V max
IINL or IINH
±1
±1
µA max
VIN = 0 or VDD
CIN, Digital Input Capacitance
5
5
pF typ
DYNAMIC CHARACT ERIST ICS2
tT RANSIT ION
120
170
120
170
ns typ
ns max
RL = 300 Ω, CL = 35 pF;
VS1 = 1.5 V/0 V, VS8 = 0 V/1.5 V;
T est Circuit 5
225
250
tOPEN
10
10
ns min
RL = 300 Ω, CL = 35 pF;
VS = +1.5 V; T est Circuit 6
RL = 300 Ω, CL = 35 pF;
VS = +1.5 V; T est Circuit 7
RL = 300 Ω, CL = 35 pF;
VS = +1.5 V; T est Circuit 7
VS = 0 V, RS = 0 Ω, CL = 1 nF;
T est Circuit 8
RL = 1 kΩ, CL = 15 pF, f = 100 kHz;
VS = 1 V rms; T est Circuit 9
RL = 1 kΩ, CL = 15 pF, f = 100 kHz;
T est Circuit 10
tON (EN)
120
170
40
60
0.5
3
120
170
40
60
0.5
3
ns typ
ns max
ns typ
ns max
pC typ
pC max
dB typ
225
75
250
90
tOFF (EN)
Charge Injection
OFF Isolation
Channel-to-Channel Crosstalk
85
85
85
9
85
9
dB typ
pF typ
CS (OFF)
CD (OFF)
ADG608
ADG609
CD (ON)
ADG608
ADG609
40
20
40
20
pF typ
pF typ
54
34
54
34
pF typ
pF typ
POWER REQUIREMENT S
IDD
0.05
0.2
0.2
2
0.05
0.2
0.2
2
µA typ
µA max
VIN = 0 V or VDD
NOT ES
1T emperature ranges are as follows: B Version: –40°C to +85°C; T Version: –55°C to +125°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–4–
REV. A
ADG608/ADG609
ABSO LUTE MAXIMUM RATINGS 1
SOIC Package
θJA, T hermal Impedance . . . . . . . . . . . . . . . . . . . . . . 77°C/W
Lead T emperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
T SSOP Package
θJA, T hermal Impedance . . . . . . . . . . . . . . . . . . . . . 158°C/W
Lead T emperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
(T A = +25°C unless otherwise noted)
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6.5 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6.5 V
Analog, Digital Inputs2 . . . . . . . . . . . . . . –0.3 V to VDD + 2 V
or 20 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . 20 mA
Peak Current, S or D
(Pulsed at 1 ms, 10% Duty Cycle Max) . . . . . . . . . . 40 mA
Operating T emperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . –55°C to +125°C
Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C
Junction T emperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic DIP Package
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >5000 V
NOT ES
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Only one absolute maximum rating may be applied at any one time.
2Overvoltages at A, S, D or EN will be clamped by internal diodes. Current should
be limited to the maximum ratings given.
θ
JA, T hermal Impedance . . . . . . . . . . . . . . . . . . . . 117°C/W
Lead T emperature, Soldering (10 sec) . . . . . . . . . . +260°C
Table I. AD G608 Truth Table
Table II. AD G609 Truth Table
A2
A1
A0
EN
ON SWITCH
A1
A0
EN
O N SWITCH P AIR
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
NONE
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
NONE
1
2
3
4
5
6
7
8
1
2
3
4
X = Don’t Care
X = Don’t Care
P IN CO NFIGURATIO NS
D IP /SO IC/TSSO P
D IP /SO IC/TSSO P
1
2
16
15
14
A1
A0
EN
1
2
16
15
14
13
12
11
A1
A0
EN
GND
A2
V
V
3
4
5
6
7
8
DD
SS
GND
V
3
4
5
6
7
8
SS
ADG609
TOP VIEW
(Not to Scale)
S1A
13 S1B
ADG608
TOP VIEW
(Not to Scale)
S1
S2
S3
V
DD
12
11
S2B
S3B
S2A
S3A
S4A
DA
S5
S6
10 S4B
DB
10 S7
S8
S4
D
9
9
REV. A
–5–
ADG608/ADG609–Typical Performance Characteristics
100
90
80
70
60
50
40
30
20
10
0
50
45
40
35
30
25
20
15
10
5
o
o
T = +25 C
A
T
= +25 C
A
V
V
= +3V
= 0V
DD
V
= +3V
= –3V
SS
DD
V
SS
V
= +5V
= –5V
DD
V
= +5V
= 0V
DD
V
SS
V
SS
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0 4.5
5.0
–5.0 –4.0 –3.0 –2.0 –1.0 0.0
1.0
2.0
3.0
4.0
5.0
V
D
(V ) – Volts
V
(V ) – Volts
S
D
S
Figure 4. RON as a Function of VD (VS): Single Supply Voltage
Figure 1. RON as a Function of VD (VS): Dual Supply Voltage
100
50
V
V
= +5V
= 0V
V
= +5V
= –5V
DD
DD
90
80
70
60
50
40
30
20
10
0
45
40
35
30
25
20
15
10
5
V
SS
SS
o
+125 C
o
+125 C
o
+85 C
o
+85 C
o
+25 C
o
+25 C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
–5.0 –4.0 –3.0 –2.0 –1.0 0.0
1.0
2.0
3.0 4.0
5.0
V
D
(V ) – Volts
V
(V ) – Volts
S
D
S
Figure 2. RON as a Function of VD (VS) for Different
Tem peratures
Figure 5. RON as a Function of VD (VS) for Different
Tem peratures
100
0.03
o
+125 C
V
V
= +5V
V
V
= +3V
= 0V
DD
DD
90
80
70
60
50
40
30
20
10
0
= –5V
o
o
SS
SS
+85 C
0.02
0.01
T
= +25 C
A
I
(OFF)
o
D
+25 C
I
(OFF)
S
0.00
I
(ON)
D
–0.01
–0.02
–0.03
0.0
0.5
1.0
1.5
2.0
2.5
3.0
–5
–4
–3
–2
–1
V
0
1
2
3
4
5
V
(V ) – Volts
S
, V – Volts
D
S
D
Figure 3. RON as a Function of VD (VS) for Different
Tem peratures
Figure 6. Leakage Currents as a Function of VD (VS)
–6–
REV. A
ADG608/ADG609
0.02
0.01
0.02
0.01
V
V
= +5V
V
V
= +3V
DD
DD
I
(OFF)
D
= 0V
o
= 0V
o
SS
SS
T
= +25 C
I
(OFF)
(ON)
T
= +25 C
A
D
A
I
(ON)
D
I
D
I
(OFF)
I
(OFF)
S
S
0.00
0.00
–0.01
–0.01
0
1
2
3
4
5
0
0.5
1.0
1.5
2.0
2.5
3.0
V
,V – Volts
D
V
, V – Volts
S
S D
Figure 10. Leakage Currents as a Function of VD (VS)
Figure 7. Leakage Currents as a Function of VD (VS)
4
4
10
10
V
V
= +5V
= –5V
V
V
= +5V
= –5V
DD
DD
SS
SS
3
2
1
0
10
10
10
10
3
2
1
0
10
10
10
10
EN = 2.4V
EN = 2.4V
EN = 0V
EN = 0V
–1
10
10
–2
–1
10
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 8. Positive Supply Current vs. Switching Frequency
Figure 11. Negative Supply Current vs. Switching Frequency
120
30
C
= 1nF
L
V
V
= +5V
= –5V
DD
110
100
90
SS
20
10
V
V
= +5V
= 0V
DD
SS
80
V
V
= +5V
= –5V
DD
SS
70
0
V
V
= +3V
= 0V
DD
SS
60
–10
–5
50
100
1k
10k
100k
1M
–4
–3
–2
–1
0
1
2
3
4
5
FREQUENCY – Hz
SOURCE VOLTAGE – V
Figure 9. Charge Injection vs. Analog Voltage VS
Figure 12. Crosstalk and Off Isolation vs. Frequency
REV. A
–7–
ADG608/ADG609
Test Circuits
I
DS
V1
V
DD
V
SS
V
V
DD
SS
S1
S2
S8
I
(OFF)
A
D
D
D
S
V
D
+0.8V
V
S
EN
GND
V
S
R
ON
= V /I
1 DS
Test Circuit 1. On Resistance
Test Circuit 3. ID (OFF)
V
V
V
DD
SS
V
V
V
DD
SS
V
SS
DD
V
SS
DD
I
(OFF)
A
S
I
(ON)
A
D
S1
S2
S8
D
S1
S8
D
V
S
V
D
+2.4V
+0.8V
EN
V
S
EN
GND
GND
V
D
Test Circuit 2. IS (OFF)
Test Circuit 4. ID (ON)
V
V
V
V
SS
DD
3V
ADDRESS
DRIVE (V
SS
DD
50%
50%
)
IN
A2
V
S1
S1
S2 THRU S7
A1
A0
V
IN
50Ω
0V
ADG608*
V
S8
S8
D
90%
V
OUT
+2.4V
EN
C
35pF
R
L
300Ω
L
V
OUT
GND
90%
tTRANSITION
tTRANSITION
* SIMILAR CONNECTION FOR ADG609
Test Circuit 5. Switching Tim e of Multiplexer, tTRANSITION
–8–
REV. A
ADG608/ADG609
V
V
V
V
SS
DD
3V
ADDRESS
DRIVE (V
SS
DD
)
IN
A2
V
S
S1
S2 THRU S7
A1
A0
V
IN
50Ω
0V
ADG608
*
S8
D
V
OUT
+2.4V
EN
80%
80%
C
35pF
V
OUT
R
300Ω
L
L
GND
tOPEN
* SIMILAR CONNECTION FOR ADG609
Test Circuit 6. Break-Before-Make Delay, tOPEN
V
V
V
V
SS
DD
3V
ENABLE
SS
DD
50%
50%
DRIVE (V
)
IN
A2
S1
S2 THRU S8
V
S
A1
A0
0V
tOFF (EN)
ADG608
*
V
0
0.9V
0.9V
0
0
D
EN
V
OUT
C
35pF
R
300Ω
L
OUTPUT
0V
L
50Ω
V
IN
GND
tON (EN)
* SIMILAR CONNECTION FOR ADG609
Test Circuit 7. Enable Delay, tON (EN), tOFF (EN)
V
V
V
V
SS
DD
3V
SS
DD
LOGIC
A2
INPUT (V
)
IN
A1
A0
S
ADG608*
GND
0V
R
S
D
V
OUT
EN
C
1nF
L
V
S
V
OUT
∆ V
OUT
V
IN
Q
= C x ∆V
L OUT
INJ
* SIMILAR CONNECTION FOR ADG609
Test Circuit 8. Charge Injection
REV. A
–9–
ADG608/ADG609
V
V
V
V
DD
DD
DD
A2
A1
A0
DD
S1
S8
A2
A1
A0
EN
D
2.4V
ADG608
V
S
1kΩ
S1
ADG608
V
L
1kΩ
OUT
R
S2
S8
V
D
OUT
EN
GND
R
1kΩ
L
V
SS
GND
V
SS
V
S
V
SS
V
SS
Test Circuit 9. OFF Isolation
Test Circuit 10. Channel-to-Channel Crosstalk
TERMINO LO GY
VDD
t
OFF (EN)
Delay time between the 50% and 90% points
of the digital input and switch “OFF”
condition.
Most positive power supply potential.
VSS
Most negative power supply potential in dual
supplies. In single supply applications, it may
be connected to ground.
tT RANSIT ION
Delay time between the 50% and 90% points
of the digital inputs and the switch “ON”
condition when switching from one address
state to another.
GND
RON
Ground (0 V) reference.
Ohmic resistance between D and S.
tOPEN
“OFF” time measured between the 80%
points of both switches when switching from
one address state to another.
∆RON
RON variation due to a change in the analog
input voltage with a constant load current.
RON Match
Difference between the RON of any two
channels.
VINL
VINH
Maximum input voltage for logic “0.”
Minimum input voltage for logic “1.”
Input current of the digital input.
IS (OFF)
Source leakage current when the switch is off.
Drain leakage current when the switch is off.
IINL (IINH
Crosstalk
)
ID (OFF)
ID, IS (ON)
A measure of unwanted signal which is
coupled through from one channel to another
as a result of parasitic capacitance.
Channel leakage current when the switch is
on.
VD, VS
Analog voltage on terminals D, S.
Off Isolation
A measure of unwanted signal coupling
through an “OFF” channel.
CS (OFF)
Channel input capacitance for “OFF”
condition.
Charge Injection A measure of the glitch impulse transferred
from the digital input to the analog output
during switching.
C
D (OFF)
Channel output capacitance for “OFF”
condition.
IDD
ISS
Positive supply current.
Negative supply current.
CD, CS (ON)
CIN
“ON” switch capacitance.
Digital input capacitance.
tON (EN)
Delay time between the 50% and 90% points
of the digital input and switch “ON”
condition.
–10–
REV. A
ADG608/ADG609
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
16-P in P lastic (N-16)
16
1
9
0.280 (7.11)
0.240 (6.10)
PIN 1
8
0.325 (8.25)
0.300 (7.62)
0.840 (21.33)
0.745 (18.93)
0.060 (1.52)
0.015 (0.38)
0.195 (4.95)
0.115 (2.93)
0.210
(5.33)
0.150
(3.81)
0.200 (5.05)
0.125 (3.18)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
16-P in SO IC (R-16A)
0.3937 (10.00)
0.3859 (9.80)
16
1
9
8
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.0688 (1.75)
0.0532 (1.35)
0.0196 (0.50)
0.0099 (0.25)
x 45°
0.0098 (0.25)
0.0040 (0.10)
8°
0°
0.0192 (0.49)
0.0138 (0.35)
0.0500
(1.27)
BSC
SEATING
PLANE
0.0500 (1.27)
0.0160 (0.41)
0.0099 (0.25)
0.0075 (0.19)
16-P in TSSO P (RU-16)
0.201 (5.10)
0.193 (4.90)
16
9
1
8
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0433
(1.10)
MAX
0.028 (0.70)
0.020 (0.50)
8°
0°
0.0118 (0.30)
0.0075 (0.19)
0.0256
(0.65)
BSC
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
REV. A
–11–
–12–
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