ADM812ZART-REEL-7 [ADI]
IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO4, TO-253D, SOT-143, 4 PIN, Power Management Circuit;
| 型号： | ADM812ZART-REEL-7 |
| 厂家： | 
ADI |
| 描述： | IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO4, TO-253D, SOT-143, 4 PIN, Power Management Circuit 光电二极管 |
| 文件： | 总8页 (文件大小：130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Microprocessor Supervisory
Circuit in 4-Lead SOT-143
ADM811/ADM812
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Superior Upgrade for MAX811/MAX812
Specified over Temperature
Low Power Consumption (5 A Typ)
Precision Voltage Monitor: 2.5 V, 3 V, 3.3 V, 5 V Options
Reset Assertion Down to 1 V VCC
140 ms Min Power-On Reset
ADM811/ADM812
V
CC
RESET
GENERATOR
RESET/RESET
V
REF
Logic Low RESET Output (ADM811)
Logic High RESET Output (ADM812)
Built-In Manual Reset
MR
DEBOUNCE
GND
APPLICATIONS
Microprocessor Systems
Controllers
Intelligent Instruments
Automotive Systems
Safety Systems
Portable Instruments
GENERAL DESCRIPTION
The ADM811/ADM812 is a reliable voltage monitoring device
suitable for use in most voltage monitoring applications. The
ADM811/ADM812 is designed to monitor six different voltages,
each allowing for a 5% or 10% degradation of standard PSU
voltages before a reset occurs. These voltages have been selected
for the effective monitoring of 2.5 V, 3 V, 3.3 V, and 5 V supply
voltage levels.
V
V
CC
CC
ADM811
MICROPROCESSOR
SYSTEM
MR
RESET
RESET
100k⍀
GND
GND
Included in this circuit is a debounced manual reset input.
Reset can be activated using an electrical switch (or an input
from another digital device) or by a degradation of the supply
voltage. The manual reset function is very useful, especially if
the circuit in which the ADM811/ADM812 is operating enters
into a state that can only be detected by the user. Allowing the
user to reset a system manually can reduce the damage or
danger that could otherwise be caused by an out-of-control or
locked system.
Figure 1. Typical ADM811 Operating Circuit
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
(VCC = Full Operating Range; TA = TMIN to TMAX; VCC typ = 5 V for L/M,
3.3 V for T/S, 3 V for R, 2.5 V for Z Models; unless otherwise noted.)
ADM811/ADM812–SPECIFICATIONS
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SUPPLY
Voltage
1.0
1.2
5.5
V
V
µA
µA
TA = 0°C to 70°C
TA = –40°C to +85°C
Current
8
5
15
10
VCC < 5.5 V, ADM81_L/M, IOUT = 0 mA
VCC < 3.6 V, ADM81_R/S/T/Z, IOUT = 0 mA
RESET VOLTAGE THRESHOLD
ADM81_L
ADM81_L
ADM81_M
ADM81_M
ADM81_T
ADM81_T
ADM81_S
ADM81_S
ADM81_R
ADM81_R
ADM81_Z
ADM81_Z
4.54
4.50
4.30
4.25
3.03
3.00
2.88
2.85
2.58
2.55
2.28
2.25
4.63
4.38
3.08
2.93
2.63
2.32
4.72
4.75
4.46
4.50
3.14
3.15
2.98
3.00
2.68
2.70
2.35
2.38
V
V
V
V
V
V
V
V
V
V
V
V
TA = 25°C
TA = –40°C to +85°C
TA = 25°C
TA = –40°C to +85°C
TA = 25°C
TA = –40°C to +85°C
TA = 25°C
TA = –40°C to +85°C
TA = 25°C
TA = –40°C to +85°C
TA = 25°C
TA = –40°C to +85°C
RESET THRESHOLD
TEMPERATURE COEFFICIENT
30
ppm/°C
VCC TO RESET/RESET DELAY
40
20
µs
µs
VOD = 125 mV, ADM81_L/M
VOD = 125 mV, ADM81_R/S/T/Z
RESET ACTIVE TIMEOUT PERIOD
140
300
560
700
ms
ms
VCC = VTH(MAX)
(ADM811-3T Only)
MANUAL RESET
Minimum Pulsewidth
Glitch Immunity
RESET/RESET Propagation Delay
Pull-Up Resistance
10
µs
100
0.5
20
ns
µs
10
30
kΩ
The Manual Reset Circuit Will Act On:
An Input Rising Above
An Input Falling Below
An Input Rising Above
An Input Falling Below
2.3
V
V
V
V
VCC > VTH(MAX), ADM81_L/M
VCC > VTH(MAX), ADM81_L/M
VCC > VTH(MAX), ADM81_R/S/T/Z
VCC > VTH(MAX), ADM81_R/S/T/Z
0.8
0.7 ϫ VCC
0.25 ϫ VCC
RESET/RESET Output Voltage
Low (ADM812R/S/T/Z)
Low (ADM812L/M)
High (ADM812R/S/T/Z/L/M)
Low (ADM811R/S/T/Z)
Low (ADM811L/M)
Low (ADM811R/S/T/Z/L/M)
High (ADM811R/S/T/Z)
High (ADM811L/M)
0.3
0.4
V
V
V
V
V
V
V
V
VCC = VTH(MAX), ISINK = 1.2 mA
VCC = VTH(MAX), ISINK = 3.2 mA
1.8 V < VCC < VTH(MIN), ISOURCE = 150 µA
VCC = VTH(MIN), ISINK = 1.2 mA
0.8 ϫ VCC
0.3
0.4
0.3
VCC = VTH(MIN), ISINK = 3.2 mA
VCC > 1.0 V, ISINK = 50 µA
VCC > VTH(MAX), ISOURCE = 500 µA
VCC > VTH(MAX), ISOURCE = 800 µA
0.8 ϫ VCC
VCC – 1.5
Specifications subject to change without notice.
–2–
REV. C
ADM811/ADM812
ABSOLUTE MAXIMUM RATINGS*
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +160°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 kV
(Typical values are at TA = 25°C, unless otherwise noted.)
Terminal Voltage (With Respect to Ground)
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
All Other Inputs . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
Input Current
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
MR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Output Current
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods of time may affect device reliability.
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Power Dissipation (TA = 70°C)
RT-4, (SOT-143) . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mW
Derate by 4 mW/°C above 70°C
θ
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 330°C/W
ORDERING GUIDE
Reset
Threshold (V)
Temperature
Range
Branding
Information
Model*
Quantity (K)
ADM811LART-REEL
ADM811LART-REEL-7
ADM811MART-REEL
ADM811MART-REEL-7
ADM811TART-REEL
ADM811TART-REEL-7
ADM811-3TART-REEL
ADM811-3TART-REEL-7
ADM811SART-REEL
ADM811SART-REEL-7
ADM811RART-REEL
ADM811RART-REEL-7
ADM811ZART-REEL
ADM811ZART-REEL-7
ADM812LART-REEL
ADM812LART-REEL-7
ADM812MART-REEL
ADM812MART-REEL-7
ADM812TART-REEL
ADM812TART-REEL-7
ADM812SART-REEL
ADM812SART-REEL-7
ADM812RART-REEL
ADM812RART-REEL-7
ADM812ZART-REEL
ADM812ZART-REEL-7
4.63
4.63
4.38
4.38
3.08
3.08
3.08
3.08
2.93
2.93
2.63
2.63
2.32
2.32
4.63
4.63
4.38
4.38
3.08
3.08
2.93
2.93
2.63
2.63
2.32
2.32
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
MBV
MBV
MBT
MBT
MBG
MBG
MB3
MB3
MBE
MBE
MBB
MBB
MBZ
MBZ
MCV
MCV
MCT
MCT
MCG
MCG
MCE
MCE
MCB
MCB
MCZ
MCZ
10
3
10
3
10
3
10
3
10
3
10
3
10
3
10
3
10
3
10
3
10
3
10
3
10
3
*Only available in reels.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADM811/ADM812 feature proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. C
–3–
ADM811/ADM812
PIN CONFIGURATION
1
4
V
GND
CC
ADM811/
ADM812
TOP VIEW
(Not to Scale)
2
3
MR
RESET/RESET
PIN FUNCTION DESCRIPTIONS
Pin Mnemonic
Function
0 V. Ground reference for all signals.
1
2
GND
RESET (ADM811) Active Low Logic Output. RESET remains low while VCC is below the reset threshold or when MR is low;
RESET then remains low for at least 140 ms (at least 300 ms for the ADM811-3T) after VCC rises above
the reset threshold.
RESET (ADM812) Active High Logic Output. RESET remains high while VCC is below the reset threshold or when MR is low;
RESET then remains high for 240 ms (typical) after VCC rises above the reset threshold.
3
4
MR
Manual Reset. This active low debounced input will ignore input pulses of 100 ns or less (typical) and is
guaranteed to accept input pulses of greater than 10 µs. Leave floating when not used.
2.5 V, 3 V, 3.3 V, or 5 V Monitored Supply Voltage.
VCC
–4–
REV. C
Typical Performance Characteristics—ADM811/ADM812
10
12
9
I
@ V = 5.5V
CC
I
@ V = 5.5V
CC
DD
DD
10
8
8
7
6
5
4
3
2
I
@ V = 3V
CC
DD
I
@ V = 3V
CC
DD
6
4
I
@ V = 1V
CC
DD
2
0
I
@ V = 1V
DD CC
1
0
–40 –20
0
20
30
50
70
85
100 120
–40 –20
0
20
30
50
70
85
100 120
TEMPERATURE – ؇C
TEMPERATURE – ؇C
TPC 1. Supply Current vs. Temperature (ADM81_R/S/T/Z)
TPC 4. Supply Current vs. Temperature (ADM81_L/M)
900
800
700
600
500
1000
900
800
700
600
500
400
V
= 20mV
400
300
200
100
0
OD
V
= 20mV
OD
300
200
V
= 125mV
OD
V
= 125mV
20
OD
100
0
V
= 200mV
V
= 200mV
OD
OD
–40 –20
0
30
50
70
85
100 120
–40 –20
0
20
30
50
70
85
100 120
TEMPERATURE – ؇C
TEMPERATURE – ؇C
TPC 2. Power-Down RESET Delay vs. Temperature
TPC 5. Power-Down RESET Delay vs. Temperature
(ADM81_R/S/T/Z)
(ADM81_L/M)
1.007
1.006
1.005
1.004
1.003
1.002
1.001
1.000
0.999
0.998
0.997
0.996
0.995
289
284
ADM81_L/M
279
274
269
264
259
254
ADM81_R/S/T/Z
249
244
–40 –20
0
20
30
50
70
85
100 120
–40 –20
0
20
30
50
70
85
100 120
TEMPERATURE – ؇C
TEMPERATURE – ؇C
TPC 3. Power-Up Reset Timeout vs. Temperature
TPC 6. Reset Threshold Deviation vs. Temperature
REV. C
–5–
ADM811/ADM812
CIRCUIT INFORMATION
Glitch Immunity
Reset Thresholds
The ADM811/ADM812 contains internal filtering circuitry
providing glitch immunity from fast transient glitches on the
power supply line.
A reset output is provided to the microprocessor whenever the
VCC input is below the reset threshold. The actual reset thresh-
old is dependent on whether an L, M, T, S, R, or Z suffix is
used. Refer to Table I.
V
REF
V
V
V
REF
V
REF
REF
CC
Table I. Reset Threshold Options
Reset
RESET
t1
t1
t1 = RESET TIME = 240ms TYPICAL
= RESET VOLTAGE THRESHOLD
Model
Threshold (V)
V
REF
ADM811LART
ADM811MART
ADM811TART
ADM811-3TART
ADM811SART
ADM811RART
ADM811ZART
ADM812LART
ADM812MART
ADM812TART
ADM812SART
ADM812RART
ADM812ZART
4.63
4.38
3.08
3.08
2.93
2.63
2.32
4.63
4.38
3.08
2.93
2.63
2.32
Figure 2. Power Fail RESET Timing
INTERFACING TO OTHER DEVICES
Output
The ADM811/ADM812 is designed to integrate with as many
devices as possible. One feature of the ADM811/ADM812 is
the reset output, which is directly proportional to VCC (this is
guaranteed only while VCC is greater than 1 V). This enables the
part to be used with both 3 V and 5 V, or any nominal voltage
within the minimum and maximum specifications for VCC
.
BENEFITS OF A VERY ACCURATE RESET THRESHOLD
Because the ADM811/ADM812 can operate effectively even when
there are large degradations of the supply voltages, the possibility
of a malfunction during a power failure is greatly reduced. Another
advantage of the ADM811/ADM812 is its very accurate internal
voltage reference circuit. Combined, these benefits produce an
exceptionally reliable microprocessor supervisory circuit.
RESET OUTPUT
On power-up and after VCC rises above the reset threshold, an
internal timer holds the reset output active for 240 ms (typical).
This is intended as a power-on reset signal for the processor. It
allows time for both the power supply and the microprocessor to
stabilize after power-up. If a power supply brownout or inter-
ruption occurs, the reset output is similarly activated and remains
active for 240 ms (typical) after the supply recovers. This allows
time for the power supply and microprocessor to stabilize.
V
CC
V
CC
ADM811
The ADM811 provides an active low reset output (RESET)
RESET
while the ADM812 provides an active high output (RESET).
During power-down of the ADM811, the RESET output remains
valid (low) with VCC as low as 1 V. This ensures that the micro-
processor is held in a stable shutdown condition as the supply
falls and also ensures that no spurious activity can occur via
the microprocessor as it powers up.
GND
Figure 3. Ensuring a Valid RESET Output
Down to VCC = 0 V
MANUAL RESET
ENSURING A VALID RESET OUTPUT DOWN TO VCC = 0 V
When VCC falls below 0.8 V, the ADM811/ADM812’s RESET
no longer sinks current. Therefore, a high impedance CMOS
logic input connected to RESET may drift to undetermined
logic levels. To eliminate this problem, a 100 kΩ resistor should
be connected from RESET to ground.
The ADM811/ADM812 is equipped with a manual reset input.
This input is designed to operate in a noisy environment where
unwanted glitches could be induced. These glitches could be
produced by the bouncing action of a switch contact, or where a
manual reset switch may be located some distance away from
the circuit (the cabling of which may pick-up noise).
The manual reset input is guaranteed to ignore logically valid
inputs that are faster than 100 ns and to accept inputs longer in
duration than 10 µs.
–6–
REV. C
ADM811/ADM812
OUTLINE DIMENSIONS
4-Lead Small Outline Transistor Package [SOT-143]
(RT-4)
Dimensions shown in millimeters
1.92 BSC
4
3
2.64
2.10
1.40
1.20
1
2
PIN 1
0.20
BSC
3.04
2.80
1.22
0.80
0.15
0.05
8؇
0؇
0.20
0.08
0.45
0.30
0.60
0.40
0.89
0.76
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS TO-253D
REV. C
–7–
ADM811/ADM812
Revision History
Location
Page
2/03—Data Sheet changed from REV. B to REV. C.
Changes FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Removed Note 2 from ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Removed Note from Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1/03—Data Sheet changed from REV. A to REV. B.
Added ADM812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Changes SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Additions to Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Changes to Manual Reset section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5/02—Data Sheet changed from REV. 0 to REV. A.
Deletion of ADM812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
–8–
REV. C
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