ADP1051 [ADI]
Digital Controller for Isolated Power Supply with PMBus Interface; 数字控制器，用于隔离型电源使用PMBus接口
| 型号： | ADP1051 |
| 厂家： | 
ADI |
| 描述： | Digital Controller for Isolated Power Supply with PMBus Interface |
| 文件： | 总17页 (文件大小：785K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Digital Controller for Isolated Power
Supply with PMBus Interface
Preliminary Technical Data
ADP1051
FEATURES
GENERAL DESCRIPTION
The ADP1051 is an advanced digital controller with PMBusTM
interface targeting high density, high efficiency DCDC power
conversion. This controller implements voltage mode control with
high speed, input line feed-forward for enhanced transient and
improved noise performance. The ADP1051 has 6 programmable
PWM outputs capable of controlling most high efficiency power
supply topologies with added control of synchronous rectification.
The device includes adaptive dead-time compensation to improve
the efficiency over the load range and programmable light load
mode operation combined with low device power consumption to
reduce system standby power losses.
Versatile, digital voltage mode controller
High speed, input voltage feed-forward control
6 PWM logic outputs with 625ps resolution
Switching frequency 50 kHz to 625 kHz
Frequency synchronization master & slave
Multiple energy saving modes
Adaptive dead-time compensation for efficiency
optimization
Low device power consumption - typical 100 mW
Direct Parallel operation
•
•
•
•
Accurate droop current share
Pre-bias start-up
Reverse current protection
Conditional over-voltage protection
The ADP1051 implements several features to enable a robust
system of parallel and redundant operation for customers that
require high availability or parallel connection. The device includes
master/slave synchronization, reverse current protection and pre-
bias start-up, accurate current sharing between power supplies and
conditional overvoltage techniques to identify and safely shutdown
an erroneous power supply in parallel operation mode.
Extensive fault detection and protections
Ultra compact package design 4*4mm 24-pin LFCSP
PMBus Compliant
Easy to use programming via Graphic User Interface (GUI)
High reliability EEPROM for programming & data storage
-40 °C ~ 125 °C operation temperature
The ADP1051 is based on flexible state machine architecture and is
register programmed using an intuitive, graphical-user interface.
The easy–to-use interface reduces design cycle time and results in a
robust, hardware coded system loaded into the built-in EEPROM.
The small size 4*4 mm LFCSP package makes the ADP1051 ideal
for ultra-compact, isolated DCDC power module or embedded
APPLICATIONS
High density, Isolated DC/DC power supplies
•
•
Intermediate bus converters
High availability parallel power systems
Server, storage, industrial, networking, and communications
infrastructure
designs.
LOAD
DC
INPUT
DRIVER
CS2-
SR1
CS1
SR2
VF
CS2+
OVP
VS+
VS-
ADP1051
OUTA
OUTB
SYNI/FLGI
DRIVER
iCoupler
OUTC
VDD
OUTD
RES
ADD RTD VCORE
PG/ALT# CTRL SDA
SCL
AGND
PMBUS
Figure 1. Typical Application Circuit
Rev. PrA
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2013 Analog Devices, Inc. All rights reserved.
ADP1051
Preliminary Technical Data
TABLE OF CONTENTS
Features .....................................................................................................1
Applications..............................................................................................1
General Description................................................................................1
Specifications............................................................................................3
Absolute Maximum Ratings ..................................................................8
Thermal Resistance.............................................................................8
Soldering ..............................................................................................8
ESD Caution.........................................................................................8
Pin Configuration and Function Descriptions....................................9
Application Configurations..................................................................11
Typical Performance Characteristics ..................................................13
Theory of Operation .............................................................................14
Outline Dimensions ..............................................................................15
Ordering Guide..................................................................................15
Rev. PrA | Page 2 of 17
Preliminary Technical Data
ADP1051
SPECIFICATIONS
VDD = 3.0V to 3.6 V, TA = -40°C to +125°C, unless otherwise noted. FSR = Full Scale Range.
Table 1. Specifications
Parameter
SUPPLY
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
VDD
IDD
VDD
IDD
3.0
3.3
3.6
V
PWM pins unloaded
Normal operation (PSON is high or low)
Shut down (VDD below UVLO)
During EEPROM programming, 40 ms
29
mA
μA
60
100
IDD + 6
mA
POWER-ON RESET
Power-ON RESET
UVLO Threshold
UVLO Hysteresis
OVLO Threshold
OVLO Debounce
VDD rising
VDD falling
3.0
V
2.750
3.7
2.850
35
2.975
4.1
V
mV
V
3.9
2
When set to 2 μs
μs
μs
When set to 500 μs
500
VCORE PIN
Output Voltage
OSCILLATOR AND PLL
PLL Frequency
330 nF capacitor between VCORE to AGND 2.50
2.6
2.70
210
V
Using RES = 10 kΩ ( 0.1%)
190
200
625
MHz
ps
DPWM Resolution
OUTA, OUTB, OUTC, OUTD, SR1,
SR2 PINS
Output Low Voltage
VOL
VOH
Sinking Current = 10 mA
Sourcing Current = 10 mA
CLOAD = 50 pF
0.4
V
Output High Voltage
Rise Time
VDD−0.4
V
3.5
1.5
ns
ns
Fall Time
CLOAD = 50 pF
VS VOLTAGE SENSE PIN
Input Voltage Range
Input Voltage FSR
VS Accurate ADC
Differential voltage from VS+ to VS-
0
1
1.60
1.6
V
V
1.6
Valid Input Voltage Range
ADC Clock Frequency
Register Update Rate
Resolution
V
1.56
100
12
MHz
Hz
Bits
Measurement Accuracy
Factory trimmed at 1.0 V
From 0% to 100% of Input Voltage Range
−10
-160
−2.5
-40
+10
+160
+2.5
+40
+1.0
+16
65
% FSR
mV
From 10% to 90% of Input Voltage Range
From 900 mV to 1.1 V
% FSR
mV
−1.0
-16
% FSR
mV
Temperature Coeffient
Common Mode Voltage Offset
VS High Speed ADC
ppm/°C
mV
-200
+200
Equivalent
Sampling
fsw
kHz
Rev. PrA | Page 3 of 17
ADP1051
Preliminary Technical Data
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
Frequency
Equivalent Resolution
Dynamic Range
VS UVP
At 390.6 kHz switching frequency
Regulation voltage TBD mV to TBD V
Based on VS Accurate ADC
6
Bits
mV
25
UVP accuracy
1
4
%
Comparator Update Speed
82
us
OVP PIN
Usable Voltage Range
Threshold Accuracy
Propagation Delay (Latency)
VF VOLTAGE SENSE PIN
Input Voltage Range
Input Voltage FSR
0.75
0
1.5
V
1
1.25
110
%
ns
Debounce time not included
Voltage from VF to AGND
58
1
1.60
1.6
V
V
1.6
General ADC
Valid Input Voltage Range
ADC Clock Frequency
Register Update Rate
Resolution
V
1.56
100
12
MHz
Hz
Bits
% FSR
mV
Measurement Accuracy
From 10% to 90% of Input Voltage FSR
From 0% to 100% of Input Voltage FSR
−3.5
-56
+3.5
+56
−10
-160
+10
% FSR
mV
+160
Feed Forward ADC
Input Voltage Range
Resolution
0.5
0
1
1.6
V
11
10
Bits
μs
Sampling Period
CS1 CURRENT SENSE PIN
Input Voltage Range
Input Voltage FSR
VIN
Differential voltage from CS1 to AGND
1
1.6
1.60
1.6
V
V
CS1 ADC
Valid Input Voltage Range
ADC Clock Frequency
Register Update Rate
Resolution
V
1.56
100
12
MHz
Hz
Bits
% FSR
mV
Measurement Accuracy
From 10% to 90% of Input Voltage Range
From 0% to 100% of Input Voltage Range
−3.5
-56
+3.5
+56
−10
-160
+10
% FSR
mV
+160
CS1 Fast OCP
Threshold Value 1
1.18
0.22
1.2
0.25
58
1.22
0.28
110
V
Threshold Value 2
V
Propagation Delay (Latency)
CS2 CURRENT SENSE PINS
Input Voltage Range
Input Voltage FSR
Debounce/blanking time not included
Differential voltage from CS2+ to CS2−
To achieve measurement accuracy
ns
0
120
mV
mV
V
120
1.15
1.9
Common Mode Voltage
Current Sink (High Side)
0.9
1.4
1.81
1.99
mA
Rev. PrA | Page 4 of 17
Preliminary Technical Data
ADP1051
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
Current Source (Low Side)
4.99 kΩ, 0.1% differential resistor
180
230
280
μA
Temperature Coefficient
CS2 ADC
70
ppm/°C
Valid Input Voltage Range
ADC Clock Frequency
Resolution
0
120
mV
1.56
12
MHz
Bits
mV
Measurement Accuracy
-1
+1
Low Side Mode with User
Trim
From 0 mV to 110 mV
−1.85
−2.22
−6.1
+2.1
% FSR
+2.52
+1.5
mV
From 110 mV to 120 mV
% FSR
mV
−6.36
+0.84
High Side Mode with User
Trim
From 0 mV to 110 mV
−1.6
+2.3
% FSR
mV
−1.92
−5.3
+2.76
+0.7
From 110 mV to 120 mV
% FSR
mV
−6.36
+0.84
CS2 Accurate OCP
Threshold Accuracy
Speed
Same as ADC accuracy
When set to 7 bits averaging speed
When set to 9 bits averaging speed
82
us
us
328
CS2 Reverse Current Comparator
Threshold Accuracy
−3 mV setting
−6 mV setting
−9 mV setting
−12 mV setting
−15 mV setting
−18 mV setting
−21 mV setting
−24 mV setting
Debounce = 40 ns
-8.5
−3.00
−6
0
mV
mV
mV
mV
mV
mV
mV
mV
ns
-12.0
-15.5
-18.5
−22.0
−25.5
−28.5
−32
0
−9
-2.9
-5.9
−8.0
−11.0
-14.0
−16.5
150
−12
−15
−18
−21
−24
110
Threshold Speed
RTD TEMPERATURE SENSE PIN
Input Voltage
Voltage from RTD to AGND
0
1.6
V
Input Voltage FSR
1.6
46
40
30
20
10
V
Source Current
When set to 46 μA, factory default setting
When set to 40 μA
44.3
38.6
28.8
18.8
9.1
47.3
42
μA
μA
μA
μA
μA
When set to 30 μA
31.7
21.5
11
When set to 20 μA
When set to 10 μA
RTD ADC
Valid Input Voltage Range
ADC Clock Frequency
Register Update Rate
Resolution
1.6
V
1.56
100
12
MHz
Hz
Bits
% FSR
Measurement Accuracy
From 2% to 20% of valid input voltage
Rev. PrA | Page 5 of 17
−0.3
+0.45
ADP1051
Preliminary Technical Data
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
−4.8
+7.2
mV
From 0% to 100% of valid input voltage
−2.6
+1.6
% FSR
OTP
Threshold Accuracy
T = 85°C with 100 kΩ||16.5 kΩ
T = 100°C with 100 kΩ||16.5 kΩ
−0.9
−14.4
-0.5
-8
+0.25
+4
% FSR
mV
+1.1
+17.6
% FSR
mV
Comparator Speed
10
ms
Temperature Readings According
to Internal Linearization Scheme
Factory trimmed to 46 µA (set Register
0xFE2D to 0xE6); NTC R0 = 100 kΩ, 1%;
beta = 4250 1%; REXT = 16.5 kΩ 1%
T = 25°C to 100°C
7
5
°C
°C
T = 100°C to 125°C
Sinking Current = 10 mA
Sinking Current = 10 mA
VDD = 3.3 V
PG/ALT# (OPEN DRAIN) PIN
Output Low Level
CTRL, SYNI/FLGI PINS
Input Low Level
Input High Level
SDA/SCL PINS
VOL
0.4
0.4
V
VIL
V
V
VIH
VDD − 0.8
Input Voltage Low
Input Voltage High
Output Voltage Low
Leakage Current
SERIAL BUS TIMING
Clock Frequency
Glitch Immunity
Bus Free Time
VIL
0.8
V
VIH
VOL
VDD − 1.2
−5
V
0.4
+5
V
µA
100
400
50
kHz
ns
µs
µs
µs
µs
µs
ns
ns
ns
ns
tSW
tBUF
4.7
4.7
4
Start Setup Time
Start Hold Time
tSU;STA
tHD;STA
tLOW
tHIGH
tR
SCL Low Time
4.7
4
SCL High Time
SCL, SDA Rise Time
SCL, SDA Fall Time
Data Setup Time
Data Hold Time
1000
300
tF
tSU;DAT
tHD;DAT
250
300
EEPROM
EEPROM Update Time
Time from the updating command to
EEPROM updating finish (TJ = 25°C)
40
ms
Reliability
Endurance1
TJ = 85°C
TJ = 125°C
TJ = 85°C
TJ = 125°C
10,000
1,000
20
Cycles
Cycles
Years
Years
Data Retention2
10
1 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.
2 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature.
Rev. PrA | Page 6 of 17
Preliminary Technical Data
ADP1051
tR
tF
tHD;STA
tLOW
SCL
tHIGH
tSU;STA
tSU;STO
tHD;STA
tHD;DAT
tSU;DAT
SDA
tBUF
P
S
S
P
Figure 2. Serial Bus Timing Diagram.
Rev. PrA | Page 7 of 17
ADP1051
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 2. Absolute Maximum Rating
Parameter
Rating
Supply Voltage (Continuous) VDD
4.2 V
Digital Pins: OUTA, OUTB, OUTC, −0.3 V to VDD + 0.3 V
OUTD, SR1, SR2, PG/ALT#, SDA, SCL
Table 3. Thermal Resistance
Package Type
24 Lead LFCSP
θJA
36.26
θJC
1.51
Unit
°C/W
VS- to AGND
−0.3 V to +0.3 V
VS, VF, OVP, RTD, ADD, CS1, CS2+, −0.3 V to VDD + 0.3 V
CS2-
SYNI/FLGI, CTRL
−0.3 V to VDD + 0.3 V
−40°C to +125°C
−65°C to +150°C
150 °C
SOLDERING
Operating Temperature Range
Storage Temperature Range
Junction Temperature
It is important to follow the correct guidelines when laying out the
PCB footprint for the ADP1051, and for soldering the part onto the
PCB. For detailed information about these guidelines, see the AN-
772 Application Note.
Peak Solder Reflow Temperature
SnPb Assemblies (10 to 30 secs)
RoHS Compliant Assemblies
(20 to 40 secs)
240 °C
260 °C
ESD CAUTION
ESD Charged Device Model
ESD Human Body Model
1.5 kV
5.0 kV
Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions
above those indicated in the operational section of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Rev. PrA | Page 8 of 17
Preliminary Technical Data
ADP1051
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
24 23 22 21
20 19
VS-
VS+
1
2
3
4
5
6
18
17
16
VCORE
PG/ALT#
CTRL
CS2-
ADP1051
TOP VIEW
(Not to Scale)
15 SDA
14 SCL
CS2+
VF
SYNI/FLGI
CS1
13
7
8
9
10 11 12
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VS-
Inverting Voltage Sense Input. This is the connection for the ground line of the power rail. There should be a
low ohmic connection to AGND. It is recommended that the resistor divider on this input have a tolerance
specification of 0.5% or better to allow for trimming.
2
3
VS+
Noninverting Voltage Sense Input. This signal is referred to VS−. It is recommended that the resistor divider on
this input have a tolerance specification of 0.5% or better to allow for trimming.
Inverting Differential Current Sense Input. Nominal voltage at this pin should be 1.15 V for best operation.
When using high-side current sensing in a 12 V application, place a 5.62 kΩ resistor between the sense resistor
and this pin. When using low-side current sensing, place a 5 kΩ resistor between the sense resistor and this pin.
When using high-side current sensing, use the formula R = (VCOMMONMODE – 1.15)/1.9mA. A 0.1% resistor must be
used to connect this circuit.
CS2-
4
CS2+
Noninverting Differential Current Sense Input. Nominal voltage at this pin should be 1.15 V for best operation.
When using high-side current sensing in a 12 V application, place a 5.62 kΩ resistor between the sense resistor
and this pin. When using low-side current sensing, place a 5 kΩ resistor between the sense resistor and this pin.
When using high-side current sensing, use the formula R = (VCOMMONMODE – 1.15)/1.9 mA. A 0.1% resistor must be
used to connect this circuit.
5
6
VF
Three optional functions can be implemented with this pin: feed forward, primary side input voltage sensing
and input voltage lost detect. It is connected upstream of the output inductor through a resistor divider
network. The nominal voltage at this pin should be 1V. This signal is referred to AGND
Primary Side Current Sense Input. This pin is connected to the primary side current sensing ADC and to the fast
OCP comparator. This signal is referred to AGND. The resistors on this input must have a tolerance specification
of 0.5% or better to allow for trimming.
CS1
7
8
9
10
SR1
SR2
OUTA
OUTB
OUTC
PWM logic output drive. This pin can be disabled when not in use. This signal is referred to AGND.
PWM logic output drive. This pin can be disabled when not in use. This signal is referred to AGND.
PWM logic output drive. This pin can be disabled when not in use. This signal is referred to AGND.
PWM logic output drive. This pin can be disabled when not in use. This signal is referred to AGND.
PWM logic output drive. This pin can be disabled when not in use. This signal is referred to AGND. This pin can
also be programmed as a synchronization output.
11
12
OUTD
PWM logic output drive. This pin can be disabled when not in use. This signal is referred to AGND. This pin can
also be programmed as a synchronization output.
13
14
15
16
SYNI/FLGI
SCL
SDA
Synchronization signal input. It also used as an external signal input to generate a flag condition.
I2C/PMBus Serial Clock Input and Output (Open Drain). This signal is referred to AGND.
I2C/PMBus Serial Data Input and Output (Open Drain). This signal is referred to AGND.
PMBus CONTROL signal. It is recommended that a 1 nF capacitor be included from the CTRL pin to AGND for
noise debounce and decoupling. This signal is referred to AGND.
CTRL
17
18
PG/ALT#
VCORE
Power Good Output (Open Drain). This signal is referred to AGND. This pin is also used PMBus ALERT# signal.
Output of 2.6 V regulator. Connect a minimum 330 nF decoupling capacitor from this pin to the AGND as close
as possible to the IC, minimizing the PCB trace length. It is recommended that the VCORE pin not be used as a
reference or to generate other logic levels using resistive dividers.
19
VDD
Positive Supply voltage 3.0 V to 3.6 V referred to AGND. Connect a 2.2 μF decoupling capacitor from this pin to
the AGND as close as possible to the IC, minimizing the PCB trace length.
Rev. PrA | Page 9 of 17
ADP1051
Preliminary Technical Data
Pin No.
Mnemonic
Description
20
AGND
IC Common Analog GND. The internal analog circuitry ground and digital circuitry ground is star connected to
this pin through bonding wires.
21
22
23
24
RES
Resistor Input. This pin sets up the internal reference for internal PLL Frequency. Connect a 10 kΩ resistor
( 0.1%) from RES to AGND. This signal is referred to AGND.
Address Select Input to program I2C/PMBus address. Connect a resistor from ADD to AGND. This signal is
referred to AGND.
Thermistor Input. Place a thermistor 100 kΩ 1% beta = 4250 1% in parallel with a 16.5 kΩ (1%) resistor. This pin
is referenced to AGND. Connect to AGND if not used.
Over Voltage Protection. This signal is used as redundant OVP protection. This signal is referred to VS-.
Exposed Pad. The ADP1051 has an exposed thermal pad on the underside of the package. For increased
reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to
the PCB AGND plane.
ADD
RTD
OVP
EP
Rev. PrA | Page 10 of 17
Preliminary Technical Data
ADP1051
APPLICATION CONFIGURATIONS
LOAD
DC
INPUT
ADP3624/
ADP3654
CS2-
SR1
CS1
SR2
VF
CS2+
OVP
VS+
VS-
ADP1051
OUTA
OUTB
SYNI/FLGI
ADuM3223/
OUTC
ADuM4223
VDD
OUTD
RES
ADD RTD VCORE
PG/ALT#
SDA
SCL
AGND
CTRL
PMBUS
Figure 4. Full Bridge Converter
LOAD
DC
INPUT
ADP3624/
ADP3654
SR1
CS1
CS2-
SR2
VF
CS2+
OVP
VS+
VS-
ADP1051
ADuM3223/
ADuM4223
OUTA
OUTB
SYNI/FLGI
VDD
OUTC
OUTD
RES
ADD RTD VCORE
PG/ALT#
SDA
SCL AGND
CTRL
PMBUS
Figure 5. Half Bridge Converter
Rev. PrA | Page 11 of 17
ADP1051
Preliminary Technical Data
DC
LOAD
INPUT
ADP3624/
ADP3654
CS2-
SR1
CS1
SR2
CS2+
OVP
VS+
VS-
VF
ADP1051
OUTA
OUTB
ADuM3221
SYNI/FLGI
OUTC
VDD
OUTD
RES
ADD RTD VCORE
PG/ALT#
SDA
SCL
AGND
CTRL
PMBUS
Figure 6. Active Clamp Forward Converter
Rev. PrA | Page 12 of 17
Preliminary Technical Data
ADP1051
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 7. VS ADC Accuracy vs. Temperature (from 10% to 90% of FSR)
Figure 8. VF ADC Accuracy vs. Temperature (from 10% to 90% of FSR)
Figure 9. CS1 ADC Accuracy vs. Temperature (from 10% to 90% of FSR)
Figure 10. CS2 ADC Accuracy vs. Temperature (from 0 mV to 120 mV)
Figure 11. RTD ADC Accuracy vs. Temperature
Figure 12. CS1 Fast OCP Threshold vs. Temperature
Rev. PrA | Page 13 of 17
ADP1051
Preliminary Technical Data
THEORY OF OPERATION
programmable PWM outputs for control of FET drivers and
synchronous rectification FET drivers. This programmability
allows many traditional and specific switching topologies to be
realized.
The ADP1051 is designed as a flexible, easy-to-use, digital power
supply controller. The ADP1051 integrates the typical functions
that are needed to control a power supply such as:
•
•
•
•
•
•
•
Output voltage sense and feedback
Voltage feed forward control
Digital loop filter compensation
PWM generation
Current, voltage, and temperature sense
Housekeeping and I2C/PMBus interface
Calibration and trimming
Conventional power supply housekeeping features, such as remote
and local voltage sense and primary side current sense, are
included. An extensive set of protections are offered, including
overvoltage protection (OVP), over current protection (OCP), over
temperature protection (OTP), under voltage protection (UVP), SR
reverse current protection (RCP).
All these features are programmable through the I2C/PMBus
interface. This interface is also used for calibrations. Other
information, such as input current, output current, and fault flags,
is also available through this digital bus interface.
The main function of controlling the output voltage is performed
using the feedback ADCs, the digital loop filter, and the PWM
block.
The feedback ADCs use a multipath approach. There is a
combination of a high speed, low resolution (fast and coarse) ADC
and a low speed, high resolution (slow and accurate) ADC. The
ADC outputs combine to form a high speed and high resolution
feedback path. Loop compensation is implemented using the digital
filter. This PID (proportional, integral, derivative) filter is
implemented in the digital domain, allowing easy programming of
filter characteristics, which is of great value in customizing and
debugging designs. The PWM block generates up to six
The internal EEPROM can store all programmed values and allows
standalone control without a microcontroller. A free, downloadable
ADP1051 GUI is available that provides all the necessary software
to program the ADP1051. To obtain the latest GUI software and a
user guide, visit http://www.analog.com/digitalpower.
The ADP1051 operates from a single 3.3V power supply and is
specified from -40°C to 125°C.
CS1
VF
CS2+
CS2-
VS+
VS-
1.2V 0.25V
-
-
VREF
OVP
OUTA
OUTB
OUTC
OUTD
SR1
+
-
DAC
ADC
RTD
ADD
PWM
ENGINE
DIGITAL CORE
OSC
8kB
EEPROM
RES
PMBus
AGND
UVLO
LDO
SR2
VDD
SYNI/FLGI
SCL
SDA
CTRL
PG/ALT#
VCORE
Figure 13. Functional Block Diagram
Rev. PrA | Page 14 of 17
Preliminary Technical Data
OUTLINE DIMENSIONS
ADP1051
Figure 14. 24-Lead 4 x 4 mm Lead frame Chip-Scale Package [LFCSP]
Mechanical Package Dimensions
ORDERING GUIDE
Model1
Temperature Range
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
CP-24-7
CP-24-7
ADP1051ACPZ-RL
ADP1051ACPZ-R7
ADP1051-240-EVALZ
ADP1051DC1-EVALZ
ADP-I2C-USB-Z
24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
ADP1051 240 W Evaluation Board
ADP1051 Daughter Card
USB to I2C Adapter
1 Z = RoHS Compliant Part.
Rev. PrA | Page 15 of 17
ADP1051
NOTES
Preliminary Technical Data
Rev. PrA | Page 16 of 17
Preliminary Technical Data
NOTES
ADP1051
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR1433-0-3/13/(PrA)
Rev. PrA | Page 17 of 17
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