ADP1870-1.0-EVALZ_技术文档

Synchronous Buck Controller with

Constant On-Time and Valley Current Mode

ADP1870/ADP1871

FEATURES

TYPICAL APPLICATIONS CIRCUIT

V

= 2.95V TO 20V

IN

Power input voltage range: 2.95 V to 20 V

On-board bias regulator

Minimum output voltage: 0.6 V

0.6 V reference voltage with 1.0% accuracy

Supports all N-channel MOSFET power stages

Available in 300 kHz, 600 kHz, and 1.0 MHz options

No current-sense resistor required

Power saving mode (PSM) for light loads (ADP1871 only)

Resistor-programmable current-sense gain

Thermal overload protection

VIN

C

ADP1870/

ADP1871

COMP/EN BST

C

IN

C

C2

R

C

R

TOP

V

OUT

C

Q1

BST

L

V

FB

DRVH

SW

OUT

R

BOT

C

GND

OUT

Q2

C

VREG2

VREG

DRVL

PGND

R

RES

LOAD

C

VREG

Short-circuit protection

Figure 1.

Precision enable input

Integrated bootstrap diode for high-side drive

Starts into a precharged load

Small, 10-lead MSOP package

100

95

90

85

80

75

70

65

60

55

50

45

40

35

30

25

V

= 5V (PSM)

IN

APPLICATIONS

Telecom and networking systems

Mid to high end servers

Set-top boxes

V

= 16.5V

IN

V

= 13V

IN

DSP core power supplies

V

= 13V (PSM)

IN

T

V

= 25°C

A

= 1.8V

OUT

= 300kHz

f

SW

V

= 16.5V (PSM)

IN

GENERAL DESCRIPTION

WÜRTH INDUCTOR:

744325120, L = 1.2µH, DCR = 1.8mΩ

INFINEON FETs:

BSC042N03MS G (UPPER/LOWER)

The ADP1870/ADP1871 are versatile current-mode, synchronous

step-down controllers that provide superior transient response,

optimal stability, and current-limit protection by using a constant

on-time, pseudo-fixed frequency with a programmable current-

limit, current-control scheme. In addition, these devices offer

optimum performance at low duty cycles by utilizing valley

current-mode control architecture. This allows the ADP1870/

ADP1871 to drive all N-channel power stages to regulate output

voltages as low as 0.6 V.

10

100

1k

10k

100k

LOAD CURRENT (mA)

Figure 2. Efficiency vs. Load Current (V_OUT= 1.8 V, 300 kHz)

In addition, an internally fixed soft start period is included to limit

input in-rush current from the input supply during startup and

to provide reverse current protection during soft start for a pre-

charged output. The low-side current-sense, current-gain scheme

and integration of a boost diode, along with the PSM/forced pulse-

width modulation (PWM) option, reduce the external part count

and improve efficiency.

The ADP1871 is the power saving mode (PSM) version of the

device and is capable of pulse skipping to maintain output

regulation while achieving improved system efficiency at light

loads (see the Power Saving Mode (PSM) Version (ADP1871)

section for more information).

The ADP1870/ADP1871 operate over the −40°C to +125°C

junction temperature range and are available in a 10-lead MSOP

package.

Available in three frequency options (300 kHz, 600 kHz, and

1.0 MHz, plus the PSM option), the ADP1870/ADP1871 are well

suited for a wide range of applications that require a single-input

power supply range from 2.95 V to 20 V. Low voltage biasing is

supplied via a 5 V internal LDO.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADP1870/ADP1871

TABLE OF CONTENTS

Features .............................................................................................. 1

Power Saving Mode (PSM) Version (ADP1871) ................... 22

Timer Operation ........................................................................ 22

Pseudo-Fixed Frequency........................................................... 23

Applications Information.............................................................. 24

Feedback Resistor Divider ........................................................ 24

Inductor Selection...................................................................... 24

Output Ripple Voltage (ΔV_RR) .................................................. 24

Output Capacitor Selection....................................................... 24

Compensation Network ............................................................ 25

Efficiency Considerations ......................................................... 26

Input Capacitor Selection.......................................................... 27

Thermal Considerations............................................................ 28

Design Example.......................................................................... 29

External Component Recommendations.................................... 31

Layout Considerations................................................................... 33

IC Section (Left Side of Evaluation Board)............................. 37

Power Section ............................................................................. 37

Differential Sensing.................................................................... 38

Typical Applications Circuits........................................................ 39

15 A, 300 kHz High Current Application Circuit.................. 39

5.5 V Input, 600 kHz Application Circuit............................... 39

300 kHz High Current Application Circuit............................ 40

Outline Dimensions....................................................................... 41

Ordering Guide .......................................................................... 41

Applications....................................................................................... 1

General Description......................................................................... 1

Typical Applications Circuit............................................................ 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

Thermal Resistance ...................................................................... 5

Boundary Condition.................................................................... 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 7

ADP1870/ADP1871 Block Diagram............................................ 18

Theory of Operation ...................................................................... 19

Startup.......................................................................................... 19

Soft Start ...................................................................................... 19

Precision Enable Circuitry ........................................................ 19

Undervoltage Lockout ............................................................... 19

On-Board Low Dropout Regulator.......................................... 19

Thermal Shutdown..................................................................... 20

Programming Resistor (RES) Detect Circuit.......................... 20

Valley Current-Limit Setting .................................................... 20

Hiccup Mode During Short Circuit......................................... 21

Synchronous Rectifier................................................................ 22

REVISION HISTORY

3/10—Revision 0: Initial Version

Rev. 0 | Page 2 of 44

ADP1870/ADP1871

SPECIFICATIONS

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). V_REG= 5 V,

V_BST− V_SW= V_REG− V_{RECT_DROP}(see Figure 40 to Figure 42). V_IN= 12 V. The specifications are valid for T_J= −40°C to +125°C,

unless otherwise specified.

Table 1.

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

POWER SUPPLY CHARACTERISTICS

High Input Voltage Range

V_IN

C_IN= 22 μF to PGND (at Pin 1)

ADP1870ARMZ-0.3/ADP1871ARMZ-0.3 (300 kHz)

ADP1870ARMZ-0.6/ADP1871ARMZ-0.6 (600 kHz)

ADP1870ARMZ-1.0/ADP1871ARMZ-1.0 (1.0 MHz)

2.95

3.25

12

20

V

Quiescent Current

Shutdown Current

I_{Q_REG}+ I_{Q_BST}V_FB= 1.5 V, no switching

1.1

190

mA

ꢀA

I_REG,SD

I_BST,SD

+

COMP/EN < 285 mV

280

Undervoltage Lockout

UVLO Hysteresis

UVLO

Rising V_IN(see Figure 35 for temperature variation)

Falling V_INfrom operational state

2.65

190

V

mV

INTERNAL REGULATOR

CHARACTERISTICS

VREG Operational Output Voltage

V_REG

C_VREG= 1 μF to PGND, 0.22 μF to GND, V_IN= 2.95 V to 20 V

ADP1870ARMZ-0.3/ADP1871ARMZ-0.3 (300 kHz)

ADP1870ARMZ-0.6/ADP1871ARMZ-0.6 (600 kHz)

ADP1870ARMZ-1.0/ADP1871ARMZ-1.0 (1.0 MHz)

V_IN= 7 V, 100 mA

2.75

3.05

4.8

5

5.5

V

VREG Output in Regulation

Load Regulation

4.981 5.16

V_IN= 12 V, 100 mA

0 mA to 100 mA, V_IN= 7 V

4.8

4.982 5.16

V

32

33

2.5

2.0

300

229

mV

mA

0 mA to 100 mA, V_IN= 20 V

Line Regulation

V_IN= 7 V to 20 V, 20 mA

V_IN= 7 V to 20 V, 100 mA

V_INto V_REGDropout Voltage

Short VREG to PGND

SOFT START

100 mA out of V_REG, V_IN≤ 5 V

V_IN= 20 V

415

320

Soft Start Period

See Figure 58

3.0

ms

ERROR AMPLIFER

FB Regulation Voltage

V_FB

T_J= +25°C

T_J= −40°C to +85°C

T_J= −40°C to +125°C

600

496

1

mV

605.8 mV

596

594.2

320

604

Transconductance

FB Input Leakage Current

CURRENT-SENSE AMPLIFIER GAIN

Programming Resistor (RES)

Value from DRVL to PGND

G_m

I_{FB, Leak}

670

50

μS

nA

V_FB= 0.6 V, COMP/EN = released

RES = 47 kΩ 1%

2.7

3

3.3

V/V

RES = 22 kΩ 1%

RES = none

RES = 100 kΩ 1%

5.5

11

22

6

12

24

6.5

13

26

V/V

SWITCHING FREQUENCY

Typical values measured at 50% time points with 0 nF

at DRVH and DRVL; maximum values are guaranteed

by bench evaluation¹

ADP1870ARMZ-0.3/

300

kHz

ADP1871ARMZ-0.3 (300 kHz)

On-Time

Minimum On-Time

Minimum Off-Time

V_IN= 5 V, V_OUT= 2 V, T_J= 25°C

V_IN= 20 V

84% duty cycle (maximum)

1120

1200 1280 ns

146

340

190

400

ns

Rev. 0 | Page 3 of 44

ADP1870/ADP1871

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

ADP1870ARMZ-0.6/

600

kHz

ADP1871ARMZ-0.6 (600 kHz)

On-Time

Minimum On-Time

Minimum Off-Time

V_IN= 5 V, V_OUT= 2 V, T_J= 25°C

V_IN= 20 V, V_OUT= 0.8 V

65% duty cycle (maximum)

500

540

82

340

1.0

580

110

400

ns

MHz

ADP1870ARMZ-1.0/

ADP1871ARMZ-1.0 (1.0 MHz)

On-Time

V_IN= 5 V, V_OUT= 2 V, T_J= 25°C

V_IN= 20 V

45% duty cycle (maximum)

285

312

60

340

85

400

ns

Minimum On-Time

Minimum Off-Time

OUTPUT DRIVER CHARACTERISTICS

High-Side Driver

Output Source Resistance

Output Sink Resistance

Rise Time²

I_SOURCE= 1.5 A, 100 ns, positive pulse (0 V to 5 V)

I_SINK= 1.5 A, 100 ns, negative pulse (5 V to 0 V)

V_BST− V_SW= 4.4 V, C_IN= 4.3 nF (see Figure 60)

V_BST− V_SW= 4.4 V, C_IN= 4.3 nF (see Figure 61)

2.25

0.7

25

3

1

Ω

ns

t_r,DRVH

t_f,DRVH

Fall Time²

11

Low-Side Driver

Output Source Resistance

Output Sink Resistance

Rise Time²

I_SOURCE= 1.5 A, 100 ns, positive pulse (0 V to 5 V)

I_SINK= 1.5 A, 100 ns, negative pulse (5 V to 0 V)

V_REG= 5.0 V, C_IN= 4.3 nF (see Figure 61)

1.6

0.7

18

2.2

1

Ω

ns

t_r,DRVL

t_f,DRVL

Fall Time²

V_REG= 5.0 V, C_IN= 4.3 nF (see Figure 60)

16

Propagation Delays

DRVL Fall to DRVH Rise²

DRVH Fall to DRVL Rise²

SW Leakage Current

Integrated Rectifier

Channel Impedance

PRECISION ENABLE THRESHOLD

Logic High Level

t_tpdhDRVH

t_tpdhDRVL

I_SWLEAK

V_BST− V_SW= 4.4 V (see Figure 60)

V_BST− V_SW= 4.4 V (see Figure 61)

V_BST= 25 V, V_SW= 20 V, V_REG= 5 V

15.4

18

ns

μA

110

330

I_SINK= 10 mA

22

Ω

V_IN= 2.9 V to 20 V, V_REG= 2.75 V to 5.5 V

245

285

37

mV

Enable Hysteresis

COMP VOLTAGE

COMP Clamp Low Voltage

V_COMP(low)

From disabled state, release COMP/EN pin to enable 0.47

device (2.75 V ≤ V_REG≤ 5.5 V)

V

COMP Clamp High Voltage

COMP Zero Current Threshold

THERMAL SHUTDOWN

V_COMP(high)

V_{COMP_ZCT}

T_TMSD

(2.75 V ≤ V_REG≤ 5.5 V)

2.55

V

1.07

Thermal Shutdown Threshold

Thermal Shutdown Hysteresis

Hiccup Current Limit Timing

Rising temperature

155

15

6

°C

ms

¹The maximum specified values are with the closed loop measured at 10% to 90% time points (see Figure 60 and Figure 61), C_GATE= 4.3 nF, and the upper- and lower-side

MOSFETs being Infineon BSC042N03MSG.

²Not automatic test equipment (ATE) tested.

Rev. 0 | Page 4 of 44

ADP1870/ADP1871

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter

THERMAL RESISTANCE

Rating

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

VREG to PGND, GND

VIN to PGND

FB, COMP/EN to GND

DRVL to PGND

SW to PGND

−0.3 V to +6 V

−0.3 V to +28 V

−0.3 V to (V_REG+ 0.3 V)

−2.0 V to +28 V

−0.6 V to (V_REG+ 0.3 V)

−0.3 V to 28 V

Table 3. Thermal Resistance

1

Package Type

θ_JA(10-Lead MSOP)

2-Layer Board

θ_JA

Unit

BST to SW

BST to PGND

213.1

171.7

°C/W

4- Layer Board

DRVH to SW

−0.3 V to V_REG

¹θ_JAis specified for the worst-case conditions; that is, θ_JAis specified for the

device soldered in a circuit board for surface-mount packages.

PGND to GND

θ_JA(10-Lead MSOP)

2-Layer Board

4-Layer Board

Operating Junction Temperature

Range

±0.3 V

213.1°C/W

171.7°C/W

−40°C to +125°C

BOUNDARY CONDITION

In determining the values given in Table 2 and Table 3, natural

convection was used to transfer heat to a 4-layer evaluation board.

Storage Temperature Range

Soldering Conditions

Maximum Soldering Lead

Temperature (10 sec)

−65°C to +150°C

JEDEC J-STD-020

300°C

ESD CAUTION

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Absolute maximum ratings apply individually only, not in

combination. Unless otherwise specified, all other voltages are

referenced to PGND.

Rev. 0 | Page 5 of 44

ADP1870/ADP1871

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VIN

COMP/EN

FB

1

2

3

4

5

10 BST

ADP1870/

ADP1871

TOP VIEW

(Not to Scale)

9

8

7

6

SW

DRVH

PGND

DRVL

GND

VREG

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic Description

1

2

3

4

VIN

COMP/EN

FB

High Input Voltage. Connect VIN to the drain of the upper-side MOSFET.

Output of the Internal Error Amplifier/IC Enable. When this pin functions as EN, applying 0 V to this pin disables the IC.

Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected.

Analog Ground Reference Pin of the IC. All sensitive analog components should be connected to this ground

plane (see the Layout Considerations section).

GND

5

6

VREG

DRVL

Internal Regulator Supply Bias Voltage for the ADP1870/ADP1871 Controller (Includes the Output Gate Drivers).

A bypass capacitor of 1 μF directly from this pin to PGND and a 0.1 μF across VREG and GND are recommended.

Drive Output for the External Lower-Side, N-Channel MOSFET. This pin also serves as the current-sense gain

setting pin (see Figure 69).

7

8

9

PGND

DRVH

SW

Power GND. Ground for the lower-side gate driver and lower-side, N-channel MOSFET.

Drive Output for the External Upper-Side, N-Channel MOSFET.

Switch Node Connection.

10

BST

Bootstrap for the Upper-Side MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected

between VREG and BST. A capacitor from BST to SW is required. An external Schottky diode can also be

connected between VREG and BST for increased gate drive capability.

Rev. 0 | Page 6 of 44

ADP1870/ADP1871

TYPICAL PERFORMANCE CHARACTERISTICS

100

95

100

95

90

85

80

75

70

65

60

55

50

45

40

35

30

25

20

15

10

5

90

V

= 13V

IN

85

80

75

70

65

60

55

50

45

40

35

30

25

20

15

10

5

V

= 13V (PSM)

IN

V

= 13V (PSM)

IN

V

= 16.5V

IN

V

= 16.5V

IN

V

= 13V

IN

T

V

= 25°C

T = 25°C

A

V

= 16.5V (PSM)

A

IN

= 0.8V

V

= 0.8V

OUT

= 300kHz

OUT

= 600kHz

V

= 16.5V

IN

(PSM)

f

SW

WÜRTH INDUCTOR:

744325072, L = 0.72µH, DCR = 1.3mΩ

INFINEON FETs:

BSC042N03MS G (UPPER/LOWER)

WÜRTH INDUCTOR:

744355147, L = 0.47µH, DCR = 0.67mΩ

INFINEON FETs:

BSC042N03MS G (UPPER/LOWER)

0

10

100

1k

10k

100k

10

100

1k

10k

100k

LOAD CURRENT (mA)

Figure 4. Efficiency—300 kHz, V_OUT= 0.8 V

Figure 7. Efficiency—600 kHz, V_OUT= 0.8 V

100

95

90

85

80

75

70

65

60

55

50

45

40

35

30

25

20

15

10

5

100

95

90

85

80

75

70

65

60

55

50

45

40

35

30

25

20

15

10

5

V

= 5V (PSM)

IN

V

IN

= 13V

V

= 13V (PSM)

IN

V

= 16.5V

IN

V

= 13V (PSM)

IN

V

= 13V

IN

V

= 16.5V

IN

V

= 16.5V (PSM)

IN

V

= 16.5V (PSM)

IN

T

V

= 25°C

T

A

V

= 25°C

A

= 1.8V

OUT

= 300kHz

OUT

= 600kHz

f

SW

WÜRTH INDUCTOR:

744325120, L = 1.2µH, DCR = 1.8mΩ

INFINEON FETs:

BSC042N03MS G (UPPER/LOWER)

WÜRTH INDUCTOR:

744325072, L = 0.72µH, DCR = 1.3mΩ

INFINEON FETs:

BSC042N03MS G (UPPER/LOWER)

0

10

0

10

100

1k

10k

100

1k

10k

LOAD CURRENT (mA)

Figure 5. Efficiency—300 kHz, V_OUT= 1.8 V

Figure 8. Efficiency—600 kHz, V_OUT= 1.8 V

100

95

90

85

80

75

70

65

60

55

50

45

40

35

30

25

20

15

10

5

100

95

90

85

80

75

70

65

60

55

50

45

40

35

30

25

20

15

10

5

V

= 16.5V (PSM)

= 13V (PSM)

V

= 13V (PSM)

IN

V

= 16.5V (PSM)

IN

V

IN

V

= 13V

IN

V

= 16.5V

IN

V

= 16.5V

IN

V

= 20V (PSM)

IN

V

= 20V

IN

T

= 25°C

T

A

V

= 25°C

A

V

= 7V

= 5V

OUT

= 300kHz

OUT

= 600kHz

f

SW

WÜRTH INDUCTOR:

7443551200, L = 2.0µH, DCR = 2.6mΩ

INFINEON FETs:

BSC042N03MS G (UPPER/LOWER)

WÜRTH INDUCTOR:

744318180, L = 1.4µH, DCR = 3.2mΩ

INFINEON FETs:

BSC042N03MS G (UPPER/LOWER)

0

10

0

10

100

1k

LOAD CURRENT (mA)

10k

100

1k

10k

LOAD CURRENT (mA)

Figure 6. Efficiency—300 kHz, V_OUT= 7 V

Figure 9. Efficiency—600 kHz, V_OUT= 5 V

Rev. 0 | Page 7 of 44

ADP1870/ADP1871

100

95

90

85

80

75

70

65

60

55

50

45

40

35

30

25

20

15

10

5

0.807

0.806

0.805

0.804

0.803

0.802

0.801

0.800

0.799

0.798

0.797

0.796

0.795

0.794

0.793

0.792

V

= 13V

IN

V

= 13V (PSM)

IN

V

= 16.5V

IN

T

V

= 25°C

A

= 0.8V

OUT

= 1.0MHz

V

= 16.5V (PSM)

IN

f

SW

WÜRTH INDUCTOR:

744303012, L = 0.12µH, DCR = 0.33mΩ

INFINEON FETs:

BSC042N03MS G (UPPER/LOWER)

V

= 13V

V

= 16.5V

IN

+125°C

+25°C

–40°C

+125°C

+25°C

–40°C

0

10

100

1k

10k

100k

0

2000

4000

6000

8000

10,000

LOAD CURRENT (mA)

Figure 10. Efficiency—1.0 MHz, V_OUT= 0.8 V

Figure 13. Output Voltage Accuracy—300 kHz, V_OUT= 0.8 V

100

95

90

85

80

75

70

65

60

55

50

45

40

35

30

25

20

15

10

5

1.821

V

= 13V

IN

1.816

1.811

1.806

1.801

1.796

1.791

1.786

V

= 13V (PSM)

IN

V

= 16.5V

IN

V

= 16.5V (PSM)

IN

T

V

f

= 25°C

A

= 1.8V

OUT

= 1.0MHz

SW

V

= 5.5V

+125°C

+25°C

–40°C

V

= 13V

+125°C

+25°C

–40°C

V

= 16.5V

IN

WÜRTH INDUCTOR:

744303022, L = 0.22µH, DCR = 0.33mΩ

INFINEON FETs:

BSC042N03MS G (UPPER/LOWER)

IN

+125°C

+25°C

–40°C

0

10

0

1500 3000 4500 6000 7500 9000 10,500 12,000 13,500 15,000

LOAD CURRENT (mA)

100

1k

10k

100k

LOAD CURRENT (mA)

Figure 11. Efficiency—1.0 MHz, V_OUT= 1.8 V

Figure 14. Output Voltage Accuracy—300 kHz, V_OUT= 1.8 V

100

95

90

85

80

75

70

65

60

55

50

45

40

35

30

25

20

15

10

5

7.100

7.095

7.090

7.085

7.080

7.075

7.070

7.065

7.060

7.055

7.050

7.045

7.040

7.035

7.030

7.025

7.020

7.015

7.010

7.005

7.000

V

= 13V (PSM)

IN

V

= 13V

IN

V

= 16.5V (PSM)

IN

V

= 16.5V

IN

T

V

= 25°C

A

= 5V

OUT

= 1.0MHz

f

SW

WÜRTH INDUCTOR:

744355090, L = 0.9µH, DCR = 1.6mΩ

INFINEON FETs:

BSC042N03MS G (UPPER/LOWER)

+125°C

+25°C

–40°C

V

= 13V

= 16.5V

IN

0

10

0

1000 2000 3000 4000 5000 6000 7000 8000 9000

LOAD CURRENT (mA)

100

1k

LOAD CURRENT (mA)

10k

100k

Figure 12. Efficiency—1.0 MHz, V_OUT= 5 V

Figure 15. Output Voltage Accuracy—300 kHz, V_OUT= 7 V

Rev. 0 | Page 8 of 44

ADP1870/ADP1871

0.808

0.806

0.804

0.802

0.800

0.798

0.796

0.794

0.792

0.807

0.805

0.803

0.801

0.799

0.797

0.795

0.793

0.791

0.789

0.787

V

= 13V

+125°C

+25°C

–40°C

V

= 16.5V

IN

+125°C

+25°C

–40°C

+125°C

+25°C

–40°C

V

= 13V

= 16.5V

IN

0

1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000

LOAD CURRENT (mA)

0

2000

4000

6000

8000

10,000

LOAD CURRENT (mA)

Figure 16. Output Voltage Accuracy—600 kHz, V_OUT= 0.8 V

Figure 19. Output Voltage Accuracy—1.0 MHz, V_OUT= 0.8 V

1.818

1.820

1.816

1.814

1.812

1.810

1.808

1.806

1.804

1.802

1.800

1.798

1.796

1.794

1.792

1.790

1.788

1.786

1.784

1.782

1.780

1.778

1.776

1.774

1.772

1.770

1.815

1.810

1.805

1.800

1.795

1.790

V

= 13V

+125°C

+25°C

–40°C

V

= 16.5V

+125°C

+25°C

–40°C

V

= 13V

V

= 16.5V

IN

+125°C

+25°C

–40°C

+125°C

+25°C

–40°C

0

1500

3000

4500

6000

7500

9000 10,500 12,000

00

1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000

LOAD CURRENT (mA)

Figure 17. Output Voltage Accuracy—600 kHz, V_OUT= 1.8 V

Figure 20. Output Voltage Accuracy—1.0 MHz, V_OUT= 1.8 V

5.030

5.04

5.03

5.02

5.01

5.00

4.99

4.98

4.97

4.96

4.95

4.94

4.93

5.025

5.020

5.015

5.010

5.005

5.000

4.995

4.990

4.985

4.980

4.975

4.970

V

= 13V

V

= 16.5V

IN

4.92

4.91

4.90

+125°C

+25°C

–40°C

+125°C

+25°C

–40°C

+125°C

+25°C

–40°C

V

= 13V

= 16.5V

= 20V

IN

0

1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000

LOAD CURRENT (mA)

0

800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800 9600

LOAD CURRENT (mA)

Figure 18. Output Voltage Accuracy—600 kHz, V_OUT= 5 V

Figure 21. Output Voltage Accuracy—1.0 MHz, V_OUT=5 V

Rev. 0 | Page 9 of 44

ADP1870/ADP1871

601.0

900

880

860

840

820

800

780

760

740

720

700

+125°C

+25°C

–40°C

600.5

V

= 5V, V = 30V

IN

REG

600.0

599.5

599.0

598.5

598.0

597.5

597.0

V

= 5V, V = 13V

IN

REG

–40.0

–7.5

25.0

57.5

90.0

122.5

13.0

13.5

14.0

14.5

15.0

(V)

15.5

16.0

16.5

TEMPERATURE (°C)

V

IN

Figure 22. Feedback Voltage vs. Temperature

Figure 25. Switching Frequency vs. High Input Voltage, 1.0 MHz,

V_INRange = 13 V to 16.5 V

280

325

315

305

295

285

275

265

255

V

= 13V

= 20V

= 16.5V

+125°C

+25°C

–40°C

+125°C

+25°C

–40°C

NO LOAD

IN

265

250

235

220

205

190

0

2000

4000

6000

8000

10,000

10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2

LOAD CURRENT (mA)

V

(V)

IN

Figure 23. Switching Frequency vs. High Input Voltage, 300 kHz, 10% of 12 V

Figure 26. Frequency vs. Load Current, 300 kHz, V_OUT= 0.8 V

650

330

320

310

300

290

280

270

260

250

240

+125°C

+25°C

–40°C

NO LOAD

V

= 20V

= 13V

= 16.5V

+125°C

+25°C

–40°C

IN

600

550

500

450

400

13.0 13.4 13.8 14.2 14.6 15.0 15.4 15.8 16.2

0

1500 3000 4500 6000 7500 9000 10,500 12,000 13,500 15,00

LOAD CURRENT (mA)

V

(V)

IN

Figure 24. Switching Frequency vs. High Input Voltage, 600 kHz, V_OUT= 1.8 V,

V_INRange = 13 V to 16.5 V

Figure 27. Frequency vs. Load Current, 300 kHz, V_OUT= 1.8 V

Rev. 0 | Page 10 of 44

ADP1870/ADP1871

338

334

330

326

322

318

314

310

306

302

298

740

733

726

719

712

705

698

691

684

677

670

663

656

649

642

635

628

621

V

= 13V

= 16.5V

+125°C

+25°C

–40°C

V

= 13V

= 16.5V

+125°C

+25°C

–40°C

IN

0

800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800 9600

LOAD CURRENT (mA)

0

800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800

LOAD CURRENT (mA)

Figure 31. Frequency vs. Load Current, 600 kHz, V_OUT= 5 V

Figure 28. Frequency vs. Load Current, 300 kHz, V_OUT= 7 V

850

775

700

625

550

475

400

+125°C

+25°C

–40°C

540

510

480

450

420

390

360

330

300

V

= 13V

= 16.5V

IN

V

= 13V

= 16.5V

+125°C

+25°C

–40°C

IN

0

1200 2400 3600 4800 6000 7200 8400 9600 10,800 12,000

LOAD CURRENT (mA)

0

2000

4000

6000

8000

10,000

12,000

LOAD CURRENT (mA)

Figure 29. Frequency vs. Load Current, 600 kHz, V_OUT= 0.8 V

Figure 32. Frequency vs. Load Current, V_OUT= 1.0 MHz, 0.8 V

675

655

635

615

595

575

555

535

515

495

1225

1150

1075

1000

925

V

= 13V

= 16.5V

+125°C

+25°C

–40°C

V

= 13V

= 16.5V

IN

850

775

700

+125°C

+25°C

–40°C

625

550

0

1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000

LOAD CURRENT (mA)

0

1200 2400 3600 4800 6000 7200 8400 9600 10,800 12,000

LOAD CURRENT (mA)

Figure 30. Frequency vs. Load Current, 600 kHz, V_OUT= 1.8 V

Figure 33. Frequency vs. Load Current, 1.0 MHz, V_OUT= 1.8 V

Rev. 0 | Page 11 of 44

ADP1870/ADP1871

1450

82

80

78

76

74

72

70

68

66

64

62

+125°C

+25°C

–40°C

V

= 13V

= 16.5V

+125°C

+25°C

–40°C

IN

1400

1350

1300

1250

1200

1150

1100

1050

1000

0

800 1600 2400 3200 4000 4800 5600 6400 7200 8000

LOAD CURRENT (mA)

5.5

6.7

7.9

9.1

10.3 11.5 12.7 13.9 15.1 16.3

(V)

V

IN

Figure 34. Frequency vs. Load Current, 1.0 MHz, V_OUT= 5 V

Figure 37. Maximum Duty Cycle vs. High Voltage Input (V_IN

)

2.658

680

630

580

530

480

430

380

330

280

230

180

V

= 2.7V

= 3.6V

= 5.5V

REG

2.657

2.656

2.655

2.654

2.653

2.652

2.651

2.650

2.649

–40

–20

0

20

40

60

80

100

120

–40

–20

0

20

40

60

80

100

120

TEMPERATURE (°C)

Figure 38. Minimum Off-Time vs. Temperature

Figure 35. UVLO vs. Temperature

680

630

580

530

480

430

380

330

280

230

180

95

90

85

80

75

70

65

60

55

+125°C

+25°C

–40°C

+125°C

+25°C

–40°C

2.7

3.1

3.5

3.9

V

4.3

(V)

4.7

5.1

5.5

300

400

500

600

700

800

900

1000

FREQUENCY (kHz)

REG

Figure 36. Maximum Duty Cycle vs. Frequency

Figure 39. Minimum Off-Time vs. V_REG(Low Input Voltage)

Rev. 0 | Page 12 of 44

ADP1870/ADP1871

800

720

640

560

480

400

320

240

160

80

72

64

56

48

40

32

24

16

8

V

= 2.7V

= 3.6V

= 5.5V

+125°C

+25°C

–40°C

300kHz

1MHz

+125°C

+25°C

–40°C

REG

300

400

500

600

700

800

900

1000

2.7

3.1

3.5

3.9

V

4.3

(V)

4.7

5.1

5.5

FREQUENCY (kHz)

REG

Figure 40. Internal Rectifier Drop vs. Frequency

Figure 43. Lower-Side MOSFET Body Diode Conduction Time vs. V_REG

1280

1200

1120

1040

960

880

800

720

640

560

480

400

320

240

160

80

V

= 5.5V

= 13V

= 16.5V

1MHz

T

= 25°C

IN

A

300kHz

OUTPUT VOLTAGE

1

INDUCTOR CURRENT

2

SW NODE

3

LOW SIDE

4

B

CH1 50mV

CH3 10V

CH2 5A ꢀ M400ns

T 35.8%

A CH2

3.90A

W

2.7

3.1

3.5

3.9

V

4.3

4.7

5.1

5.5

B

CH4 5V

W

(V)

REG

Figure 41. Internal Boost Rectifier Drop vs. V_REG(Low Input Voltage)

Over V_INVariation

Figure 44. Power Saving Mode (PSM) Operational Waveform, 100 mA

720

300kHz

1MHz

+125°C

+25°C

–40°C

OUTPUT VOLTAGE

640

560

480

400

320

240

160

80

1

INDUCTOR CURRENT

2

SW NODE

3

LOW SIDE

4

B

CH1 50mV

CH3 10V

CH2 5A ꢀ M4.0µs

T 35.8%

A CH2

3.90A

W

2.7

3.1

3.5

3.9

V

4.3

4.7

5.1

5.5

B

CH4 5V

W

(V)

REG

Figure 42. Internal Boost Rectifier Drop vs. V_REG

Figure 45. PSM Waveform at Light Load, 500 mA

Rev. 0 | Page 13 of 44

ADP1870/ADP1871

OUTPUT VOLTAGE

2

4

OUTPUT VOLTAGE

INDUCTOR CURRENT

12A NEGATIVE STEP

SW NODE

1

3

1

3

SW NODE

LOW SIDE

4

B

CH1 5A

CH3 10V

ꢀ

M400ns

T 30.6%

A CH3

2.20V

CH1 10A ꢀ CH2 200mV

CH3 20V CH4 5V

M20µs

T 48.2%

A CH1

3.40A

W

B

CH4 100mV

W

Figure 49. Negative Step During Heavy Load Transient Behavior—PSM Enabled,

12 A (See Figure 93 Application Circuit)

Figure 46. CCM Operation at Heavy Load, 12 A

(See Figure 93 for Application Circuit)

OUTPUT VOLTAGE

2

4

OUTPUT VOLTAGE

12A STEP

1

2

LOW SIDE

1

3

SW NODE

LOW SIDE

A CH1 3.40A

4

3

B

CH1 10A

CH3 20V

ꢀ

CH2 200mV

CH4 5V

M2ms

T 75.6%

CH1 10A

CH3 20V

ꢀ

CH2 5V

CH4 200mV

M2ms

T 15.6%

A CH1

6.20A

W

B

W

Figure 47. Load Transient Step—PSM Enabled, 12 A

(See Figure 93 Application Circuit)

Figure 50. Load Transient Step—Forced PWM at Light Load, 12 A

(See Figure 93 Application Circuit)

OUTPUT VOLTAGE

4

2

12A POSITIVE STEP

SW NODE

1

2

3

LOW SIDE

1

3

SW NODE

LOW SIDE

4

B

CH1 10A ꢀ CH2 200mV

CH3 20V CH4 5V

M20µs

T 30.6%

A CH1

3.40A

CH1 10A ꢀ CH2 5V

M20µs

T 43.8%

A CH1

6.20A

W

B

CH3 20V

CH4 200mV

W

Figure 48. Positive Step During Heavy Load Transient Behavior—PSM Enabled,

12 A, V_OUT= 1.8 V (See Figure 93 Application Circuit)

Figure 51. Positive Step During Heavy Load Transient Behavior—Forced PWM

at Light Load, 12 A, V_OUT= 1.8 V (See Figure 93 Application Circuit)

Rev. 0 | Page 14 of 44

ADP1870/ADP1871

OUTPUT VOLTAGE

2

1

INDUCTOR CURRENT

12A NEGATIVE STEP

2

4

1

SW NODE

LOW SIDE

3

4

SW NODE

B

LOW

SIDE

3

B

CH1 10A ꢀ CH2 200mV

M10µs

A CH1

5.60A

CH1 2V

CH2 5A

CH4 5V

ꢀ

M2ms

T 32.8%

A CH1

720mV

W

CH3 20V

CH4 5V

T 23.8%

CH3 10V

Figure 52. Negative Step During Heavy Load Transient Behavior—Forced PWM

at Light Load, 12 A (See Figure 93 Application Circuit)

Figure 55. Start-Up Behavior at Heavy Load, 12 A, 300 kHz

(See Figure 93 Application Circuit)

OUTPUT VOLTAGE

1

INDUCTOR CURRENT

2

INDUCTOR CURRENT

LOW SIDE

2

4

SW NODE

3

B

CH1 2V

CH3 10V

CH2 5A

CH4 5V

ꢀ

M4ms

T 49.4%

A CH1

920mV

CH1 2V

CH3 10V

CH2 5A

CH4 5V

ꢀ

M4ms

T 41.6%

A CH1

720mV

W

Figure 53. Output Short-Circuit Behavior Leading to Hiccup Mode

Figure 56. Power-Down Waveform During Heavy Load

1

OUTPUT VOLTAGE

1

2

INDUCTOR CURRENT

2

SW NODE

3

4

LOW SIDE

4

B

CH1 5V

CH3 10V

CH2 10A

CH4 5V

ꢀ

M10µs

T 36.2%

A CH2

8.20A

CH1 50mV

CH2 5A

CH4 5V

ꢀ

M2µs

T 35.8%

A CH2

3.90A

W

B

CH3 10V

W

Figure 57. Output Voltage Ripple Waveform During PSM Operation

at Light Load, 2 A

Figure 54. Magnified Waveform During Hiccup Mode

Rev. 0 | Page 15 of 44

ADP1870/ADP1871

18ns (

t

)

,DRVL

LOW SIDE

r

OUTPUT VOLTAGE

1

4

HIGH SIDE

24ns (

t

)

pdh,DRVL

LOW SIDE

4

HS MINUS

SW

11ns (t _,DRVH

f

)

SW NODE

3

SW NODE

3

2

M

INDUCTOR CURRENT

2

T

= 25°C

A

B

CH1 1V

CH3 10V

CH2 5A

CH4 2V

ꢀ

M1ms

T 63.2%

A CH1

1.56V

CH2 5V

CH4 2V

M20ns

T 39.2%

A CH2

4.20V

W

B

CH3 5V

MATH 2V 20ns

W

Figure 58. Soft Start and RES Detect Waveform

Figure 61. Upper-Side Driver Falling and Lower-Side Rising Edge Waveforms

(C_IN= 4.3 nF (Upper-/Lower-Side MOSFET),

Q

_TOTAL= 27 nC (V_GS= 4.4 V (Q1), V_GS= 5 V (Q3))

V

= 5.5V

= 3.6V

= 2.7V

REG

T

= 25°C

A

570

550

530

510

490

470

450

430

LOW SIDE

4

HIGH SIDE

SW NODE

3

2

M

HS MINUS

SW

–40

–20

0

20

40

60

80

100

120

CH2 5V

CH4 2V

M40ns

T 29.0%

A CH2

4.20V

CH3 5V

MATH 2V 40ns

TEMPERATURE (°C)

Figure 59. Output Drivers and SW Node Waveforms

Figure 62. Transconductance (G_m) vs. Temperature

680

630

580

530

480

430

380

330

T

= 25°C

+125°C

+25°C

–40°C

A

LOW SIDE

16ns (t _,DRVL)

f

4

22ns (

t

)

pdhDRVH

HIGH SIDE

25ns (

t

)

,DRVH

r

SW NODE

3

2

HS MINUS

SW

M

CH2 5V

CH4 2V

M40ns

T 29.0%

A CH2

4.20V

2.7

3.0

3.3

3.6

3.9

V

4.2

(V)

4.5

4.8

5.1

5.4

CH3 5V

MATH 2V 40ns

REG

Figure 63. Transconductance (G_m) vs. V_REG

Figure 60. Upper-Side Driver Rising and Lower-Side Falling Edge Waveforms

(C_IN= 4.3 nF (Upper-/Lower-Side MOSFET),

Q_TOTAL= 27 nC (V_GS= 4.4 V (Q1), V_GS= 5 V (Q3))

Rev. 0 | Page 16 of 44

ADP1870/ADP1871

1.30

1.25

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

0.80

0.75

0.70

+125°C

+25°C

–40°C

2.7

3.1

3.5

3.9

4.3

(V)

4.7

5.1

5.5

V

REG

Figure 64. Quiescent Current vs. V_REG

Rev. 0 | Page 17 of 44

ADP1870/ADP1871

ADP1870/ADP1871 BLOCK DIAGRAM

VREG

ADP1870/ADP1871

t_ONTIMER

VIN

C

PRECISION

ENABLE BLOCK

TO ENABLE

ALL BLOCKS

I

LDO

SW

INFORMATION

R (TRIMMED)

VREG

t_ON= 2RC(V

/V

)

OUT IN

REF

SW FILTER

VREG

BST

BIAS BLOCK

AND REFERENCE

STATE

MACHINE

REF_ZERO

TON

I

SS

DRVH

SW

BG_REF

SS

COMP

PSM

300kꢀ

8kꢀ

BG_REF

LEVEL

SHIFT

HS

LS

HI

C

SS

SS_REF

COMP/

EN

SW

LO

INL_HICC

ERROR

AMP

FB

VREG

BG_REF

DRVL

PGND

0.6V

PWM

I

REV

COMP

CS

AMP

LOWER

COMP

CLAMP

RES DETECT AND

GAIN SET

REF_ZERO

ADC

CS GAIN SET

0.4V

GND

Figure 65. ADP1870/ADP1871 Block Diagram

Rev. 0 | Page 18 of 44

ADP1870/ADP1871

THEORY OF OPERATION

ADP1870/ADP1871, reducing the supply current of the devices

to approximately 140 μA. For more information, see Figure 67.

The ADP1870/ADP1871 are versatile current-mode, synchronous

step-down controllers that provide superior transient response,

optimal stability, and current limit protection by using a constant

on-time, pseudo-fixed frequency with a programmable current-

sense gain, current-control scheme. In addition, these devices offer

optimum performance at low duty cycles by utilizing valley

current-mode control architecture. This allows the ADP1870/

ADP1871 to drive all N-channel power stages to regulate output

voltages as low as 0.6 V.

ADP1870/ADP1871

FB

VREG

SS

ERROR

AMPLIFIER

0.6V

COMP/EN

STARTUP

C

PRECISION

ENABLE

C

C2

R

C

The ADP1870/ADP1871 have an internal regulator (VREG) for

biasing and supplying power for the integrated MOSFET drivers.

A bypass capacitor should be located directly across the VREG

(Pin 5) and PGND (Pin 7) pins. Included in the power-up sequence

is the biasing of the current-sense amplifier, the current-sense

gain circuit (see the Programming Resistor (RES) Detect Circuit

section), the soft start circuit, and the error amplifier.

TO ENABLE

ALL BLOCKS

285mV

Figure 66. Release COMP/EN Pin to Enable the ADP1870/ADP1871

COMP/EN

The current-sense blocks provide valley current information

(see the Programming Resistor (RES) Detect Circuit section)

and are a variable of the compensation equation for loop stability

(see the Compensation Network section). The valley current

information is extracted by forcing 0.4 V across the DRVL output

and PGND pin, which generates a current depending on the

resistor across DRVL and PGND in a process performed by the

RES detect circuit. The current through the resistor is used to set

the current-sense amplifier gain. This process takes approximately

800 μs, after which the drive signal pulses appear at the DRVL

and DRVH pins synchronously and the output voltage begins to

rise in a controlled manner through the soft start sequence.

>2.4V

2.4V

HICCUP MODE INITIALIZED

MAXIMUM CURRENT (UPPER CLAMP)

1.0V

ZERO CURRENT

USABLE RANGE ONLY AFTER SOFT START

PERIOD IF CONTUNUOUS CONDUCTION

MODE OF OPERATION IS SELECTED.

500mV

LOWER CLAMP

285mV

0V

PRECISION ENABLE THRESHOLD

35mV HYSTERESIS

The rise time of the output voltage is determined by the soft

start and error amplifier blocks (see the Soft Start section). At

the beginning of a soft start, the error amplifier charges the

external compensation capacitor, causing the COMP/EN pin to

rise above the enable threshold of 285 mV, thus enabling the

ADP1870/ADP1871.

Figure 67. COMP/EN Voltage Range

UNDERVOLTAGE LOCKOUT

The undervoltage lockout (UVLO) feature prevents the part from

operating both the upper- and lower-side MOSFETs at extremely

low or undefined input voltage (V_IN) ranges. Operation at an

undefined bias voltage may result in the incorrect propagation

of signals to the high-side power switches. This, in turn, results

in invalid output behavior that can cause damage to the output

devices, ultimately destroying the device tied at the output. The

UVLO level has been set at 2.65 V (nominal).

SOFT START

The ADP1870/ADP1871 have digital soft start circuitry, which

involves a counter that initiates an incremental increase in current,

by 1 μA, via a current source on every cycle through a fixed internal

capacitor. The output tracks the ramping voltage by producing

PWM output pulses to the upper-side MOSFET. The purpose is to

limit the in-rush current from the high voltage input supply (V_IN)

to the output (V_OUT).

ON-BOARD LOW DROPOUT REGULATOR

The ADP1870 uses an on-board LDO to bias the internal digital

and analog circuitry. With proper bypass capacitors connected

to the VREG pin (output of internal LDO), this pin also provides

power for the internal MOSFET drivers. It is recommended to

float VREG if VIN is utilized for greater than 5.5 V operation.

The minimum voltage where bias is guaranteed to operate is

2.75 V at VREG.

PRECISION ENABLE CIRCUITRY

The ADP1870/ADP1871 employ precision enable circuitry. The

enable threshold is 285 mV typical with 35 mV of hysteresis.

The devices are enabled when the COMP/EN pin is released,

allowing the error amplifier output to rise above the enable

threshold (see Figure 66). Grounding this pin disables the

For applications where VIN is decoupled from VREG, the

minimum voltage at VIN must be 2.9 V. It is recommended that

Rev. 0 | Page 19 of 44

ADP1870/ADP1871

VIN and VREG be tied together if the VIN pin is subjected to a

2.75 V rail.

SW

CS

AMP

PGND

Table 5. Power Input and LDO Output Configurations

ADC

VIN

VREG

Comments

CS GAIN SET

DRVL

0.4V

>5.5 V

<5.5 V

Float

Must use the LDO

Connect to VIN

LDO drop voltage is not

realized (that is, if V_IN=

2.75 V, then V_REG= 2.75

V)

RES

<5.5 V

Float

LDO drop is realized

Ranges above

and below 5.5

V

LDO drop is realized,

minimum V_INrecom-

mendation is 2.95 V

Figure 69. RES Detect Circuit for Current-Sense Gain Programming

Table 6. Current-Sense Gain Programming

Resistor

A_CS

47 kΩ

22 kΩ

Open

100 kΩ

3 V/V

6 V/V

12 V/V

24 V/V

THERMAL SHUTDOWN

The thermal shutdown is a self-protection feature to prevent the

IC from damage due to a very high operating junction temperature.

If the junction temperature of the device exceeds 155°C, the part

enters the thermal shutdown state. In this state, the device shuts off

both the upper- and lower-side MOSFETs and disables the entire

controller immediately, thus reducing the power consumption of

the IC. The part resumes operation after the junction temperature

of the part cools to less than 140°C.

VALLEY CURRENT-LIMIT SETTING

The architecture of the ADP1870/ADP1871 is based on valley

current-mode control. The current limit is determined by three

components: the R_ONof the lower-side MOSFET, the error ampli-

fier output voltage swing (COMP), and the current-sense gain.

The COMP range is internally fixed at 1.4 V. The current-sense

gain is programmable via an external resistor at the DRVL pin (see

the Programming Resistor (RES) Detect Circuit section). The

PROGRAMMING RESISTOR (RES) DETECT CIRCUIT

Upon startup, one of the first blocks to become active is the RES

detect circuit. This block powers up before soft start begins. It

forces a 0.4 V reference value at the DRVL output (see Figure 68)

and is programmed to identify four possible resistor values: 47 kΩ,

22 kΩ, open, and 100 kΩ.

R_ONof the lower-side MOSFET can vary over temperature and

usually has a positive T_C(meaning that it increases with tempera-

ture); therefore, it is recommended to program the current-sense

gain resistor based on the rated R_ONof the MOSFET at 125°C.

The RES detect circuit digitizes the value of the resistor at the

DRVL pin (Pin 6). An internal ADC outputs a 2-bit digital code

that is used to program four separate gain configurations in the

current-sense amplifier (see Figure 69). Each configuration corre-

sponds to a current-sense gain (A_CS) of 3 V/V, 6 V/V, 12 V/V,

24 V/V, respectively (see Table 6 and Table 7). This variable is used

for the valley current-limit setting, which sets up the appropriate

current-sense gain for a given application and sets the compensation

necessary to achieve loop stability (see the Valley Current-Limit

Setting and Compensation Network sections).

Because the ADP1870/ADP1871 are based on valley current

control, the relationship between I_CLIMand I_LOADis as follows:

K_I

2

⎛

⎝

⎞

⎟

⎠

I_CLIM= I_LOAD× 1 −

⎜

where:

K_Iis the ratio between the inductor ripple current and the

desired average load current (see Figure 70).

I_CLIMis the desired valley current limit.

I_LOADis the current load.

ADP1870/

ADP1871

Q1

Establishing K_Ihelps to determine the inductor value (see the

Inductor Selection section), but in most cases K_I= 0.33.

DRVH

SW

Q2

DRVL

I

LOAD

3

RIPPLE CURRENT =

R

RES

CS GAIN

PROGRAMMING

LOAD CURRENT

Figure 68. Programming Resistor Location

VALLEY CURRENT LIMIT

Figure 70. Valley Current Limit to Average Current Relation

Rev. 0 | Page 20 of 44

ADP1870/ADP1871

When the desired valley current limit (I_CLIM) has been determined,

the current-sense gain can be calculated as follows:

The valley current limit is programmed as outlined in Table 7

and Figure 71. The inductor chosen must be rated to handle the

peak current, which is equal to the valley current from Table 7

plus the peak-to-peak inductor ripple current (see the Inductor

Selection section). In addition, the peak current value must be

used to compute the worst-case power dissipation in the

MOSFETs (see Figure 72).

1.4 V

I_CLIM

=

A

_CS×R_ON

where:

_ONis the channel impedance of the lower-side MOSFET.

R

49A

A_CSis the current-sense gain multiplier (see Table 6 and Table 7).

MAXIMUM DC LOAD

CURRENT

Although the ADP1870/ADP1871 have only four discrete current-

sense gain settings for a given R_ONvariable, Table 7 and Figure 71

outline several available options for the valley current setpoint

based on various R_ONvalues.

39.5A

ΔI = 65%

OF 37A

INDUCTOR

CURRENT

COMP

OUTPUT

37A

35A

ΔI = 45%

OF 32.25A

32.25A

Table 7. Valley Current Limit Program¹

ΔI = 33%

OF 30A

30A

Valley Current Level

2.4V

47 kΩ

22 kΩ

Open

100 kΩ

A_CS= 24 V/V

38.9

29.2

23.3

19.5

16.7

13

11.7

10.6

5.83

7.5

3.25

R_ON

(mΩ) A_CS= 3 V/V

A_CS= 6 V/V

A_CS= 12 V/V

VALLEY CURRENT-LIMIT

THRESHOLD (SET FOR 25A)

1.5

2

2.5

3

3.5

4.5

5

5.5

10

COMP

OUTPUT

SWING

39.0

33.4

26.0

23.4

21.25

11.7

7.75

6.5

0A

1V

Figure 72. Valley Current-Limit Threshold in Relation to Inductor Ripple Current

23.3

15.5

13.0

HICCUP MODE DURING SHORT CIRCUIT

15

18

31.0

26.0

A current-limit violation occurs when the current across the

source and drain of the lower-side MOSFET exceeds the

current-limit setpoint. When 32 current-limit violations are

detected, the controller enters idle mode and turns off the

MOSFETs for 6 ms, allowing the converter to cool down. Then,

the controller reestablishes soft start and begins to cause the

output to ramp up again (see Figure 73). While the output

ramps up, COMP is monitored to determine if the violation is

still present. If it is still present, the idle event occurs again,

followed by the full-chip power-down sequence. This cycle

continues until the violation no longer exists. If the violation

disappears, the converter is allowed to switch normally,

maintaining regulation.

¹Refer to Figure 71 for more information and a graphical representation.

39

37

35

RES = 47kꢀ

= 3V/V

33

31

29

27

25

23

21

19

17

15

13

11

9

A

CS

RES = 22kꢀ

= 6V/V

A

RES = NO RES

= 12V/V

CS

A

CS

RES = 100kꢀ

A

= 24V/V

7

CS

5

3

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

(mꢀ)

R

ON

Figure 71. Valley Current-Limit Value vs. R_ONof the Lower-Side MOSFET

for Each Programming Resistor (RES)

REPEATED CURRENT-LIMIT

VIOLATION DETECTED

HS

A PREDETERMINED NUMBER SOFT START IS

OF PULSES IS COUNTED TO REINITIALIZED TO

ALLOW THE CONVERTER MONITOR IF THE

CLIM

TO COOL DOWN

VIOLATION

STILL EXISTS

ZERO

CURRENT

Figure 73. Idle Mode Entry Sequence Due to Current-Limit Violation

Rev. 0 | Page 21 of 44

ADP1870/ADP1871

As soon as the forward current through the lower-side

MOSFET decreases to a level where

SYNCHRONOUS RECTIFIER

The ADP1870/ADP1871 employ an internal lower-side MOSFET

driver to drive the external upper- and lower-side MOSFETs.

The synchronous rectifier not only improves overall conduction

efficiency, but also ensures proper charging to the bootstrap

capacitor located at the upper-side driver input. This is beneficial

during startup to provide sufficient drive signal to the external

upper-side MOSFET and to attain fast turn-on response, which is

essential for minimizing switching losses. The integrated upper-

and lower-side MOSFET drivers operate in complementary

fashion with built-in anticross conduction circuitry to prevent

unwanted shoot-through current that may potentially damage the

MOSFETs or reduce efficiency as a result of excessive power loss.

10 mV = I_Q2× R_ON(Q2)

the zero-cross comparator (or I_REVcomparator) emits a signal to

turn off the lower-side MOSFET. From this point, the slope of the

inductor current ramping down becomes steeper (see Figure 76)

as the body diode of the lower-side MOSFET begins to conduct

current and continues conducting current until the remaining

energy stored in the inductor has been depleted.

ANOTHER t_ONEDGE IS

TRIGGERED WHEN V

OUT

FALLS BELOW REGULATION

SW

t_ON

POWER SAVING MODE (PSM) VERSION (ADP1871)

The power saving mode version of the ADP1870 is the ADP1871.

The ADP1871 operates in the discontinuous conduction mode

(DCM) and pulse skips at light load to mid load currents. It

outputs pulses as necessary to maintain output regulation. Unlike

the continuous conduction mode (CCM), DCM operation

prevents negative current, thus allowing improved system

efficiency at light loads. Current in the reverse direction through

this pathway, however, results in power dissipation and therefore

a decrease in efficiency.

HS AND LS

IN IDLE MODE

LS

ZERO-CROSS COMPARATOR

DETECTS 10mV OFFSET AND

TURNS OFF LS

I

LOAD

0A

10mV = R

× I

LOAD

ON

HS

Figure 76. 10 mV Offset to Ensure Prevention of Negative Inductor Current

t_ON

The system remains in idle mode until the output voltage drops

below regulation. A PWM pulse is then produced, turning on the

upper-side MOSFET to maintain system regulation. The

ADP1871 does not have an internal clock, so it switches purely

as a hysteretic controller as described in this section.

HS AND LS ARE OFF

OR IN IDLE MODE

LS

t_OFF

TIMER OPERATION

The ADP1870/ADP1871 employ a constant on-time architecture,

which provides a variety of benefits, including improved load

and line transient response when compared with a constant

(fixed) frequency current-mode control loop of comparable

loop design. The constant on-time timer, or t_ONtimer, senses

the high input voltage (V_IN) and the output voltage (V_OUT) using

SW waveform information to produce an adjustable one-shot

PWM pulse that varies the on-time of the upper-side MOSFET in

response to dynamic changes in input voltage, output voltage, and

load current conditions to maintain regulation. It then generates

an on-time (t_ON) pulse that is inversely proportional to V_IN.

AS THE INDUCTOR

CURRENT APPROACHES

ZERO CURRENT, THE STATE

I

LOAD

MACHINE TURNS OFF THE

LOWER-SIDE MOSFET.

0A

Figure 74. Discontinuous Mode of Operation (DCM)

To minimize the chance of negative inductor current buildup,

an on-board zero-cross comparator turns off all upper- and

lower-side switching activities when the inductor current

approaches the zero current line, causing the system to enter

idle mode, where the upper- and lower-side MOSFETs are

turned off. To ensure idle mode entry, a 10 mV offset, connected

in series at the SW node, is implemented (see Figure 75).

ZERO-CROSS

V_OUT

t_ON= K ×

V_IN

where:

SW

COMPARATOR

K is a constant that is trimmed using an RC timer product for

the 300 kHz, 600 kHz, and 1.0 MHz frequency options.

I

Q2

10mV

Q2

LS

Figure 75. Zero-Cross Comparator with 10 mV of Offset

Rev. 0 | Page 22 of 44

ADP1870/ADP1871

V

IN

VREG

To illustrate this feature more clearly, this section describes

one such load transient event—a positive load step—in detail.

During load transient events, the high-side driver output pulse

width stays relatively consistent from cycle to cycle; however,

the off-time (DRVL on-time) dynamically adjusts according to

the instantaneous changes in the external conditions mentioned.

t_ON

C

I

SW

INFORMATION

When a positive load step occurs, the error amplifier (out of phase

of the output, V_OUT) produces new voltage information at its output

(COMP). In addition, the current-sense amplifier senses new

inductor current information during this positive load transient

event. The error amplifier’s output voltage reaction is compared

with the new inductor current information that sets the start of

the next switching cycle. Because current information is produced

from valley current sensing, it is sensed at the down ramp of the

inductor current, whereas the voltage loop information is sensed

through the counter action upswing of the error amplifier’s

output (COMP).

R (TRIMMED)

Figure 77. Constant On-Time Time

The constant on-time (t_ON) is not strictly “constant” because it

varies with V_INand V_OUT. However, this variation occurs in such

a way as to keep the switching frequency virtually independent

of V_INand V_OUT

.

The t_ONtimer uses a feedforward technique, applied to the constant

on-time control loop, making it a pseudo-fixed frequency to a first

order. Second-order effects, such as dc losses in the external power

MOSFETs (see the Efficiency Consideration section), cause some

variation in frequency vs. load current and line voltage. These

effects are shown in Figure 23 to Figure 34. The variations in

frequency are much reduced compared with the variations

generated when the feedforward technique is not utilized.

The result is a convergence of these two signals (see Figure 78),

which allows an instantaneous increase in switching frequency

during the positive load transient event. In summary, a positive

load step causes V_OUTto transient down, which causes COMP to

transient up and therefore shortens the off-time. This resulting

increase in frequency during a positive load transient helps to

quickly bring V_OUTback up in value and within the regulation

window.

The feedforward technique establishes the following relationship:

1

f_SW

=

K

where f_SWis the controller switching frequency (300 kHz,

600 kHz, and 1.0 MHz).

Similarly, a negative load step causes the off-time to lengthen in

response to V_OUTrising. This effectively increases the inductor

demagnetizing phase, helping to bring V_OUTwithin regulation.

In this case, the switching frequency decreases, or experiences a

foldback, to help facilitate output voltage recovery.

The t_ONtimer senses V_INand V_OUTto minimize frequency

variation as previously explained. This provides a pseudo-fixed

frequency as explained in the Pseudo-Fixed Frequency section.

To allow headroom for V_INand V_OUTsensing, adhere to the

following equations:

Because the ADP1870/ADP1871 has the ability to respond rapidly

to sudden changes in load demand, the recovery period in which

the output voltage settles back to its original steady state operating

point is much quicker than it would be for a fixed-frequency

equivalent. Therefore, using a pseudo-fixed frequency results in

significantly better load transient performance than using a

fixed frequency.

V

_REG≥ V_IN/8 + 1.5

V_REG≥ V_OUT/4

For typical applications where V_REGis 5 V, these equations are

not relevant; however, for lower V_REGinputs, care may be

required.

PSEUDO-FIXED FREQUENCY

The ADP1870/ADP1871 employ a constant on-time control

scheme. During steady state operation, the switching frequency

stays relatively constant, or pseudo-fixed. This is due to the one-

shot t_ONtimer that produces a high-side PWM pulse with a

“fixed” duration, given that external conditions such as input

voltage, output voltage, and load current are also at steady state.

During load transients, the frequency momentarily changes for

the duration of the transient event so that the output comes

back within regulation more quickly than if the frequency were

fixed or if it were to remain unchanged. After the transient

event is complete, the frequency returns to a pseudo-fixed

frequency value to a first order.

LOAD CURRENT

DEMAND

CS AMP

OUTPUT

ERROR AMP

OUTPUT

VALLEY

TRIP POINTS

PWM OUTPUT

f_SW

>f_SW

Figure 78. Load Transient Response Operation

Rev. 0 | Page 23 of 44

ADP1870/ADP1871

APPLICATIONS INFORMATION

Table 8. Recommended Inductors

FEEDBACK RESISTOR DIVIDER

L

DCR

I_SAT

Dimensions

(mm)

Model

The required resistor divider network can be determined for a

given V_OUTvalue because the internal band gap reference (V_REF

is fixed at 0.6 V. Selecting values for R_Tand R_Bdetermines the

minimum output load current of the converter. Therefore, for a

given value of R_B, the R_Tvalue can be determined through the

following expression:

(μH) (mΩ) (A)

Manufacturer

Würth Elek.

AIC Technology

Number

)

0.12

0.22

0.47

0.72

0.9

0.33

0.67

1.3

55

30

50

35

28

25

20

24

22

10.2 × 7

744303012

744303022

744355147

744325072

744355090

744325120

7443552100

744318180

7443551200

CEP125U-R80

10.2 × 7

13.2 × 12.8

10.5 × 10.2

13 × 12.8

10.5 × 10.2

14 × 12.8

13.2 × 12.8

1.6

1.2

1.8

(V_OUT−0.6 V)

R_T= R_B×

1.0

3.3

0.6 V

1.4

3.2

2.0

2.6

INDUCTOR SELECTION

0.8

2.5

16.5 12.5 × 12.5

The inductor value is inversely proportional to the inductor

ripple current. The peak-to-peak ripple current is given by

OUTPUT RIPPLE VOLTAGE (ΔV_RR)

I_LOAD

3

The output ripple voltage is the ac component of the dc output

voltage during steady state. For a ripple error of 1.0%, the

output capacitor value needed to achieve this tolerance can be

determined using the following equation. (Note that an

accuracy of 1.0% is possible only during steady state conditions,

not during load transients.)

ΔI_L= K _I× I_LOAD

≈

where K_Iis typically 0.33.

The equation for the inductor value is given by

(V_IN−V_OUT

ΔI_L× f_SW

)

V_OUT

V_IN

L =

×

ΔV_RR= (0.01)×V_OUT

where:

V_INis the high voltage input.

_OUTis the desired output voltage.

_SWis the controller switching frequency (300 kHz, 600 kHz, and

OUTPUT CAPACITOR SELECTION

The primary objective of the output capacitor is to facilitate the

reduction of the output voltage ripple; however, the output

capacitor also assists in the output voltage recovery during load

transient events. For a given load current step, the output

voltage ripple generated during this step event is inversely

proportional to the value chosen for the output capacitor. The

speed at which the output voltage settles during this recovery

period depends on where the crossover frequency (loop

bandwidth) is set. This crossover frequency is determined by

the output capacitor, the equivalent series resistance (ESR) of

the capacitor, and the compensation network.

V

f

1.0 MHz).

When selecting the inductor, choose an inductor saturation

rating that is above the peak current level, and then calculate

the inductor current ripple (see the Valley Current-Limit

Setting section and Figure 79).

52

50

ΔI = 50%

ΔI = 40%

48

46

44

42

40

38

36

34

32

30

28

26

24

22

20

18

16

14

12

10

8

To calculate the small-signal voltage ripple (output ripple

voltage) at the steady state operating point, use the following

equation:

ΔI = 33%

⎛

⎜

⎝

⎞

⎟

⎠

1

C_OUT= ΔI_L×

8× f_SW

×

[

ΔV_RIPPLE−(ΔI_L×ESR)

]

where ESR is the equivalent series resistance of the output

capacitors.

To calculate the output load step, use the following equation:

6

8

10 12 14 16 18 20 22 24 26 28 30

VALLEY CURRENT LIMIT (A)

ΔI_LOAD

C_OUT= 2 ×

Figure 79. Peak Inductor Current vs. Valley Current Limit for 33%, 40%, and

50% of Inductor Ripple Current

f_SW×(ΔV_DROOP− (ΔI_LOAD× ESR))

where ΔV_DROOPis the amount that V_OUTis allowed to deviate for

a given positive load current step (ΔI_LOAD).

Rev. 0 | Page 24 of 44

ADP1870/ADP1871

Ceramic capacitors are known to have low ESR. However, the

trade-off of using X5R technology is that up to 80% of its capaci-

tance might be lost due to derating as the voltage applied across

the capacitor is increased (see Figure 80). Although X7R series

capacitors can also be used, the available selection is limited to

only up to 22 μF.

Error Amplifier Output Impedance (Z_COMP

)

Assuming that C_C2is significantly smaller than C_COMP, C_C2can

be omitted from the output impedance equation of the error

amplifier. The transfer function simplifies to

R

_COMP( f_CROSS+ f_ZERO)

Z_COMP

=

f_CROSS

20

10

and

X7R (50V)

0

1

12

f_CROSS

=

× f_SW

–10

–20

–30

–40

where f_ZERO, the zero frequency, is set to be 1/4^thof the crossover

frequency for the ADP1870.

–50

Error Amplifier Gain (G_M)

The error amplifier gain (transconductance) is

G_M= 500 μA/V

X5R (25V)

–60

–70

X5R (16V)

–80

10µF TDK 25V, X7R, 1210 C3225X7R1E106M

22µF MURATA 25V, X7R, 1210 GRM32ER71E226KE15L

47µF MURATA 16V, X5R, 1210 GRM32ER61C476KE15L

–90

Current-Sense Loop Gain (G_CS)

The current-sense loop gain is

1

–100

0

5

10

15

20

25

30

DC VOLTAGE (V

)

DC

G_CS

=

(A/V)

Figure 80. Capacitance vs. DC Voltage Characteristics for Ceramic Capacitors

A

_CS×R_ON

Electrolytic capacitors satisfy the bulk capacitance requirements

for most high current applications. Because the ESR of electrolytic

capacitors is much higher than that of ceramic capacitors, when

using electrolytic capacitors, several MLCCs should be mounted

in parallel to reduce the overall series resistance.

where:

A_CS(V/V) is programmable for 3 V/V, 6 V/V, 12 V/V, and 24 V/V

(see the Programming Resistor (RES) Detect Circuit and Valley

Current-Limit Setting sections).

R_ONis the channel impedance of the lower-side MOSFET.

COMPENSATION NETWORK

Crossover Frequency

Due to their current-mode architecture, the ADP1870/ADP1871

require Type II compensation. To determine the component

values needed for compensation (resistance and capacitance

values), it is necessary to examine the converter’s overall loop

gain (H) at the unity gain frequency (f_SW/10) when H = 1 V/V:

The crossover frequency is the frequency at which the overall

loop (system) gain is 0 dB (H = 1 V/V). For current-mode

converters, such as the ADP1870, it is recommended that the

user set the crossover frequency between 1/10^thand 1/15^thof the

switching frequency.

V_OUT

1

H =1 V/V = G_M×G_CS

×

× Z_COMP× Z_FILT

f_CROSS

=

f_SW

V_REF

12

The relationship between C_COMPand f_ZERO(zero frequency) is as

follows:

Examining each variable at high frequency enables the unity-

gain transfer function to be simplified to provide expressions

for the R_COMPand C_COMPcomponent values.

1

)

f _ZERO

=

2π× R_COMP×C_COMP

Output Filter Impedance (Z_FILT

)

The zero frequency is set to 1/4^thof the crossover frequency.

Combining all of the above parameters results in

Examining the filter’s transfer function at high frequencies

simplifies to

1

Z_FILTER

=

f_CROSS

2πf_CROSSC_OUTV_OUT

R_COMP

=

×

sC_OUT

at the crossover frequency (s = 2πf_CROSS).

f_CROSS+ f_ZERO

G_MG_CS

V_REF

1

C_COMP

2×π×R_COMP× f_ZERO

Rev. 0 | Page 25 of 44

ADP1870/ADP1871

800

720

640

560

480

400

320

240

160

80

EFFICIENCY CONSIDERATIONS

V

= 2.7V

= 3.6V

= 5.5V

REG

One of the important criteria to consider in constructing a dc-to-dc

converter is efficiency. By definition, efficiency is the ratio of the

output power to the input power. For high power applications at

load currents up to 20 A, the following are important MOSFET

parameters that aid in the selection process:

•

V_{GS (TH)}: the MOSFET support voltage applied between the

gate and the source

•

R_{DS (ON)}: the MOSFET on resistance during channel

conduction

+125°C

+25°C

–40°C

•

Q_G: the total gate charge

C_N1: the input capacitance of the upper-side switch

C_N2: the input capacitance of the lower-side switch

300

400

500

600

700

800

900

1000

SWITCHING FREQUENCY (kHz)

Figure 81. Internal Rectifier Voltage Drop vs. Switching Frequency

The following are the losses experienced through the external

component during normal switching operation:

Switching Loss

The SW node transitions due to the switching activities of the

upper- and lower-side MOSFETs. This causes removal and

replenishing of charge to and from the gate oxide layer of the

MOSFET, as well as to and from the parasitic capacitance

associated with the gate oxide edge overlap and the drain and

source terminals. The current that enters and exits these charge

paths presents additional loss during these transition times. This

loss can be approximately quantified by using the following

equation, which represents the time in which charge enters and

exits these capacitive regions:

•

Channel conduction loss (both of the MOSFETs)

MOSFET driver loss

MOSFET switching loss

Body diode conduction loss (lower-side MOSFET)

Inductor loss (copper and core loss)

Channel Conduction Loss

During normal operation, the bulk of the loss in efficiency is due

to the power dissipated through MOSFET channel conduction.

Power loss through the upper-side MOSFET is directly pro-

portional to the duty cycle (D) for each switching period, and

the power loss through the lower-side MOSFET is directly

proportional to 1 − D for each switching period. The selection

of MOSFETs is governed by the amount of maximum dc load

current that the converter is expected to deliver. In particular,

the selection of the lower-side MOSFET is dictated by the

maximum load current because a typical high current application

employs duty cycles of less than 50%. Therefore, the lower-side

MOSFET is in the on state for most of the switching period.

t_SW-TRANS= R_GATE× C_TOTAL

where:

C_TOTALis the C_GD+ C_GSof the external MOSFET.

R_GATEis the gate input resistance of the external MOSFET.

The ratio of this time constant to the period of one switching cycle

is the multiplying factor to be used in the following expression:

t_SW-TRANS

P_SW(LOSS)

=

× I_LOAD×V_IN×2

t_SW

× I_L²_OAD

or

P_N1,N2(CL)

=

[

D × R_N1(ON)

+

(1− D

)

× R_N2(ON)

]

P_SW(LOSS)= f_SW×R_GATE×C_TOTAL× I_LOAD×V_IN×2

MOSFET Driver Loss

Other dissipative elements are the MOSFET drivers. The con-

tributing factors are the dc current flowing through the driver

during operation and the Q_GATEparameter of the external MOSFETs.

P_{DR(LOSS )}

V_REG

=

[

V_DR

×

(

f_SWC_upperFETV_DR+ I_BIAS

)

]

+

[

×

(

f_SWC_lowerFETV_REG+ I_BIAS

)]

where:

C_upperFETis the input gate capacitance of the upper-side MOSFET.

C_lowerFETis the input gate capacitance of the lower-side MOSFET.

I_BIASis the dc current flowing into the upper- and lower-side drivers.

V_DRis the driver bias voltage (that is, the low input voltage

(V_REG) minus the rectifier drop (see Figure 81)).

V_REGis the bias voltage.

f_SWis the controller switching frequency (300 kHz, 600 kHz, and

1.0 MHz)

Rev. 0 | Page 26 of 44

ADP1870/ADP1871

Diode Conduction Loss

application to achieve minimal loss and negligible electromagnetic

interference (EMI).

The ADP1870/ADP1871 employ anticross conduction circuitry

that prevents the upper- and lower-side MOSFETs from conducting

current simultaneously. This overlap control is beneficial, avoiding

large current flow that may lead to irreparable damage to the

external components of the power stage. However, this blanking

period comes with the trade-off of a diode conduction loss

occurring immediately after the MOSFETs change states and

continuing well into idle mode. The amount of loss through the

body diode of the lower-side MOSFET during the antioverlap

state is given by the following expression:

P_DCR(LOSS)= DCR× I_L²_OAD

+ Core Loss

INPUT CAPACITOR SELECTION

The goal in selecting an input capacitor is to reduce or minimize

input voltage ripple and to reduce the high frequency source

impedance, which is essential for achieving predictable loop

stability and transient performance.

The problem with using bulk capacitors, other than their

physical geometries, is their large equivalent series resistance

(ESR) and large equivalent series inductance (ESL). Aluminum

electrolytic capacitors have such high ESR that they cause

undesired input voltage ripple magnitudes and are generally not

effective at high switching frequencies.

t_BODY(LOSS)

P_BODY(LOSS)

=

× I_LOAD×V_F×2

t_SW

where:

t_BODY(LOSS)is the body conduction time (refer to Figure 82 for

dead time periods).

If bulk capacitors are to be used, it is recommended that muli-

layered ceramic capacitors (MLCC) be used in parallel due to

their low ESR values. This dramatically reduces the input voltage

ripple amplitude as long as the MLCCs are mounted directly

across the drain of the upper-side MOSFET and the source

terminal of the lower-side MOSFET (see the Layout Considerations

section). Improper placement and mounting of these MLCCs

may cancel their effectiveness due to stray inductance and an

increase in trace impedance.

t_SWis the period per switching cycle.

V_Fis the forward drop of the body diode during conduction.

(Refer to the selected external MOSFET data sheet for more

information about the V_Fparameter.)

80

+125°C

+25°C

–40°C

1MHz

300kHz

72

64

56

48

40

32

24

16

8

V_OUT

×

(

V_IN−V_OUT

)

I_CIN,rms= I_LOAD,max

×

V_OUT

The maximum input voltage ripple and maximum input capacitor

rms current occur at the end of the duration of 1 − D while the

upper-side MOSFET is in the off state. The input capacitor rms

current reaches its maximum at Time D. When calculating the

maximum input voltage ripple, account for the ESR of the input

capacitor as follows:

2.7

3.4

4.1

4.8

5.5

V

(V)

REG

V_RIPPLE,max= V_RIPP+ (I_LOAD,max× ESR)

Figure 82. Body Diode Conduction Time vs. Low Voltage Input (V_REG

)

where:

Inductor Loss

V_RIPPis usually 1% of the minimum voltage input.

I_LOAD,maxis the maximum load current.

ESR is the equivalent series resistance rating of the input capacitor.

During normal conduction mode, further power loss is caused

by the conduction of current through the inductor windings,

which have dc resistance (DCR). Typically, larger sized inductors

have smaller DCR values.

Inserting V_RIPPLE,maxinto the charge balance equation to calculate

the minimum input capacitor requirement gives

The inductor core loss is a result of the eddy currents generated

within the core material. These eddy currents are induced by the

changing flux, which is produced by the current flowing through

the windings. The amount of inductor core loss depends on the

core material, the flux swing, the frequency, and the core volume.

Ferrite inductors have the lowest core losses, whereas powdered

iron inductors have higher core losses. It is recommended that

shielded ferrite core material type inductors be used with the

ADP1870/ADP1871 for a high current, dc-to-dc switching

I_LOAD,max

D(1− D)

f_SW

C_IN,min

=

×

V_RIPPLE,max

or

I_LOAD,max

4 f_SWV_RIPPLE,max

C_IN,min

=

where D = 50%.

Rev. 0 | Page 27 of 44

ADP1870/ADP1871

The maximum junction temperature allowed for the ADP1870/

ADP1871 ICs is 125°C. This means that the sum of the ambient

temperature (T_A) and the rise in package temperature (T_R),

which is caused by the thermal impedance of the package and

the internal power dissipation, should not exceed 125°C, as

dictated by the following expression:

THERMAL CONSIDERATIONS

The ADP1870/ADP1871 are used for dc-to-dc, step down, high

current applications that have an on-board controller, an on-board

LDO, and on-board MOSFET drivers. Because applications may

require up to 20 A of load current delivery and be subjected to

high ambient temperature surroundings, the selection of external

upper- and lower-side MOSFETs must be associated with careful

thermal consideration to not exceed the maximum allowable

junction temperature of 125°C. To avoid permanent or irreparable

damage if the junction temperature reaches or exceeds 155°C, the

part enters thermal shutdown, turning off both external MOSFETs,

and does not reenable until the junction temperature cools to

140°C (see the On-Board Low Dropout Regulator section).

T_J= T_R× T_A

where:

(1)

T_Ais the ambient temperature.

T_Jis the maximum junction temperature.

T_Ris the rise in package temperature due to the power

dissipated from within.

The rise in package temperature is directly proportional to its

thermal impedance characteristics. The following equation

represents this proportionality relationship:

In addition, it is important to consider the thermal impedance

of the package. Because the ADP1870/ADP1871 employ an on-

board LDO, the ac current (fxCxV) consumed by the internal

drivers to drive the external MOSFETs adds another element of

power dissipation across the internal LDO. Equation 3 shows the

power dissipation calculations for the integrated drivers and for

the internal LDO.

T_R= θ_JA× P_DR(LOSS)

(2)

where:

θ_JAis the thermal resistance of the package from the junction to

the outside surface of the die, where it meets the surrounding air.

P_DR(LOSS)is the overall power dissipated by the IC.

Table 9 lists the thermal impedance for the ADP1870/ADP1871,

which are available in a 10-lead MSOP.

The bulk of the power dissipated is due to the gate capacitance

of the external MOSFETs and current running through the on-

board LDO. The power loss equations for the MOSFET drivers

and internal low dropout regulator (see the MOSFET Driver

Loss section in the Efficiency Consideration section) are:

Table 9. Thermal Impedance for 10-lead MSOP

Parameter

Thermal Impedance

10-Lead MSOP θ_JA

2-Layer Board

4-Layer Board

213.1°C/W

171.7°C/W

P_DR(LOSS)= [V_DR× (f_SWC_upperFETV_DR+ I_BIAS)] +

[V_REG× (f_SWC_lowerFETV_REG+ I_BIAS)]

(3)

Figure 83 specifies the maximum allowable ambient temperature

that can surround the ADP1870/ADP1871 IC for a specified

high input voltage (V_IN). Figure 83 illustrates the temperature

derating conditions for each available switching frequency for

low, typical, and high output setpoints for the 10-lead MSOP

package. All temperature derating criteria are based on a

maximum IC junction temperature of 125°C.

where:

C_upperFETis the input gate capacitance of the upper-side MOSFET.

C_lowerFETis the input gate capacitance of the lower-side MOSFET.

I_BIASis the dc current (2 mA) flowing into the upper- and lower-

side drivers.

V_DRis the driver bias voltage (the low input voltage (V_REG

minus the rectifier drop (see Figure 81)).

V_REGis the LDO output/bias voltage.

)

150

600kHz

300kHz

1MHz

V

= 0.8V

OUT

140

130

120

110

100

90

= 1.8V

= HIGH SETPOINT

(4)

P_{DISS (LDO)}= P_{DR(LOSS )}+ (V_IN−V_REG)× ( f_SW×C_total×V_REG+ I_BIAS

)

where:

P_DISS(LDO)is the power dissipated through the pass device in the

LDO block across VIN and VREG.

80

70

C_totalis the C_GD+ C_GSof the external MOSFET.

V_REGis the LDO output voltage and bias voltage.

V_INis the high voltage input.

60

50

40

I_BIASis the dc input bias current.

P_DR(LOSS)is the MOSFET driver loss.

30

20

10

0

5.5

7.0

8.5 10.0 11.5 13.0 14.5 16.0 17.5 19.0

(V)

V

IN

Figure 83. Ambient Temperature vs. V_INfor 10-Lead MSOP (171°C/W),

4-Layer EVB, CIN = 4.3 nF (Upper-/Lower-Side MOSFET)

Rev. 0 | Page 28 of 44

ADP1870/ADP1871

For example, if the external MOSFET characteristics are θ_JA

(10-lead MSOP) = 171.2°C/W, f_SW= 300 kHz, I_BIAS= 2 mA,

Inductor

Determine inductor ripple current amplitude as follows:

C_upperFET= 3.3 nF, C_lowerFET= 3.3 nF, V_DR= 4.62 V, and V_REG= 5.0 V,

I_LOAD

3

then the power loss is

ΔI_L≈

= 5 A

P_{DR (LOSS )}

V_REG

=

(

[

V_DR

×

(

f _SWC _upperFETV_DR+ I _BIAS

)

]

so calculating for the inductor value

+

[

×

f _SWC _lowerFETV_REG+ I _BIAS

)]

= (4.62 × (300 ×10 ³× 3.3 ×10 ⁻⁹× 4.62 + 0.002 ))

(V_IN,MAX−V_OUT

ΔI_L× f_SW

)

V_OUT

V_IN,MAX

L =

×

+ (5.0 × (300 ×10 ³× 3.3 ×10 ⁻⁹× 5.0 + 0.002 ))

= 57.12 mW

(13.2 V −1.8 V) 1.8 V

×

=

5 V×300×10³13.2 V

P_DISS(LDO)= (V_IN−V_REG)×( f_SW×C_total×V_REG+ I_BIAS

)

= (13 V −5 V)×(300×10³×3.3×10⁻⁹×5+0.002)

= 1.03 μH

= 55.6 mW

The inductor peak current is approximately

15 A + (5 A × 0.5) = 17.5 A

P_DISS(TOTAL)= P_DISS(LDO)+ P_DR(LOSS)

= 77.13 mW + 55.6 mW

= 132.73 mW

Therefore, an appropriate inductor selection is 1.0 μH with

DCR = 3.3 mꢀ (Würth Elektronik 7443552100) from Table 8

with peak current handling of 20 A.

The rise in package temperature (for 10-lead MSOP) is

P_DCR(LOSS)= DCR×I_L²

T_R= θ_JA×P_DR(LOSS)

=171.2°C ×132.05 mW

= 22.7°C

= 0.003 × (15 A)²= 675 mW

Current Limit Programming

The valley current is approximately

15 A − (5 A × 0.5) = 12.5 A

Assuming a maximum ambient temperature environment of 85°C,

T_J= T_R×T_A= 22.7°C +85°C =107.72°C

Assuming a lower-side MOSFET R_ONof 4.5 mꢀ and 13 A as

the valley current limit from Table 7 and Figure 71 indicates, a

programming resistor (RES) of 100 kꢀ corresponds to an A_CS

of 24 V/V.

which is below the maximum junction temperature of 125°C.

DESIGN EXAMPLE

The ADP1870/ADP1871 are easy to use, requiring only a few

design criteria. For example, the example outlined in this section

uses only four design criteria: V_OUT= 1.8 V, I_LOAD= 15 A (pulsing),

V_IN= 12 V (typical), and f_SW= 300 kHz.

Choose a programmable resistor of R_RES= 100 kΩ for a current-

sense gain of 24 V/V.

Output Capacitor

Input Capacitor

Assume that a load step of 15 A occurs at the output and no more

than 5% is allowed for the output to deviate from the steady state

operating point. In this case, the ADP1870’s advantage is that

because the frequency is pseudo-fixed, the converter is able to

respond quickly because of the immediate, though temporary,

increase in switching frequency.

The maximum input voltage ripple is usually 1% of the

minimum input voltage (11.8 V × 0.01 = 120 mV).

V

_RIPP= 120 mV

_MAX,RIPPLE= V_RIPP− (I_LOAD,MAX× ESR)

= 120 mV − (15 A × 0.001) = 45 mV

I_LOAD,MAX

15 A

4 f_SWV_MAX,RIPPLE4×300×10³×105 mV

ΔV_DROOP= 0.05 × 1.8 V = 90 mV

C_IN,min

=

Assuming that the overall ESR of the output capacitor ranges

from 5 mꢀ to 10 mꢀ,

= 120 μF

ΔI_LOAD

_SW×(ΔV_DROOP)

Choose five 22 μF ceramic capacitors. The overall ESR of five

22 μF ceramic capacitors is less than 1 mꢀ.

C_OUT= 2×

f

15 A

I

_RMS= I_LOAD/2 = 7.5 A

_CIN= (I_RMS)²× ESR = (7.5 A)²× 1 mꢀ = 56.25 mW

= 2×

300×10³×(90 mV)

P

= 1.11 mF

Therefore, an appropriate inductor selection is five 270 μF

polymer capacitors with a combined ESR of 3.5 mꢀ.

Rev. 0 | Page 29 of 44

ADP1870/ADP1871

Assuming an overshoot of 45 mV, determine if the output

capacitor that was calculated previously is adequate:

1

C_COMP

=

2πR_COMPf_ZERO

(L×I ²

)

1

LOAD

=

C_OUT

=

2×3.14 ×100×10³×6.25×10³

2

(

(V_OUT− ΔV_OVSHT)²−

1×10⁻⁶×(15 A)²

(1.8 − 45 mV)²−(1.8)²

(

V_OUT

)

= 250 pF

=

Loss Calculations

Duty cycle = 1.8/12 V = 0.15

R_{ON (N2)}= 5.4 mꢀ

= 1.4 mF

Choose five 270 μF polymer capacitors.

The rms current through the output capacitor is

t

_BODY(LOSS)= 20 ns (body conduction time)

V_F= 0.84 V (MOSFET forward voltage)

(V_IN,MAX−V_OUT

L× f_SW

)

V_OUT

V_IN,MAX

1

2

1

3

I_RMS

=

×

C_IN= 3.3 nF (MOSFET gate input capacitance)

Q_N1,N2= 17 nC (total MOSFET gate charge)

R_GATE= 1.5 ꢀ (MOSFET gate input resistance)

(13.2 V −1.8 V) 1.8 V

×

1

2

1

=

×

=1.49 A

1ꢁF×300×10³13.2 V

3

P_N1,N2(CL)

=

[

D×R_N1(ON)

+

(

1− D

)

×R_N2(ON)

]

×I_L²_OAD

The power loss dissipated through the ESR of the output

capacitor is

= (0.15 × 0.0054 + 0.85 × 0.0054) × (15 A)²

= 1.215 W

P

_COUT= (I_RMS)²× ESR = (1.5 A)²× 1.4 mꢀ = 3.15 mW

t_BODY(LOSS)

Feedback Resistor Network Setup

P_BODY(LOSS)

=

×I_LOAD×V_F×2

t_SW

It is recommended to use R_B= 15 kꢀ. Calculate R_Tas follows:

= 20 ns × 300 × 10³× 15 A × 0.84 × 2

= 151.2 mW

(1.8 V −0.6 V)

R_T=15 kꢀ×

= 30 kꢀ

0.6 V

Compensation Network

P

_SW(LOSS)= f_SW× R_GATE× C_TOTAL× I_LOAD× V_IN× 2

= 300 × 10³× 1.5 Ω × 3.3 × 10⁻⁹× 15 A × 12 × 2

= 534.6 mW

To calculate R_COMP, C_COMP, and C_PAR, the transconductance

parameter and the current-sense gain variable are required. The

transconductance parameter (G_M) is 500 μA/V, and the current-

sense loop gain is

P_{DR (LOSS )}

=

(

[

V_DR

×

(

f _SWC _upperFETV_DR+ I _BIAS

)

]

+

[V_REG

×

f _SWC _lowerFETV_REG+ I _BIAS

)]

= (4.62 × (300 ×10 ³× 3.3 ×10 ⁻⁹× 4.62 + 0.002 ))

+ (5.0 × (300 ×10 ³× 3.3 ×10 ⁻⁹× 5.0 + 0.002 ))

1

G_CS

=

= 8.33 A/V

= 57.12 mW

A_CSR_ON24×0.005

P_DISS(LDO)= (V_IN−V_REG)×( f_SW×C_total×V_REG+ I_BIAS

= (13 V −5 V)×(300×10³×3.3×10⁻⁹×5+0.002)

= 55.6 mW

)

where A_CSand R_ONare taken from setting up the current limit

(see the Programming Resistor (RES) Detect Circuit and Valley

Current-Limit Setting sections).

The crossover frequency is 1/12^thof the switching frequency:

P

_COUT= (I_RMS)²× ESR = (1.5 A)²× 1.4 mꢀ = 3.15 mW

300 kHz/12 = 25 kHz

= 0.003 × (15 A)²= 675 mW

P_DCR(LOSS)= DCR× I_L²_OAD

The zero frequency is 1/4^thof the crossover frequency:

25 kHz/4 = 6.25 kHz

P

_CIN= (I_RMS)²× ESR = (7.5 A)²× 1 mꢀ = 56.25 mW

P

_LOSS= P_N1,N2+ P_BODY(LOSS)+ P_SW+ P_DCR+ P_DR+ P_DISS(LDO)

f_CROSS

f_CROSS+ f_ZERO

2πf_CROSSC_OUTV_OUT

+ P_COUT+ P_CIN

R_COMP

=

×

G_MG_CS

V_REF

= 1.215 W + 151.2 mW + 534.6 mW + 57.12 mW + 55.6

+ 3.15 mW + 675 mW + 56.25 mW

= 2.655 W

25×10³

2 × 3.141× 25×10³×1.11×10⁻³1.8

=

×

25×10³+ 6.25×10³

500 ×10⁻⁶× 8.3

0.6

= 100 kꢀ

Rev. 0 | Page 30 of 44

ADP1870/ADP1871

EXTERNAL COMPONENT RECOMMENDATIONS

The configurations listed in Table 10 are with f_CROSS= 1/12 × f_SW, f_ZERO= ¼ × f_CROSS, R_RES= 100 kꢀ, R_BOT= 15 kꢀ, R_ON= 5.4 mΩ

(BSC042N03MS G), V_REG= 5 V (float), and a maximum load current of 14 A.

The ADP1871 models listed in Table 10 are the PSM versions of the device.

Table 10. External Component Values

Marking Code

V_OUTV_IN

C_IN

(μF)

C_OUT

(μF)

L¹

(μH)

R_C

(kΩ)

C_COMP

(pF)

C_PAR

(pF)

R_TOP

(kΩ)

SAP Model

ADP1870 ADP1871 (V)

(V)

13

ADP1870ARMZ-0.3-R7/

ADP1871ARMZ-0.3-R7

LDW

LDX

LDY

LDG

LDM

LDN

0.8

1.2

1.8

2.5

3.3

5

5 × 22²

4 × 22²

5 × 22²

4 × 22²

5 × 560³

4 × 560³

4 × 270⁴

3 × 270⁴

2 × 330⁵

330⁵

0.72

1.0

1.53

2.0

3.27

47

34

47

34

47

34

47

34

47

34

47

740

571

800

740

592

829

339

326

271

407

307

430

362

326

296

415

380

223

163

233

210

268

326

261

233

217

74

57

80

74

59

83

34

33

27

41

31

43

36

33

30

41

38

22

16

23

21

27

33

26

23

22

5.0

15.0

30.0

47.5

67.5

110.0

160.0

15.0

30.0

47.5

67.5

110.0

160.0

5.0

15.0

30.0

47.5

15.0

30.0

47.5

67.5

110.0

15.0

30.0

47.5

67.5

110.0

160.0

5.0

15.0

30.0

47.5

15.0

30.0

47.5

67.5

110.0

15.0

30.0

47.5

67.5

7

22²+ ( 4 × 47⁶) 3.44

1.2

1.8

2.5

3.3

5

16.5 4 × 22²

16.5 3 × 22²

4 × 560³

4 × 270⁴

2 × 330⁵

2 × 150⁷

22²+ 4 × 47⁶

4 × 560³

4 × 270⁴

3 × 270⁴

3 × 180⁸

5 × 270⁴

3 × 330⁵

3 × 270⁴

2 × 270⁴

150⁷

4 × 270⁴

2 × 330⁵

3 × 270⁴

330⁵

4 × 47⁶

3 × 47⁶

4 × 270⁴

2 × 330⁵

3 × 180⁸

270⁴

1.0

1.67

2.00

3.84

4.44

0.22

0.47

0.90

1.00

1.76

0.47

0.72

0.90

1.0

7

ADP1870ARMZ-0.6-R7/

ADP1871ARMZ-0.6-R7

0.8

1.2

1.8

2.5

1.2

1.8

2.5

3.3

5

1.2

1.8

2.5

3.3

5

5.5

13

5 × 22²

3 × 22²

5 × 10⁹

16.5 3 × 10⁹

16.5 4 × 10⁹

2.0

7

ADP1870ARMZ-1.0-R7/

ADP1871ARMZ-1.0-R7

0.8

1.2

1.8

2.5

1.2

1.8

2.5

3.3

5

1.2

1.8

2.5

3.3

5.5

13

5 × 22²

3 × 22²

3 × 10⁹

4 × 10⁹

5 × 10⁹

4 × 10⁹

0.22

0.47

0.72

1.0

0.47

0.72

3 × 330⁵

3 × 270⁴

270⁴

3 × 47⁶

4 × 270⁴

3 × 270⁴

3 × 180⁸

270⁴

16.5 3 × 10⁹

16.5 4 × 10⁹

Rev. 0 | Page 31 of 44

ADP1870/ADP1871

Marking Code

V_OUTV_IN

ADP1870 ADP1871 (V) (V)

C_IN

(μF)

16.5 3 × 10⁹

C_OUT

(μF)

L¹

(μH)

R_C

(kΩ)

C_COMP

(pF)

C_PAR

(pF)

R_TOP

(kΩ)

SAP Model

LDY

LDN

5

7

3 × 47⁶

1.0

34

268

228

27

23

110.0

160.0

22²+ 47⁶

¹See the Inductor Selection section and Table 11.

²22 μF Murata 25 V, X7R, 1210 GRM32ER71E226KE15L (3.2 mm × 2.5 mm × 2.5 mm).

³560 μF Panasonic (SP-series) 2 V, 7 mΩ, 3.7 A EEFUE0D561LR (4.3 mm × 7.3 mm × 4.2 mm).

⁴270 μF Panasonic (SP-series) 4 V, 7 mΩ, 3.7 A EEFUE0G271LR (4.3 mm × 7.3 mm × 4.2 mm).

⁵330 μF Panasonic (SP-series) 4 V, 12 mΩ, 3.3 A EEFUE0G331R (4.3 mm × 7.3 mm × 4.2 mm).

⁶47 μF Murata 16 V, X5R, 1210 GRM32ER61C476KE15L (3.2 mm × 2.5 mm × 2.5 mm).

⁷150 μF Panasonic (SP-series) 6.3 V, 10 mΩ, 3.5 A EEFUE0J151XR (4.3 mm × 7.3 mm × 4.2 mm).

⁸180 μF Panasonic (SP-series) 4 V, 10 mΩ, 3.5 A EEFUE0G181XR (4.3 mm × 7.3 mm × 4.2 mm).

⁹10 μF TDK 25 V, X7R, 1210 C3225X7R1E106M.

Table 11. Recommended Inductors

L (μH)

0.12

0.22

0.47

0.72

0.9

1.2

1.0

1.4

2.0

DCR (mΩ)

0.33

0.67

1.3

1.6

1.8

3.3

3.2

I_SAT(A)

Dimension (mm)

10.2 × 7

13.2 × 12.8

10.5 × 10.2

13 × 12.8

10.5 × 10.2

14 × 12.8

Manufacturer

Model Number

744303012

744303022

744355147

744325072

744355090

744325120

7443552100

744318180

7443551200

CEP125U-R80

55

30

50

35

28

25

20

24

Würth Elektronik

AIC Technology

2.6

2.5

22

16.5

13.2 × 10.8

12.5 × 12.5

0.8

Table 12. Recommended MOSFETs

R_ON

(mΩ)

I_D

(A)

V_DS

(V)

C_IN

Q_TOTAL

V_GS= 4.5 V

(nF) (nC)

Package

Manufacturer

Model Number

Upper-Side MOSFET

(Q1/Q2)

5.4

47

30

3.2

1.6

20

PG-TDSON8

Infineon

BSC042N03MS G

10.2

6.0

9

53

19

14

47

30

10

35

25

20

PG-TDSON8

SO-8

Infineon

Vishay

International Rectifier

Infineon

BSC080N03MS G

Si4842DY

IRF7811

2.4

3.2

Lower-Side MOSFET

(Q3/Q4)

5.4

PG-TDSON8

BSC042N03MS G

10.2

6.0

82

19

30

1.6

10

35

PG-TDSON8

SO-8

Infineon

Vishay

BSC080N03MS G

Si4842DY

Rev. 0 | Page 32 of 44

ADP1870/ADP1871

LAYOUT CONSIDERATIONS

Figure 84 shows the schematic of a typical ADP1870/ADP1871

used for a high current application. Blue traces denote high current

pathways. VIN, PGND, and V_OUTtraces should be wide and

possibly replicated, descending down into the multiple layers.

Vias should populate, mainly around the positive and negative

terminals of the input and output capacitors, alongside the source

of Q1/Q2, the drain of Q3/Q4, and the inductor.

The performance of a dc-to-dc converter depends highly on

how the voltage and current paths are configured on the printed

circuit board (PCB). Optimizing the placement of sensitive

analog and power components is essential to minimize output

ripple, maintain tight regulation specifications, and reduce

PWM jitter and electromagnetic interference.

HIGH VOLTAGE INPUT

= 12V

V

IN

JP3

C28

10µF

C3

C4

C5

C6

C7

C8

C9

C

571pF

R

47kꢀ

C

ADP1870/

ADP1871

22µF

N/A

C12

100nF

C

57pF

F

C

1

2

3

10

9

Q1

Q3

Q2

VIN

BST

COMP/EN

FB

SW

1.0µH

V

= 1.8V, 15A

OUT

R1 30kꢀ

V

8

DRVH

OUT

+

C20

270µF

C21

270µF

C22

270µF

C23

R6

2ꢀ

R2

15kꢀ

R4

0ꢀ

270µF

Q4

4

5

7

6

GND

PGND

DRVL

C13

1.5nF

VREG

+

C2

0.1µF

C1

1µF

C24

N/A

C25

N/A

C26

N/A

C27

N/A

C14 TO C19

N/A

R5

100kꢀ

MURATA: (HIGH VOLTAGE INPUT CAPACITORS)

22µF, 25V, X7R, 1210 GRM32ER71E226KE15L

PANASONIC: (OUTPUT CAPACITORS)

270µF, SP-SERIES, 4V, 7mꢀ EEFUE0G271LR

INFINEON MOSFETs:

BSC042N03MS G (LOWER SIDE)

BSC080N03MS G (UPPER SIDE)

WÜRTH INDUCTORS:

1µH, 3.3mꢀ, 20A 7443552100

Figure 84. ADP1870 High Current Evaluation Board Schematic (Blue Traces Indicate High Current Paths)

Rev. 0 | Page 33 of 44

ADP1870/ADP1871

SENSITIVE ANALOG

COMPONENTS

LOCATED FAR

FROM THE NOISY

POWER SECTION.

SEPARATE ANALOG GROUND

PLANE FOR THE ANALOG

COMPONENTS (THAT IS,

COMPENSATION AND

FEEDBACK RESISTORS).

OUTPUT CAPACITORS

ARE MOUNTED ON THE

RIGHTMOST AREA OF

THE EVB, WRAPPING

BACK AROUND TO THE

MAIN POWER GROUND

PLANE, WHERE IT MEETS

WITH THE NEGATIVE

TERMINALS OF THE

BYPASS POWER CAPACITOR (C1)

FOR VREG BIAS DECOUPLING

AND HIGH FREQUENCY

CAPACITOR (C2) AS CLOSE AS

POSSIBLE TO THE IC.

INPUT CAPACITORS

ARE MOUNTED CLOSE

TO DRAIN OF Q1/Q2

AND SOURCE OF Q3/Q4.

Figure 85. Overall Layout of the ADP1870 High Current Evaluation Board

Rev. 0 | Page 34 of 44

ADP1870/ADP1871

Figure 86. Layer 2 of Evaluation Board

Rev. 0 | Page 35 of 44

ADP1870/ADP1871

TOP RESISTOR

FEEDBACK TAP

V

SENSE TAP LINE

OUT

EXTENDING BACK TO THE

TOP RESISTOR IN THE

FEEDBACK DIVIDER

NETWORK (SEE FIGURE 86

TO FIGURE 88). THIS

OVERLAPS WITH PGND

SENSE TAP LINE EXTENDING

BACK TO THE ANALOG

PLANE (SEE FIGURE 88,

LAYER 4 FOR PGND TAP).

Figure 87. Layer 3 of Evaluation Board

Rev. 0 | Page 36 of 44

ADP1870/ADP1871

BOTTOM RESISTOR

TAP TO THE ANALOG

GROUND PLANE

PGND SENSE TAP FROM

NEGATIVE TERMINALS OF

OUTPUT BULK CAPACITORS.

THIS TRACK PLACEMENT

SHOULD BE DIRECTLY

BELOW THE V

SENSE

LINE FROM FIGURE 84.

OUT

Figure 88. Layer 4 (Bottom Layer) of Evaluation Board

(yellow arrow) is maintained as Q1/Q2 turns off and Q3/Q4

turns on. When Q3/Q4 turns on, the current direction continues to

be maintained (red arrow) as it circles from the bulk capacitor’s

power ground terminal to the output capacitors, through the

Q3/Q4. Arranging the power planes in this manner minimizes

the area in which changes in flux occur if the current through

Q1/Q2 stops abruptly. Sudden changes in flux, usually at source

terminals of Q1/Q2 and drain terminal of Q3/Q4, cause large

dV/dt’s at the SW node.

IC SECTION (LEFT SIDE OF EVALUATION BOARD)

A dedicated plane for the analog ground plane (GND) should

be separate from the main power ground plane (PGND). With

the shortest path possible, connect the analog ground plane to

the GND pin (Pin 4). This plane should be on only the top layer

of the evaluation board. To avoid crosstalk interference, there

should not be any other voltage or current pathway directly

below this plane on Layer 2, Layer 3, or Layer 4. Connect the

negative terminals of all sensitive analog components to the

analog ground plane. Examples of such sensitive analog com-

ponents include the resistor divider’s bottom resistor, the high

frequency bypass capacitor for biasing (0.1 μF), and the

compensation network.

The SW node is near the top of the evaluation board. The SW

node should use the least amount of area possible and be away

from any sensitive analog circuitry and components because

this is where most sudden changes in flux density occur. When

possible, replicate this pad onto Layer 2 and Layer 3 for thermal

relief and eliminate any other voltage and current pathways directly

beneath the SW node plane. Populate the SW node plane with

vias, mainly around the exposed pad of the inductor terminal

and around the perimeter of the source of Q1/Q2 and the drain

of Q3/Q4. The output voltage power plane (V_OUT) is at the right-

most end of the evaluation board. This plane should be replicated,

descending down to multiple layers with vias surrounding the

inductor terminal and the positive terminals of the output bulk

capacitors. Ensure that the negative terminals of the output

capacitors are placed close to the main power ground (PGND),

as previously mentioned. All of these points form a tight circle

Mount a 1 μF bypass capacitor directly across the VREG pin

(Pin 5) and the PGND pin (Pin 7). In addition, a 0.1 μF should

be tied across the VREG pin (Pin 5) and the GND pin (Pin 4).

POWER SECTION

As shown in Figure 85, an appropriate configuration to localize

large current transfer from the high voltage input (V_IN) to the

output (V_OUT) and then back to the power ground is to put the

V_INplane on the left, the output plane on the right, and the main

power ground plane in between the two. Current transfers from

the input capacitors to the output capacitors, through Q1/Q2,

during the on state (see Figure 89). The direction of this current

Rev. 0 | Page 37 of 44

ADP1870/ADP1871

(component geometry permitting) that minimizes the area of

flux change as the event switches between D and 1 − D.

SW

VOUT

LAYER 1: SENSE LINE FOR SW

(DRAIN OF LOWER MOSFET)

LAYER 1: SENSE LINE FOR PGND

(SOURCE OF LOWER MOSFET)

Figure 90. Drain/Source Tracking Tapping of the Lower-Side MOSFET for CS

Amp Differential Sensing (Yellow Sense Line on Layer 2)

Differential sensing should also be applied between the

outermost output capacitor to the feedback resistor divider (see

Figure 87 and Figure 88). Connect the positive terminal of the

output capacitor to the top resistor (R_T). Connect the negative

terminal of the output capacitor to the negative terminal of the

bottom resistor, which connects to the analog ground plane as

well. Both of these track lines, as previously mentioned, should

be narrow and away from any other active device or voltage/

current path.

VIN

PGND

Figure 89. Primary Current Pathways During the On State of the Upper-Side

MOSFET (Left Arrow) and the On State of the Lower-Side MOSFET (Right Arrow)

DIFFERENTIAL SENSING

Because the ADP1870/ADP1871 operate in valley current-

mode control, a differential voltage reading is taken across the

drain and source of the lower-side MOSFET. The drain of the

lower-side MOSFET should be connected as close as possible to

the SW pin (Pin 9) of the IC. Likewise, the source should be

connected as close as possible to the PGND pin (Pin 7) of the

IC. When possible, both of these track lines should be narrow

and away from any other active device or voltage/current path.

Rev. 0 | Page 38 of 44

ADP1870/ADP1871

TYPICAL APPLICATIONS CIRCUITS

15 A, 300 kHz HIGH CURRENT APPLICATION CIRCUIT

HIGH VOLTAGE INPUT

= 12V

V

IN

JP3

C28

10µF

C3

C4

C5

C6

C7

C8

C9

C

571pF

R

47kꢀ

C

ADP1870/

ADP1871

22µF

N/A

C12

100nF

C

57pF

F

C

1

2

3

10

9

Q1

Q3

Q2

VIN

BST

COMP/EN

FB

SW

1.0µH

V

= 1.8V, 15A

OUT

R1 30kꢀ

V

8

DRVH

OUT

+

C20

270µF

C21

270µF

C22

270µF

C23

R6

2ꢀ

R2

15kꢀ

R4

0ꢀ

270µF

Q4

4

5

7

6

GND

PGND

DRVL

C13

1.5nF

VREG

+

C2

0.1µF

C1

1µF

C24

N/A

C25

N/A

C26

N/A

C27

N/A

C14 TO C19

N/A

R5

100kꢀ

MURATA: (HIGH VOLTAGE INPUT CAPACITORS)

22µF, 25V, X7R, 1210 GRM32ER71E226KE15L

PANASONIC: (OUTPUT CAPACITORS)

270µF, SP-SERIES, 4V, 7mꢀ EEFUE0G271LR

INFINEON MOSFETs:

BSC042N03MS G (LOWER SIDE)

BSC080N03MS G (UPPER SIDE)

WÜRTH INDUCTORS:

1µH, 3.3mꢀ, 20A 7443552100

Figure 91. Application Circuit for 12 V Input, 1.8 V Output, 15 A, 300 kHz (Q2/Q4 No Connect)

5.5 V INPUT, 600 kHz APPLICATION CIRCUIT

HIGH VOLTAGE INPUT

= 5.5V

V

IN

JP3

C28

10µF

C3

C4

C5

C6

C7

C8

C9

C

571pF

R

47kꢀ

C

ADP1870/

ADP1871

22µF

N/A

C12

100nF

C

57pF

F

C

1

2

3

Q1

Q3

Q2

VIN

BST 10

9

8

COMP/EN

FB

SW

0.47µH

V

= 2.5V, 15A

OUT

R1 30kꢀ

V

DRVH

OUT

+

C20

180µF

C21

180µF

C22

180µF

C23

N/A

R6

2ꢀ

R2

15kꢀ

R4

0ꢀ

Q4

4

5

GND

PGND

DRVL

7

6

C13

1.5nF

VREG

+

C2

0.1µF

C1

1µF

C24

N/A

C25

N/A

C26

N/A

C27

N/A

C14 TO C19

N/A

R5

100kꢀ

MURATA: (HIGH VOLTAGE INPUT CAPACITORS)

22µF, 25V, X7R, 1210 GRM32ER71E226KE15L

PANASONIC: (OUTPUT CAPACITORS)

180µF, SP-SERIES, 4V, 10mꢀ EEFUE0G181XR

INFINEON MOSFETs:

BSC042N03MS G (LOWER SIDE)

BSC080N03MS G (UPPER SIDE)

WÜRTH INDUCTORS:

0.47µH, 0.8mꢀ, 50A 744355147

Figure 92. Application Circuit for 5.5 V Input, 2.5 V Output, 15 A, 600 kHz (Q2/Q4 No Connect)

Rev. 0 | Page 39 of 44

ADP1870/ADP1871

300 kHz HIGH CURRENT APPLICATION CIRCUIT

HIGH VOLTAGE INPUT

= 13V

V

IN

JP3

C28

10µF

C3

C4

C5

C6

C7

C8

C9

C

528pF

R

43kꢀ

C

ADP1870/

ADP1871

22µF

N/A

270µF

C12

100nF

C

53pF

F

C

1

2

3

10

9

Q1

Q3

Q2

VIN

BST

COMP/EN

FB

SW

1.4µH

V

= 1.8V, 12A

OUT

R1 30kꢀ

V

DRVH

8

OUT

+

C20

270µF

C21

270µF

C22

270µF

C23

R6

2ꢀ

R2

15kꢀ

R4

0ꢀ

270µF

Q4

4

5

7

6

GND

PGND

DRVL

C13

1.5nF

VREG

+

C2

0.1µF

C1

1µF

C24

N/A

C25

N/A

C26

N/A

C27

N/A

C14 TO C19

N/A

R5

100kꢀ

MURATA: (HIGH VOLTAGE INPUT CAPACITORS)

22µF, 25V, X7R, 1210 GRM32ER71E226KE15L

SANYO OSCON:

270µF, 16SVPC270M, 14mꢀ

PANASONIC: (OUTPUT CAPACITORS)

270µF, SP-SERIES, 4V, 7mꢀ EEFUE0G271LR

INFINEON MOSFETs:

BSC042N03MS G (LOWER SIDE)

BSC080N03MS G (UPPER SIDE)

WÜRTH INDUCTORS:

0.72µH, 1.65mꢀ, 35A 744325072

Figure 93. Application Circuit for 13 V Input, 1.8 V Output, 12 A, 300 kHz (Q2/Q4 No Connect)

Rev. 0 | Page 40 of 44

ADP1870/ADP1871

OUTLINE DIMENSIONS

3.10

3.00

2.90

10

1

6

5

5.15

4.90

4.65

3.10

3.00

2.90

PIN 1

IDENTIFIER

0.50 BSC

0.95

0.85

0.75

15° MAX

1.10 MAX

0.70

0.55

0.40

0.15

0.05

0.23

0.13

6°

0°

0.30

0.15

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-BA

Figure 94. 10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Package Option

RM-10

Branding

LDW

LDX

LDY

LDG

ADP1870ARMZ-0.3-R7

ADP1870ARMZ-0.6-R7

ADP1870ARMZ-1.0-R7

ADP1871ARMZ-0.3-R7

ADP1871ARMZ-0.6-R7

ADP1871ARMZ-1.0-R7

ADP1870-0.3-EVALZ

ADP1870-0.6-EVALZ

ADP1870-1.0-EVALZ

ADP1871-0.3-EVALZ

ADP1871-0.6-EVALZ

ADP1871-1.0-EVALZ

−40°C to +125°C

10-Lead Mini Small Outline Package [MSOP]

Evaluation Board

RM-10

LDM

LDN

Evaluation Board

¹Z = RoHS Compliant Part.

Rev. 0 | Page 41 of 44

ADP1870/ADP1871

NOTES

Rev. 0 | Page 42 of 44

ADP1870/ADP1871

NOTES

Rev. 0 | Page 43 of 44

ADP1870/ADP1871

NOTES

registered trademarks are the property of their respective owners.

D08730-0-3/10(0)

Rev. 0 | Page 44 of 44


型号：	ADP1870-1.0-EVALZ
厂家：	ADI
描述：	Synchronous Buck Controller with Constant On-Time and Valley Current Mode 同步降压控制器具有恒定导通时间和谷值电流模式控制器
文件：	总44页 (文件大小：1932K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADP1870-1.0-EVALZ [ADI]

相关型号：

ADP1870ACPZ-0.3-R7

ADP1870ACPZ-0.6-R7

ADP1870ACPZ-1.0-R7

ADP1870ARMZ-0.3-R7

ADP1870ARMZ-0.6-R7

ADP1870ARMZ-1.0-R7

ADP1871

ADP1871-0.3-EVALZ

ADP1871-0.6-EVALZ

ADP1871-1.0-EVALZ

ADP1871ACPZ-0.3-R7

ADP1871ACPZ-0.6-R7