ADP3158JR-REEL [ADI]
IC SWITCHING CONTROLLER, PDSO16, SO-16, Switching Regulator or Controller;
| 型号： | ADP3158JR-REEL |
| 厂家： | 
ADI |
| 描述： | IC SWITCHING CONTROLLER, PDSO16, SO-16, Switching Regulator or Controller 开关 光电二极管 |
| 文件： | 总16页 (文件大小：191K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4-Bit Programmable
Synchronous Buck Controllers
a
ADP3158/ADP3178
FEATURES
FUNCTIO NAL BLO CK D IAGRAM
Optimally Compensated Active Voltage Positioning
with Gain and Offset Adjustment (ADOPT™) for
Superior Load Transient Response
Complies with VRM Specifications with Lowest
System Cost
VCC
CT
ADP3158/ADP3178
UVLO
& BIAS
DRVH
OSCILLATOR
PWM
DRIVE
4-Bit Digitally Programmable 1.3 V to 2.05 V Output
N-Channel Synchronous Buck Driver
DRVL
GND
Total Accuracy ꢀ0.8% Over Temperature
Two On-Board Linear Regulator Controllers Designed
to Meet System Power Sequencing Requirements
High Efficiency Current-Mode Operation
Short Circuit Protection for Switching Regulator
Overvoltage Protection Crowbar Protects Micro-
processors with No Additional External Components
REF
REFERENCE
DAC+20%
V
LR1
CS–
CS+
LRFB1
CMP
– +
LRDRV1
V
LR2
APPLICATIONS
LRFB2
Core Supply Voltage Generation for:
g
m
Intel Pentium® III
LRDRV2
COMP
Intel Celeron™
REF
VID DAC
VID3
VID2
VID1
VID0
GENERAL D ESCRIP TIO N
standard current-mode architectures, active voltage positioning
adjusts the output voltage as a function of the load current so it
is always optimally positioned for a system transient. T hey also
provide accurate and reliable short circuit protection and
adjustable current limiting. T he devices include an integrated
overvoltage crowbar function to protect the microprocessor
from destruction in case the core supply exceeds the nominal
programmed voltage by more than 20%.
T he ADP3158 and ADP3178 are highly efficient synchronous
buck switching regulator controllers optimized for converting a
5 V main supply into the core supply voltage required by high-
performance processors. These devices use an internal 4-bit DAC
to read a voltage identification (VID) code directly from the
processor, which is used to set the output voltage between 1.3 V
and 2.05 V. T hey use a current mode, constant off-time archi-
tecture to drive two N-channel MOSFETs at a programmable
switching frequency that can be optimized for regulator size and
efficiency.
T he AD P3158 and AD P3178 contain two linear regulator
controllers that are designed to drive external N -channel
M OSFET s. T he outputs are internally fixed at 2.5 V and 1.8 V
in the ADP3158, while the ADP3178 provides adjustable out-
puts that are set using an external resistor divider. T hese
linear regulators are used to generate the auxiliary voltages
(AGP, GT L, etc.) required in most motherboard designs,
and have been designed to provide a high bandwidth load-
transient response.
T he ADP3158 and ADP3178 also use a unique supplemental
regulation technique called Analog Devices Optimal Positioning
T echnology (ADOPT ) to enhance load transient performance.
Active voltage positioning results in a dc/dc converter that
meets the stringent output voltage specifications for high-
performance processors, with the minimum number of output
capacitors and smallest footprint. Unlike voltage-mode and
T he ADP3158 and ADP3178 are specified over the commercial
temperature range of 0°C to 70°C and are available in a 16-lead
SOIC package.
ADOPT is a trademark of Analog Devices, Inc.
Pentium is a registered trademark of Intel Corporation.
Celeron is a trademark of Intel Corporation.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2001
ADP3158/ADP3178–SPECIFICATIONS(VCC = 12 V, T = 0ꢁC to 70ꢁC, unless otherwise noted.)
A
P aram eter
Sym bol
Conditions
Min
Typ
Max
Unit
SWIT CHING REGULAT OR
Output Accuracy
VCS–
1.3 V Output
1.65 V Output
2.05 V Output
Line Regulation
Crowbar T rip Point
Crowbar Reset Point
Crowbar Response T ime
Figure 1
Figure 1
Figure 1
1.289
1.637
2.034
1.3
1.311
1.663
2.066
V
V
V
%
%
%
ns
1.65
2.05
0.06
120
50
∆VOUT
VCROWBAR
VCC = 10 V to 14 V
% of Nominal DAC Voltage
% of Nominal DAC Voltage
Overvoltage to DRVL Going High
115
40
125
60
tCROWBAR
400
VID INPUT S
Input Low Voltage
Input High Voltage
Input Current
Pull-Up Resistance
Internal Pull-Up Voltage
VIL(VID)
VIH(VID)
IVID
0.6
250
5.7
V
V
µA
kΩ
V
2.0
VID(X) = 0 V
185
30
5.4
RVID
20
5.0
OSCILLAT OR
Off T ime
CT Charge Current
TA = 25°C, CT = 200 pF
TA = 25°C, VOUT in Regulation
TA = 25°C, VOUT = 0 V
3.5
130
25
4.0
150
35
4.5
170
45
µs
µA
µA
ICT
ERROR AMPLIFIER
Output Resistance
T ransconductance
RO(ERR)
gm(ERR)
IO(ERR)
VCOMP(MAX)
VCOMP(OFF)
BWERR
1
MΩ
mmho
µA
V
mV
kHz
2.05
600
2.2
625
3.0
750
500
2.35
900
Output Current
CS– Forced to VOUT – 3%
CS– Forced to VOUT – 3%
Maximum Output Voltage
Output Disable T hreshold
–3 dB Bandwidth
COMP = Open
CURRENT SENSE
T hreshold Voltage
VCS(T H)
CS– Forced to VOUT – 3%
CS– ≤ 0.45 V
0.8 V ≤ COMP ≤ 1 V
CS+ = CS– = VOUT
CS+ – (CS–) > 87 mV to DRVH
Going Low
69
35
78
45
1
0.5
50
87
54
5
mV
mV
mV
µA
Input Bias Current
Response T ime
ICS+, ICS–
tCS
5
ns
OUT PUT DRIVERS
Output Resistance
Output T ransition T ime
RO(DRV(X))
tR, tF
IL = 50 mA
CL = 3000 pF
6
80
Ω
ns
LINEAR REGULAT ORS
Feedback Current
LR1 Feedback Voltage
IFB(X)
VLRFB(1)
0.3
2.5
1
2.56
µA
V
ADP3158, Figure 2,
VCC = 4.5 V to 12.6 V
ADP3178, Figure 2,
VCC = 4.5 V to 12.6 V
ADP3158, Figure 2,
VCC = 4.5 V to 12.6 V
ADP3178, Figure 2,
2.44
0.97
1.75
0.97
4.2
1.0
1.8
1.0
1.03
1.85
1.03
V
V
V
V
LR2 Feedback Voltage
Driver Output Voltage
VLRFB(2)
VCC = 4.5 V to 12.6 V
VCC = 4.5 V, VLRFB(X) = 0 V
VLRDRV(X)
SUPPLY
DC Supply Current2
UVLO T hreshold Voltage
UVLO Hysteresis
ICC
VUVLO
7
7
1
9
7.25
1.2
mA
V
V
6.75
0.8
NOT ES
1All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
2Dynamic supply current is higher due to the gate charge being delivered to the external MOSFET s.
Specifications subject to change without notice.
–2–
REV. A
ADP3158/ADP3178
ABSO LUTE MAXIMUM RATINGS*
P IN FUNCTIO N D ESCRIP TIO NS
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V
DRVH, DRVL, LRDRV1, LRDRV2 . . . . . –0.3 V to VCC + 0.3 V
All Other Inputs and Outputs . . . . . . . . . . . . –0.3 V to +10 V
Operating Ambient T emperature Range . . . . . . . 0°C to 70°C
Operating Junction T emperature . . . . . . . . . . . . . . . . . 125°C
Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C
θJA
P in Mnem onic Function
1–4 VID0–VID3 Voltage Identification DAC Inputs.
T hese pins are pulled up to an internal
reference, providing a Logic 1 if left
open. T he DAC output programs the CS–
regulation voltage from 1.3 V to 2.05 V.
T wo-Layer Board . . . . . . . . . . . . . . . . . . . . . . . . . 125°C/W
Four-Layer Board . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
Lead T emperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
5, 12 LRFB1,
LRFB2
Feedback connections for the linear
regulator controllers.
6, 11 LRDRV1,
LRDRV2
Gate drives for the respective linear
regulator N-channel MOSFET s.
7
CS–
Current Sense Negative Node. Negative
input for the current comparator. T his pin
also connects to the internal error ampli-
fier that senses the output voltage.
*T his is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged. Unless otherwise specified, all voltages are referenced
to GND.
P IN CO NFIGURATIO N
8
CS+
Current Sense Positive Node. Positive
input for the current comparator. T he
output current is sensed as a voltage at this
pin with respect to CS–.
1
2
3
4
5
6
7
8
16 GND
VID0
VID1
15 DRVH
9
CT
External capacitor connected from CT to
ground sets the Off-time of the device.
14
13
12
11
10
9
DRVL
VCC
VID2
ADP3158/
ADP3178
TOP VIEW
VID3
10
COMP
Error Amplifier Output and Compensation
Point. T he voltage at this output programs
the output current control level between
CS+ and CS–.
LRFB2
LRDRV2
COMP
CT
LRFB1
LRDRV1
CS–
(Not to Scale)
CS+
13
14
VCC
Supply Voltage for the device.
DRVL
Low-Side MOSFET Drive. Gate drive for
the synchronous rectifier N-channel
MOSFET . T he voltage at DRVL swings
from GND to VCC.
15
16
DRVH
GND
High-Side MOSFET Drive. Gate drive
for the buck switch N-channel MOSFET .
T he voltage at DRVH swings from GND
to VCC.
Ground Reference. GND should have a
low impedance path to the source of the
synchronous MOSFET .
O RD ERING GUID E
Tem perature
Range
LD O
Voltage
P ackage
D escription
P ackage
O ption
Model
ADP3158JR
ADP3178JR
0°C to 70°C
0°C to 70°C
2.5 V, 1.8 V
Adjustable
SO = Small Outline Package
SO = Small Outline Package
R-16A (SO-16)
R-16A (SO-16)
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3158/ADP3178 feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. T herefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–3–
ADP3158/ADP3178–Typical Performance Characteristics
TEK RUN
TRIG'D
60
50
40
VCC
1
30
20
10
0
V
CORE
2
CH1 5.00V B
CH2 500mV B M 10.0ms A CH1
W
5.90V
0
100
200
300
400
500
600
700
800
W
OSCILLATOR FREQUENCY – kHz
0.00000 s
TPC 1. Supply Current vs. Operating Frequency Using
MOSFETs of Figure 3
TPC 4. Power-On Start-Up Waveform
TEK RUN
TRIG'D
25
20
T
= 25ꢁC
A
V
= 1.65V
OUT
DRVH
15
10
1
5
0
DRVL
CH1 5.00V
B
CH2
5.00V B M 1.00ꢂs
A
CH1
5.90V
–0.5
0
0.5
W
W
OUTPUT ACCURACY – % of Nominal
–2.6500ꢂs
TPC 2. Gate Switching Waveforms Using MOSFETs of
Figure 3
TPC 5. Output Accuracy Distribution
TEK RUN
TRIG'D
DRVH
DRVL
CH1 2.00V
B
CH2 2.00V B M 1.00ns
W
A
CH1
5.88V
W
150.000ꢂs
TPC 3. Driver Transition Waveforms Using MOSFETs of
Figure 3
–4–
REV. A
ADP3158/ADP3178
such techniques do not allow the minimum possible number of
output capacitors to be used. ADOPT, as used in the ADP3158
and ADP3178, provides a bandwidth for transient response that
is limited only by parasitic output inductance. This yields opti-
mal load transient response with the minimum number of output
capacitors.
ADP3158/
ADP3178
1
2
3
4
5
6
7
8
16
GND
VID0
VID1
DRVH 15
4-BIT CODE
14
VID2
DRVL
13
12
11
10
9
12V
VCC
LRFB2
LRDRV2
COMP
CT
VID3
+
1ꢂF
100nF
LRFB1
LRDRV1
CS–
Cycle-by-Cycle O per ation
During normal operation (when the output voltage is regulated),
the voltage error amplifier and the current comparator are the
main control elements. During the on-time of the high-side
MOSFET, the current comparator monitors the voltage between
the CS+ and CS– pins. When the voltage level between the two
pins reaches the threshold level, the DRVH output is switched
to ground, which turns off the high-side MOSFET . T he timing
capacitor CT is then charged at a rate determined by the off-
time controller. While the timing capacitor is charging, the DRVL
output goes high, turning on the low-side MOSFET . When the
voltage level on the timing capacitor has charged to the upper
threshold voltage level, a comparator resets a latch. T he output
of the latch forces the low-side drive output to go low and the
high-side drive output to go high. As a result, the low-side switch
is turned off and the high-side switch is turned on. The sequence
is then repeated. As the load current increases, the output voltage
starts to decrease. T his causes an increase in the output of the
voltage-error amplifier, which, in turn, leads to an increase in
the current comparator threshold, thus tracking the load cur-
rent. T o prevent cross conduction of the external MOSFET s,
feedback is incorporated to sense the state of the driver output
pins. Before the low-side drive output can go high, the high-side
drive output must be low. Likewise, the high-side drive output is
unable to go high while the low-side drive output is high.
V
CS–
100ꢃ
CS+
AD820
+
100nF
1.2V
Figure 1. Closed Loop Output Voltage Accuracy
Test Circuit
ADP3158/
ADP3178
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VID0
GND
DRVH
DRVL
VCC
VID1
VCC
+
VID2
1ꢂF
100nF
VID3
V
V
LRFB2
LRDRV2
COMP
CT
LRFB1
LRDRV1
CS–
LR1
LR2
10nF
10nF
CS+
Figure 2. Linear Regulator Output Voltage Accuracy
Test Circuit
TH EO RY O F O P ERATIO N
T he ADP3158 and ADP3178 use a current-mode, constant off-
time control technique to switch a pair of external N-channel
MOSFET s in a synchronous buck topology. Constant off-time
operation offers several performance advantages, including that
no slope compensation is required for stable operation. A unique
feature of the constant off-time control technique is that since
the off-time is fixed, the converter’s switching frequency is a
function of the ratio of input voltage to output voltage. T he
fixed off-time is programmed by the value of an external capaci-
tor connected to the CT pin. T he on-time varies in such a way
that a regulated output voltage is maintained as described below
in the cycle-by-cycle operation. The on-time does not vary under
fixed input supply conditions, and it varies only slightly as a
function of load. This means that the switching frequency remains
fairly constant in a standard computer application.
O utput Cr owbar
An added feature of using an N-channel MOSFET as the syn-
chronous switch is the ability to crowbar the output with the
same MOSFET . If the output voltage is 20% greater than the
targeted value, the controller IC will turn on the lower MOSFET ,
which will current-limit the source power supply or blow its fuse,
pull down the output voltage, and thus save the microprocessor
from destruction. T he crowbar function releases at approxi-
mately 50% of the nominal output voltage. For example, if the
output is programmed to 1.5 V, but is pulled up to 1.85 V or
above, the crowbar will turn on the lower MOSFET . If in this
case the output is pulled down to less than 0.75 V, the crowbar
will release, allowing the output voltage to recover to 1.5 V if
the fault condition has been removed.
O n-boar d Linear Regulator Contr oller s
Active Voltage P ositioning
T he ADP3158 and ADP3178 include two linear regulator con-
trollers to provide a low cost solution for generating additional
supply rails. In the ADP3158, these regulators are internally set
to 2.5 V (LR1) and 1.8 V (LR2) with ±2.5% accuracy. T he
ADP3178 is designed to allow the outputs to be set externally
using a resistor divider. T he output voltage is sensed by the high
input impedance LRFB(x) pin and compared to an internal
fixed reference.
T he output voltage is sensed at the CS– pin. A voltage error
amplifier, (gm), amplifies the difference between the output
voltage and a programmable reference voltage. T he reference
voltage is programmed to between 1.3 V and 2.05 V by an inter-
nal 4-bit DAC that reads the code at the voltage identification
(VID) pins. (Refer to Table I for output voltage vs. VID pin code
information.) A unique supplemental regulation technique called
Analog Devices Optimal Positioning T echnology (ADOPT )
adjusts the output voltage as a function of the load current so it
is always optimally positioned for a load transient. Standard
(passive) voltage positioning, sometimes recommended for use
with other architectures, has poor dynamic performance which
renders it ineffective under the stringent repetitive transient
conditions specified in Intel VRM documents. Consequently,
T he LRDRV(x) pin controls the gate of an external N-channel
MOSFET resulting in a negative feedback loop. T he only addi-
tional components required are a capacitor and resistor for
stability. T he maximum output load current is determined by
the size and thermal impedance of the external power MOSFET
that is placed in series with the supply.
REV. A
–5–
ADP3158/ADP3178
D2
MBR052LT1
5V STANDBY
12V
D3
MBR052LT1
+
C6
1ꢂF
L2
1ꢂH
5V
+
+
+
C9
1000ꢂF
C7
22ꢂF
C8
1000ꢂF
ADP3158/
ADP3178
Q4
*
L1
1.7ꢂH
1000ꢂF ꢄ 5
R12
4mꢃ
VCC CORE
1.30V TO
2.05V
24mꢃ (EACH)
1
2
3
4
5
6
7
8
16
GND
VID0
VID1
VID2
VID3
LRFB1
+
+
+
+
+
DRVH 15
15A
FROM CPU
Q3**
14
13
12
11
10
9
DRVL
VCC
U1
C17 C18 C19C20 C21
LRFB2
C11
68pF
C2
68pF
3.3V
3.3V
LRDRV1 LRDRV2
R
A
COMP
CT
CS–
C15
1ꢂF
C12
1ꢂF
78.7kꢃ
CS+
R11
10kꢃ
Q2*
C
2.7nF
Q1*
R2
10kꢃ
OC
C3
150pF
R
B
*
SUB45N03-13L
**SUB75N03-07
V
1.8V,
2A
10.5kꢃ
LR2
V
LR1
+
C2
2.5V, 2A
+
100ꢂF
R4
220ꢃ
C1
100ꢂF
C10
1nF
R3
220ꢃ
Figure 3. 15 A Pentium III Application Circuit
The linear regulator controllers have been designed so that they
remain active even when the switching controller is in UVLO mode
to ensure that the output voltages of the linear regulators will track
the 3.3 V supply as required by Intel design specifications. By
diode ORing the VCC input of the IC to the 5 VSB and 12 V
supplies as shown in Figure 3, the switching output will be disabled
in standby mode, but the linear regulators will begin conducting
once VCC rises above about 1 V. During start-up the linear out-
puts will track the 3.3 V supply up until they reach their respective
regulation points, regardless of the state of the 12 V supply. Once
the 12 V supply has exceeded the 5 VSB supply by more than a
diode drop, the controller IC will track the 12 V supply. Once the
12 V supply has risen above the UVLO value, the switching regula-
tor will begin its start-up sequence.
AP P LICATIO N INFO RMATIO N
Specifications for a D esign Exam ple
T he design parameters for a typical 750 MHz Pentium III appli-
cation (shown in Figure 3) are as follows:
Input Voltage: (VIN) = 5 V
Auxiliary Input: (VCC) = 12 V
Output Voltage (VVID) = 1.7 V
Maximum Output Current (IO(MAX)) = 15 A
Minimum Output Current (IO(MIN)) = 1 A
Static tolerance of the supply voltage for the processor core
(∆VO) = +40 mV (–80 mV) = 120 mV
T ransient tolerance (for less than 2 µs) of the supply voltage
for the processor core when the load changes between the
minimum and maximum values with a di/dt of 20 A/µs
(∆VO(T RANSIENT )) = +80 mV (–130 mV) = 210 mV
Table I. O utput Voltage vs. VID Code
VID 3
VID 2
VID 1
VID 0
VO UT(NO M)
Input current di/dt when the load changes between the mini-
mum and maximum values < 0.1 A/µs.
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1.30 V
1.35 V
1.40 V
1.45 V
1.50 V
1.55 V
1.60 V
1.65 V
1.70 V
1.75 V
1.80 V
1.85 V
1.90 V
1.95 V
2.00 V
2.05 V
T he above requirements correspond to Intel’s published power
supply requirements based on VRM 8.4 guidelines.
–6–
REV. A
ADP3158/ADP3178
CT Selection for Operating Frequency
Inductance Selection
The ADP3158 and ADP3178 use a constant off-time architecture
with tOFF determined by an external timing capacitor CT. Each
time the high-side N-channel MOSFET switch turns on, the volt-
age across CT is reset to 0 V. During the off-time, CT is charged
by a constant current of 150 µA. Once CT reaches 3.0 V, a new
on-time cycle is initiated. The value of the off-time is calculated
using the continuous-mode operating frequency. Assuming a
nominal operating frequency (fNOM) of 200 kHz at an output volt-
age of 1.7 V, the corresponding off-time is:
T he choice of inductance determines the ripple current in the
inductor. Less inductance leads to more ripple current, which
increases the output ripple voltage and the conduction losses in
the MOSFET s, but allows using smaller-size inductors and, for
a specified peak-to-peak transient deviation, output capacitors
with less total capacitance. Conversely, a higher inductance means
lower ripple current and reduced conduction losses, but requires
larger-size inductors and more output capacitance for the same
peak-to-peak transient deviation. T he following equation shows
the relationship between the inductance, oscillator frequency,
peak-to-peak ripple current in an inductor and input and
output voltages.
VOUT
VIN
1
tOFF = 1 –
tOFF = 1 −
×
fNOM
VOUT × tOFF
(1)
1.7V
5V
1
L =
(4)
×
= 3.3 µs
IL(RIPPLE )
200 kHz
For 4 A peak-to-peak ripple current, which corresponds to
T he timing capacitor can be calculated from the equation:
approximately 25% of the 15 A full-load dc current in an inductor,
Equation 4 yields an inductance of
tOFF × ICT
3.3 µs ×150 µA
3V
CT =
=
≈ 150 pF
(2)
(3)
1.7V × 3.3 µs
VT (TH )
L =
= 1.4 µH
4 A
A 1.5 µH inductor can be used, which gives a calculated ripple
current of 3.8 A at no load. T he inductor should not saturate at
the peak current of 17 A and should be able to handle the sum
of the power dissipation caused by the average current of 15 A
in the winding and the core loss.
VIN – IO ( MAX ) ×(RDS(ON )HSF + RSENSE + RL ) –VOUT
1
fMIN
=
×
tOFF VIN – IO ( MAX ) ×(RDS(ON )HSF + RSENSE + RL – RDS(ON )LSF )
)
T he converter only operates at the nominal operating frequency
at the above-specified VOUT and at light load. At higher values
of VOUT , or under heavy load, the operating frequency decreases
due to the parasitic voltage drops across the power devices. T he
actual minimum frequency at VOUT = 1.7 V is calculated to be
195 kHz (see Equation 3), where:
D esigning an Inductor
Once the inductance is known, the next step is either to design an
inductor or find a standard inductor that comes as close as
possible to meeting the overall design goals. T he first decision
in designing the inductor is to choose the core material. T here
are several possibilities for providing low core loss at high frequen-
cies. Two examples are the powder cores (e.g., Kool-Mµ® from
Magnetics, Inc.) and the gapped soft ferrite cores (e.g., 3F3 or 3F4
from Philips). Low frequency powdered iron cores should be
avoided due to their high core loss, especially when the inductor
value is relatively low and the ripple current is high.
RDS(ON)HSF is the resistance of the high-side MOSFET
(estimated value: 14 mΩ)
RDS(ON)LSF is the resistance of the low-side MOSFET
(estimated value: 6 mΩ)
RSENSE is the resistance of the sense resistor
(estimated value: 4 mΩ)
T wo main core types can be used in this application. Open
magnetic loop types, such as beads, beads on leads, and rods
and slugs, provide lower cost but do not have a focused mag-
netic field in the core. The radiated EMI from the distributed
magnetic field may create problems with noise interference in
the circuitry surrounding the inductor. Closed-loop types, such
as pot cores, PQ, U, and E cores, or toroids, cost more, but
have much better EMI/RFI performance. A good compromise
between price and performance are cores with a toroidal shape.
RL is the resistance of the inductor
(estimated value: 3 mΩ)
REV. A
–7–
ADP3158/ADP3178
amount of voltage positioning used, which, for an optimal design,
should utilize the maximum that the regulation window will allow.
The error determination is a closed-loop calculation, but it can
be closely approximated. To maintain a conservative design while
avoiding an impractical design, various error sources should
be considered and summed statistically.
T here are many useful references for quickly designing a power
inductor. T able II gives some examples.
Table II. Magnetics D esign References
Magnetic Designer Software
Intusoft (http://www.intusoft.com)
T he output ripple voltage can be factored into the calculation by
summing the output ripple current with the maximum output
current to determine an effective maximum dynamic current
change. T he remaining errors are summed separately according
to the formula:
Designing Magnetic Components for High-Frequency DC-DC
Converters
McLyman, Kg Magnetics
ISBN 1-883107-00-08
VWIN = (V∆ –VVID × 2 kVID ) ×
Selecting a Standar d Inductor
(5)
The companies listed in T able III can provide design consul-
tation and deliver power inductors optimized for high power
applications upon request.
2
IO
kCSF
2
2
2
1 –
kRCS
+
+ kRT + kEA = 95 mV
IO + IO∆
2
Table III. P ower Inductor Manufacturers
where kVID = 0.5% is the initial programmed voltage tolerance
from the graph of T PC 6, kRCS = 2% is the tolerance of the
current sense resistor, kCSF = 10% is the summed tolerance of
the current sense filter components, kRT = 2% is the tolerance of
the two termination resistors added at the COMP pin, and kEA
= 8% accounts for the IC current loop gain tolerance including
the gm tolerance.
Coilcraft
(847) 639-6400
http://www.coilcraft.com
Coiltronics
(561) 752-5000
http://www.coiltronics.com
Sumida Electric Company
(408) 982-9660
http://www.sumida.com
T he remaining window is then divided by the maximum output
current plus the ripple to determine the maximum allowed ESR
and output resistance:
VWIN
95 mV
IO + IO∆ 15 A + 3.8 A
T he output filter capacitor bank must have an ESR of less
C O UT Selection—D eter m ining the ESR
RE ( MAX ) = ROUT ( MAX )
=
=
= 5 mΩ
(6)
T he required equivalent series resistance (ESR) and capacitance
drive the selection of the type and quantity of the output capaci-
tors. T he ESR must be small enough to contain the voltage
deviation caused by a maximum allowable CPU transient cur-
rent within the specified voltage limits, giving consideration also
to the output ripple and the regulation tolerance. T he capaci-
tance must be large enough that the voltage across the capacitor,
which is the sum of the resistive and capacitive voltage deviations,
does not deviate beyond the initial resistive deviation while the
inductor current ramps up or down to the value corresponding
to the new load current. T he maximum allowed ESR also repre-
than 5 mΩ. One can, for example, use five ZA series capacitors
from Rubycon which would give an ESR of 4.8 mΩ. Without
ADOPT voltage positioning, the ESR would need to be less than
3 mΩ, yielding a 50% increase to eight Rubycon output capacitors.
CO UT —Checking the Capacitance
As long as the capacitance of the output capacitor is above a
critical value and the regulating loop is compensated with ADOPT,
the actual value has no influence on the peak-to-peak deviation
of the output voltage to a full step change in the load current.
T he critical capacitance can be calculated as follows:
IO
sents the maximum allowed output resistance, ROUT
.
T he cumulative errors in the output voltage regulation cuts into
the available regulation window, VWIN. When considering dynamic
load regulation this relates directly to the ESR. When consider-
ing dc load regulation, this relates directly to the programmed
output resistance of the power converter.
COUT (CRIT )
=
× L
RE ×VOUT
(7)
15 A
=
×1.5 µH = 2.6 mF
5 mΩ ×1.7
Some error sources, such as initial voltage accuracy and ripple
voltage, can be directly deducted from the available regulation
window, while other error sources scale proportionally to the
T he critical capacitance for the five ZA series Rubycon capaci-
tors is 2.6 mF while the equivalent capacitance is 5 mF. T he
capacitance is safely above the critical value.
–8–
REV. A
ADP3158/ADP3178
RSENSE
VIN is expected to drop below 8 V, logic-level threshold MOSFETs
(VGS(T H) < 2.5 V) are strongly recommended. Only logic-level
MOSFET s with VGS ratings higher than the absolute maximum
value of VCC should be used.
The value of RSENSE is based on the maximum required output
current. The current comparators of the ADP3158 and ADP3178
have a minimum current limit threshold of 69 mV. Note that the
69 mV value cannot be used for the maximum specified nominal
current, as headroom is needed for ripple current and tolerances.
The maximum output current IO(MAX) determines the RDS(ON)
requirement for the two power MOSFETs. When the ADP3158
and ADP3178 are operating in continuous mode, the simplifying
assumption can be made that one of the two MOSFETs is always
The current comparator threshold sets the peak of the inductor
current yielding a maximum output current, IO, which equals twice
the peak inductor current value less half of the peak-to-peak induc-
tor ripple current. From this the maximum value of RSENSE is
calculated as:
conducting the average load current. For VIN = 5 V and VOUT
1.65 V, the maximum duty ratio of the high-side FET is:
=
DHSF ( MAX ) = 1 – ( fMIN × tOFF
)
(12)
VCS(CL )( MIN )
69 mV
DHSF ( MAX ) = 1 – (195 kHz × 3.3 µs) = 36%
RSENSE
≤
=
= 4 mΩ
IL(RIPPLE )
15 A +1.9 A
(8)
IO
+
T he maximum duty ratio of the low-side (synchronous rectifier)
MOSFET is:
2
In this case, 4 mΩ was chosen as the closest standard value.
(13)
DLSF ( MAX ) = 1 – DHSF ( MAX ) = 54%
Once RSENSE has been chosen, the output current at the point
where current limit is reached, IOUT (CL), can be calculated using
the maximum current sense threshold of 87 mV:
T he maximum rms current of the high-side MOSFET is:
2
2
IL(VALLEY ) +(IL(VALLEY ) × IL(PEAK ) ) + IL(PEAK )
IRMSHSF
=
=
DHSF ( MAX ) ×
3
VCS(CL )( MAX ) IL(RIPPLE )
(14)
IOUT (CL )
=
–
13.1 A2 +(13.1 A ×16.1 A) +16.1 A2
RSENSE
87 mV 3.8 A
2
IRMSHSF
36% ×
= 8.8 A rms
3
(9)
=
–
≈ 20 A
T he maximum rms current of the low-side MOSFET is:
4 mΩ
2
2
2
At output voltages below 450 mV, the current sense threshold is
reduced to 54 mV, and the ripple current is negligible. T here-
fore, at dead short the output current is reduced to:
IL(VALLEY ) + IL(VALLEY ) × IL(PEAK ) + IL(PEAK )
IRMSLSF
=
=
DLSF ( MAX ) ×
3
(15)
13.1 A2 +(13.1 A ×16.1 A) +16.1 A2
IRMSLSF
54% ×
= 10.8 A rms
3
54 mV
IOUT (SC )
=
= 13.5 A
(10)
T he RDS(ON) for each MOSFET can be derived from the allowable
dissipation. If 10% of the maximum output power is allowed for
MOSFET dissipation, the total dissipation will be:
4 mΩ
To safely carry the current under maximum load conditions, the
sense resistor must have a power rating of at least:
(16)
PD( FETs) = 0.1×VOUT × IOUT ( MAX ) = 2.26 W
= (IO )2 × RSENSE = (20 A)2 × 4 mΩ = 1.6 W
Allocating half of the total dissipation for the high-side MOSFET
and half for the low-side MOSFET and assuming that switching
losses are small relative to the dc conduction losses, the required
minimum MOSFET resistances will be:
(11)
PR
SENSE
P ower MO SFETs
T wo external N-channel power MOSFET s must be selected for
use with the ADP3158 and ADP3178, one for the main switch
and an identical one for the synchronous switch. T he main
selection parameters for the power MOSFETs are the threshold
voltage (VGS(TH)) and the ON-resistance (RDS(ON)).
PHSF
1.13W
8.8 A2
RDS(ON )HSF
≤
≤
=
= 15 mΩ
= 10 mΩ
(17)
(18)
2
IHSF
PLSF
1.13W
10.8 A2
T he minimum input voltage dictates whether standard threshold
or logic-level threshold MOSFET s must be used. For VIN > 8 V,
standard threshold MOSFET s (VGS(T H) < 4 V) may be used. If
RDS(ON )LSF
=
2
ILSF
REV. A
–9–
ADP3158/ADP3178
Note that there is a trade-off between converter efficiency and
cost. Larger MOSFET s reduce the conduction losses and allow
higher efficiency, but increase the system cost. If efficiency is not a
low ESR input capacitor sized for the maximum rms current
must be used. T he maximum rms capacitor current is given by:
major concern, a Vishay-Siliconix SUB45N03-13L (RDS(ON)
10 mΩ nominal, 16 mΩ worst-case) for the high-side and a
Vishay-Siliconix SUB75N03-07 (RDS(ON) = 6 mΩ nominal,
10 mΩ worst-case) for the low-side are good choices.
=
2
IC(RMS ) = IO DHSF − DHSF
=
(22)
15 A 0.36 – 0.362 = 7.2 A
T he high-side MOSFET dissipation is:
For a ZA-type capacitor with 1000 µF capacitance and 6.3 V
voltage rating, the ESR is 24 mΩ and the maximum allowable
ripple current at 100 kHz is 2 A. At 105°C, at least four such
capacitors must be connected in parallel to handle the calculated
ripple current. At 50°C ambient, however, a higher ripple cur-
rent can be tolerated, so three capacitors in parallel are adequate.
VIN × IL( PEAK ) × QG × fMIN
2
PDHSF = IRMSHSF × RDS(ON )
PDHSF = 8.8 A2 ×16 mΩ +
+
2 × IG
(19)
5V ×15 A × 70 nC ×195 kHz
2 ×1 A
= 1.75 W
where the second term represents the turn-off loss of the
MOSFET . In the second term, QG is the gate charge to be
removed from the gate for turn-off and IG is the gate current.
From the data sheet, QG is 70 nC and the gate drive current
provided by the ADP3159 is about 1 A.
T he ripple voltage across the three paralleled capacitors is:
ESRC( IN )
nC
DHSF
VC( IN )RIPPLE = IO
×
+
nC × CIN × fMAX
(23)
24 mΩ
36%
VC( IN )RIPPLE = 15 A ×
+
= 129 mV
T he low-side MOSFET dissipation is:
3
3 ×1000 µF ×195 kHz
2
PDLSF = IRMSLSF × RDS(ON )
PDLSF = 10.8 A2 ×10 mΩ = 1.08 W
T o further reduce the effect of the ripple voltage on the system
supply voltage bus, and to reduce the input-current di/dt to
below the recommended maximum of 0.1 A/ms, an additional
small inductor (L > 1 µH @ 10 A) should be inserted between
the converter and the supply bus.
(20)
Note that there are no switching losses in the low-side MOSFET.
Surface mount MOSFET s are preferred in CPU core converter
applications due to their ability to be handled by automatic
assembly equipment. T he T O-263 package offers the power
handling of a T O-220 in a surface-mount package. H owever,
this package still needs adequate copper area on the PCB to
help move the heat away from the package.
Feedback Com pensation for Active Voltage P ositioning
Optimized compensation of the ADP3158 and ADP3178 allows
the best possible containment of the peak-to-peak output voltage
deviation. Any practical switching power converter is inherently
limited by the inductor in its output current slew rate to a value
much less than the slew rate of the load. Therefore, any sudden
change of load current will initially flow through the output capaci-
tors, and this will produce an output voltage deviation equal to the
ESR of the output capacitor array times the load current change.
T he junction temperature for a given area of 2-ounce copper
can be approximated using:
T = θ × PD +T
(21)
(
)
J
JA
A
assuming:
JA = 45°C/W for 0.5 in2
TRIG'D
TEK RUN: 200kS/s SAMPLE
θ
θJA = 36°C/W for 1 in2
θJA = 28°C/W for 2 in2
For 1 in2 of copper area attached to each transistor and an
ambient temperature of 50°C:
TJHSF = (36°C/W × 1.48 W) + 50°C = 103°C
TJLSF = (36°C/W × 1.08 W) + 50°C = 89°C
All of the above-calculated junction temperatures are safely
below the 175°C maximum specified junction temperature of
the selected MOSFET s.
2
C IN Selection and Input Cur r ent di/dt Reduction
In continuous inductor-current mode, the source current of the
high-side MOSFET is approximately a square wave with a duty
ratio equal to VOUT /VIN and an amplitude of one-half of the
maximum output current. T o prevent large voltage transients, a
CH1
100mV
CH2
M 250ꢂs
CH2
680mV
Figure 4. Transient Response of the Circuit of Figure 3
–10–
REV. A
ADP3158/ADP3178
where K is a constant determined by internal characteristics of the
ADP3158 and ADP3178, peak-to-peak inductor current ripple
(IRIPPLE), and the current sampling resistor (RSENSE). K can be
calculated using Equations 28 and 29. VDIV is the resistor divider
supply voltage (e.g., the recommended 12 V supply) and VOUT(OS) is
the output voltage offset from the nominal VID-programmed value
under no load condition. This offset is given by Equation 30.
100
90
80
70
60
50
40
30
T he closest 1% value for RA is 78.7 kΩ. T his value is then used
to solve for RB:
20
10
0
RA × RCOMP 78.7 kΩ × 9.2 kΩ
RB =
=
= 10.4 kΩ
(27)
(28)
RA – RCOMP
78.7 kΩ – 9.2 kΩ
0
2
4
6
8
10
12
14
16
18
20
T he nearest 1% value of 10.5 kΩ was chosen for RB.
OUTPUT CURRENT – A
IL(RIPPLE )
(RSENSE × nI )
gm × RTOTAL
VGNL
VCC
Figure 5. Efficiency vs. Load Current of the Circuit
of Figure 3
K =
K =
×
+
–
2
gm × RTOTAL 2 × gm ROGM
T o correctly implement active voltage positioning, the low fre-
quency output impedance (i.e., the output resistance) of the
converter should be made equal to the maximum ESR of the
output capacitor array. T his can be achieved by having a single-
pole roll-off of the voltage gain of the gm error amplifier, where
the pole frequency coincides with the ESR zero of the output
capacitor. A gain with single-pole roll-off requires that the gm
amplifier output pin be terminated by the parallel combination
of a resistor and capacitor. T he required resistor value can be
calculated from the equation:
3.8 A
4 mΩ × 25
1.174
12V
×
+
−
2
2.2 mmho × 9.1 kΩ
2.2 mmho × 9.1 kΩ 2 × 2.2 mmho × 130 kΩ
= 4.7 ×10–2
IL(RIPPLE ) × RSENSE × nI
VIN −VVID
VGNL =VGNL0
+
−
× tD × RSENSE × nI
2
L
(29)
3.8 A × 4 mΩ × 25
5V – 1.7V
1.5 µH
VGNL = 1V +
−
× 75 ns × 4 mΩ × 25 = 1.174V
2
ROGM × RTOTAL 1 MΩ × 9.1 kΩ
RCOMP
where:
RTOTAL
=
=
= 9.2 kΩ
RE ( MAX ) × IL( RIPPLE )
(24)
(25)
VOUT (OS ) = V
−VVID
−
−VVID × kVID
ROGM – RTOTAL 1 MΩ – 9.1 kΩ
(
)
OUT ( MAX )
2
5 mΩ × 3.8 A
(30)
nI × RSENSE
25 × 4 mΩ
VOUT (OS ) = 40 mV −
−1.7V × 5 ×10–3 = 22 mV
=
=
= 9.1 kΩ
2
gm × RE ( MAX ) 2.2 mmho × 5 mΩ
Finally, the compensating capacitance is determined from the
equality of the pole frequency of the error amplifier gain and the
zero frequency of the impedance of the output capacitor:
In Equations 24 and 25, ROGM is the internal resistance of the gm
amplifier, nI is the division ratio from the output voltage to
signal of the gm amplifier to the PWM comparator, and gm is the
transconductance of the gm amplifier itself.
Although a single termination resistor equal to RCOMP would yield
the proper voltage positioning gain, the dc biasing of that resistor
would determine how the regulation band is centered (i.e., offset).
Note that sometimes the specified regulation band is asymmetrical
with respect to the nominal VID voltage. With the ADP3158 and
ADP3178, the offset is already considered part of the design
procedure—no special provision is required. To accomplish the dc
biasing, it is simplest to use two resistors to terminate the gm
amplifier output, with the lower resistor (RB) tied to ground and
the upper resistor (RA) to the 12 V supply of the IC. The values of
these resistors can be calculated using:
COUT × ESR 5 mF × 4.8 mΩ
COC
=
=
= 2.6 nF
(31)
RTOTAL
9.1 kΩ
T he closest standard value for COC is 2.7 nF.
VDIV
12V
RA
=
=
= 79.1 kΩ
(26)
gm ×(VOUT (OS ) + K ) 2.2 mmho ×(22 mV + 4.7 ×10–2
)
REV. A
–11–
ADP3158/ADP3178
Tr ade-O ffs Between D C Load Regulation and AC Load
Regulation
Efficiency of the Linear Regulator s
T he efficiency and corresponding power dissipation of each
of the linear regulators are not determined by the controller
IC. Rather, these are a function of input and output voltage and
load current. Efficiency is approximated by the formula:
Casual observation of the circuit operation—e.g., with a voltmeter
—would make it appear that the dc load regulation appears to
be rather poor compared to a conventional regulator (see Figure
4). T his would be especially noticeable under very light or very
heavy loads where the voltage is “positioned” near one of the
extremes of the regulation window rather than near the nominal
center value. It must be noted and understood that this low gain
characteristic (i.e., loose dc load regulation) is inherently required
to allow improved transient containment (i.e., to achieve tighter
ac load regulation). That is, the dc load regulation is intentionally
sacrificed (but kept within specification) in order to minimize
the number of capacitors required to contain the load transients
produced by the CPU.
VOUT
η = 100% ×
(34)
VIN
T he corresponding power dissipation in the MOSFET , together
with any resistance added in series from input to output, is given by:
(35)
PLDO = (VIN –VOUT ) × IOUT
Minimum power dissipation and maximum efficiency are accom-
plished by choosing the lowest available input voltage that exceeds
the desired output voltage. However, if the chosen input source
is itself generated by a linear regulator, its power dissipation will
be increased in proportion to the additional current it must
now provide.
3.3V
ADP3158/
ADP3178
1ꢂF
Im plem enting Cur r ent Lim it for the Linear Regulator s
T he circuit of Figure 4 gives an example of a current limit pro-
tection circuit that can be used in conjunction with the linear
regulators. T he output voltage is internally set by the LRFB
pin. T he value of the current sense resistor may be calculated
as follows:
V
LR2
1kꢃ
LRDRV1
LRFB1
2.5V, 2.2A
R
S
68pF
250mꢃ
10kꢃ
100ꢂF
2.5V
540 mV 540 mV
Figure 6. Adding Overcurrent Protection to the
Linear Regulator
RS
=
= 250 mΩ
(36)
IO ( MAX )
2.2 A
Linear Regulator s
T he power rating of the current sense resistor must be at least:
T he two linear regulators provide a low cost, convenient, and
versatile solution for generating additional supply rails. T he
maximum output load current is determined by the size and
thermal impedance of the external N-channel power MOSFET
that is placed in series with the supply. T he output voltage is
sensed at the LRFB pin and compared to an internal reference
voltage in a negative feedback loop which keeps the output voltage
in regulation. If the load is reduced or increased, the MOSFET
drive will also be reduced or increased by the controller IC to
provide a well-regulated ±2.5% accurate output voltage.
The LRFB threshold of the ADP3158 are internally set at 2.5 V
(LRFB1) and 1.8 V (LRFB2), while the LRFB pins of the
ADP3178 are compared to an internal 1 V reference. This allows
the use of an external resistor divider network to program the linear
regulator output voltage. The correct resistor values for setting the
output voltage of the linear regulators in the ADP3178 can be
determined using:
2
(37)
PD (R = RS × IO ( MAX ) = 1.2W
)
S
T he maximum linear regulator MOSFET junction temperature
with a shorted output is:
TJ( MAX ) = TA +(θJC ×VIN × IO ( MAX )
)
(38)
TJ( MAX ) = 50°C + (1.4°C/W ×(3.3V × 2.2 A) = 60°C
which is within the maximum allowed by the MOSFET ’s data
sheet specification. T he maximum MOSFET junction tempera-
ture at nominal output is:
TJ( NOM ) = TA +(θJC ×(VIN –VOUT ) × IO ( NOM )
)
(39)
TJ( NOM ) = 50°C + (1.4°C/W ×(3.3V – 2.5 V ) × 2 A) = 52°C
T his example assumes an infinite heatsink. T he practical limita-
tion will be based on the actual heatsink used.
RU + RL
V
=V
×
OUT ( LR )
LRFB
RL
(32)
Assuming that RL = 10 kΩ, VOUT(LR) = 1.2 V and rearranging
Equation 32 to solve for RU yields:
10 kΩ × V
−V
LRFB
(
)
OUT ( LR )
RU
RU
=
=
V
LRFB
(33)
10 kΩ × 1.2 V −1V
(
)
= 2 kΩ
1V
–12–
REV. A
ADP3158/ADP3178
LAYO UT AND CO MP O NENT P LACEMENT GUID ELINES
T he following guidelines are recommended for optimal perfor-
mance of a switching regulator in a PC system:
diode, if used, including all interconnecting PCB traces and
planes. T he use of short and wide interconnection traces is
especially critical in this path for two reasons: it minimizes
the inductance in the switching loop, which can cause high-
energy ringing, and it accommodates the high current demand
with minimal voltage loss.
Gener al Recom m endations
1. For best results, a four-layer PCB is recommended. T his
should allow the needed versatility for control circuitry
interconnections with optimal placement, a signal ground
plane, power planes for both power ground and the input
power (e.g., 5 V), and wide interconnection traces in the
rest of the power delivery current paths.
8. A power Schottky diode (1 ~ 2 A dc rating) placed from the
lower MOSFET ’s source (anode) to drain (cathode) will
help to minimize switching power dissipation in the upper
MOSFET . In the bñôÖÑx of an effective Schottky diode,
this dissipation occurs through the following sequence of
switching events. T he lower MOSFET turns off in advance
of the upper MOSFET turning on (necessary to prevent
cross-conduction). T he circulating current in the power
converter, no longer finding a path for current through the
channel of the lower MOSFET , draws current through the
inherent body-drain diode of the MOSFET . T he upper
MOSFET turns on, and the reverse recovery characteristic
of the lower MOSFET’s body-drain diode prevents the drain
voltage from being pulled high quickly. The upper MOSFET
then conducts very large current while it momentarily has a
high voltage forced across it, which translates into added
power dissipation in the upper MOSFET. The Schottky diode
minimizes this problem by carrying a majority of the circu-
lating current when the lower MOSFET is turned off, and
by virtue of its essentially nonexistent reverse recovery time.
2. Whenever high currents must be routed between PCB
layers, vias should be used liberally to create several parallel
current paths so that the resistance and inductance intro-
duced by these current paths is minimized and the via
current rating is not exceeded.
3. If critical signal lines (including the voltage and current
sense lines of the controller IC) must cross through power
circuitry, it is best if a ground plane can be interposed
between those signal lines and the traces of the power
circuitry. T his serves as a shield to minimize noise injec-
tion into the signals at the cost of making signal ground a
bit noisier.
4. T he GND pin should connect first to a ceramic bypass
capacitor (on the VCC pin) and then into the power ground
plane. However, the ground plane should not extend under
other signal components, including the controller IC itself.
9. Whenever a power-dissipating component (e.g., a power
MOSFET ) is soldered to a PCB, the liberal use of vias,
both directly on the mounting pad and immediately sur-
rounding it, is recommended. T wo important reasons for
this are: improved current rating through the vias (if it is a
current path), and improved thermal performance—espe-
cially if the vias extend to the opposite side of the PCB where
a plane can more readily transfer the heat to the air.
5. T he output capacitors should also be connected as closely
as possible to the load (or connector) that receives the
power (e.g., a microprocessor core). If the load is distributed,
the capacitors should also be distributed, and generally in
proportion to where the load tends to be more dynamic. It
is also advised to keep the planar interconnection path short
(i.e., have input and output capacitors close together).
6. Absolutely avoid crossing any signal lines over the switching
power path loop, described below.
10. The output power path, though not as critical as the switch-
ing power path, should also be routed to encompass a small
area. The output power path is formed by the current path
through the inductor, the current sensing resistor, the out-
put capacitors, and back to the input capacitors.
P ower Cir cuitr y
7. T he switching power path should be routed on the PCB to
encompass the smallest possible area in order to minimize
radiated switching noise energy (i.e., EMI). Failure to take
proper precaution often results in EMI problems for the
entire PC system as well as noise-related operational prob-
lems in the power converter control circuitry. The switching
power path is the loop formed by the current path through
the input capacitors, the two FET s, and the power Schottky
11. For best EMI containment, the ground plane should extend
fully under all the power components. These are: the input
capacitors, the power MOSFET s and Schottky diode, the
inductor, the current sense resistor, any snubbing elements
that might be added to dampen ringing, and the output
capacitors.
REV. A
–13–
ADP3158/ADP3178
Signal Cir cuitr y
13. T he CS+ and CS– traces should be Kelvin-connected to
the current sense resistor so that the additional voltage drop
due to current flow on the PCB at the current sense resistor
connections does not affect the sensed voltage. It is desir-
able to have the controller IC close to the output capacitor
bank and not in the output power path, so that any voltage
drop between the output capacitors and the GND pin is
minimized, and voltage regulation is not compromised.
12. T he output voltage is sensed and regulated between the
GND pin (which connects to the signal ground plane) and
the CS– pin. T he output current is sensed (as a voltage)
and regulated between the CS– pin and the CS+ pin. In
order to avoid differential mode noise pickup in those sensed
signals, their loop areas should be small. T hus the CS–
trace should be routed atop the signal ground plane, and
the CS+ and CS– traces should be routed as a closely
coupled pair (CS+ should be over the signal ground plane
as well).
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
16-Lead SO IC
(R-16A/SO -16)
0.3937 (10.00)
0.3859 (9.80)
16
1
9
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
8
PIN 1
0.0688 (1.75)
0.0532 (1.35)
0.050 (1.27)
BSC
0.0196 (0.50)
0.0099 (0.25)
ꢄ 45ꢁ
8ꢁ
0ꢁ
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0500 (1.27)
0.0160 (0.41)
0.0099 (0.25)
0.0075 (0.19)
–14–
REV. A
Revision History–ADP3158/ADP3178
Location
P age
Global change from ADP3158 to ADP3158/ADP3178
Change from REV. 0 to REV. A.
Edits to GENERAL DESCRIPT ION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to FUNCT IONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edit to ERROR AMPLIFIER section of the SPECIFICAT IONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Addition to LINEAR REGULAT ORS section of the SPECIFICAT IONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Addition to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to the On-board Linear Regulator Controllers section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Edits to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Edits to Equations 24, 27, and 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Addition of new text to Linear Regulators section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
–15–
REV. A
–16–
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