ADP7102ACPZ-3.0-R7_技术文档

20 V, 300 mA, Low Noise, CMOS LDO

Data Sheet

ADP7102

FEATURES

TYPICAL APPLICATION CIRCUITS

Input voltage range: 3.3 V to 20 V

Maximum output current: 300 mA

VOUT = 5V

VIN

VOUT

VIN = 8V

+

CIN

1µF

COUT

1µF

SENSE

Low noise: 15 µV rms for fixed output versions

PSRR performance of 60 dB at 10 kHz, V_OUT= 3.3 V

Reverse current protection

Low dropout voltage: 200 mV at 300 mA load

Initial accuracy: 0.8%

RPG

100kΩ

R1

100kΩ

ON

EN/

UVLO

OFF

R2

100kΩ

PG

GND

Accuracy over line, load, and temperature: −2%, +1%

Low quiescent current (V_IN= 5 V), I_GND= 750 μA with 300 mA

load

Low shutdown current: 40 µA at V_IN= 12 V

Stable with small 1 µF ceramic output capacitor

7 fixed output voltage options: 1.5 V, 1.8 V, 2.5 V, 3 V, 3.3 V,

5 V, and 9 V

Adjustable output from 1.22 V to V_IN– V_DO

Foldback current limit and thermal overload protection

User programmable precision UVLO/enable

Power good indicator

Figure 1. ADP7102 with Fixed Output Voltage, 5 V

VOUT = 5V

COUT

1µF

VIN

VOUT

ADJ

VIN = 8V

+

CIN

1µF

R1

40.2kΩ

R2

13kΩ

R3

100kΩ

ON

RPG

100kΩ

EN/

UVLO

OFF

R4

100kΩ

PG

GND

Figure 2. ADP7102 with Adjustable Output Voltage, 5 V

8-lead LFCSP and 8-lead SOIC packages

APPLICATIONS

Regulation to noise sensitive applications: ADC, DAC

circuits, precision amplifiers, high frequency oscillators,

clocks, and PLLs

Communications and infrastructure

Medical and healthcare

Industrial and instrumentation

GENERAL DESCRIPTION

The ADP7102 is a CMOS, low dropout linear regulator that

operates from 3.3 V to 20 V and provides up to 300 mA of

output current. This high input voltage LDO is ideal for

regulation of high performance analog and mixed signal

circuits operating from 19 V to 1.22 V rails. Using an

advanced proprietary architecture, it provides high power

supply rejection, low noise, and achieves excellent line and

load transient response with just a small 1 µF ceramic

output capacitor.

The ADP7102 output noise voltage is 15 μV rms and is inde-

pendent of the output voltage. A digital power good output

allows power system monitors to check the health of the output

voltage. A user programmable precision undervoltage lockout

function facilitates sequencing of multiple power supplies.

The ADP7102 is available in 8-lead, 3 mm × 3 mm LFCSP

and 8-lead SOIC packages. The LFCSP offers a very compact

solution and also provides excellent thermal performance for

applications requiring up to 300 mA of output current in a

small, low-profile footprint.

The ADP7102 is available in 7 fixed output voltage options and

an adjustable version, which allows output voltages that range

from 1.22 V to V_IN− V_DOvia an external feedback divider.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADP7102

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Theory of Operation ...................................................................... 17

Applications Information .............................................................. 18

Capacitor Selection .................................................................... 18

Programable Undervoltage Lockout (UVLO)........................... 19

Power Good Feature .................................................................. 20

Noise Reduction of the Adjustable ADP7102 ........................ 20

Current Limit and Thermal Overload Protection ................. 21

Thermal Considerations............................................................ 21

Printed Circuit Board Layout Considerations............................ 24

Outline Dimensions....................................................................... 25

Ordering Guide .......................................................................... 26

Applications....................................................................................... 1

Typical Application Circuits............................................................ 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Input and Output Capacitor, Recommended Specifications.. 4

Absolute Maximum Ratings............................................................ 5

Thermal Data ................................................................................ 5

ESD Caution.................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

Typical Performance Characteristics ............................................. 7

REVISION HISTORY

11/11—Rev. 0 to Rev. A

Changes to Figure 50...................................................................... 14

10/11—Revision 0: Initial Version

Rev. A | Page 2 of 28

Data Sheet

ADP7102

SPECIFICATIONS

V_IN= (V_OUT+ 1 V) or 3.3 V (whichever is greater), EN = V_IN, I_OUT= 10 mA, C_IN= C_OUT= 1 µF, T_A= 25°C, unless otherwise noted.

Table 1.

Parameter

Symbol

V_IN

Conditions

Min

Typ

400

450

650

750

40

Max

Unit

V

INPUT VOLTAGE RANGE

OPERATING SUPPLY CURRENT

3.3

20

I_GND

I_OUT= 100 µA, V_IN= 10 V

I_OUT= 100 µA, V_IN= 10 V, T_J= −40°C to +125°C

I_OUT= 10 mA, V_IN= 10 V

I_OUT= 10 mA, V_IN= 10 V, T_J= −40°C to +125°C

I_OUT= 150 mA, V_IN= 10 V

I_OUT= 150 mA, V_IN= 10 V, T_J= −40°C to +125°C

I_OUT= 300 mA, V_IN= 10 V

I_OUT= 300 mA, V_IN= 10 V, T_J= −40°C to +125°C

EN = GND, V_IN= 12 V

EN = GND, V_IN= 12 V, T_J= −40°C to +125°C

EN = GND, V_IN= 0 V, V_OUT= 20 V

µA

900

1050

1250

1400

75

SHUTDOWN CURRENT

I_GND-SD

INPUT REVERSE CURRENT

I_REV-INPUT

0.3

EN = GND, V_IN= 0 V, V_OUT= 20 V, T_J= −40°C to +125°C

5

OUTPUT VOLTAGE ACCURACY

Fixed Output Voltage Accuracy

V_OUT

I_OUT= 10 mA

1 mA < I_OUT< 300 mA, V_IN= (V_OUT+ 1 V) to 20 V,

T_J= −40°C to +125°C

–0.8

–2

+0.8

+1

%

Adjustable Output Voltage

Accuracy

V_ADJ

I_OUT= 10 mA

1.21

1.22 1.23

1.232

V

1 mA < I_OUT< 300 mA, V_IN= (V_OUT+ 1 V) to 20 V,

T_J= −40°C to +125°C

1.196

−0.015

LINE REGULATION

LOAD REGULATION ¹

∆V_OUT/∆V_INV_IN= (V_OUT+ 1 V) to 20 V, T_J= −40°C to +125°C

∆V_OUT/∆I_OUTI_OUT= 1 mA to 300 mA

+0.015 %/V

%/A

0.2

I_OUT= 1 mA to 300 mA, T_J= −40°C to +125°C

1.0

%/A

nA

ADJ INPUT BIAS CURRENT

SENSE INPUT BIAS CURRENT

DROPOUT VOLTAGE²

ADJ_I-BIAS

1 mA < I_OUT< 300 mA, V_IN= (V_OUT+ 1 V) to 20 V,

ADJ connected to VOUT

1 mA < I_OUT< 300 mA, V_IN= (V_OUT+ 1 V) to 20 V,

SENSE connected to VOUT, V_OUT= 1.5 V

10

1

SENSE_I-BIAS

V_DROPOUT

μA

I_OUT= 10 mA

I_OUT= 10 mA, T_J= −40°C to +125°C

I_OUT= 150 mA

I_OUT= 150 mA, T_J= −40°C to +125°C

I_OUT= 300 mA

I_OUT= 300 mA, T_J= −40°C to +125°C

V_OUT= 5 V

20

mV

µs

40

100

200

175

325

750

START-UP TIME³

t_START-UP

I_LIMIT

800

575

CURRENT-LIMIT THRESHOLD⁴

PG OUTPUT LOGIC LEVEL

PG Output Logic High

PG Output Logic Low

450

1.0

mA

PG_HIGH

PG_LOW

I_OH< 1 µA

I_OL< 2 mA

V

0.4

PG OUTPUT THRESHOLD

Output Voltage Falling

Output Voltage Rising

THERMAL SHUTDOWN

Thermal Shutdown Threshold

Thermal Shutdown Hysteresis

PG_FALL

PG_RISE

−9.2

−6.5

%

TS_SD

T_Jrising

150

15

°C

TS_SD-HYS

Rev. A | Page 3 of 28

ADP7102

Data Sheet

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

PROGRAMMABLE EN/UVLO

UVLO Threshold rising

UVLO Threshold falling

UVLO_RISE

UVLO_FALL

3.3 V ≤ V_IN≤ 20 V, T_J= −40°C to +125°C

3.3 V ≤ V_IN≤ 20 V, T_J= −40°C to +125°C, 10 kΩ

in series with enable pin

1.18

1.23 1.28

1.13

V

UVLO Hysteresis Current

Enable Pulldown Current

INPUT VOLTAGE

UVLO_HYS

I_EN-IN

V_EN> 1.25 V, T_J= −40°C to +125°C

EN = V_IN

7.5

9.8

500

12

µA

nA

Start Threshold

Shutdown Threshold

Hysteresis

V_START

V_SHUTDOWN

T_J= −40°C to +125°C

3.2

V

mV

2.45

250

15

18

OUTPUT NOISE

OUT_NOISE

10 Hz to 100 kHz, V_IN= 5.5 V, V_OUT= 1.8 V

10 Hz to 100 kHz, V_IN= 6.3 V, V_OUT= 3.3 V

10 Hz to 100 kHz, V_IN= 8 V, V_OUT= 5 V

10 Hz to 100 kHz, V_IN= 12 V, V_OUT= 9 V

10 Hz to 100 kHz, V_IN= 5.5 V, V_OUT= 1.5 V,

adjustable mode

µV rms

10 Hz to 100 kHz, V_IN= 12 V, V_OUT= 5 V,

adjustable mode

10 Hz to 100 kHz, V_IN= 18 V, V_OUT= 15 V,

adjustable mode

30

65

µV rms

POWER SUPPLY REJECTION RATIO PSRR

100 kHz, V_IN= 4.3 V, V_OUT= 3.3 V

100 kHz, V_IN= 6 V, V_OUT= 5 V

10 kHz, V_IN= 4.3 V, V_OUT= 3.3 V

10 kHz, V_IN= 6 V, V_OUT= 5 V

100 kHz, V_IN= 3.3 V, V_OUT= 1.8 V, adjustable mode

100 kHz, V_IN= 6 V, V_OUT= 5 V, adjustable mode

100 kHz, V_IN= 16 V, V_OUT= 15 V, adjustable mode

10 kHz, V_IN= 3.3 V, V_OUT= 1.8 V, adjustable mode

10 kHz, V_IN= 6 V, V_OUT= 5 V, adjustable mode

10 kHz, V_IN= 16 V, V_OUT= 15 V, adjustable mode

50

60

50

60

80

dB

¹Based on an end-point calculation using 1 mA and 300 mA loads. See Figure 6 for typical load regulation performance for loads less than 1 mA.

²Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output

voltages above 3.0 V.

³Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value.

⁴Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 5.0 V

output voltage is defined as the current that causes the output voltage to drop to 90% of 5.0 V, or 4.5 V.

INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS

Table 2.

Parameter

Minimum Input and Output Capacitance¹

Capacitor ESR

Symbol

C_MIN

R_ESR

Conditions

Min

0.7

0.001

Typ

Max

Unit

µF

Ω

T_A= −40°C to +125°C

0.2

¹The minimum input and output capacitance should be greater than 0.7 μF over the full range of operating conditions. The full range of operating conditions in the

application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;

Y5V and Z5U capacitors are not recommended for use with any LDO.

Rev. A | Page 4 of 28

Data Sheet

ADP7102

ABSOLUTE MAXIMUM RATINGS

Table 3.

board design is required. The value of θ_JAmay vary, depending

on PCB material, layout, and environmental conditions. The

specified values of θ_JAare based on a 4-layer, 4 in. × 3 in. circuit

board. See JESD51-7 and JESD51-9 for detailed information on

the board construction. For additional information, see the

AN-617 Application Note, MicroCSP™ Wafer Level Chip Scale

Package, available at www.analog.com.

Parameter

Rating

VIN to GND

VOUT to GND

EN/UVLO to GND

–0.3 V to +22 V

–0.3 V to +20 V

–0.3 V to VIN

PG to GND

–0.3 V to VIN

SENSE/ADJ to GND

–0.3 V to VOUT

–65°C to +150°C

–40°C to +125°C

–40°C to +85°C

JEDEC J-STD-020

Ψ_JBis the junction-to-board thermal characterization parameter

Storage Temperature Range

Operating Junction Temperature Range

Operating Ambient Temperature Range

Soldering Conditions

with units of °C/W. The package’s Ψ_JBis based on modeling and

calculation using a 4-layer board. The JESD51-12, Guidelines

for Reporting and Using Electronic Package Thermal

Information, states that thermal characterization parameters are

not the same as thermal resistances. Ψ_JBmeasures the

component power flowing through multiple thermal paths

rather than a single path as in thermal resistance, θ_JB. Therefore,

Stresses above those listed under absolute maximum ratings

may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or

any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Ψ

_JBthermal paths include convection from the top of the

package as well as radiation from the package, factors that make

_JBmore useful in real-world applications. Maximum junction

Ψ

temperature (T_J) is calculated from the board temperature (T_B)

and power dissipation (P_D) using the formula

THERMAL DATA

T_J= T_B+ (P_D× Ψ_JB)

Absolute maximum ratings apply individually only, not in

combination. The ADP7102 can be damaged when the junction

temperature limit is exceeded. Monitoring ambient temperature

does not guarantee that T_Jis within the specified temperature

limits. In applications with high power dissipation and poor

thermal resistance, the maximum ambient temperature may

have to be derated.

See JESD51-8 and JESD51-12 for more detailed information

about Ψ_JB.

Thermal Resistance

θ_JAand Ψ_JBare specified for the worst-case conditions, that is, a

device soldered in a circuit board for surface-mount packages.

θ

_JCis a parameter for surface-mount packages with top

mounted heatsinks. θ_JCis presented here for reference only.

In applications with moderate power dissipation and low PCB

thermal resistance, the maximum ambient temperature can

exceed the maximum limit as long as the junction temperature

is within specification limits. The junction temperature (T_J) of

the device is dependent on the ambient temperature (T_A), the

power dissipation of the device (P_D), and the junction-to-

ambient thermal resistance of the package (θ_JA).

Table 4. Thermal Resistance

Package Type

8-Lead LFCSP

8-Lead SOIC

Ψ_JB

Unit

°C/W

θ_JA

θ_JC

40.1

48.5

27.1

58.4

17.2

31.3

Maximum junction temperature (T_J) is calculated from the

ambient temperature (T_A) and power dissipation (P_D) using the

formula

ESD CAUTION

T_J= T_A+ (P_D× θ_JA)

Junction-to-ambient thermal resistance (θ_JA) of the package is

based on modeling and calculation using a 4-layer board. The

junction-to-ambient thermal resistance is highly dependent on

the application and board layout. In applications where high

maximum power dissipation exists, close attention to thermal

Rev. A | Page 5 of 28

ADP7102

Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

VOUT 1

SENSE/ADJ 2

GND 3

8 VIN

VOUT

SENSE/ADJ

GND

1

2

3

4

8

7

6

5

VIN

ADP7102

7 PG

ADP7102

PG

TOP VIEW

6 GND

5 EN/UVLO

GND

(Not to Scale)

NC

EN/UVLO

NC 4

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO

THIS PIN.

1. NC = NO CONNECT. DO NOT CONNECT TO

THIS PIN.

2. IT IS HIGHLY RECOMMENDED THAT THE

EXPOSED PAD ON THE BOTTOM OF THE

PACKAGE BE CONNECTED TO THE GROUND

PLANE ON THE BOARD.

2. IT IS HIGHLY RECOMMENDED THAT THE

EXPOSED PAD ON THE BOTTOM OF THE

PACKAGE BE CONNECTED TO THE GROUND

PLANE ON THE BOARD.

Figure 3. LFCSP Package

Figure 4. Narrow Body SOIC Package

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

2

VOUT

SENSE/ADJ

Regulated Output Voltage. Bypass VOUT to GND with a 1 µF or greater capacitor.

Sense (SENSE). Measures the actual output voltage at the load and feeds it to the error amplifier.

Connect SENSE as close as possible to the load to minimize the effect of IR drop between the

regulator output and the load. This function applies to fixed voltages only.

Adjust Input (ADJ). An external resistor divider sets the output voltage. This function applies to

adjustable voltages only.

3

4

5

GND

NC

EN/UVLO

Ground.

Do Not Connect to this Pin.

Enable Input (EN). Drive EN high to turn on the regulator; drive EN low to turn off the regulator.

For automatic startup, connect EN to VIN.

Programmable Undervoltage Lockout (UVLO). When the programmable UVLO function is used,

the upper and lower thresholds are determined by the programming resistors.

6

7

GND

PG

Ground.

Power Good. This open-drain output requires an external pull-up resistor to VIN or VOUT. If the

part is in shutdown, current limit, thermal shutdown, or falls below 90% of the nominal output

voltage, PG immediately transitions low. If the power good function is not used, the pin may be

left open or connected to ground.

8

VIN

Regulator Input Supply. Bypass VIN to GND with a 1 µF or greater capacitor.

EPAD

Exposed Pad. Exposed paddle on the bottom of the package. The EPAD enhances thermal

performance and is electrically connected to GND inside the package. It is highly recommended

that the EPAD be connected to the ground plane on the board.

Rev. A | Page 6 of 28

Data Sheet

ADP7102

TYPICAL PERFORMANCE CHARACTERISTICS

V_IN= 5 V, V_OUT= 3.3 V, I_OUT= 1 mA, C_IN= C_OUT= 1 µF, T_A= 25°C, unless otherwise noted.

900

800

700

600

500

400

300

200

100

0

3.35

3.33

3.31

3.29

3.27

3.25

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 300mA

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 300mA

–40°C

–5°C

25°C

°C

85°C

125°C

–40°C

–5°C

25°C

°C

85°C

125°C

T

(

)

T

(

)

J

Figure 5. Output Voltage vs. Junction Temperature

Figure 8. Ground Current vs. Junction Temperature

3.35

3.33

3.31

3.29

3.27

3.25

700

600

500

400

300

200

100

0

0.1

1

10

(mA)

100

1000

0.1

1

10

(mA)

100

1000

I

LOAD

Figure 6. Output Voltage vs. Load Current

Figure 9. Ground Current vs. Load Current

3.35

3.33

3.31

3.29

3.27

3.25

900

800

700

600

500

400

300

200

100

0

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 300mA

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 300mA

4

6

8

10

12

(V)

14

16

18

20

4

6

8

10

12

(V)

14

16

18

20

V

IN

Figure 10. Ground Current vs. Input Voltage

Figure 7. Output Voltage vs. Input Voltage

Rev. A | Page 7 of 28

ADP7102

Data Sheet

1400

1200

1000

800

600

400

200

0

160

3.3V

4.0V

6.0V

8.0V

12.0V

20.0V

140

120

100

80

60

40

LOAD = 5mA

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 300mA

20

0

–50

3.10

3.20

3.30

3.40

(V)

3.50

3.60

3.70

–25

0

25

50

75

100

125

V

TEMPERATURE (°C)

IN

Figure 11. Shutdown Current vs. Temperature at Various Input Voltages

Figure 14. Ground Current vs. Input Voltage (in Dropout)

5.05

5.04

5.03

5.02

5.01

5.00

4.99

4.98

4.97

4.96

4.95

200

V

A

= 3.3V

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 300mA

OUT

T

= 25°C

180

160

140

120

100

80

60

40

20

0

1

10

100

1000

–40°C

–5°C

25°C

°C

85°C

125°C

I

(mA)

T

(

)

LOAD

J

Figure 12. Dropout Voltage vs. Load Current

Figure 15. Output Voltage vs. Junction Temperature, V_OUT= 5 V

5.05

5.04

5.03

5.02

5.01

5.00

4.99

4.98

4.97

4.96

4.95

3.35

3.30

3.25

3.20

3.15

3.10

3.05

3.00

2.95

2.90

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 300mA

0.1

1

10

(mA)

100

1000

3.10

3.20

3.30

3.40

(V)

3.50

3.60

3.70

I

LOAD

V

IN

Figure 13. Output Voltage vs. Input Voltage (in Dropout)

Figure 16. Output Voltage vs. Load Current, V_OUT= 5 V

Rev. A | Page 8 of 28

Data Sheet

ADP7102

5.05

900

800

700

600

500

400

300

200

100

0

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 300mA

LOAD = 1mA

5.04

5.03

5.02

5.01

5.00

4.99

4.98

4.97

4.96

4.95

LOAD = 10mA

LOAD = 100mA

LOAD = 300mA

6

8

10

12

14

16

18

20

6

8

10

12

14

16

18

20

V

(V)

IN

V

(V)

IN

Figure 17. Output Voltage vs. Input Voltage, V_OUT= 5 V

Figure 20. Ground Current vs. Input Voltage, V_OUT= 5 V

180

160

140

120

100

80

1000

900

800

700

600

500

400

300

200

100

0

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 300mA

V

= 5V

= 25°C

OUT

T

A

60

40

20

0

1

10

100

1000

–40°C

–5°C

25°C

°C

85°C

125°C

I

(mA)

LOAD

T

(

)

J

Figure 18. Ground Current vs. Junction Temperature, V_OUT= 5 V

Figure 21. Dropout Voltage vs. Load Current, V_OUT= 5 V

700

600

500

400

300

200

100

0

5.05

5.00

4.95

4.90

4.85

4.80

4.75

4.70

4.65

LOAD = 5mA

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 300mA

0.1

1

10

(mA)

100

1000

4.8

4.9

5.0

5.1

(V)

5.2

5.3

5.4

I

V

LOAD

IN

Figure 22. Output Voltage vs. Input Voltage (in Dropout), V_OUT= 5 V

Figure 19. Ground Current vs. Load Current, V_OUT= 5 V

Rev. A | Page 9 of 28

ADP7102

Data Sheet

1.85

1.83

1.81

1.79

1.77

1.75

2500

2000

1500

1000

500

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 300mA

LOAD = 5mA

0

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 300mA

–500

2

4

6

8

10

12

(V)

14

16

18

20

4.80

4.90

5.00

5.10

(V)

5.20

5.30

5.40

V

IN

V

IN

Figure 23. Ground Current vs. Input Voltage (in Dropout), V_OUT= 5 V

Figure 26. Output Voltage vs. Input Voltage, V_OUT= 1.8 V

900

800

700

600

500

400

300

200

100

0

1.85

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 300mA

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

1.83

1.81

1.79

1.77

1.75

LOAD = 300mA

–40°C

–5°C

25°C

(°C)

85°C

125°C

–40°C

–5°C

25°C

°C

85°C

125°C

T

J

T

(

)

J

Figure 24. Output Voltage vs. Junction Temperature, V_OUT= 1.8 V

Figure 27. Ground Current vs. Junction Temperature, V_OUT= 1.8 V

700

600

500

400

300

200

100

0

1.85

1.83

1.81

1.79

1.77

1.75

0.1

1

10

(mA)

100

1000

0.1

1

10

(mA)

100

1000

I

LOAD

Figure 25. Output Voltage vs. Load Current, V_OUT= 1.8 V

Figure 28. Ground Current vs. Load Current, V_OUT= 1.8 V

Rev. A | Page 10 of 28

Data Sheet

ADP7102

5.08

5.07

5.06

5.05

5.04

5.03

5.02

5.01

5.00

4.99

4.98

1200

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 300mA

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 300mA

1000

800

600

400

200

0

6

8

10

12

14

16

18

20

2

4

6

8

10

12

(V)

14

16

18

20

V

(V)

IN

V

IN

Figure 29. Ground Current vs. Input Voltage, V_OUT= 1.8 V

Figure 32. Output Voltage vs. Input Voltage, V_OUT= 5 V, Adjustable

5.08

5.07

5.06

5.05

5.04

5.03

5.02

5.01

5.00

4.99

4.98

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 300mA

2.0

3.3V

4V

5V

6V

8V

10V

12V

15V

18V

20V

1.5

1.0

0.5

0

–40°C

–5°C

25°C

°C

85°C

125°C

–40

–20

0

20

40

60

80

100

120

140

T

(

)

J

TEMPERATURE (°C)

Figure 33. Reverse Input Current vs. Temperature, V_IN= 0 V, Different

Voltages on V_OUT

Figure 30. Output Voltage vs. Junction Temperature, V_OUT= 5 V, Adjustable

5.08

5.07

5.06

5.05

5.04

5.03

5.02

5.01

5.00

4.99

4.98

0

LOAD = 300mA

LOAD = 100mA

–10

LOAD = 10mA

LOAD = 1mA

–20

–30

–40

–50

–60

–70

–80

–90

–100

0.1

1

10

(mA)

100

1000

10

100

1k

10k

100k

1M

10M

I

LOAD

FREQUENCY (Hz)

Figure 34. Power Supply Rejection Ratio vs. Frequency, V_OUT= 1.8 V,

_IN= 3.3 V

Figure 31. Output Voltage vs. Load Current, V_OUT= 5 V, Adjustable

V

Rev. A | Page 11 of 28

ADP7102

Data Sheet

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

LOAD = 1mA

LOAD = 300mA

LOAD = 10mA

LOAD = 100mA

LOAD = 300mA

LOAD = 100mA

LOAD = 10mA

LOAD = 1mA

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 35. Power Supply Rejection Ratio vs. Frequency, V_OUT= 3.3 V,

Figure 38. Power Supply Rejection Ratio vs. Frequency, V_OUT= 5 V, V_IN= 6.5 V

V_IN= 4.8 V

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

LOAD = 300mA

LOAD = 100mA

LOAD = 10mA

LOAD = 1mA

LOAD = 10mA

–10

LOAD = 100mA

LOAD = 300mA

–20

–30

–40

–50

–60

–70

–80

–90

–100

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 36. Power Supply Rejection Ratio vs. Frequency, V_OUT= 3.3 V,

Figure 39. Power Supply Rejection Ratio vs. Frequency, V_OUT= 5 V, V_IN= 6 V

V_IN= 4.3 V

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

LOAD = 1mA

LOAD = 300mA

LOAD = 100mA

LOAD = 10mA

LOAD = 1mA

LOAD = 10mA

–10

LOAD = 100mA

LOAD = 300mA

–20

–30

–40

–50

–60

–70

–80

–90

–100

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 40. Power Supply Rejection Ratio vs. Frequency, V_OUT= 5 V, V_IN= 5.5 V

Figure 37. Power Supply Rejection Ratio vs. Frequency, V_OUT= 3.3 V,

_IN= 3.8 V

V

Rev. A | Page 12 of 28

Data Sheet

ADP7102

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 300mA

LOAD = 10mA

LOAD = 100mA

LOAD = 300mA

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 41. Power Supply Rejection Ratio vs. Frequency, V_OUT= 5 V, V_IN= 5.3 V

Figure 44. Power Supply Rejection Ratio vs. Frequency, V_OUT= 5 V, V_IN= 6 V,

Adjustable with Noise Reduction Circuit

0

LOAD = 1mA

LOAD = 10mA

–10

LOAD = 100mA

LOAD = 300mA

–20

LOAD = 300mA

–20

–30

–40

–50

–60

–70

–80

–90

–100

–30

–40

–50

–60

–70

–80

–90

–100

0

0.25

0.50

0.75

1.00

1.25

1.50

10

100

1k

10k

100k

1M

10M

HEADROOM VOLTAGE (V)

FREQUENCY (Hz)

Figure 42. Power Supply Rejection Ratio vs. Frequency, V_OUT= 5 V, V_IN= 5.2 V

Figure 45. Power Supply Rejection Ratio vs. Headroom Voltage, 100 Hz,

V_OUT= 5 V

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 300mA

–10

LOAD = 100mA

LOAD = 300mA

–20

–30

–40

–50

–60

–70

–80

–90

–100

10

100

1k

10k

100k

1M

10M

0

0.25

0.50

0.75

1.00

1.25

1.50

FREQUENCY (Hz)

HEADROOM VOLTAGE

Figure 43. Power Supply Rejection Ratio vs. Frequency, V_OUT= 5 V, V_IN= 6 V,

Adjustable

Figure 46. Power Supply Rejection Ratio vs. Headroom Voltage, 1 kHz,

_OUT= 5 V

V

Rev. A | Page 13 of 28

ADP7102

Data Sheet

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

10

3.3V

LOAD = 1mA

5V

LOAD = 10mA

LOAD = 100mA

LOAD = 300mA

5V ADJ

5V ADJ NR

1

0.1

0.01

–100

0

0.25

0.50

0.75

1.00

1.25

1.50

10

100

1k

10k

100k

HEADROOM VOLTAGE (V)

FREQUENCY (Hz)

Figure 47. Power Supply Rejection Ratio vs. Headroom Voltage, 10 kHz,

Figure 50. Output Noise Spectral Density, I_LOAD= 10 mA, C_OUT= 1 μF

V_OUT= 5 V

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 300mA

LOAD CURRENT

1

OUTPUT VOLTAGE

2

B

CH1 200mA Ω^BCH2 50mV

M 20µs

A CH1

76mA

0

0.25

0.50

0.75

1.00

1.25

1.50

W

T 10.4%

HEADROOM VOLTAGE (V)

Figure 48. Power Supply Rejection Ratio vs. Headroom Voltage, 100 kHz,

_OUT= 5 V

Figure 51. Load Transient Response, C_IN, C_OUT= 1 μF, I_LOAD= 1 mA to 300 mA,

_OUT= 1.8 V, V_IN= 5 V

V

30

25

20

15

10

5

LOAD CURRENT

1

OUTPUT VOLTAGE

2

3.3V

1.8V

5V

ADJ

5V

NR

Ω ^B

0

B

W

CH1 200mA

CH2 50mV

M 20µs

A CH1

168mA

W

0.00001

0.0001

0.001

0.01

0.1

1

T

10.2%

LOAD CURRENT (A)

Figure 49. Output Noise vs. Load Current and Output Voltage,

C_OUT= 1 μF

Figure 52. Load Transient Response, C_IN, C_OUT= 1 μF, I_LOAD= 1 mA to 300 mA,

_OUT= 3.3 V, V_IN= 5 V

V

Rev. A | Page 14 of 28

Data Sheet

ADP7102

LOAD CURRENT

INPUT VOLTAGE

1

OUTPUT VOLTAGE

2

1

OUTPUT VOLTAGE

2

B

Ω ^B

W

CH1 1V

CH2 10mV

M 4µs

A CH4

1.56V

CH1 200mA

CH2 50mV

M 20µs

W

A CH1

216mA

W

T 9.8%

T

10.2%

Figure 55. Line Transient Response, C_IN, C_OUT= 1 μF, I_LOAD= 300 mA,

_OUT= 3.3 V

Figure 53. Load Transient Response, C_IN, C_OUT= 1 μF, I_LOAD= 1 mA to 300 mA,

_OUT= 5 V, V_IN= 7 V

V

INPUT VOLTAGE

OUTPUT VOLTAGE

2

1

2

1

B

CH1 1V

CH2 10mV

M 4µs

T 9.8%

A CH4

1.56V

CH1 1V

CH2 10mV

M 4µs

W

A CH4

1.56V

W

T

9.8%

Figure 54. Line Transient Response, C_IN, C_OUT= 1 μF, I_LOAD= 300 mA,

_OUT= 1.8 V

Figure 56. Line Transient Response, C_IN, C_OUT= 1 μF, I_LOAD= 300 mA, V_OUT= 5 V

V

Rev. A | Page 15 of 28

ADP7102

Data Sheet

INPUT VOLTAGE

OUTPUT VOLTAGE

2

1

OUTPUT VOLTAGE

2

1

B

CH1 1V

CH2 10mV

M 4µs

T 9.8%

A CH4

1.56V

B

W

CH1 1V

CH2 10mV

M 4µs

T 9.8%

A CH4

1.56V

W

Figure 57. Line Transient Response, C_IN, C_OUT= 1 μF, I_LOAD= 1 mA, V_OUT= 1.8 V

Figure 59. Line Transient Response, C_IN, C_OUT= 1 μF, I_LOAD= 1 mA, V_OUT= 5 V

INPUT VOLTAGE

OUTPUT VOLTAGE

2

1

B

CH1 1V

CH2 10mV

M 4µs

T 9.8%

A CH4

1.56V

W

Figure 58. Line Transient Response, C_IN, C_OUT= 1 μF, I_LOAD= 1 mA, V_OUT= 3.3 V

Rev. A | Page 16 of 28

Data Sheet

ADP7102

THEORY OF OPERATION

The ADP7102 is a low quiescent current, low-dropout linear

regulator that operates from 3.3 V to 20 V and provides up to

300 mA of output current. Drawing a low 750 μA of quiescent

current (typical) at full load makes the ADP7102 ideal for

battery-operated portable equipment. Typical shutdown

current consumption is 40 μA at room temperature.

is higher than the reference voltage, the gate of the PMOS

device is pulled higher, allowing less current to pass and

decreasing the output voltage.

The ADP7102 is available in 7 fixed output voltage options,

ranging from 1.8 V to 9 V and in an adjustable version with

an output voltage that can be set to between 1.22 V and 19 V

by an external voltage divider. The output voltage can be set

according to the following equation:

Optimized for use with small 1 µF ceramic capacitors, the

ADP7102 provides excellent transient performance.

V

_OUT= 1.22 V(1 + R1/R2)

VIN

VOUT

VREG

10µA

VOUT = 5V

VIN

VOUT

VIN = 8V

SHORT-CIRCUIT,

THERMAL

GND

+

R1

+

PGOOD

R1

PG

CIN

1µF

COUT

1µF

40.2kΩ

PROTECT

ADJ

SENSE

R3

100kΩ

SHUTDOWN

ON

R2

RPG

100kΩ

EN/

UVLO

R2

13kΩ

OFF

EN/

UVLO

R4

100kΩ

PG

GND

1.22V

REFERENCE

Figure 62. Typical Adjustable Output Voltage Application Schematic

Figure 60. Fixed Output Voltage Internal Block Diagram

The value of R2 should be less than 200 kΩ to minimize

errors in the output voltage caused by the ADJ pin input

current. For example, when R1 and R2 each equal 200 kΩ,

the output voltage is 2.44 V. The output voltage error

introduced by the ADJ pin input current is 2 mV or 0.08%,

assuming a typical ADJ pin input current of 10 nA at 25°C.

VIN

VOUT

VREG

10µA

SHORT-CIRCUIT,

THERMAL

GND

PGOOD

PG

PROTECT

SHUTDOWN

The ADP7102 uses the EN/UVLO pin to enable and disable

the VOUT pin under normal operating conditions. When

EN/UVLO is high, VOUT turns on, when EN is low, VOUT

turns off. For automatic startup, EN/UVLO can be tied to VIN.

EN/

UVLO

SENSE

1.22V

REFERENCE

The ADP7102 incorporates reverse current protections

circuitry that prevents current flow backwards through the

pass element when the output voltage is greater than the input

voltage. A comparator senses the difference between the input

and output voltages. When the difference between the input

voltage and output voltage exceeds 55 mV, the body of the PFET

is switched to V_OUTand turned off or opened. In other words,

the gate is connected to VOUT.

Figure 61. Adjustable Output Voltage Internal Block Diagram

Internally, the ADP7102 consists of a reference, an error

amplifier, a feedback voltage divider, and a PMOS pass

transistor. Output current is delivered via the PMOS pass

device, which is controlled by the error amplifier. The error

amplifier compares the reference voltage with the feedback

voltage from the output and amplifies the difference. If the

feedback voltage is lower than the reference voltage, the gate

of the PMOS device is pulled lower, allowing more current to

pass and increasing the output voltage. If the feedback voltage

Rev. A | Page 17 of 28

ADP7102

Data Sheet

APPLICATIONS INFORMATION

Figure 64 depicts the capacitance vs. voltage bias characteristic

of an 0402, 1 µF, 10 V, X5R capacitor. The voltage stability of a

capacitor is strongly influenced by the capacitor size and voltage

rating. In general, a capacitor in a larger package or higher voltage

rating exhibits better stability. The temperature variation of the

X5R dielectric is ~ 15% over the −40°C to +85°C temperature

range and is not a function of package or voltage rating.

1.2

CAPACITOR SELECTION

Output Capacitor

The ADP7102 is designed for operation with small, space-

saving ceramic capacitors but functions with most commonly

used capacitors as long as care is taken with regard to the

effective series resistance (ESR) value. The ESR of the out-

put capacitor affects the stability of the LDO control loop. A

minimum of 1 µF capacitance with an ESR of 0.2 Ω or less is

recommended to ensure the stability of the ADP7102. Transient

response to changes in load current is also affected by output

capacitance. Using a larger value of output capacitance improves

the transient response of the ADP7102 to large changes in load

current. Figure 63 shows the transient responses for an output

capacitance value of 1 µF.

1.0

0.8

0.6

0.4

0.2

0

LOAD CURRENT

1

0

2

4

6

8

10

VOLTAGE (V)

Figure 64. Capacitance vs. Voltage Characteristic

OUTPUT VOLTAGE

2

Use Equation 1 to determine the worst-case capacitance

accounting for capacitor variation over temperature,

component tolerance, and voltage.

C

_EFF= C_BIAS× (1 − TEMPCO) × (1 − TOL)

where:

_BIASis the effective capacitance at the operating voltage.

(1)

B

CH1 200mA Ω^BCH2 50mV

M 20µs

T 10.4%

A CH1

76mA

W

C

Figure 63. Output Transient Response, V_OUT= 1.8 V, C_OUT= 1 µF

TEMPCO is the worst-case capacitor temperature coefficient.

TOL is the worst-case component tolerance.

Input Bypass Capacitor

Connecting a 1 µF capacitor from VIN to GND reduces

the circuit sensitivity to printed circuit board (PCB) layout,

especially when long input traces or high source impedance

are encountered. If greater than 1 µF of output capacitance is

required, the input capacitor should be increased to match it.

In this example, the worst-case temperature coefficient

(TEMPCO) over −40°C to +85°C is assumed to be 15% for

an X5R dielectric. The tolerance of the capacitor (TOL) is

assumed to be 10%, and C_BIASis 0.94 μF at 1.8 V, as shown

in Figure 64.

Input and Output Capacitor Properties

Substituting these values in Equation 1 yields

Any good quality ceramic capacitors can be used with the

ADP7102, as long as they meet the minimum capacitance and

maximum ESR requirements. Ceramic capacitors are manufac-

tured with a variety of dielectrics, each with different behavior

over temperature and applied voltage. Capacitors must have a

dielectric adequate to ensure the minimum capacitance over

the necessary temperature range and dc bias conditions. X5R

or X7R dielectrics with a voltage rating of 6.3 V to 50 V are

recommended. Y5V and Z5U dielectrics are not recommended,

due to their poor temperature and dc bias characteristics.

C

_EFF= 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF

Therefore, the capacitor chosen in this example meets the

minimum capacitance requirement of the LDO over temper-

ature and tolerance at the chosen output voltage.

To guarantee the performance of the ADP7102, it is imperative

that the effects of dc bias, temperature, and tolerances on the

behavior of the capacitors be evaluated for each application.

Rev. A | Page 18 of 28

Data Sheet

ADP7102

PROGRAMABLE UNDERVOLTAGE LOCKOUT (UVLO)

VOUT = 5V

VIN

VOUT

VIN = 8V

ON

+

CIN

1µF

COUT

1µF

The ADP7102 uses the EN/UVLO pin to enable and disable

the VOUT pin under normal operating conditions. As shown

in Figure 65, when a rising voltage on EN crosses the upper

threshold, VOUT turns on. When a falling voltage on EN/

UVLO crosses the lower threshold, VOUT turns off. The

hysteresis of the EN/UVLO threshold is determined by

the Thevenin equivalent resistance in series with the EN/

UVLO pin.

SENSE

RPG

100kΩ

R1

100kΩ

EN/

UVLO

OFF

R2

100kΩ

PG

GND

Figure 66. Typical EN Pin Voltage Divider

Figure 65 shows the typical hysteresis of the EN/UVLO pin.

This prevents on/off oscillations that can occur due to noise

on the EN pin as it passes through the threshold points.

2.0

1.8

1.6

1.4

1.2

The ADP7102 uses an internal soft-start to limit the inrush

current when the output is enabled. The start-up time for the

3.3 V option is approximately 580 μs from the time the EN

active threshold is crossed to when the output reaches 90%

of its final value. As shown in Figure 67, the start-up time is

dependent on the output voltage setting.

V

, EN RISE

, EN FALL

OUT

1.0

0.8

0.6

0.4

0.2

0

OUT

6

5V

5

1.00

1.25

1.50

1.75

2.00

2.25

2.50

2.75

3.00

4

Figure 65. Typical V_OUTResponse to EN Pin Operation

3.3V

The upper and lower thresholds are user programmable and

can be set using two resistors. When the EN/UVLO pin voltage

is below 1.22 V, the LDO is disabled. When the EN/UVLO pin

voltage transitions above 1.22 V, the LDO is enabled and 10 µA

hysteresis current is sourced out of the pin raising the voltage,

thus providing threshold hysteresis. Typically, two external

resistors program the minimum operational voltage for the LDO.

The resistance values, R1 and R2 can be determined from:

3

ENABLE

2

1

0

500

1000

1500

2000

TIME (µs)

R1 = V_HYS/10 μA

R2 = 1.22 V × R1/(V_IN− 1.22 V)

where:

Figure 67. Typical Start-Up Behavior

V_INis the desired turn-on voltage.

V_HYSis the desired EN/UVLO hysteresis level.

Hysteresis can also be achieved by connecting a resistor in series

with EN/UVLO pin. For the example shown in Figure 66, the

enable threshold is 2.44 V with a hysteresis of 1 V.

Rev. A | Page 19 of 28

ADP7102

Data Sheet

POWER GOOD FEATURE

NOISE REDUCTION OF THE ADJUSTABLE

ADP7102

The ADP7102 provides a power good pin (PG) to indicate

the status of the output. This open-drain output requires an

external pull-up resistor to VIN. If the part is in shutdown

mode, current-limit mode, or thermal shutdown, or if it falls

below 90% of the nominal output voltage, the power-good pin

(PG) immediately transitions low. During soft-start, the rising

threshold of the power-good signal is 93.5% of the nominal

output voltage.

The ultralow output noise of the fixed output ADP7102 is

achieved by keeping the LDO error amplifier in unity gain

and setting the reference voltage equal to the output voltage.

This architecture does not work for an adjustable output

voltage LDO. The adjustable output ADP7102 uses the more

conventional architecture where the reference voltage is fixed

and the error amplifier gain is a function of the output voltage.

The disadvantage of the conventional LDO architecture is that

the output voltage noise is proportional to the output voltage.

The open-drain output is held low when the ADP7102 has

sufficient input voltage to turn on the internal PG transistor.

The PG transistor is terminated via a pull-up resistor to VOUT

or VIN.

The adjustable LDO circuit may be modified slightly to

reduce the output voltage noise to levels close to that of the

fixed output ADP7102. The circuit shown in Figure 70 adds

two additional components to the output voltage setting resistor

divider. C_NRand R_NRare added in parallel with R_FB1to reduce

the ac gain of the error amplifier. R_NRis chosen to be equal to

Power-good accuracy is 93.5% of the nominal regulator output

voltage when this voltage is rising, with a 90% trip point when

this voltage is falling. Regulator input voltage brownouts or

glitches trigger power no good signals if V_OUTfalls below 90%.

R_FB2; this limits the ac gain of the error amplifier to approxi-

A normal power-down causes the power good signal to go low

when V_OUTdrops below 90%.

mately 6 dB. The actual gain is the parallel combination of R_NR

and R_FB1, divided by R_FB2. This ensures that the error amplifier

always operates at greater than unity gain.

Figure 68 and Figure 69 show the typical power good rising and

falling threshold over temperature.

C

_NRis chosen by setting the reactance of C_NRequal to R_FB1

−

6

R_NRat a frequency between 50 Hz and 100 Hz. This sets the

PG –40°C

PG –5°C

PG +25°C

frequency where the ac gain of the error amplifier is 3 dB

down from its dc gain.

5

4

3

2

1

0

PG +85°C

PG +125°C

VOUT = 5V

COUT

1µF

VIN

VOUT

VIN = 8V

R

+

CIN

1µF

FB1

+

C

NR

40.2kΩ

100nF

ADJ

R

13kΩ

NR

ON

100kΩ

R

13kΩ

EN/

UVLO

100kΩ

OFF

FB2

PG

GND

Figure 70. Noise Reduction Modification to Adjustable LDO

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

5.0

The noise of the LDO is approximately the noise of the fixed

output LDO (typically 15 µV rms) times the square root of the

parallel combination of R_NRand R_FB1divided by R_FB2. Based on

the component values shown in Figure 70, the ADP7102 has the

following characteristics:

V

(V)

OUT

Figure 68. Typical Power Good Threshold vs. Temperature, V_OUTRising

6

PG –40°C

PG –5°C

PG +25°C

PG +85°C

5

4

3

2

1

0

PG +125°C

•

DC gain of 4.09 (12.2 dB)

3 dB roll off frequency of 59 Hz

High frequency ac gain of 1.82 (5.19 dB)

Noise reduction factor of 1.35 (2.59 dB)

RMS noise of the adjustable LDO without noise reduction

of 27.8 µV rms

•

RMS noise of the adjustable LDO with noise reduc-

tion (assuming 15 µV rms for fixed voltage option) of

20.25 µV rms

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

5.0

V

(V)

OUT

Figure 69. Typical Power Good Threshold vs. Temperature, V_OUTFalling

Rev. A | Page 20 of 28

Data Sheet

ADP7102

To guarantee reliable operation, the junction temperature

CURRENT LIMIT AND THERMAL OVERLOAD

PROTECTION

of the ADP7102 must not exceed 125°C. To ensure that the

junction temperature stays below this maximum value, the

user must be aware of the parameters that contribute to

junction temperature changes. These parameters include

ambient temperature, power dissipation in the power device,

and thermal resistances between the junction and ambient air

(θ_JA). The θ_JAnumber is dependent on the package assembly

compounds that are used and the amount of copper used to

solder the package GND pins to the PCB.

The ADP7102 is protected against damage due to excessive

power dissipation by current and thermal overload protection

circuits. The ADP7102 is designed to current limit when the

output load reaches 400 mA (typical). When the output load

exceeds 400 mA, the output voltage is reduced to maintain a

constant current limit.

Thermal overload protection is included, which limits the

junction temperature to a maximum of 150°C (typical). Under

extreme conditions (that is, high ambient temperature and/or

high power dissipation) when the junction temperature starts to

rise above 150°C, the output is turned off, reducing the output

current to zero. When the junction temperature drops below

135°C, the output is turned on again, and output current is

restored to its operating value.

Table 6 shows typical θ_JAvalues of the 8-lead SOIC and 8-lead

LFCSP packages for various PCB copper sizes. Table 7 shows

the typical Ψ_JBvalues of the 8-lead SOIC and 8-lead LFCSP.

Table 6. Typical θ_JAValues

θ

_JA(°C/W)

SOIC

167.8

111

Copper Size (mm²)

25¹

100

500

LFCSP

165.1

125.8

68.1

Consider the case where a hard short from VOUT to ground

occurs. At first, the ADP7102 current limits, so that only 400 mA is

conducted into the short. If self heating of the junction is great

enough to cause its temperature to rise above 150°C, thermal

shutdown activates, turning off the output and reducing the

output current to zero. As the junction temperature cools and

drops below 135°C, the output turns on and conducts 400 mA

into the short, again causing the junction temperature to rise

above 150°C. This thermal oscillation between 135°C and

150°C causes a current oscillation between 400 mA and 0 mA

that continues as long as the short remains at the output.

65.9

1000

6400

56.4

42.1

56.1

45.8

¹Device soldered to minimum size pin traces.

Table 7. Typical Ψ_JBValues

Model

LFCSP

SOIC

Ψ_JB(°C/W)

15.1

31.3

Current and thermal limit protections are intended to protect

the device against accidental overload conditions. For reliable

operation, device power dissipation must be externally limited

so the junction temperature does not exceed 125°C.

The junction temperature of the ADP7102 is calculated from

the following equation:

T_J= T_A+ (P_D× θ_JA)

(2)

(3)

where:

THERMAL CONSIDERATIONS

T_Ais the ambient temperature.

P_Dis the power dissipation in the die, given by

In applications with low input-to-output voltage differential,

the ADP7102 does not dissipate much heat. However, in

applications with high ambient temperature and/or high

input voltage, the heat dissipated in the package may become

large enough that it causes the junction temperature of the

die to exceed the maximum junction temperature of 125°C.

P_D= [(V_IN− V_OUT) × I_LOAD] + (V_IN× I_GND

where:

)

I

_LOADis the load current.

I_GNDis the ground current.

V_INand V_OUTare input and output voltages, respectively.

When the junction temperature exceeds 150°C, the converter

enters thermal shutdown. It recovers only after the junction

temperature has decreased below 135°C to prevent any permanent

damage. Therefore, thermal analysis for the chosen application

is very important to guarantee reliable performance over all

conditions. The junction temperature of the die is the sum of

the ambient temperature of the environment and the tempera-

ture rise of the package due to the power dissipation, as shown

in Equation 2.

Power dissipation due to ground current is quite small and

can be ignored. Therefore, the junction temperature equation

simplifies to the following:

T_J= T_A+ {[(V_IN− V_OUT) × I_LOAD] × θ_JA}

(4)

As shown in Equation 4, for a given ambient temperature,

input-to-output voltage differential, and continuous load

current, there exists a minimum copper size requirement for

the PCB to ensure that the junction temperature does not rise

above 125°C. Figure 71 to Figure 78 show junction temperature

calculations for different ambient temperatures, power dissipa-

tion, and areas of PCB copper.

Rev. A | Page 21 of 28

ADP7102

Data Sheet

145

135

125

115

105

95

145

135

125

115

105

95

85

75

65

55

2

45

6400mm

45

2

500mm

2

35

25mm

35

T

MAX

T

MAX

J

25

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4

TOTAL POWER DISSIPATION (W)

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4

TOTAL POWER DISSIPATION (W)

Figure 71. LFCSP, T_A= 25°C

Figure 74. SOIC, T_A= 25°C

140

130

120

110

100

90

140

130

120

100

110

90

80

70

2

6400mm

2

500mm

60

2

25mm

J

25mm

J

T

MAX

T

MAX

50

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

TOTAL POWER DISSIPATION (W)

Figure 75. SOIC, T_A= 50°C

Figure 72. LFCSP, T_A= 50°C

145

135

125

115

105

95

145

135

125

115

105

95

85

2

6400mm

2

75

500mm

75

2

25mm

J

25mm

J

T

MAX

T

MAX

65

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

TOTAL POWER DISSIPATION (W)

Figure 73. LFCSP, T_A= 85°C

Figure 76. SOIC, T_A= 85°C

Rev. A | Page 22 of 28

Data Sheet

ADP7102

140

120

100

80

In the case where the board temperature is known, use the

thermal characterization parameter, Ψ_JB, to estimate the

junction temperature rise (see Figure 77 and Figure 78).

Maximum junction temperature (T_J) is calculated from

the board temperature (T_B) and power dissipation (P_D)

using the following formula:

60

T_J= T_B+ (P_D× Ψ_JB)

(5)

The typical value of Ψ_JBis 15.1°C/W for the 8-lead LFCSP

40

package and 31.3°C/W for the 8-lead SOIC package.

TB = 25°C

TB = 50°C

TB = 65°C

TB = 85°C

20

140

T

MAX

J

0

120

100

80

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

TOTAL POWER DISSIPATION (W)

Figure 78. SOIC

60

40

TB = 25°C

TB = 50°C

20

TB = 65°C

TB = 85°C

T

MAX

J

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

TOTAL POWER DISSIPATION (W)

Figure 77. LFCSP

Rev. A | Page 23 of 28

ADP7102

Data Sheet

PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS

Heat dissipation from the package can be improved by

increasing the amount of copper attached to the pins of the

ADP7102. However, as listed in Table 6, a point of diminishing

returns is eventually reached, beyond which an increase in the

copper size does not yield significant heat dissipation benefits.

Place the input capacitor as close as possible to the VIN and

GND pins. Place the output capacitor as close as possible to the

VOUT and GND pins. Use of 0805 or 0603 size capacitors and

resistors achieves the smallest possible footprint solution on

boards where area is limited.

Figure 80. Example SOIC PCB Layout

Figure 79. Example LFCSP PCB Layout

Rev. A | Page 24 of 28

Data Sheet

ADP7102

OUTLINE DIMENSIONS

2.48

2.38

2.23

3.00

BSC SQ

5

8

EXPOSED

PAD

1.74

1.64

1.49

0.50

0.40

0.30

4

1

INDEX

AREA

PIN 1

INDICATOR

(R 0.2)

TOP VIEW

BOTTOM VIEW

0.80 MAX

0.55 NOM

0.80

0.75

0.70

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.30

0.25

0.18

0.20 REF

0.50 BSC

COMPLIANT TO JEDEC STANDARDS MO-229-WEED-4

Figure 81. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]

3 mm × 3 mm Body, Very Very Thin, Dual Lead

(CP-8-5)

Dimensions shown in millimeters

5.00

4.90

4.80

3.098

0.356

5

6.20

6.00

5.80

8

4.00

3.90

3.80

2.41

0.457

4

1

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

BOTTOM VIEW

45°

1.27 BSC

3.81 REF

TOP VIEW

SECTION OF THIS DATA SHEET.

1.65

1.25

1.75

1.35

0.50

0.25

0.17

0.10 MAX

0.05 NOM

SEATING

PLANE

8°

0°

0.51

0.31

1.04 REF

COPLANARITY

0.10

1.27

0.40

COMPLIANT TO JEDEC STANDARDS MS-012-AA

Figure 82. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]

Narrow Body

(RD-8-2)

Dimensions shown in millimeters

Rev. A | Page 25 of 28

ADP7102

Data Sheet

ORDERING GUIDE

Temperature

Range

Output

Package

Description

Package

Option

Model¹

Voltage (V)^{2, 3}

Branding

LHO

LJV

LJW

LJZ

LKO

LK1

LK2

ADP7102ACPZ-R7

−40°C to +125°C

Adjustable

1.5

1.8

2.5

3.0

3.3

5

9

LFCSP_WD

SOIC_N_EP

CP-8-5

RD-8-2

ADP7102ACPZ-1.5-R7

ADP7102ACPZ-1.8-R7

ADP7102ACPZ-2.5-R7

ADP7102ACPZ-3.0-R7

ADP7102ACPZ-3.3-R7

ADP7102ACPZ-5.0-R7

ADP7102ACPZ-9.0-R7

ADP7102ARDZ-R7

ADP7102ARDZ-1.5-R7

ADP7102ARDZ-1.8-R7

ADP7102ARDZ-2.5-R7

ADP7102ARDZ-3.0-R7

ADP7102ARDZ-3.3-R7

ADP7102ARDZ-5.0-R7

ADP7102ARDZ-9.0-R7

ADP7102CP-EVALZ

ADP7102RD-EVALZ

ADP7102CPZ-REDYKIT

ADP7102RDZ-REDYKIT

LLC

Adjustable

1.5

1.8

2.5

3.0

3.3

5

9

3.3

LFCSP Evaluation Board

SOIC Evaluation Board

LFCSP REDYKIT

SOIC REDYKIT

¹Z = RoHS Compliant Part.

²For additional voltage options, contact a local Analog Devices, Inc., sales or distribution representative.

³The ADP7102CP-EVALZ and ADP7102RD-EVALZ evaluation boards are preconfigured with a 3.3 V ADP7102.

Rev. A | Page 26 of 28

Data Sheet

NOTES

ADP7102

Rev. A | Page 27 of 28

ADP7102

NOTES

Data Sheet

registered trademarks are the property of their respective owners.

D09506-0-11/11(A)

Rev. A | Page 28 of 28


型号：	ADP7102ACPZ-3.0-R7
厂家：	ADI
描述：	20 V, 300 mA, Low Noise, CMOS LDO 20 V 300毫安，低噪声， CMOS LDO
文件：	总28页 (文件大小：744K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADP7102ACPZ-3.0-R7 [ADI]

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