ADSP-BF544_技术文档

•

Blackfin^®

Embedded Processor

Preliminary Technical Data

ADSP-BF542/BF544/BF547/BF548/BF549

FEATURES

PERIPHERALS

Up to 600 MHz High-Performance Blackfin Processor

High-Speed USB On-the-Go (OTG) with Integrated PHY

Two 16-Bit MACs, Two 40-Bit ALUs, Four 8-Bit Video ALUs

RISC-Like Register and Instruction Model

SD/SDIO Controller

ATA/ATAPI-6 Controller

0.9 V to 1.3 V Core VDD with On-chip Voltage Regulation

2.5 V and 3.3 V-Tolerant I/O with Specific 5V-Tolerant Pins

400-ball Lead-Free mBGA and 360-ball Lead-Free pBGA pack-

age options.

Up to four Synchronous Serial Ports (SPORTs)

Up to three Serial Peripheral Interfaces (SPI-Compatible)

Up to four UARTs, two with Automatic Hardware Flow

Control

Up to two CAN (Controller Area Network) 2.0B Interfaces

Up to two TWI (Two-Wire Interface) Controllers

8- or 16-Bit Asynchronous Host DMA Interface

Multiple Enhanced Parallel Peripheral Interfaces (EPPIs), Sup-

porting ITU-R BT.656 Video Formats and 18/24-bit LCD

Connections

MEMORY

Up to 324K bytes of on-chip memory comprised of:

Instruction SRAM/cache; instruction SRAM;

data SRAM/cache; additional dedicated data SRAM;

scratchpad SRAM (see Table 1 on Page 3 for available

memory configurations

External Sync Memory Controller Supporting

DDR/Mobile DDR SDRAM

External Async Memory Controller Supporting 8/16 bit Async

Memories and Burst Flash Devices

Media Transceiver (MXVR) for connection to a MOST^®

Network

Pixel Compositor for overlays, alpha blending, and color

conversion

Up to eleven 32-Bit Timers/Counters with PWM Support

Real-Time Clock (RTC) and Watchdog Timer

Up/Down Counter With Support for Rotary Encoder

Up to 152 General Purpose I/O (GPIOs)

On-Chip PLL Capable of 0.5x to 64x Frequency Multiplication

Debug/JTAG Interface

NAND Flash Controller

Four Memory-to-Memory DMA pairs, two with ext. requests

Memory Management Unit Providing Memory Protection

Flexible Booting Options

Code Security with Lockbox^TMSecure Technology

One-Time-Programmable (OTP) Memory

VOLTAGE

REGULATOR

JTAG TEST AND

EMULATION

WATCHDOG

TIMER

CAN (0-1)

RTC

OTP

TWI (0-1)

HOST DMA

UART (0-1)

UART (2-3)

SPI (0-1)

PAB 16

TIMERS(0-10)

INTERRUPTS

B

COUNTER

KEYPAD

L2

SRAM

L1

INSTR ROM

L1

INSTR SRAM

DATA SRAM

SPI (2)

32-BIT DMA

16-BIT DMA

MXVR

DAB1 32

DAB0 16

DCB 32

EAB 64

DEB 32

SPORT (2-3)

SPORT (0-1)

SD / SDIO

USB

BOOT

ROM

EXTERNAL PORT

NOR, DDR1 CONTROL

ATAPI

EPPI (0-2)

DDR1

16

ASYNC

16

NAND FLASH

CONTRLOLLER

PIXEL

COMPOSITOR

•

Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.

Figure 1. ADSP-BF549 Functional Block Diagram

Rev. PrG

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel:781/329-4700

Fax:781/461-3113

www.analog.com

ADSP-BF542/4/7/8/9

Preliminary Technical Data

TABLE OF CONTENTS

General Description ................................................. 3

Low-Power Architecture ......................................... 4

System Integration ................................................ 4

ADSP-BF542/4/7/8/9 Processor Peripherals ................ 4

Blackfin Processor Core .......................................... 4

Memory Architecture ............................................ 5

DMA Controllers ................................................ 10

Real-Time Clock ................................................. 11

Watchdog Timer ................................................ 12

Timers ............................................................. 12

Up/Down Counter and Thumbwheel Interface .......... 12

Serial Ports (SPORTs) .......................................... 12

Serial Peripheral Interface (SPI) Ports ...................... 13

UART Ports (UARTs) .......................................... 13

Controller Area Network (CAN) ............................ 13

TWI Controller Interface ...................................... 14

Ports ................................................................ 14

Pixel Compositor (PIXC) ...................................... 14

Enhanced Parallel Peripheral Interface (EPPI) ........... 14

USB On-The-Go Dual-Role Device Controller ........... 15

ATA/ATAPI–6 Interface ...................................... 15

Keypad Interface ................................................. 15

Secure Digital (SD)/SDIO Controller ....................... 15

Code Security .................................................... 15

Media Transceiver Mac Layer (MXVR) .................... 16

Dynamic Power Management ................................ 16

Voltage Regulation .............................................. 17

Clock Signals ...................................................... 17

Booting Modes ................................................... 19

Instruction Set Description .................................... 22

Development Tools .............................................. 22

Designing an Emulator-Compatible Processor Board

(Target) ......................................................... 22

Related Documents .............................................. 22

Pin Descriptions .................................................... 23

Specifications ........................................................ 32

Operating Conditions ........................................... 32

Electrical Characteristics ....................................... 34

ESD Sensitivity ................................................... 34

Absolute Maximum Ratings ................................... 35

Package Information ............................................ 35

Timing Specifications ........................................... 36

Power Dissipation ............................................... 64

Test Conditions .................................................. 64

Environmental Conditions .................................... 65

400-Ball CSP_BGA PACKAGE .................................. 67

360-Ball pBGA PACKAGE ....................................... 73

Outline Dimensions ................................................ 79

Surface Mount Design .......................................... 81

Ordering Guide ..................................................... 82

REVISION HISTORY

Revision PrG: Corrections and additions to PrF:

• Addition of DDR and Mobile DDR Timing parameters.

Rev. PrG

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Preliminary Technical Data

GENERAL DESCRIPTION

The ADSP-BF542/4/7/8/9 processors are members of the Black-

fin family of products, incorporating the Analog Devices/Intel

Micro Signal Architecture (MSA). Blackfin processors combine

a dual-MAC state-of-the-art signal processing engine, the

advantages of a clean, orthogonal RISC-like microprocessor

instruction set, and single-instruction, multiple-data (SIMD)

multimedia capabilities into a single instruction-set

architecture.

ADSP-BF542/4/7/8/9

Specific peripherals for ADSP-BF542/4/7/8/9 processors are

shown in Table 2.

Table 2. ADSP-BF54x Specific Peripherals for Processors

Module

Specific performance and memory configurations for

ADSP-BF542/4/7/8/9 processors are shown in Table 1.

EBIU (async)

NAND Flash Controller

ATAPI

3

–

3

–

3

–

3

–

Table 1. ADSP-BF542/4/7/8/9 Processor Features

Processor

Features

Host DMA Port (HOSTDP)

SD/SDIO Controller

EPPI0

3

–

3

–

3

–

Lockbox^TMCode Security

SD/SDIO Controller

Pixel Compositor

18- or 24-bit EPPI0 with LCD

16-bit EPPI1, 8-bit EPPI2

Host DMA Port

NAND Flash Controller

ATAPI

1

2

3

4

1

–

2

3

4

1

–

2

3

4

1

–

1

–

2

3

1

–

1

–

1

–

1

2

3

1

8

EPPI1

3

–

EPPI2

SPORT0

SPORT1

3

–

3

–

SPORT2

SPORT3

SPI0

SPI1

SPI2

High Speed USB OTG

Keypad Interface

MXVR

UART0

3

–

3

–

UART1

CAN ports¹

UART2

UART3

3

–

3

–

TWI ports

High Speed USB OTG

CAN0¹

CAN1¹

SPI ports

3

–

UART ports

–

SPORTs

TWI0

3

–

3

–

Up / Down Counter

Timers

TWI1

11 11 11 11

152 152 152 152 152

Timer 0-7

Timer 8-10

Up / Down Counter

Keypad Interface

MXVR

3

–

General-purpose I/O pins

Memory

Configura-

tions

L1 Instruction SRAM/Cache 16 16 16 16 16

3

–

L1 Instruction SRAM

L1 Data SRAM/Cache

L1 Data SRAM

L1 Scratchpad SRAM

L1 ROM²

48 48 48 48 48

32 32 32 32 32

(K Bytes)

–

GPIOs

3

4

¹CAN on the ADSP-BF544 and ADSP-BF542 is only available on automotive

grade devices.

64 64 64 64 64

L2

128 128 128 64

–

4

L3 Boot ROM²

4

Maximum Core Instruction Rate (MHz) 533 600 600 533 600

¹Automotive Only.

²This ROM is not customer configurable.

Rev. PrG

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December 2007

ADSP-BF542/4/7/8/9

Preliminary Technical Data

The ADSP-BF542/4/7/8/9 processors are completely code and

pin compatible. They differ only with respect to their perfor-

mance, on-chip memory, and selection of I/O peripherals.

Specific performance, memory, and feature configurations, are

shown in Table 1.

memory spaces, including external DDR and asynchronous

memory. Multiple on-chip buses running at up to 133 MHz

provide enough bandwidth to keep the processor core running

along with activity on all of the on-chip and external

peripherals.

By integrating a rich set of industry-leading system peripherals

and memory, Blackfin processors are the platform of choice for

next-generation applications that require RISC-like program-

mability, multimedia support and leading-edge signal

processing in one integrated package.

The ADSP-BF542/4/7/8/9 processor includes an on-chip volt-

age regulator in support of the ADSP-BF542/4/7/8/9 processor

dynamic power management capability. The voltage regulator

provides a range of core voltage levels when supplied from a sin-

gle 2.70 V to 3.6 V input. The voltage regulator can be bypassed

at the user's discretion.

LOW-POWER ARCHITECTURE

BLACKFIN PROCESSOR CORE

Blackfin processors provide world-class power management

and performance. Blackfin processors are designed in a low

power and low voltage design methodology and feature on-chip

dynamic power management, the ability to vary both the voltage

and frequency of operation to significantly lower overall power

consumption. Varying the voltage and frequency can result in a

substantial reduction in power consumption, compared with

just varying the frequency of operation. This translates into

longer battery life for portable appliances.

As shown in Figure 2 on Page 5, the Blackfin processor core

contains two 16-bit multipliers, two 40-bit accumulators, two

40-bit ALUs, four video ALUs, and a 40-bit shifter. The compu-

tation units process 8-bit, 16-bit, or 32-bit data from the register

file.

The compute register file contains eight 32-bit registers. When

performing compute operations on 16-bit operand data, the

register file operates as 16 independent 16-bit registers. All

operands for compute operations come from the multiported

register file and instruction constant fields.

SYSTEM INTEGRATION

The ADSP-BF542/4/7/8/9 processors are highly integrated sys-

tem-on-a-chip solutions for the next generation of embedded

network connected applications. By combining industry-stan-

dard interfaces with a high performance signal processing core,

users can develop cost-effective solutions quickly without the

need for costly external components. The system peripherals

include a high speed USB OTG (On-The-Go) controller with

integrated PHY, CAN 2.0B controllers, TWI controllers, UART

ports, SPI ports, serial ports (SPORTs), ATAPI controller,

SD/SDIO controller, a real-time clock, a watchdog timer, LCD

controller, and multiple enhanced parallel peripheral interfaces.

Each MAC can perform a 16-bit by 16-bit multiply in each

cycle, accumulating the results into the 40-bit accumulators.

Signed and unsigned formats, rounding, and saturation are

supported.

The ALUs perform a traditional set of arithmetic and logical

operations on 16-bit or 32-bit data. In addition, many special

instructions are included to accelerate various signal processing

tasks. These include bit operations such as field extract and pop-

ulation count, modulo 2³²multiply, divide primitives, saturation

and rounding, and sign/exponent detection. The set of video

instructions include byte alignment and packing operations, 16-

bit and 8-bit adds with clipping, 8-bit average operations, and 8-

bit subtract/absolute value/accumulate (SAA) operations. Also

provided are the compare/select and vector search instructions.

ADSP-BF542/4/7/8/9 PROCESSOR PERIPHERALS

The ADSP-BF542/4/7/8/9 processor contains a rich set of

peripherals connected to the core via several high bandwidth

buses, providing flexibility in system configuration as well as

excellent overall system performance (see Figure 1 on Page 1).

The general-purpose peripherals include functions such as

UARTs, SPI, TWI, timers with pulse width modulation (PWM)

and pulse measurement capability, general purpose I/O pins, a

real-time clock, and a watchdog timer. This set of functions sat-

isfies a wide variety of typical system support needs and is

augmented by the system expansion capabilities of the part. The

ADSP-BF542/4/7/8/9 processor contains dedicated network

communication modules and high-speed serial and parallel

ports, an interrupt controller for flexible management of inter-

rupts from the on-chip peripherals or external sources, and

power management control functions to tailor the performance

and power characteristics of the processor and system to many

application scenarios.

For certain instructions, two 16-bit ALU operations can be per-

formed simultaneously on register pairs (a 16-bit high half and

16-bit low half of a compute register). By also using the second

ALU, quad 16-bit operations are possible.

The 40-bit shifter can perform shifts and rotates and is used to

support normalization, field extract, and field deposit

instructions.

The program sequencer controls the flow of instruction execu-

tion, including instruction alignment and decoding. For

program flow control, the sequencer supports PC relative and

indirect conditional jumps (with static branch prediction), and

subroutine calls. Hardware is provided to support zero-over-

head looping. The architecture is fully interlocked, meaning that

the programmer need not manage the pipeline when executing

instructions with data dependencies.

All of the peripherals, except for general-purpose I/O, CAN,

TWI, real-time clock, and timers, are supported by a flexible

DMA structure. There are also separate memory DMA channels

dedicated to data transfers between the processor's various

The address arithmetic unit provides two addresses for simulta-

neous dual fetches from memory. It contains a multiported

register file consisting of four sets of 32-bit index, modify,

Rev. PrG

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December 2007

Preliminary Technical Data

ADSP-BF542/4/7/8/9

length, and base registers (for circular buffering), and eight

additional 32-bit pointer registers (for C-style indexed stack

manipulation).

The architecture provides three modes of operation: user mode,

supervisor mode, and emulation mode. User mode has

restricted access to certain system resources, thus providing a

protected software environment, while supervisor mode has

unrestricted access to the system and core resources.

Blackfin processors support a modified Harvard architecture in

combination with a hierarchical memory structure. Level 1 (L1)

memories are those that typically operate at the full processor

speed with little or no latency. At the L1 level, the instruction

memory holds instructions only. The two data memories hold

data, and a dedicated scratchpad data memory stores stack and

local variable information.

The Blackfin processor instruction set has been optimized so

that 16-bit opcodes represent the most frequently used instruc-

tions, resulting in excellent compiled code density. Complex

DSP instructions are encoded into 32-bit opcodes, representing

fully featured multifunction instructions. Blackfin processors

support a limited multi-issue capability, where a 32-bit instruc-

tion can be issued in parallel with two 16-bit instructions,

allowing the programmer to use many of the core resources in a

single instruction cycle.

In addition, multiple L1 memory blocks are provided, offering a

configurable mix of SRAM and cache. The memory manage-

ment unit (MMU) provides memory protection for individual

tasks that may be operating on the core and can protect system

registers from unintended access.

The Blackfin processor assembly language uses an algebraic syn-

tax for ease of coding and readability. The architecture has been

optimized for use in conjunction with the C/C++ compiler,

resulting in fast and efficient software implementations.

ADDRESS ARITHMETIC UNIT

SP

FP

P5

P4

P3

P2

P1

P0

I3

I2

I1

I0

L3

L2

L1

L0

B3

B2

B1

B0

M3

M2

M1

M0

DAG1

DAG0

DA1 32

DA0 32

32

PREG

32

RAB

SD 32

LD1 32

LD0 32

ASTAT

32

SEQUENCER

ALIGN

R7.H

R6.H

R5.H

R4.H

R3.H

R2.H

R1.H

R0.H

R7.L

R6.L

R5.L

R4.L

R3.L

R2.L

R1.L

R0.L

16

8

DECODE

BARREL

SHIFTER

LOOP BUFFER

40

40 40

A0

A1

CONTROL

UNIT

32

DATA ARITHMETIC UNIT

Figure 2. Blackfin Processor Core

resources, including internal memory, external memory, and

I/O control registers, occupy separate sections of this common

address space. The memory portions of this address space are

MEMORY ARCHITECTURE

The ADSP-BF542/4/7/8/9 processor views memory as a single

unified 4G byte address space, using 32-bit addresses. All

Rev. PrG

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December 2007

ADSP-BF542/4/7/8/9

Preliminary Technical Data

arranged in a hierarchical structure to provide a good cost/per-

formance balance of some very fast, low-latency on-chip

memory as cache or SRAM, and larger, lower-cost and perfor-

mance off-chip memory systems. See Figure 3 on Page 6.

0xFFFF FFFF

The on-chip L1 memory system is the highest-performance

memory available to the Blackfin processor. The off-chip mem-

ory system, accessed through the external bus interface unit

(EBIU), provides expansion with flash memory, SRAM, and

double-rate SDRAM (DDR1), optionally accessing up to

516M bytes of physical memory.

CORE MMR REGISTERS (2M BYTE)

0xFFE0 0000

0xFFC0 0000

SYSTEM MMR REGISTERS (2M BYTE)

RESERVED

0xFFB0 1000

0xFFB0 0000

SCRATCHPAD SRAM (4K BYTE)

RESERVED

0xFFA2 4000

0xFFA1 4000

Most of the ADSP-BF542/4/7/8/9 processors also include an L2

SRAM memory array which provides up to 128K bytes of high

speed SRAM operating at one half the frequency of the core, and

slightly longer latency than the L1 memory banks (For informa-

tion on L2 memory in each processor, see Table 1.) The L2

memory is a unified instruction and data memory and can hold

any mixture of code and data required by the system design.

The Blackfin cores share a dedicated low latency 64-bit wide

data path port into the L2 SRAM memory.

L1 ROM (64K BYTE)

INSTRUCTION SRAM / CACHE (16K BYTE)

RESERVED

0xFFA1 0000

0xFFA0 C000

INSTRUCTION BANK B SRAM (16K BYTE)

0xFFA0 8000

INSTRUCTION BANK A SRAM (32K BYTE)

RESERVED

0xFFA0 0000

0xFF90 8000

DATA BANK B SRAM / CACHE (16K BYTE)

DATA BANK B SRAM (16K BYTE)

0xFF90 4000

The memory DMA controllers (DMAC1 and DMAC0) pro-

vides high-bandwidth data-movement capability. They can

perform block transfers of code or data between the internal

memory and the external memory spaces.

0xFF90 0000

0xFF80 8000

0xFF80 4000

RESERVED

DATA BANK A SRAM / CACHE (16K BYTE)

DATA BANK A SRAM (16K BYTE)

RESERVED

0xFF80 0000

0xFEB2 0000

L2 SRAM (128K BYTE)

0xFEB0 0000

0xEF00 1000

0xEF00 0000

RESERVED

BOOT ROM (4K BYTE)

RESERVED

0x3000 0000

0x2C00 0000

ASYNC MEMORY BANK 3 (64M BYTE)

ASYNC MEMORY BANK 2 (64M BYTE)

0x2800 0000

0x2400 0000

ASYNC MEMORY BANK 1 (64M BYTE)

ASYNC MEMORY BANK 0 (64M BYTE)

0x2000 0000

RESERVED

TOP OF LAST

DDR PAGE

DDR1 MEM BANK 1 (8M BYTE 256M BYTE)

DDR1 MEM BANK 0 (8M BYTE 256M BYTE)

0x0000 0000

Figure 3. ADSP-BF547BF548/BF549 Internal/External Memory Map¹

1

This memory map applies to all ADSP-BF542/4/7/8/9 processors, except for L2

memory population. ADSP-BF544 includes 64K Byte of L2 memory: 0xFEB0

0000 - 0xFEB0 FFFF. ADSP-BF542 includes no L2 memory. See also Table 1.

Internal (On-Chip) Memory

The ADSP-BF542/4/7/8/9 processor has several blocks of on-

chip memory providing high-bandwidth access to the core.

The first block is the L1 instruction memory, consisting of

48K bytes SRAM, and also 16K bytes that can be configured as a

four-way set-associative cache or SRAM. This memory is

accessed at full processor speed.

The second on-chip memory block is the L1 data memory, con-

sisting of 64K bytes SRAM, of which 32K bytes can be

configured as a two-way set associative cache. This memory

block is accessed at full processor speed.

Rev. PrG

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December 2007

Preliminary Technical Data

ADSP-BF542/4/7/8/9

The third memory block is a 4K byte scratchpad SRAM which

runs at the same speed as the L1 memories, but is only accessible

as data SRAM and cannot be configured as cache memory.

Another common use of NAND flash is for storage of multime-

dia files or other large data segments. In this case, a software file

system may be used to manage reading and writing of the

NAND flash device. The file system selects memory segments

for storage with the goal of avoiding bad blocks and equally dis-

tributing memory accesses across all address locations.

Hardware features of the NFC include:

The fourth memory block is the factory programmed L1

instruction ROM, operating at full processor speed. This ROM

is not customer configurable.

The fifth memory block is the L2 SRAM, providing 128K bytes

of unified instruction and data memory, operating at one half

the frequency of the core.

• Support for page program, page read, and block erase of

NAND flash devices, with accesses aligned to page

boundaries.

Finally, there is a 4K boot ROM connected as L3 memory. It

operates at full SCLK rate.

• Error checking and correction (ECC) hardware that facili-

tates error detection and correction.

External (Off-Chip) Memory

• A single 8-bit or 16-bit external bus interface for com-

mands, addresses and data.

Through the External Bus Interface Unit (EBIU) the

ADSP-BF542/4/7/8/9 processors provide glueless connectivity

to external 16-bit wide memories, such as DDR SDRAM,

Mobile DDR, SRAM, NOR flash, NAND flash, and FIFO

devices. To provide the best performance, the bus system of the

DDR interface is completely separate from the other parallel

interfaces.

• Support for SLC (single level cell) NAND flash devices

unlimited in size, with page sizes of 256 and 512 bytes.

Larger page sizes can be supported in software.

• Capability of releasing external bus interface pins during

long accesses.

• Support for internal bus requests of 16 or 32 bits.

The DDR/Mobile DDR memory controller can gluelessly man-

age up to two banks of double-rate synchronous dynamic

memory (DDR1 SDRAM). The 16-bit wide interface operates at

SCLK frequency, enabling maximum throughput of 532

Mbyte/s. The DDR controller is augmented with a queuing

mechanism that performs efficient bursts into the DDR. The

controller is an industry standard DDR1 SDRAM controller

with each bank supporting from 64 Mbit to 512 Mbit device

sizes and 4-, 8-, or 16-bit widths. The controller supports up to

256 Mbytes per external bank. With 2 external banks, the con-

troller supports up to 512 Mbytes total. Each bank is

independently programmable and is contiguous with adjacent

banks regardless of the sizes of the different banks or their

placement.

• DMA engine to transfer data between internal memory and

NAND flash device.

One-time-Programmable Memory

The ADSP-BF542/4/7/8/9 has 64K bits of one-time program-

mable (OTP) non-volatile memory that can be programmed by

the developer only one time. It includes the array and logic to

support read access and programming. Additionally, its pages

can be write protected.

OTP enables developers to store both public and private data

on-chip. In addition to storing public and private key data for

applications requiring security, it also allows developers to store

completely user-definable data such as customer ID, product

ID, MAC address, etc. Hence generic parts can be shipped

which are then programmed and protected by the developer

within this non-volatile memory.

Traditional 16-bit asynchronous memories, such as SRAM,

EPROM, and flash devices, can be connected to one of the four

64 MByte asynchronous memory banks, represented by four

memory select strobes. Alternatively, these strobes can function

as bank-specific read or write strobes preventing further glue

logic when connecting to asynchronous FIFO devices.

I/O Memory Space

The ADSP-BF542/4/7/8/9 processors do not define a separate

I/O space. All resources are mapped through the flat 32-bit

address space. On-chip I/O devices have their control registers

mapped into memory-mapped registers (MMRs) at addresses

near the top of the 4G byte address space. These are separated

into two smaller blocks, one which contains the control MMRs

for all core functions, and the other which contains the registers

needed for setup and control of the on-chip peripherals outside

of the core. The MMRs are accessible only in supervisor mode

and appear as reserved space to on-chip peripherals.

In addition, the external bus can connect to advanced flash

device technologies, such as:

• Page-mode NOR flash devices

• Synchronous burst-mode NOR flash devices

• NAND flash devices

NAND Flash Controller (NFC)

The ADSP-BF542/4/7/8/9 provides a NAND Flash Controller

(NFC) as part of the external bus interface. NAND flash devices

provide high-density, low-cost memory. However, NAND flash

devices also have long random access times, invalid blocks, and

lower reliability over device lifetimes. Because of this, NAND

flash is often used for read-only code storage. In this case, all

DSP code can be stored in NAND flash and then transferred to a

faster memory (such as DDR or SRAM) before execution.

Booting

The ADSP-BF542/4/7/8/9 processor contains a small on-chip

boot kernel, which configures the appropriate peripheral for

booting. If the ADSP-BF542/4/7/8/9 processor is configured to

Rev. PrG

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December 2007

ADSP-BF542/4/7/8/9

Preliminary Technical Data

boot from boot ROM memory space, the processor starts exe-

cuting from the on-chip boot ROM. For more information, see

Booting Modes on Page 19.

Table 3. Core Event Controller (CEC)

Priority

Event Class

EVT Entry

(0 is Highest)

Event Handling

0

Emulation/Test Control EMU

Reset RST

Non-Maskable Interrupt NMI

The event controller on the ADSP-BF542/4/7/8/9 processor

handles all asynchronous and synchronous events to the proces-

sor. The ADSP-BF542/4/7/8/9 processor provides event

handling that supports both nesting and prioritization. Nesting

allows multiple event service routines to be active simulta-

neously. Prioritization ensures that servicing of a higher-

priority event takes precedence over servicing of a lower-prior-

ity event. The controller provides support for five different types

of events:

1

2

3

Exception

EVX

4

Reserved

—

5

Hardware Error

IVHW

IVTMR

IVG7

6

Core Timer

7

General Interrupt 7

General Interrupt 8

General Interrupt 9

General Interrupt 10

General Interrupt 11

General Interrupt 12

General Interrupt 13

General Interrupt 14

General Interrupt 15

8

IVG8

• Emulation. An emulation event causes the processor to

enter emulation mode, allowing command and control of

the processor via the JTAG interface.

9

IVG9

10

11

12

13

14

15

IVG10

IVG11

IVG12

IVG13

IVG14

IVG15

• Reset. This event resets the processor.

• Non-Maskable Interrupt (NMI). The NMI event can be

generated by the software watchdog timer or by the NMI

input signal to the processor. The NMI event is frequently

used as a power-down indicator to initiate an orderly shut-

down of the system.

Although the ADSP-BF542/4/7/8/9 processor provides a default

mapping, the user can alter the mappings and priorities of

interrupt events by writing the appropriate values into the inter-

rupt assignment registers (IAR). Table 4 describes the inputs

into the SIC and the default mappings into the CEC.

• Exceptions. Events that occur synchronously to program

flow (that is, the exception is taken before the instruction is

allowed to complete). Conditions such as data alignment

violations and undefined instructions cause exceptions.

• Interrupts. Events that occur asynchronously to program

flow. They are caused by input pins, timers, and other

peripherals, as well as by an explicit software instruction.

Table 4. System Interrupt Controller (SIC)

Peripheral IRQ

(IRQ) Source

IRQ

GP IRQ

Core

Each event type has an associated register to hold the return

address and an associated return-from-event instruction. When

an event is triggered, the state of the processor is saved on the

supervisor stack.

ID (at Reset) IRQ ID

PLL Wakeup IRQ

0

1

IVG7

IVG8

IVG9

IVG10

IVG11

0

1

2

3

4

DMAC0 Status (generic)

EPPI0 Error IRQ

The ADSP-BF542/4/7/8/9 processor event controller consists of

two stages, the core event controller (CEC) and the system

interrupt controller (SIC). The core event controller works with

the system interrupt controller to prioritize and control all sys-

tem events. Conceptually, interrupts from the peripherals enter

into the SIC, and are then routed directly into the general-pur-

pose interrupts of the CEC.

2

SPORT0 Error IRQ

SPORT1 Error IRQ

SPI0 Status IRQ

3

4

5

UART0 Status IRQ

Real-Time Clock IRQ

DMA12 IRQ (EPPI0)

DMA0 IRQ (SPORT0 RX)

DMA1 IRQ (SPORT0 TX)

DMA2 IRQ (SPORT1 RX)

DMA3 IRQ (SPORT1 TX)

DMA4 IRQ (SPI0)

6

7

Core Event Controller (CEC)

8

The CEC supports nine general-purpose interrupts (IVG15–7),

in addition to the dedicated interrupt and exception events. Of

these general-purpose interrupts, the two lowest-priority inter-

rupts (IVG15–14) are recommended to be reserved for software

interrupt handlers, leaving seven prioritized interrupt inputs to

support the peripherals of the ADSP-BF542/4/7/8/9 processor.

Table 3 describes the inputs to the CEC, identifies their names

in the event vector table (EVT), and lists their priorities.

9

10

11

12

13

14

15

16

17

DMA6 IRQ (UART0 RX)

DMA7 IRQ (UART0 TX)

Timer 8 IRQ

System Interrupt Controller (SIC)

The system interrupt controller provides the mapping and rout-

ing of events from the many peripheral interrupt sources to the

prioritized general-purpose interrupt inputs of the CEC.

Timer 9 IRQ

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Preliminary Technical Data

ADSP-BF542/4/7/8/9

Table 4. System Interrupt Controller (SIC) (Continued)

Peripheral IRQ

(IRQ) Source

IRQ

GP IRQ

Core

Peripheral IRQ

(IRQ) Source

IRQ

GP IRQ

Core

ID (at Reset) IRQ ID

Timer 10 IRQ

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

IVG11

IVG12

IVG13

IVG7

4

5

6

0

2

3

4

6

4

0

Host DMA Status

Reserved

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

IVG7

0

1

4

Pin IRQ 0 (PINT0)

Pin IRQ 1 (PINT1)

Pixel Compositor (PIXC) Status IRQ

NFC Status IRQ

ATAPI Status IRQ

CAN1 Status IRQ

DMAR0 Block IRQ

DMAR1 Block IRQ

DMAR0 Overflow Error IRQ

DMAR1 Overflow Error IRQ

DMA15 IRQ (PIXC IN0)

DMA16 IRQ (PIXC IN1)

DMA17 IRQ (PIXC OUT)

DMA22 IRQ (SDH/NFC)

Counter (CNT) IRQ

Keypad (KEY) IRQ

CAN1 RX IRQ

IVG7

MDMA Stream 0 IRQ

MDMA Stream 1 IRQ

Software Watchdog Timer IRQ

DMAC1 Status (generic)

SPORT2 Error IRQ

IVG7

SPORT3 Error IRQ

IVG7

MXVR Synchronous Data IRQ

SPI1 Status IRQ

IVG7

IVG8

SPI2 Status IRQ

IVG7

IVG8

UART1 Status IRQ

IVG7

IVG8

UART2 Status IRQ

IVG7

IVG8

CAN0 Status IRQ

IVG7

IVG8

DMA18 IRQ (SPORT2 RX)

DMA19 IRQ (SPORT2 TX)

DMA20 IRQ (SPORT3 RX)

DMA21 IRQ (SPORT3 TX)

DMA13 IRQ (EPPI1)

DMA14 IRQ (EPPI2, Host DMA)

DMA5 IRQ (SPI1)

IVG9

IVG8

IVG9

IVG11

IVG9

CAN1 TX IRQ

IVG9

SDH Mask 0 IRQ

SDH Mask 1 IRQ

Reserved

IVG9

IVG10

IVG11

IVG13

IVG11

IVG7

USB_INT0 IRQ

USB_INT1 IRQ

USB_INT2 IRQ

USB_DMAINT IRQ

OTPSEC IRQ

DMA23 IRQ (SPI2)

DMA8 IRQ (UART1 RX)

DMA9 IRQ (UART1 TX)

DMA10 IRQ (ATAPI RX)

DMA11 IRQ (ATAPI TX)

TWI0 IRQ

Reserved

TWI1 IRQ

Reserved

CAN0 Receive IRQ

Reserved

CAN0 Transmit IRQ

MDMA Stream 2 IRQ

MDMA Stream 3 IRQ

MXVR Status IRQ

Reserved

Timer 0 IRQ

Timer 1 IRQ

MXVR Control Message IRQ

MXVR Asynchronous Packet IRQ

EPPI1 Error IRQ

Timer 2 IRQ

Timer 3 IRQ

Timer 4 IRQ

EPPI2 Error IRQ

IVG7

Timer 5 IRQ

UART3 Status IRQ

IVG7

Timer 6 IRQ

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ADSP-BF542/4/7/8/9

Preliminary Technical Data

Table 4. System Interrupt Controller (SIC) (Continued)

triggered the interrupt. A set bit indicates the peripheral is

asserting the interrupt, and a cleared bit indicates the

peripheral is not asserting the event.

Peripheral IRQ

(IRQ) Source

IRQ

GP IRQ

Core

ID (at Reset) IRQ ID

• SIC interrupt wakeup enable register (SIC_IWR). By

enabling the corresponding bit in this register, a peripheral

can be configured to wake up the processor, should the

core be idled when the event is generated. (For more infor-

mation, see Dynamic Power Management on Page 16.)

Timer 7 IRQ

93

94

95

IVG11

IVG12

4

5

Pin IRQ 2 (PINT2)

Pin IRQ 3 (PINT3)

Because multiple interrupt sources can map to a single general-

purpose interrupt, multiple pulse assertions can occur simulta-

neously, before or during interrupt processing for an interrupt

event already detected on this interrupt input. The IPEND reg-

ister contents are monitored by the SIC as the interrupt

acknowledgement.

Event Control

The ADSP-BF542/4/7/8/9 processor provides the user with a

very flexible mechanism to control the processing of events. In

the CEC, three registers are used to coordinate and control

events. Each register is 16 bits wide:

• CEC interrupt latch register (ILAT). The ILAT register

indicates when events have been latched. The appropriate

bit is set when the processor has latched the event and

cleared when the event has been accepted into the system.

This register is updated automatically by the controller, but

it may be written only when its corresponding IMASK bit

is cleared.

The appropriate ILAT register bit is set when an interrupt rising

edge is detected (detection requires two core clock cycles). The

bit is cleared when the respective IPEND register bit is set. The

IPEND bit indicates that the event has entered into the proces-

sor pipeline. At this point the CEC recognizes and queues the

next rising edge event on the corresponding event input. The

minimum latency from the rising edge transition of the general-

purpose interrupt to the IPEND output asserted is three core

clock cycles; however, the latency can be much higher, depend-

ing on the activity within and the state of the processor.

• CEC interrupt mask register (IMASK). The IMASK regis-

ter controls the masking and unmasking of individual

events. When a bit is set in the IMASK register, that event is

unmasked and is processed by the CEC when asserted. A

cleared bit in the IMASK register masks the event, prevent-

ing the processor from servicing the event even though the

event may be latched in the ILAT register. This register

may be read or written while in supervisor mode. (Note

that general-purpose interrupts can be globally enabled and

disabled with the STI and CLI instructions, respectively.)

DMA CONTROLLERS

ADSP-BF542/4/7/8/9 processors have multiple, independent

DMA channels that support automated data transfers with min-

imal overhead for the processor core. DMA transfers can occur

between the ADSP-BF542/4/7/8/9 processor’s internal memo-

ries and any of its DMA-capable peripherals. Additionally,

DMA transfers can be accomplished between any of the DMA-

capable peripherals and external devices connected to the exter-

nal memory interfaces, including DDR and asynchronous

memory controllers.

• CEC interrupt pending register (IPEND). The IPEND reg-

ister keeps track of all nested events. A set bit in the IPEND

register indicates the event is currently active or nested at

some level. This register is updated automatically by the

controller but may be read while in supervisor mode.

While the USB controller and MXVR have their own dedicated

DMA controllers, the other on-chip peripherals are managed by

two centralized DMA controllers, called DMAC1 (32-bit) and

DMAC0 (16-bit). Both operate in the SCLK domain. Each DMA

controller manages twelve independent peripheral DMA chan-

nels, as well as 2 independent memory DMA streams. The

DMAC1 controller masters high-bandwidth peripherals over a

dedicated 32-bit DMA access bus (DAB32). Similarly, the

DMAC0 controller masters most of serial interfaces over the 16-

bit DAB16 bus. Individual DMA channels have fixed access pri-

ority on the DAB buses. DMA priority of peripherals is

The SIC allows further control of event processing by providing

three 32-bit interrupt control and status registers. Each register

contains a bit corresponding to each of the peripheral interrupt

events shown in Table 4 on Page 8.

• SIC interrupt mask register (SIC_IMASK). This register

controls the masking and unmasking of each peripheral

interrupt event. When a bit is set in the register, that

peripheral event is unmasked and is processed by the sys-

tem when asserted. A cleared bit in the register masks the

peripheral event, preventing the processor from servicing

the event.

managed by flexible peripheral-to-DMA channel assignment.

All four DMA controllers use the same 32-bit DCB bus to

exchange data with L1 memory. This includes L1 ROM, but

excludes scratchpad memory. Fine granulation of L1 memory

and special DMA buffers minimize potential memory conflicts,

if the L1 memory is accessed by the core contemporaneously.

Similarly, there are dedicated DMA buses between the DMAC1,

DMAC0, and USB DMA controllers and the external bus inter-

face unit (EBIU) that arbitrates DMA accesses to external

memories and boot ROM.

• SIC interrupt status register (SIC_ISR). As multiple periph-

erals can be mapped to a single event, this register allows

the software to determine which peripheral event source

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Preliminary Technical Data

ADSP-BF542/4/7/8/9

The ADSP-BF542/4/7/8/9 processor DMA controllers support

both 1-dimensional (1D) and 2-dimensional (2D) DMA trans-

fers. DMA transfer initialization can be implemented from

registers or from sets of parameters called descriptor blocks.

configuration words in order to send/receive data to any valid

internal or external memory location. The Host DMA Port con-

troller includes the following features:

• Allows an external master to configure DMA read/write

data transfers and read port status

The 2D DMA capability supports arbitrary row and column

sizes up to 64K elements by 64K elements, and arbitrary row

and column step sizes up to 32K elements. Furthermore, the

column step size can be less than the row step size, allowing

implementation of interleaved data streams. This feature is

especially useful in video applications where data can be de-

interleaved on the fly.

• Uses a flexible asynchronous memory protocol for its

external interface

• Allows an 8- or 16-bit external data interface to the host

device

• Supports half-duplex operation

Examples of DMA types supported by the ADSP-BF542/4/7/8/9

processor DMA controller include:

• Supports Little/Big Endian data transfers

• Acknowledge mode allows flow control on host

transactions

• A single, linear buffer that stops upon completion

• A circular, auto-refreshing buffer that interrupts on each

full or fractionally full buffer

• Interrupt mode guarantees a burst of FIFO depth host

transactions

• 1-D or 2-D DMA using a linked list of descriptors

REAL-TIME CLOCK

• 2-D DMA using an array of descriptors, specifying only the

base DMA address within a common page

The ADSP-BF542/4/7/8/9 processor Real-Time Clock (RTC)

provides a robust set of digital watch features, including current

time, stopwatch, and alarm. The RTC is clocked by a

32.768 KHz crystal external to the ADSP-BF542/4/7/8/9 proces-

sors. The RTC peripheral has dedicated power supply pins so

that it can remain powered up and clocked even when the rest of

the processor is in a low-power state. The RTC provides several

programmable interrupt options, including interrupt per sec-

ond, minute, hour, or day clock ticks, interrupt on

In addition to the dedicated peripheral DMA channels, both the

DMAC1 and the DMAC0 controllers feature two memory

DMA channel pairs for transfers between the various memories

of the ADSP-BF542/4/7/8/9 processor system. This enables

transfers of blocks of data between any of the memories—

including external DDR, ROM, SRAM, and flash memory—

with minimal processor intervention. Like peripheral DMAs,

memory DMA transfers can be controlled by a very flexible

descriptor-based methodology or by a standard register-based

autobuffer mechanism.

programmable stopwatch countdown, or interrupt at a pro-

grammed alarm time.

The 32.768 KHz input clock frequency is divided down to a

1 Hz signal by a prescaler. The counter function of the timer

consists of four counters: a 60-second counter, a 60-minute

counter, a 24-hour counter, and an 32,768-day counter.

The memory DMA channels of the DMAC1 controller

(MDMA2 and MDMA3) can be optionally controlled by the

external DMA request input pins. When used in conjunction

with the External Bus Interface Unit (EBIU), this so-called

Handshaked Memory DMA (HMDMA) scheme can be used to

efficiently exchange data with block-buffered or FIFO-style

devices connected externally. Users can select whether the DMA

request pins control the source or the destination side of the

memory DMA. It allows control of the number of data transfers

for memory DMA. The number of transfers per edge is pro-

grammable. This feature can be programmed to allow memory

DMA to have an increased priority on the external bus relative

to the core.

When enabled, the alarm function generates an interrupt when

the output of the timer matches the programmed value in the

alarm control register. There are two alarms: The first alarm is

for a time of day. The second alarm is for a day and time of that

day.

The stopwatch function counts down from a programmed

value, with one-second resolution. When the stopwatch is

enabled and the counter underflows, an interrupt is generated.

Like the other peripherals, the RTC can wake up the

ADSP-BF542/4/7/8/9 processor from sleep mode upon genera-

tion of any RTC wakeup event. Additionally, an RTC wakeup

event can wake up the ADSP-BF542/4/7/8/9 processor from

deep sleep mode, and wake up the on-chip internal voltage reg-

ulator from the hibernate operating mode.

Host DMA Port Interface

The Host DMA port (HOSTDP) facilitates a host device exter-

nal to the ADSP-BF542/4/7/8/9 to be a DMA master and

transfer data back and forth. The host device always masters the

transactions and the processor is always a DMA slave device.

The HOSTDP port is enabled through the peripheral access bus.

Once the port has been enabled, the transaction are controlled

by the external host. The external host programs standard DMA

Rev. PrG

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December 2007

ADSP-BF542/4/7/8/9

Preliminary Technical Data

Connect RTC pins RTXI and RTXO with external components

as shown in Figure 4.

The timer units can be used in conjunction with the two UARTs

and the CAN controller to measure the width of the pulses in

the data stream to provide a software auto-baud detect function

for the respective serial channels.

The timers can generate interrupts to the processor core provid-

ing periodic events for synchronization, either to the system

clock or to a count of external signals.

RTXI

RTXO

R1

X1

In addition to the general-purpose programmable timers,

another timer is also provided by the processor core. This extra

timer is clocked by the internal processor clock and is typically

used as a system tick clock for generation of operating system

periodic interrupts.

C1

C2

UP/DOWN COUNTER AND THUMBWHEEL

INTERFACE

SUGGESTED COMPONENTS:

ECLIPTEK EC38J (THROUGH-HOLE PACKAGE)

EPSON MC405 12 PF LOAD (SURFACE MOUNT PACKAGE)

C1 = 22 PF

C2 = 22 PF

R1 = 10 M:

A 32-bit up/down counter is provided that can sense 2-bit

quadrature or binary codes as typically emitted by industrial

drives or manual thumb wheels. The counter can also operate in

general-purpose up/down count modes. Then, count direction

is either controlled by a level-sensitive input pin or by two edge

detectors.

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.

CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2

SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 PF.

Figure 4. External Components for RTC

A third input can provide flexible zero marker support and can

alternatively be used to input the push-button signal of thumb

wheels. All three pins have a programmable debouncing circuit.

WATCHDOG TIMER

The ADSP-BF542/4/7/8/9 processor includes a 32-bit timer that

can be used to implement a software watchdog function. A soft-

ware watchdog can improve system availability by forcing the

processor to a known state through generation of a hardware

reset, non-maskable interrupt (NMI), or general-purpose inter-

rupt, if the timer expires before being reset by software. The

programmer initializes the count value of the timer, enables the

appropriate interrupt, then enables the timer. Thereafter, the

software must reload the counter before it counts to zero from

the programmed value. This protects the system from remain-

ing in an unknown state where software, which would normally

reset the timer, has stopped running due to an external noise

condition or software error.

An internal signal forwarded to the timer unit enables one timer

to measure the intervals between count events. Boundary regis-

ters enable auto-zero operation or simple system warning by

interrupts when programmable count values are exceeded.

SERIAL PORTS (SPORTS)

The ADSP-BF542/4/7/8/9 processor incorporates up to four

dual-channel synchronous serial ports (SPORT0, SPORT1,

SPORT2, SPORT3) for serial and multiprocessor communica-

tions. The SPORTs support the following features:

• I²S capable operation.

• Bidirectional operation. Each SPORT has two sets of inde-

pendent transmit and receive pins, enabling eight channels

of I²S stereo audio.

If configured to generate a hardware reset, the watchdog timer

resets both the core and the ADSP-BF542/4/7/8/9 processor

peripherals. After a reset, software can determine if the watch-

dog was the source of the hardware reset by interrogating a

status bit in the watchdog timer control register.

• Buffered (8-deep) transmit and receive ports. Each port has

a data register for transferring data words to and from

other processor components and shift registers for shifting

data in and out of the data registers.

The timer is clocked by the system clock (SCLK), at a maximum

frequency of f_SCLK

.

• Clocking. Each transmit and receive port can either use an

external serial clock or generate its own, in frequencies

ranging from (f_SCLK/131,070) Hz to (f_SCLK/2) Hz.

TIMERS

There are up to two timer units in the ADSP-BF542/4/7/8/9

processors. One unit provides eight general-purpose program-

mable timers and the other unit provides three. Each timer has

an external pin that can be configured either as a Pulse Width

Modulator (PWM) or timer output, as an input to clock the

timer, or as a mechanism for measuring pulse widths and peri-

ods of external events. These timers can be synchronized to an

external clock input on the TMRx pins, an external clock

TMRCLK input pin, or to the internal SCLK.

• Word length. Each SPORT supports serial data words from

3 to 32 bits in length, transferred most-significant-bit first

or least-significant-bit first.

• Framing. Each transmit and receive port can run with or

without frame sync signals for each data word. Frame sync

signals can be generated internally or externally, active high

or low, and with either of two pulsewidths and early or late

frame sync.

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Preliminary Technical Data

ADSP-BF542/4/7/8/9

• Companding in hardware. Each SPORT can perform

A-law or μ-law companding according to ITU recommen-

dation G.711. Companding can be selected on the transmit

and/or receive channel of the SPORT without additional

latencies.

includes support for 5 to 8 data bits, 1 or 2 stop bits, and none,

even, or odd parity. Each UART port supports two modes of

operation:

• PIO (programmed I/O). The processor sends or receives

data by writing or reading I/O-mapped UART registers.

The data is double-buffered on both transmit and receive.

• DMA operations with single-cycle overhead. Each SPORT

can automatically receive and transmit multiple buffers of

memory data. The processor can link or chain sequences of

DMA transfers between a SPORT and memory.

• DMA (Direct Memory Access). The DMA controller trans-

fers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. Each UART has two dedicated

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates. Flexi-

ble interrupt timing options are available on the transmit

side.

• Interrupts. Each transmit and receive port generates an

interrupt upon completing the transfer of a data word or

after transferring an entire data buffer or buffers through

DMA.

• Multichannel capability. Each SPORT supports 128 chan-

nels out of a 1024-channel window and is compatible with

the H.100, H.110, MVIP-90, and HMVIP standards.

Each UART port's baud rate, serial data format, error code gen-

eration and status, and interrupts are programmable:

SERIAL PERIPHERAL INTERFACE (SPI) PORTS

• Supporting bit rates ranging from (f_SCLK/ 1,048,576) to

(f_SCLK) bits per second.

The ADSP-BF542/4/7/8/9 processor has up to three SPI-com-

patible ports that allow the processor to communicate with

multiple SPI-compatible devices.

• Supporting data formats from 7 to 12 bits per frame.

• Both transmit and receive operations can be configured to

generate maskable interrupts to the processor.

Each SPI port uses three pins for transferring data: two data pins

(master output-slave input, MOSI, and master input-slave out-

put, MISO) and a clock pin (serial clock, SCK). An SPI chip

select input pin (SPISS) lets other SPI devices select the proces-

sor, and three SPI chip select output pins per SPI port let the

processor select other SPI devices. The SPI select pins are recon-

figured programmable flag pins. Using these pins, the SPI ports

provide a full-duplex, synchronous serial interface, which sup-

ports both master/slave modes and multimaster environments.

The UART port’s clock rate is calculated as:

f

SCLK

-----------------------------------------------------------------------------

UART Clock Rate =

(1 – EDBO)

16

× UART_Divisor

Where the 16-bit UART Divisor comes from the UARTx_DLH

register (most significant 8 bits) and UARTx_DLL register (least

significant 8 bits, and EDBO is a bit in the UARTx_GCTL

register).

The SPI port’s baud rate and clock phase/polarities are pro-

grammable, and it has an integrated DMA controller,

configurable to support transmit or receive data streams. The

SPI’s DMA controller can only service unidirectional accesses at

any given time.

In conjunction with the general-purpose timer functions, auto-

baud detection is supported.

UART1 and UART3 feature a pair of RTS (request to send) and

CTS (clear to send) signals for hardware flow purposes. The

transmitter hardware is automatically prevented from sending

further data when the CTS input is de-asserted. The receiver can

automatically de-assert its RTS output when the enhanced

receive FIFO exceeds a certain high-water level. The capabilities

of the UARTs are further extended with support for the Infrared

Data Association (IrDA®) Serial Infrared Physical Layer Link

Specification (SIR) protocol.

The SPI port’s clock rate is calculated as:

f

SCLK

--------------------------------

SPI Clock Rate =

2 × SPI_Baud

Where the 16-bit SPI_BAUD register contains a value of 2 to

65,535.

During transfers, the SPI port simultaneously transmits and

receives by serially shifting data in and out on its two serial data

lines. The serial clock line synchronizes the shifting and sam-

pling of data on the two serial data lines.

CONTROLLER AREA NETWORK (CAN)

The ADSP-BF542/4/9 processor offers up to two CAN control-

lers that are communication controllers that implement the

Controller Area Network (CAN) 2.0B (active) protocol. This

protocol is an asynchronous communications protocol used in

both industrial and automotive control systems. The CAN pro-

tocol is well suited for control applications due to its capability

to communicate reliably over a network since the protocol

incorporates CRC checking message error tracking, and fault

node confinement. CAN controllers are only available on the

Automotive Grade versions for ADSP-BF542 and ADSP-BF544

processors. CAN is always available on the Industrial Grade ver-

UART PORTS (UARTS)

The ADSP-BF542/4/7/8/9 processor provides up to four full-

duplex Universal Asynchronous Receiver/Transmitter (UART)

ports. Each UART port provides a simplified UART interface to

other peripherals or hosts, supporting full-duplex, DMA-sup-

ported, asynchronous transfers of serial data. A UART port

Rev. PrG

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December 2007

ADSP-BF542/4/7/8/9

Preliminary Technical Data

sion of the ADSP-BF548 processor and the Automotive Grade

version of the ADSP-BF549 processor since those only have one

version each offered.

functions, the richness of GPIO functionality guarantees unre-

strictive pin usage. Every pin that is not used by any function

can be configured in GPIO mode on an individual basis.

The ADSP-BF542/4/9 CAN controllers offer the following

features:

After reset, all pins are in GPIO mode by default. Neither GPIO

output nor input drivers are active by default. Unused pins can

be left unconnected, therefore. GPIO data and direction control

registers provide flexible write-one-to-set and write-one-to-

clear mechanisms so that independent software threads do not

need to protect against each other because of expensive read-

modify-write operations when accessing the same port.

• 32 mailboxes (8 receive only, 8 transmit only, 16 config-

urable for receive or transmit).

• Dedicated acceptance masks for each mailbox.

• Additional data filtering on first two bytes.

• Support for both the standard (11-bit) and extended (29-

bit) identifier (ID) message formats.

Pin Interrupts

Due to its large number of port pins, the ADSP-BF542/4/7/8/9

processors introduce a new scheme to manage pin interrupts.

Every port pin can request interrupts in either an edge-sensitive

or a level-sensitive manner with programmable polarity. Inter-

rupt functionality is decoupled from GPIO operation. Four

system-level interrupt channels (INT0, INT1, INT2 and INT3)

are reserved for this purpose. Each of these interrupt channels

can manage up to 32 interrupt pins. The assignment from pin to

interrupt is not performed at a pin by pin level. Rather, groups

of eight pins (half ports) can be flexibly assigned to interrupt

channels.

• Support for remote frames.

• Active or passive network support.

• CAN wakeup from hibernation mode (lowest static power

consumption mode).

• Interrupts, including: TX complete, RX complete, error,

global.

The electrical characteristics of each network connection are

very demanding so the CAN interface is typically divided into

two parts: a controller and a transceiver. This allows a single

controller to support different drivers and CAN networks. The

ADSP-BF542/4/9 CAN module represents only the controller

part of the interface. The controller interface supports connec-

tion to 3.3V high-speed, fault-tolerant, single-wire transceivers.

Every pin interrupt channel features a special set of 32-bit mem-

ory-mapped registers that enable half-port assignment and

interrupt management. This not only includes masking, identi-

fication, and clearing of requests, it also enables access to the

respective pin states and use of the interrupt latches regardless

of whether the interrupt is masked or not. Most control registers

feature multiple MMR address entries to write-one-to-set or

write-one-to-clear them individually.

TWI CONTROLLER INTERFACE

The ADSP-BF542/4/7/8/9 processor includes up to two Two

Wire Interface (TWI) modules for providing a simple exchange

method of control data between multiple devices. The modules

are compatible with the widely used I²C bus standard. The TWI

modules offer the capabilities of simultaneous Master and Slave

operation, support for both 7-bit addressing and multimedia

data arbitration. Each TWI interface uses two pins for transfer-

ring clock (SCL) and data (SDA) and supports the protocol at

speeds up to 400k bits/sec. The TWI interface pins are compati-

ble with 5 V logic levels.

PIXEL COMPOSITOR (PIXC)

The pixel compositor (PIXC) provides image overlay with

transparent-color support, alpha blending, and color space con-

version capability for output to TFT-LCDs as well as

NTSC/PAL video encoders. It provides all of the control to

allow two data streams from two separate data buffers to be

combined, blended, and converted into appropriate forms for

both LCD panels and digital video outputs. The main image

buffer provides the basic background image, which is presented

in the data stream. The overlay image buffer allows the user to

add multiple foreground text, graphics, or video objects on top

of the main image or video data stream.

Additionally, the ADSP-BF542/4/7/8/9 processor’s TWI mod-

ules are fully compatible with Serial Camera Control Bus

(SCCB) functionality for easier control of various CMOS cam-

era sensor devices.

PORTS

ENHANCED PARALLEL PERIPHERAL INTERFACE

(EPPI)

Because of their rich set of peripherals, the

ADSP-BF542/4/7/8/9 processors group the many peripheral

signals to ten ports—referred to as Port A to Port J. Most ports

contain 16 pins, a few have less. Many of the associated pins are

shared by multiple signals. The ports function as multiplexer

controls. Every port has its own set of memory-mapped regis-

ters to control port muxing and GPIO functionality.

The ADSP-BF542/4/7/8/9 processor provides up to three

Enhanced Parallel Peripheral Interfaces (EPPIs), supporting

data widths up to 24 bits wide. The EPPI supports direct con-

nection to TFT LCD panels, parallel A/D and D/A converters,

video encoders and decoders, image sensor modules and other

general purpose peripherals.

General-Purpose I/O (GPIO)

Every pin in Port A to Port J can function as a GPIO pin result-

ing in a GPIO pin count of 154. While it is unlikely that all

GPIOs will be used in an application as all pins have multiple

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Preliminary Technical Data

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The following features are supported in the EPPI module.

ATA/ATAPI–6 INTERFACE

• Programmable data length: 8, 10, 12, 14, 16, 18, and 24 bits

per clock.

The ATAPI interface connects to CD/DVD and HDD drives,

and is ATAPI-6 compliant. The controller implements the

peripheral I/O mode, the multi-DMA mode, and the Ultra

DMA mode. The DMA modes enable faster data transfer and

reduced host management. The ATAPI Controller supports

PIO, Multi-DMA, and Ultra DMA ATAPI accesses. Key fea-

tures include:

• Bi-directional and half-duplex port.

• Clock can be provided externally or can be generated

internally.

• Various framed and non-framed operating modes. Frame

syncs can be generated internally or can be supplied by an

external device.

• Supports PIO modes 0,1,2,3,4

• Supports Multiword DMA modes 0,1,2

• Various general purpose modes with one frame syncs, two

frame syncs, three frame syncs and zero frame sync modes

for both receive and transmit directions.

• Supports Ultra DMA modes 0,1,2,3,4,5 (up to UDMA 100)

• Programmable timing for ATA interface unit

• Supports CompactFlash Card using True IDE mode

• ITU-656 status word error detection and correction for

ITU-656 Receive modes.

KEYPAD INTERFACE

• ITU-656 preamble and status word decode.

The keypad interface is a 16-pin interface module that is used to

detect the key pressed in a 8x8 (maximum) keypad matrix. The

size of the input keypad matrix is programmable. The interface

is capable of filtering the bounce on the input pins, which is

common in keypad applications. The width of the filtered

bounce is programmable. The module is capable of generating

an interrupt request to the core once it identifies that any key

has been pressed.

• Three different modes for ITU-656 receive modes: active

video only, vertical blanking only, and entire field mode.

• Horizontal and vertical windowing for GP 2 and 3 frame

sync modes.

• Optional packing and unpacking of data to/from 32 bits

from/to 8, 16 and 24 bits. If packing/unpacking is enabled,

endianness can be changed to change the order of pack-

ing/unpacking of bytes/words.

The interface supports a press-release-press mode and infra-

structure for a press-hold mode. The former mode identifies a

press, release and press of a key as two consecutive presses of the

same key whereas the later mode checks the input key’s state in

periodic intervals to determine the number of times the same

key is meant to be pressed. It is possible to detect when multiple

keys are pressed simultaneously, and to provide limited key res-

olution capability when this happens.

• Optional sign extension or zero fill for receive modes.

• During receive modes, alternate even or odd data samples

can be filtered out.

• Programmable clipping of data values for 8-bit transmit

modes.

• RGB888 can be converted to RGB666 or RGB565 for trans-

mit modes.

SECURE DIGITAL (SD)/SDIO CONTROLLER

• Various de-interleaving/interleaving modes for receiv-

ing/transmitting 4:2:2 YCrCb data.

The SD/SDIO controller is a serial interface that stores data at a

data rate of up to 10M bytes per second using a 4-bit data line.

The interface runs at 25 MHz.

• FIFO watermarks and urgent DMA features.

• Clock gating by an external device asserting the clock gat-

ing control signal.

The SD/SDIO controller supports the SD memory mode only.

The interface supports all the power modes and performs error

checking by CRC.

• Configurable LCD Data Enable (DEN) output available on

Frame Sync 3.

CODE SECURITY

USB ON-THE-GO DUAL-ROLE DEVICE CONTROLLER

An OTP/security system consisting of a blend of hardware and

software provides customers with a flexible and rich set of code

The USB OTG controller provides a low-cost connectivity solu-

tion for consumer mobile devices such as cell phones, digital

still cameras and MP3 players, allowing these devices to transfer

data using a point-to-point USB connection without the need

for a PC host. The USBDRC module can operate in a traditional

USB peripheral-only mode as well as the host mode presented

in the On-The-Go (OTG) supplement [1] to the USB 2.0 Speci-

fication [2]. In host mode, the USB module supports transfers at

high-speed (480Mbps), full-speed (12Mbps), and low-speed

(1.5Mbps) rates. Peripheral-only mode supports the high- and

full-speed transfer rates.

TM

security features with Lockbox ¹secure technology. Key fea-

tures include:

• OTP memory

• Unique chip ID

• Code authentication

• Secure mode of operation

¹Lockbox is a trademark of Analog Devices, Inc.

Rev. PrG

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December 2007

ADSP-BF542/4/7/8/9

Preliminary Technical Data

The security scheme is based upon the concept of authentica-

tion of digital signatures using standards-based algorithms and

provides a secure processing environment in which to execute

code and protect assets.

of the ADSP-BF542/4/7/8/9 processor peripherals also reduces

power consumption. See Table 5 for a summary of the power

settings for each mode.

Full-On Operating Mode – Maximum Performance

MEDIA TRANSCEIVER MAC LAYER (MXVR)

In the full-on mode, the PLL is enabled and is not bypassed,

providing capability for maximum operational frequency. This

is the power-up default execution state in which maximum per-

formance can be achieved. The processor core and all enabled

peripherals run at full speed.

The ADSP-BF549 processor provides a Media Transceiver

(MXVR) MAC layer, allowing the processor to be connected

directly to a MOST^®¹network through just an FOT or Electrical

PHY.

The MXVR is fully compatible with the industry standard stan-

dalone MOST controller devices, supporting 22.579 Mbps or

24.576 Mbps data transfer. It offers faster lock times, greater jit-

ter immunity, a sophisticated DMA scheme for data transfers,

and the high-speed internal interface to the core and L1 mem-

ory allows the full bandwidth of the network to be utilized. The

MXVR can operate as either the network master or as a network

slave.

Active Operating Mode – Moderate Power Savings

In the active mode, the PLL is enabled but bypassed. Because the

PLL is bypassed, the processor’s core clock (CCLK) and system

clock (SCLK) run at the input clock (CLKIN) frequency. In this

mode, the CLKIN to CCLK multiplier ratio can be changed,

although the changes are not realized until the Full-On mode is

entered. DMA access is available to appropriately configured L1

memories.

The MXVR supports synchronous data, asynchronous packets,

and control messages using dedicated DMA channels which

operate autonomously from the processor core moving data to

and from L1 and/or L2 memory. Synchronous data is trans-

ferred to or from the synchronous data physical channels on the

MOST bus through eight programmable DMA channels. The

synchronous data DMA channels can operate in various modes

including modes which trigger DMA operation when data pat-

terns are detected in the receive data stream. Furthermore two

DMA channels support asynchronous traffic and a further two

support control message traffic.

In the active mode, it is possible to disable the PLL through the

PLL Control register (PLL_CTL). If disabled, the PLL must be

re-enabled before transitioning to the full-on or sleep modes.

Table 5. Power Settings

Full On

Active

Enabled

No

Enabled Enabled On

Interrupts are generated when a user defined amount of syn-

chronous data has been sent or received by the processor or

when asynchronous packets or control messages have been sent

or received.

Enabled/ Yes

Disabled

Sleep

Enabled

-

Disabled Enabled On

Disabled Disabled On

Disabled Disabled Off

Deep Sleep Disabled

Hibernate Disabled

The MXVR peripheral can wake up the ADSP-BF549 processor

from sleep mode when a wakeup preamble is received over the

network or based on any other MXVR interrupt event. Addi-

tionally, detection of network activity by the MXVR can be used

to wake up the ADSP-BF549 processor from sleep mode or

hibernate. These features allow the ADSP-BF549 to operate in a

low-power state when there is no network activity or when data

is not currently being received or transmitted by the MXVR.

Sleep Operating Mode – High Dynamic Power Savings

The sleep mode reduces dynamic power dissipation by disabling

the clock to the processor core (CCLK). The PLL and system

clock (SCLK), however, continue to operate in this mode. Typi-

cally an external event or RTC activity will wake up the

processor. When in the sleep mode, assertion of wakeup will

cause the processor to sense the value of the BYPASS bit in the

PLL control register (PLL_CTL). If BYPASS is disabled, the pro-

cessor will transition to the full on mode. If BYPASS is enabled,

the processor will transition to the active mode.

The MXVR clock is provided through a dedicated external crys-

tal or crystal oscillator. The frequency of external crystal or

crystal oscillator can be 256Fs, 384Fs, 512Fs, or 1024Fs for

Fs = 38kHz, 44.1kHz, or 48kHz. If using a crystal to provide the

MXVR clock, use a parallel-resonant, fundamental mode,

microprocessor-grade crystal.

When in the sleep mode, system DMA access to L1 memory is

not supported.

DYNAMIC POWER MANAGEMENT

Deep Sleep Operating Mode – Maximum Dynamic Power

Savings

The ADSP-BF542/4/7/8/9 processor provides five operating

modes, each with a different performance/power profile. In

addition, dynamic power management provides the control

functions to dynamically alter the processor core supply voltage,

further reducing power dissipation. Control of clocking to each

The deep sleep mode maximizes dynamic power savings by dis-

abling the clocks to the processor core (CCLK) and to all

synchronous peripherals (SCLK). Asynchronous peripherals,

such as the RTC, may still be running but will not be able to

access internal resources or external memory. This powered-

¹MOST is a registered trademark of Standard Microsystems, Corp.

Rev. PrG

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December 2007

Preliminary Technical Data

ADSP-BF542/4/7/8/9

down mode can only be exited by assertion of the reset interrupt

(RESET) or by an asynchronous interrupt generated by the

RTC. When in deep sleep mode, an RTC asynchronous inter-

rupt causes the processor to transition to the active mode.

Assertion of RESET while in deep sleep mode causes the proces-

sor to transition to the full on mode.

VOLTAGE REGULATION

The ADSP-BF542/4/7/8/9 processor provides an on-chip volt-

age regulator that can generate processor core voltage levels

from an external supply. (Note specifications as indicated in

Operating Conditions on Page 32.) Figure 5 shows the typical

external components required to complete the power manage-

ment system. The regulator controls the internal logic voltage

levels and is programmable with the voltage regulator control

register (VR_CTL) in increments of 50 mV. To reduce standby

power consumption, the internal voltage regulator can be pro-

grammed to remove power to the processor core while keeping

Hibernate State – Maximum Static Power Savings

The hibernate state maximizes static power savings by disabling

the voltage and clocks to the processor core (CCLK) and to all

the synchronous peripherals (SCLK). The internal voltage regu-

lator for the processor can be shut off by writing b#00 to the

FREQ bits of the VR_CTL register. This disables both CCLK

and SCLK. Furthermore, it sets the internal power supply volt-

age (V_DDINT) to 0V to provide the greatest power savings mode.

Any critical information stored internally (memory contents,

register contents, etc.) must be written to a non-volatile storage

device prior to removing power if the processor state is to be

preserved.

I/O power supplied. While in hibernate mode, V_DDEXT, V_DDRTC

,

V

_DDDDR, V_DDUSB, and V_DDVRcan still be applied, eliminating the

need for external buffers. The voltage regulator can be activated

from this power down state by assertion of the RESET pin,

which will then initiate a boot sequence. The regulator can also

be disabled and bypassed at the user’s discretion. For additional

information, see “Switching Regulator Design Considerations

for the ASDP-BF533 Blackfin Processors” (EE-228).

Since V_DDEXTis still supplied in this mode, all of the external

pins tri-state, unless otherwise specified. This allows other

devices that may be connected to the processor to have power

still applied without drawing unwanted current.

The internal supply regulator can be woken up by CAN, by the

MXVR, by the keypad, by the up/down counter, by the USB,

and by some GPIO pins. It can also be woken up by a real-time

clock wakeup event or by asserting the RESET pin. Waking up

from hibernate state initiates the hardware reset sequence.

2.70V TO 3.6V

INPUT VOLTAGE

RANGE

S E T OF DE COUPL ING

CAP ACITOR S

V

DDVR

(L OW-INDUCTANCE )

V

DDVR

DDINT

+

100μF

With the exception of the VR_CTL and the RTC registers, all

internal registers and memories lose their content in hibernate

state. State variables may be held in external SRAM or SDRAM.

10μH

100nF

+

100μF

FDS 9431A

100μF

10μF

LOW E S R

Power Savings

ZHC S 1000

VR

OUT

As shown in Table 6, the ADSP-BF542/4/7/8/9 processor sup-

ports different power domains. The use of multiple power

domains maximizes flexibility, while maintaining compliance

with industry standards and conventions. By isolating the inter-

nal logic of the ADSP-BF542/4/7/8/9 processor into its own

power domain, separate from the RTC and other I/O, the pro-

cessor can take advantage of dynamic power management,

without affecting the RTC or other I/O devices. There are no

sequencing requirements for the various power domains.

S HOR T AND L OW-

INDUCTANCE WIR E

NOTE : DE S IGNE R S HOUL D MINIMIZE

TR ACE L E NGTH TO FDS 9431A.

GND

Figure 5. Voltage Regulator Circuit

Table 6. Power Domains

CLOCK SIGNALS

Power Domain

VDD Range

V_DDINT

The ADSP-BF542/4/7/8/9 processor can be clocked by an exter-

nal crystal, a sine wave input, or a buffered, shaped clock

derived from an external clock oscillator.

All internal logic, except RTC, DDR, and USB

RTC internal logic and crystal I/O

DDR external memory supply

USB internal logic and crystal I/O

Internal voltage regulator

MXVR PLL and logic

V_DDRTC

V_DDDDR

V_DDUSB

V_DDVR

If an external clock is used, it should be a TTL compatible signal

and must not be halted, changed, or operated below the speci-

fied frequency during normal operation. This signal is

connected to the processor’s CLKIN pin. When an external

clock is used, the XTAL pin must be left unconnected.

V_DDMP

All other I/O

V_DDEXT

Alternatively, because the ADSP-BF542/4/7/8/9 processor

includes an on-chip oscillator circuit, an external crystal may be

used. For fundamental frequency operation, use the circuit

Rev. PrG

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December 2007

ADSP-BF542/4/7/8/9

Preliminary Technical Data

shown in Figure 6. A parallel-resonant, fundamental frequency,

microprocessor-grade crystal is connected across the CLKIN

and XTAL pins. The on-chip resistance between CLKIN and the

XTAL pin is in the 500 kΩ range. Further parallel resistors are

typically not recommended. The two capacitors and the series

resistor shown in Figure 6 fine tune phase and amplitude of the

sine frequency.

voltages V_DDINTand V_DDEXT, the VCO is always permitted to run

up to the frequency specified by the part’s speed grade. The

CLKOUT pin reflects the SCLK frequency to the off-chip world.

It functions as reference for many timing specifications. While

inactive by default, it can be enabled using the EBIU_SDGCTL

and EBIU_AMGCTL registers.

The capacitor and resistor values shown in Figure 6 are typical

values only. The capacitor values are dependent upon the crystal

manufacturers’ load capacitance recommendations and the PCB

physical layout. The resistor value depends on the drive level

specified by the crystal manufacturer. System designs should

verify the customized values based on careful investigations on

multiple devices over temperature range.

DYNAMIC MODIFICATION

ON-THE-FLY

DYNAMIC MODIFICATION

REQUIRES PLL SEQUENCING

CCLK

SCLK

ꢀ 1, 2, 4, 8

ꢀ 1:15

PLL

0.5x - 64x

CLKIN

VCO

BLACKFIN

SCLK ꢁ CCLK/2

SCLK ꢁ 133MHz

CLKOUT

TO PLL CIRCUITRY

EN

CLKBUF

Figure 7. Frequency Modification Methods

EN

All on-chip peripherals are clocked by the system clock (SCLK).

The system clock frequency is programmable by means of the

SSEL3–0 bits of the PLL_DIV register. The values programmed

into the SSEL fields define a divide ratio between the PLL output

(VCO) and the system clock. SCLK divider values are two

through 15. Table 7 illustrates typical system clock ratios. The

default ratio is 4.

XTAL

CLKIN

18 pF*

3306*

FOR OVERTONE

OPERATION ONLY:

18 pF*

NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED

DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE

ANALYZE CAREFULLY.

Table 7. Example System Clock Ratios

Example Frequency Ratios

(MHz)

VCO

200

Signal Name Divider Ratio

Figure 6. External Crystal Connections

SSEL3–0

VCO/SCLK

SCLK

100

50

0010

2:1

A third-overtone crystal can be used at frequencies above 25

MHz. The circuit is then modified to ensure crystal operation

only at the third overtone, by adding a tuned inductor circuit as

shown in Figure 6. A design procedure for third-overtone oper-

ation is discussed in detail in application note EE-168.

0110

6:1

300

1010

10:1

500

50

Note that the divisor ratio must be chosen to limit the system

clock frequency to its maximum of f_SCLK. The SSEL value can be

changed dynamically without any PLL lock latencies by writing

the appropriate values to the PLL divisor register (PLL_DIV).

The Blackfin core runs at a different clock rate than the on-chip

peripherals. As shown in Figure 7 on Page 18, the core clock

(CCLK) and system peripheral clock (SCLK) are derived from

the input clock (CLKIN) signal. An on-chip PLL is capable of

multiplying the CLKIN signal by a programmable

0.5

؋

to 64

؋

multiplication factor (bounded by specified mini-

mum and maximum VCO frequencies). The default multiplier

is 8

؋

, but it can be modified by a software instruction sequence.

On-the-fly frequency changes can be effected by simply writing

to the PLL_DIV register.

The core clock (CCLK) frequency can also be dynamically

changed by means of the CSEL1–0 bits of the PLL_DIV register.

Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in

Table 8. The default ratio is 1. This programmable core clock

capability is useful for fast core frequency modifications.

On-the-fly CCLK and SCLK frequency changes can be effected

by simply writing to the PLL_DIV register. Whereas the maxi-

mum allowed CCLK and SCLK rates depend on the applied

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December 2007

Preliminary Technical Data

ADSP-BF542/4/7/8/9

The maximum CCLK frequency not only depends on the part's

speed grade, it also depends on the applied V_DDINTvoltage. See

Table 16 through Table 18 for details.

pins of the reset configuration register, sampled during power-

on resets and software-initiated resets, implement the following

modes:

• Idle–no boot mode (BMODE=0x0) — In this mode, the

processor goes into idle. The idle boot mode helps to

recover from illegal operating modes, in the case the user

misconfigured the OTP memory.

Table 8. Core Clock Ratios

Signal Name Divider Ratio Example Frequency Ratios

CSEL1–0

VCO/CCLK

(MHz)

VCO

300

• Boot from 8- or 16-bit external flash memory

(BMODE=0x1) — In this mode, the boot kernel loads the

first block header from address 0x2000 0000 and—depend-

ing on instructions containing in the header—the boot

kernel performs 8-bit or 16-bit boot or starts program exe-

cution at the address provided by the header. By default, all

configuration settings are set for the slowest device possible

(3-cycle hold time; 15-cycle R/W access times; 4-cycle

setup).

CCLK

300

150

125

25

00

01

10

11

1:1

2:1

4:1

8:1

300

500

200

BOOTING MODES

The ADSP-BF542/4/7/8/9 processor has many mechanisms

(listed in Table 9) for automatically loading internal and exter-

nal memory after a reset. The boot mode is defined by four

BMODE input pins dedicated to this purpose. There are two

categories of boot modes: In master boot modes the processor

actively loads data from parallel or serial memories. In slave

boot modes the processor receives data from an external host

devices.

The ARDY is not enabled by default. It can however, be

enabled by OTP programming. Similarly, all interface

behavior and timings can customized up by OTP program-

ming. This includes activation of burst-mode or page-

mode operation. In this mode, all signals belonging to the

asynchronous interface are enabled at port muxing level.

• Boot from 16-bit asynchronous FIFO (BMODE=0x2) — In

this mode, the boot kernel starts booting from address

0x2030 0000. Every 16-bit word that boot kernel has to read

from the FIFO must be requested by an low pulse on the

DMAR1 pin.

Table 9. Booting Modes

BMODE3–0 Description

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Idle–no boot

• Boot from serial SPI memory, EEPROM or flash

Boot from 8- or 16-bit external flash memory

Boot from 16-bit asynchronous FIFO

Boot from serial SPI memory (EEPROM or flash)

Boot from SPI host device

Boot from serial TWI memory (EEPROM/flash)

Boot from TWI host

(BMODE=0x3) — Eight-, 16-, 24- or 32-bit addressable

devices are supported. (internal note: no special support for

DataFlashes, as they understand now also standard SPI

protocol). The processor uses the PE4 GPIO pin to select a

single SPI EEPROM/flash device, submits a read command

and successive address bytes (0x00) until a valid 8-, 16-,

24-, or 32-bit addressable device is detected. Pull-up resis-

tors are required on the SSEL and MISO pins. By default, a

value of 0x85 is written to the SPI_BAUD register.

Boot from UART host

Reserved

• Boot from SPI host device (BMODE=0x4) — The proces-

sor operates in SPI slave mode (using SPI0) and is

configured to receive the bytes of the.LDR file from an SPI

host (master) agent. In the host, the HWAIT signal must be

interrogated by the host before every transmitted byte. A

pull-up resistor is required on the SPISS input. A pull-

down on the serial clock may improve signal quality and

booting robustness.

Boot from (DDR) SDRAM

Boot from OTP memory

Reserved

Boot from 8- or16-bit NANDflash memory via NFC

Boot from 16-Bit Host DMA

Boot from 8-Bit Host DMA

• Boot from serial TWI memory, EEPROM/flash

The boot modes listed in Table 9 provide a number of mecha-

nisms for automatically loading the processor’s internal and

external memories after a reset. By default all boot modes use

the slowest meaningful configuration settings. Default settings

can be altered via the initialization code feature at boot time or

by proper OTP programming at pre-boot time.The BMODE

(BMODE=0x5) — The processor operates in master mode

(using TWI0) and selects the TWI slave with the unique id

0xA0. The processor submits successive read commands to

the memory device starting at two byte internal address

0x0000 and begins clocking data into the processor. The

TWI memory device should comply with Philips I²C Bus

Specification version 2.1 and have the capability to auto-

increment its internal address counter such that the con-

tents of the memory device can be read sequentially. By

default, a prescale value of 0xA and CLKDIV value of

Rev. PrG

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ADSP-BF542/4/7/8/9

Preliminary Technical Data

0x0811 is used. Unless, altered by OTP settings an I²C

memory that takes two address bytes is assumed. Develop-

ment tools ensure that data that is booted to memories that

cannot be accessed by the Blackfin core is written to inter-

mediate storage place and then copied to final destination

via Memory DMA.

NAND flash boot supports the following features:

• Device Auto Detection.

• Error Detection & Correction for maximum

reliability.

• No boot stream size limitation.

• Boot from TWI host (BMODE=0x6) — The TWI host

agent selects the slave with the unique id 0x5F. The proces-

sor (using TWI0) replies with an acknowledgement and the

host can then download the boot stream. The TWI host

agent should comply with Philips I²C Bus Specification ver-

sion 2.1. An I²C multiplexer can be used to select one

processor at a time when booting multiple processors from

a single TWI.

• Peripheral DMA via channel 22 providing efficient

transfer of all data (excluding the ECC parity data).

• Software configurable boot mode for booting from

boot streams expanding multiple blocks including bad

blocks.

• Software configurable boot mode for booting from

multiple copies of the boot stream allowing for han-

dling of bad blocks and uncorrectable errors.

• Boot from UART host (BMODE=0x7) — In this mode, the

processor uses UART1 as booting source. Using an auto-

baud handshake sequence, a boot-stream-formatted

program is downloaded by the host. The host agent selects

a bit rate within the UART’s clocking capabilities.

• Configurable timing via OTP memory.

Small page NAND flash devices must have a 512 byte page

size, 32 pages per block, a 16 byte spare area size and a bus

configuration of 8 bits. By default all read requests from the

NAND flash are followed by 4 address cycles. If the NAND

flash device requires only 3 address cycles the device must

be capable of ignoring the additional address cycles.

When performing the autobaud, the UART expects a “@”

(0x40) character (eight bits data, one start bit, one stop bit,

no parity bit) on the RXD pin to determine the bit rate. It

then replies with an acknowledgement which is composed

of 4 bytes: 0xBF, the value of UART_DLL, the value of

UART_DLH, 0x00. The host can then download the boot

stream. The processor deasserts the RTS output to hold off

the host; CTS functionality is not enabled at boot time.

The small page NAND flash device must comply with the

following command set:

Reset: 0xFF

Read lower half of page: 0x00

Read upper half of page: 0x01

Read spare area: 0x50

• Boot from (DDR) SDRAM (BMODE=0xA) — In this

mode, the boot kernel starts booting from address

0x0000 0010. This is a warm boot scenario only. The

SDRAM is expected to contain a valid boot stream and the

SDRAM controller must have been configured by the OTP

settings.

For large page NAND flash devices the 4 byte electronic

signature is read in order to configure the kernel for boot-

ing, this allows support for multiple large page devices.

Byte 4 of the electronic signature must comply with the fol-

lowing specification in Table 10 on page 21.

• Boot from 8-bit and 16-bit external NAND flash memory

(BMODE=0xD) - In this mode, auto detection of the

NAND flash device is performed. The processor configures

PORTJ GPIO pins PJ1 and PJ2 to enable the NAND CE

and NAND RB signals respectively. For correct device

operation pull-up resistors are required on both CE (PJ1)

and RB (PJ2) signals. By default a value of 0x0033 is written

to the NFC_CTL register. The booting procedure always

starts by booting from byte 0 of block 0 of the NAND flash

device.

Any configuration from Table 10 that also complies with

the command set listed below is directly supported by the

boot kernel. There are no restrictions on the page size or

block size as imposed by the small page boot kernel.

Large page devices must support the following command

set:

Reset: 0xFF

Read Electronic Signature: 0x90

Read: 0x00, 0x30 (confirm command)

Large page devices must not support or react to NAND

flash command 0x50. This is a small page NAND flash

command used for device auto detection.

By default the boot kernel will always issue 5 address cycles,

therefore if a large page device requires only 4 cycles, the

device must be capable of ignoring the additional address

cycles.

Rev. PrG

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Page 20 of 82

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December 2007

Preliminary Technical Data

ADSP-BF542/4/7/8/9

16-bit NAND flash memory devices must only support the

issuing of command and address cycles via the lower 8 bits

of the data bus. Devices that make use of the full 16-bit bus

for command and address cycles are not supported.

as the SDRAM controller, then returns using an RTS

instruction. The routine may also by the final application

which will never return to the boot kernel.

• Boot from 8-Bit Host DMA (BMODE=0xF) — In this

mode, the Host DMA port is configured in 8-bit interrupt

mode, little endian. Unlike in other modes, here the host is

responsible for interpreting the boot stream. It writes data

block per data block into the Host DMA port. Before con-

figuring the DMA settings for each block, the host may

either poll the ALLOW_CONFIG bit in HOST_STATUS

or wait to be interrupted by the HWAIT signal. When

using HWAIT, the host must still check ALLOW_CONFIG

at least once before beginning to configure the Host DMA

Port. The host will receive an interrupt from the

Table 10. Byte 4 Electronic Signature Specification

Page Size (excluding D1:D0 00

1KBytes

spare area)

01

2KBytes

10

11

4KBytes

8KBytes

HOST_ACK signal every time it is allowed to send the next

FIFO depth (Sixteen 32-bit words) of information. When

the host sends an HIRQ control command, the boot kernel

issues a CALL instruction to address 0xFFA0 0000. It is the

host's responsibility to ensure valid code has been place at

this address. The routine at 0xFFA0 0000 can be a simple

initialization routine to configure internal resources, such

as the SDRAM controller, then returns using an RTS

instruction. The routine may also by the final application

which will never return to the boot kernel.

Spare Area Size

D2

0

1

8Bytes / 512Bytes

16Bytes /

512Bytes

BlockSize(excluding D5:4

spare area)

00

01

10

11

0

64KBytes

128 kBytes

256KBytes

512KBytes

x8

For each of the boot modes, a 16-byte header is first read from

an external memory device. The header specifies the number of

bytes to be transferred and the memory destination address.

Multiple memory blocks may be loaded by any boot sequence.

Once all blocks are loaded, program execution commences from

the address stored in the EVT1 register.

Bus width

D6

1

x16

Not Used for

configuration

D3, D7

Prior to booting, the pre-boot routine interrogates the OTP

memory. Individual boot modes can be customized or even dis-

abled based on OTP programming. External hardware,

especially booting hosts may watch the HWAIT signal to deter-

mine when the pre-boot has finished and the boot kernel starts

the boot process. By programming OTP memory, the user can

instruct the preboot routine to also customize: PLL and Voltage

Regulator; DDR Controller; and Asynchronous Interface.

• Boot from OTP memory (BMODE=0xB) — This provides

a stand-alone booting method. The boot stream is loaded

from on-chip OTP memory. By default the boot stream is

expected to start from OTP page 0x40 on and can occupy

all public OTP memory up to page 0xDF. This is 2560

bytes. Since the start page is programmable the maximum

size of the boot stream can be extended to 3072 bytes.

The boot kernel differentiates between a regular hardware reset

and a wakeup-from-hibernate event to speed up booting in the

later case. Bits 6-4 in the system reset configuration (SYSCR)

register can be used to bypass pre-boot routine and/or boot ker-

nel in case of a software reset. They can also be used to simulate

a wakeup-from-hibernate boot in the software reset case.

• Boot from 16-Bit Host DMA (BMODE=0xE) — In this

mode, the host DMA port is configured in 16-bit Acknowl-

edge mode, little endian. Unlike in other modes, here the

host is responsible for interpreting the boot stream. It

writes data block per data block into the Host DMA port.

Before configuring the DMA settings for each block, the

host may either poll the ALLOW_CONFIG bit in

HOST_STATUS or wait to be interrupted by the HWAIT

signal. When using HWAIT, the host must still check

ALLOW_CONFIG at least once before beginning to con-

figure the Host DMA Port. After completing the

configuration the host is required to poll the READY bit in

HOST_STATUS before beginning to transfer data. When

the host sends an HIRQ control command, the boot kernel

issues a CALL instruction to 0xFFA0 0000 address. It is the

host's responsibility to ensure valid code has been placed at

this address. The routine at 0xFFA0 0000 can be a simple

initialization routine to configure internal resources, such

The boot process can be further customized by “initialization

code.” This is a piece of code that is loaded and executed prior to

the regular application boot. Typically, this is used to configure

the DDR controller or to speed up booting by managing PLL,

clock frequencies, wait states, or serial bit rates.

The boot ROM also features C-callable function entries that can

be called by the user application at run time. This enables sec-

ond-stage boot or boot management schemes to be

implemented with ease.

Rev. PrG

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Page 21 of 82

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December 2007

ADSP-BF542/4/7/8/9

Preliminary Technical Data

allowing the developer to load code, set breakpoints, observe

variables, observe memory, and examine registers. The proces-

sor must be halted to send data and commands, but once an

operation has been completed by the emulator, the processor

system is set running at full speed with no impact on system

timing.

INSTRUCTION SET DESCRIPTION

The Blackfin processor family assembly language instruction set

employs an algebraic syntax designed for ease of coding and

readability. The instructions have been specifically tuned to pro-

vide a flexible, densely encoded instruction set that compiles to

a very small final memory size. The instruction set also provides

fully featured multifunction instructions that allow the pro-

grammer to use many of the processor core resources in a single

instruction. Coupled with many features more often seen on

microcontrollers, this instruction set is very efficient when com-

piling C and C++ source code. In addition, the architecture

supports both user (algorithm/application code) and supervisor

(O/S kernel, device drivers, debuggers, ISRs) modes of opera-

tion, allowing multiple levels of access to core processor

resources.

To use these emulators, the target board must include a header

that connects the processor’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, multiprocessor scan

chains, signal buffering, signal termination, and emulator pod

logic, see Analog Devices JTAG Emulation Technical Reference

(EE-68) on the Analog Devices web site under

www.analog.com/ee-notes. This document is updated regularly

to keep pace with improvements to emulator support.

The assembly language, which takes advantage of the proces-

sor’s unique architecture, offers the following advantages:


型号：	ADSP-BF544
厂家：	ADI
描述：	Embedded Processor 嵌入式处理器
文件：	总82页 (文件大小：1486K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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