ADUC836BCPZ_技术文档

®

MicroConverter , Dual 16-Bit -

ADCs with Embedded 62 kB Flash MCU

ADuC836

FEATURES

FUNCTIONAL BLOCK DIAGRAM

High Resolution - ADCs

AV

DD

2 Independent ADCs (16-Bit Resolution)

16-Bit No Missing Codes, Primary ADC

16-Bit rms (16-Bit p-p) Effective Resolution @ 20 Hz

Offset Drift 10 nV/C, Gain Drift 0.5 ppm/C

Memory

62 Kbytes On-Chip Flash/EE Program Memory

4 Kbytes On-Chip Flash/EE Data Memory

Flash/EE, 100Year Retention, 100 Kcycles Endurance

3 Levels of Flash/EE Program Memory Security

In-Circuit Serial Download (No External Hardware)

High Speed User Download (5 Seconds)

2304 Bytes On-Chip Data RAM

8051 Based Core

8051 Compatible Instruction Set

32 kHz External Crystal

On-Chip Programmable PLL (12.58 MHz Max)

3  16-BitTimer/Counter

AV

ADuC836

DD

IEXC1

IEXC2

CURRENT

SOURCE

AIN1

AIN2

PRIMARY

16-BIT- ADC

BUF

PGA

MUX

12-BIT

DAC

BUF

DAC

AIN3

AIN4

AIN5

AGND

DUAL

16-BIT

-DAC

AUXILIARY

16-BIT- ADC

PWM0

PWM1

MUX

TEMP

SENSOR

DUAL

16-BIT

PWM

EXTERNAL

INTERNAL

BAND GAP

REFIN–

REFIN+

V

REF

DETECT

V

REF

8051-BASED MCU WITH ADDITIONAL

PERIPHERALS

RESET

62 KBYTES FLASH/EE PROGRAM MEMORY

4 KBYTES FLASH/EE DATA MEMORY

2304 BYTES USER RAM

DV

DD

POR

3  16 BIT TIMERS

BAUDRATE TIMER

POWER SUPPLY MON

WATCHDOG TIMER

DGND

PLL AND PROG

CLOCK DIV

2

4  PARALLEL

PORTS

UART, SPI, AND I C

WAKE-UP/

RTC TIMER

OSC

SERIAL I/O

26 Programmable I/O Lines

11 Interrupt Sources, 2 Priority Levels

Dual Data Pointer, Extended 11-Bit Stack Pointer

On-Chip Peripherals

XTAL1 XTAL2

GENERAL DESCRIPTION

Internal Power on Reset Circuit

The ADuC836 is a complete smart transducer front end, integrating

two high resolution - ADCs, an 8-bit MCU, and program/data

Flash/EE memory on a single chip.

12-BitVoltage Output DAC

Dual 16-Bit - DACs/PWMs

On-ChipTemperature Sensor

Dual Excitation Current Sources

Time Interval Counter (Wake-Up/RTCTimer)

UART, SPI^®, and I²C^®Serial I/O

High Speed Baud Rate Generator (Including 115,200)

WatchdogTimer (WDT)

The two independent ADCs (primary and auxiliary) include a

temperature sensor and a PGA (allowing direct measurement

of low level signals).The ADCs with on-chip digital ﬁltering and

programmable output data rates are intended for the measure-

ment of wide dynamic range, low frequency signals, such as those

in weigh scale, strain gage, pressure transducer, or temperature

measurement applications.

Power Supply Monitor (PSM)

Power

Normal: 2.3 mA Max @ 3.6V (Core CLK = 1.57 MHz)

Power-Down: 20 A Max withWake-UpTimer Running

Speciﬁed for 3V and 5V Operation

Package andTemperature Range

52-Lead MQFP (14 mm  14 mm), –40C to +125C

56-Lead LFCSP (8 mm  8 mm), –40C to +85C

The device operates from a 32 kHz crystal with an on-chip PLL

generating a high frequency clock of 12.58 MHz.This clock is

routed through a programmable clock divider from which the MCU

core clock operating frequency is generated.The microcontroller

core is an 8052 and therefore 8051 instruction set compatible

with 12 core clock periods per machine cycle.

APPLICATIONS

Intelligent Sensors

Weigh Scales

Portable Instrumentation, Battery-Powered Systems

4–20 mATransmitters

Data Logging

62 Kbytes of nonvolatile Flash/EE program memory, 4 Kbytes of

nonvolatile Flash/EE data memory, and 2304 bytes of data RAM

are provided on-chip.The program memory can be conﬁgured as

data memory to give up to 60 Kbytes of NV data memory in data

logging applications.

On-chip factory ﬁrmware supports in-circuit serial download and

debug modes (via UART), as well as single-pin emulation mode

via the EA pin.The ADuC836 is supported by a QuickStart™

development system featuring low cost software and hardware

development tools.

Precision System Monitoring

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed byAnalog Devices for its

use, nor for any infringements of patents or other rights of third parties

that may result from its use. No license is granted by implication or other-

wiseunder any patent or patent rights ofAnalog Devices.Trademarks and

registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

ADuC836

TABLE OF CONTENTS

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . .1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .1

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . .9

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . .9

DETAILED BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . .10

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . .10

MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . .13

NONVOLATILE FLASH/EE MEMORY

Flash/EE Memory Overview . . . . . . . . . . . . . . . . . . . . . . . .29

Flash/EE Memory and the ADuC836 . . . . . . . . . . . . . . . . .29

ADuC836 Flash/EE Memory Reliability . . . . . . . . . . . . . . .29

Flash/EE Program Memory . . . . . . . . . . . . . . . . . . . . . . . .30

Serial Downloading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Parallel Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

User Download Mode (ULOAD) . . . . . . . . . . . . . . . . . . . .31

Flash/EE Program Memory Security . . . . . . . . . . . . . . . . . .31

Lock, Secure, and Serial Safe Modes . . . . . . . . . . . . . . . . . .31

Using the Flash/EE Data Memory . . . . . . . . . . . . . . . . . . .32

ECON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Programming the Flash/EE Data Memory . . . . . . . . . . . . .33

Flash/EE MemoryTiming . . . . . . . . . . . . . . . . . . . . . . . . . .33

OTHER ON-CHIP PERIPHERALS

DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

On-Chip PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Time Interval Counter (Wake-Up/RTCTimer) . . . . . . . . .40

WatchdogTimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Power Supply Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . .44

I²C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Dual Data Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

SPECIAL FUNCTION REGISTERS (SFRS) . . . . . . . . . .14

Accumulator SFR (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . .14

B SFR (B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Data Pointer (DPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Stack Pointer (SP and SPH) . . . . . . . . . . . . . . . . . . . . . . . .15

Program StatusWord (PSW) . . . . . . . . . . . . . . . . . . . . . . . .15

Power Control SFR (PCON) . . . . . . . . . . . . . . . . . . . . . . .15

ADuC836 Conﬁguration SFR (CFG836) . . . . . . . . . . . . . .15

Complete SFR Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

8052 COMPATIBLE ON-CHIP PERIPHERALS

ADC SFR INTERFACE

Parallel I/O Ports 0–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

UART Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

UART Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Baud Rate Generation UsingTimer 1 andTimer 2 . . . . . . .59

Baud Rate Generation UsingTimer 3 . . . . . . . . . . . . . . . . .60

Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

ADCSTAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

ADCMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

ADC0CON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

ADC1CON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

ADC0H/ADC0M/ADC1H/ADC1L . . . . . . . . . . . . . . . . . .20

OF0H/OF0M/OF1H/OF1L . . . . . . . . . . . . . . . . . . . . . . . .20

GN0H/GN0M/GN1H/GN1L . . . . . . . . . . . . . . . . . . . . . . .20

SF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

ICON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

HARDWARE DESIGN CONSIDERATIONS

External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . .63

Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Power-On Reset (POR) Operation . . . . . . . . . . . . . . . . . . .64

Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Wake-Up from Power-Down Latency . . . . . . . . . . . . . . . . .65

Grounding and Board Layout Recommendations . . . . . . . .66

ADuC836 System Self-Identiﬁcation . . . . . . . . . . . . . . . . . .66

Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

PRIMARY AND AUXILIARY ADC NOISE

PERFORMANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

PRIMARY AND AUXILIARY ADC CIRCUIT

DESCRIPTION

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Primary ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Auxiliary ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Analog Input Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Primary and Auxiliary ADC Inputs . . . . . . . . . . . . . . . . . . .25

Analog Input Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Programmable Gain Ampliﬁer . . . . . . . . . . . . . . . . . . . . . . .25

Bipolar/Unipolar Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Burnout Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Excitation Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Reference Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

- Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Digital Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

ADC Chopping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

OTHER HARDWARE CONSIDERATIONS

In-Circuit Serial Download Access . . . . . . . . . . . . . . . . . . .67

Embedded Serial Port Debugger . . . . . . . . . . . . . . . . . . . . .67

Single-Pin Emulation Mode . . . . . . . . . . . . . . . . . . . . . . . .67

Typical System Conﬁguration . . . . . . . . . . . . . . . . . . . . . . .68

QUICKSTART DEVELOPMENT SYSTEM . . . . . . . . . . .69

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . .70

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . .80

–2–

REV. A

ADuC836

(AV_DD= 2.7 V to 3.6 V or 4.75 V to 5.25 V, DV_DD= 2.7 V to 3.6 V or 4.75 V to 5.25 V,

REFIN(+) = 2.5 V; REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 =

32.768 kHz Crystal; all speciﬁcations T_MINto T_MAX, unless otherwise noted.)

SPECIFICATIONS¹

Parameter

ADuC836

Test Conditions/Comments

Unit

ADC SPECIFICATIONS

Conversion Rate

5.4

105

On Both Channels

Programmable in 0.732 ms Increments

Hz min

Hz max

Primary ADC

No Missing Codes²

Resolution

16

13.5

16

20Hz Update Rate

Bits min

Bits p-p typ

Range = ±20 mV, 20 Hz Update Rate

Range = ±2.56V, 20 Hz Update Rate

Output NoiseVaries with Selected

Output Noise

SeeTables X and XI in

ADuC836 ADC Description Update Rate and Gain Range

Integral Nonlinearity

Offset Error³

±15

±3

1 LSB

ppm of FSR max

V typ

Offset Error Drift

±10

±0.5

±2

nV/°C typ

V typ

LSB typ

ppm/°C typ

V typ

dBs typ

Full-Scale Error⁴

Range = ±20 mV to ±640 mV

Range = ±1.28V to ±2.56V

Gain Error Drift⁵

ADC Range Matching

Power Supply Rejection (PSR)

AIN = 18 mV

AIN = 7.8 mV, Range = ±20 mV

AIN = 1V, Range = ±2.56V

95

80

dBs typ

Common-Mode DC Rejection

On AIN

95

113

125

At DC, AIN = 7.8 mV, Range = ±20 mV

At DC, AIN = 1V, Range = ±2.56V

20 Hz Update Rate

50 Hz/60 Hz ±1 Hz, AIN = 7.8 mV,

Range = ±20 mV

50 Hz/60 Hz ±1 Hz, AIN = 1V,

Range = ±2.56V

50 Hz/60 Hz ±1 Hz, AIN = 1V,

Range = ±2.56V

dBs typ

On REFIN

Common-Mode 50 Hz/60 Hz Rejection

On AIN

95

90

dBs typ

On REFIN

Normal Mode 50 Hz/60 Hz Rejection

On AIN

On REFIN

60

50 Hz/60 Hz ±1 Hz, 20 Hz Update Rate

dBs typ

Auxiliary ADC

No Missing Codes²

Resolution

16

Bits min

Bits p-p typ

Range = ±2.5V, 20 Hz Update Rate

Output Noise

SeeTable XII in ADuC836 Output NoiseVaries with Selected

ADC Description

Update Rate

Integral Nonlinearity

Offset Error³

±15

–2

ppm of FSR max

LSB typ

Offset Error Drift

1

V/°C typ

LSB typ

ppm/°C typ

dBs typ

Full-Scale Error⁶

–2.5

±0.5

80

Gain Error Drift⁵

Power Supply Rejection (PSR)

Normal Mode 50 Hz/60 Hz Rejection

On AIN

AIN = 1V, 20 Hz Update Rate

60

50 Hz/60 Hz ±1 Hz

50 Hz/60 Hz ±1 Hz, 20 Hz Update Rate

dBs typ

On REFIN

DAC PERFORMANCE

DC Speciﬁcations⁷

Resolution

12

Bits

Relative Accuracy

Differential Nonlinearity

Offset Error

±3

–1

±50

±1

LSB typ

LSB max

mV max

% max

% typ

Guaranteed 12-Bit Monotonic

Gain Error⁸

AV_DDRange

V_REFRange

AC Speciﬁcations^{2, 7}

Voltage Output SettlingTime

Digital-to-Analog Glitch Energy

15

10

SettlingTime to 1 LSB of FinalValue

1 LSB Change at Major Carry

s typ

nVs typ

REV. A

–3–

ADuC836

SPECIFICATIONS (continued)

Parameter

ADuC836

Test Conditions/Comments

Unit

INTERNAL REFERENCE

ADC Reference

ReferenceVoltage

1.25 ± 1%

45

100

InitialTolerance @ 25°C,V_DD= 5V

V min/max

dBs typ

ppm/°C typ

Power Supply Rejection

ReferenceTempco

DAC Reference

ReferenceVoltage

Power Supply Rejection

ReferenceTempco

2.5 ± 1%

50

±100

InitialTolerance @ 25°C,V_DD= 5V

V min/max

dBs typ

ppm/°C typ

ANALOG INPUTS/REFERENCE INPUTS

Primary ADC

Differential InputVoltage Ranges^{9, 10}

External ReferenceVoltage = 2.5V

RN2, RN1, RN0 of ADC0CON Set to

0 0 0 (Unipolar Mode 0 mV to 20 mV)

0 0 1 (Unipolar Mode 0 mV to 40 mV)

0 1 0 (Unipolar Mode 0 mV to 80 mV)

0 1 1 (Unipolar Mode 0 mV to 160 mV)

1 0 0 (Unipolar Mode 0 mV to 320 mV)

1 0 1 (Unipolar Mode 0 mV to 640 mV)

1 1 0 (Unipolar Mode 0V to 1.28V)

1 1 1 (Unipolar Mode 0V to 2.56V)

T_MAX= 85°C

Bipolar Mode (ADC0CON3 = 0)

±20

±40

±80

±160

±320

±640

±1.28

±2.56

mV

V

Analog Input Current²

±1

nA max

pA/°C typ

V min

V max

±5

±15

T_MAX= 125°C

T_MAX= 85°C

T_MAX= 125°C

Analog Input Current Drift

Absolute AINVoltage Limits²

AGND + 100 mV

AV_DD– 100 mV

Auxiliary ADC

InputVoltage Range^{9, 10}

0 toV_REF

Unipolar Mode, for Bipolar Mode

See Note 11

V

Average Analog Input Current

Average Analog Input Current Drift²

Absolute AINVoltage Limits^{2, 11}

125

±2

Input CurrentWillVary with Input

Voltage on the Unbuffered Auxiliary ADC pA/V/°C typ

nA/V typ

AGND – 30 mV

AV_DD+ 30 mV

V min

V max

External Reference Inputs

REFIN(+) to REFIN(–) Range²

1

V min

V max

A/V typ

nA/V/°C typ

V min

AV_DD

1

±0.1

0.3

0.65

Average Reference Input Current

Average Reference Input Current Drift

“NO Ext. REF”TriggerVoltage

Both ADCs Enabled

NOXREF Bit Active if V_REF< 0.3V

NOXREF Bit Inactive if V_REF> 0.65V

V max

ADC SYSTEM CALIBRATION

Full-Scale Calibration Limit

Zero-Scale Calibration Limit

Input Span

1.05  FS

–1.05  FS

0.8  FS

2.1  FS

V max

V min

V max

ANALOG (DAC) OUTPUT

Voltage Range

0 toV_REF

0 to AV_DD

10

100

0.5

DACRN = 0 in DACCON SFR

DACRN = 1 in DACCON SFR

From DAC Output to AGND

V typ

k typ

pF typ

 typ

A typ

Resistive Load

Capacitive Load

Output Impedance

I_SINK

50

TEMPERATURE SENSOR

Accuracy

Thermal Impedance (_JA)

±2

90

52

°C typ

°C/W typ

MQFP Package

CSP Package (Base Floating)¹²

–4–

REV. A

ADuC836

Parameter

ADuC836

Test Conditions/Comments

Unit

TRANSDUCER BURNOUT CURRENT SOURCES

AIN+ Current

AIN– Current

–100

+100

AIN+ Is the Selected Positive Input

to the Primary ADC

AIN– Is the Selected Negative Input

to the Auxiliary ADC

nA typ

InitialTolerance @ 25°C

Drift

±10

0.03

% typ

%/°C typ

EXCITATION CURRENT SOURCES

Output Current

InitialTolerance @ 25°C

Drift

Initial Current Matching @ 25°C

Drift Matching

–200

±10

200

±1

20

1

0.1

AV_DD– 0.6

AGND

Available from Each Current Source

A typ

% typ

ppm/°C typ

% typ

ppm/°C typ

A/V typ

V max

Matching between Both Current Sources

AV_DD= 5V + 5%

Line Regulation (AV_DD

)

Load Regulation

Output Compliance²

V min

LOGIC INPUTS

All Inputs Except SCLOCK, RESET,

and XTAL1²

V_INL, Input LowVoltage

0.8

0.4

2.0

DV_DD= 5V

DV_DD= 3V

V max

V min

V_INH, Input HighVoltage

SCLOCK and RESET Only

(Schmitt-Triggered Inputs)²

V_T+

1.3/3

DV_DD= 5V

DV_DD= 3V

DV_DD= 5V

DV_DD= 3V

DV_DD= 5V

DV_DD= 3V

V min/V max

0.95/2.5

0.8/1.4

0.4/1.1

0.3/0.85

V_T–

V_{T+ –}V_T–

Input Currents

Port 0, P1.2–P1.7, EA

±10

V_IN= 0V orV_DD

A max

A min/A max

A max

A min/A max

SCLOCK, MOSI, MISO, SS¹³

–10 min, –40 max

±10

V_IN= 0V, DV_DD= 5V, Internal Pull-Up

V_IN=V_DD, DV_DD= 5V

V_IN= 0V, DV_DD= 5V

V_IN=V_DD, DV_DD= 5V,

Internal Pull-Down

RESET

35 min, 105 max

P1.0, P1.1, Ports 2 and 3

±10

–180

–660

–20

–75

5

V_IN=V_DD, DV_DD= 5V

V_IN= 2V, DV_DD= 5V

A max

A min

A max

A min

A max

pF typ

V_IN= 450 mV, DV_DD= 5V

All Digital Inputs

Input Capacitance

CRYSTAL OSCILLATOR (XTAL1 AND XTAL2)

Logic Inputs, XTAL1 Only²

V_INL, Input LowVoltage

0.8

0.4

3.5

2.5

18

DV_DD= 5V

DV_DD= 3V

DV_DD= 5V

DV_DD= 3V

V max

V min

pF typ

V_INH, Input HighVoltage

XTAL1 Input Capacitance

XTAL2 Output Capacitance

18

REV. A

–5–

ADuC836

SPECIFICATIONS (continued)

Parameter

ADuC836

Test Conditions/Comments

Unit

LOGIC OUTPUTS (Not Including XTAL2)²

V_OH, Output HighVoltage

2.4

0.4

±10

5

V_DD= 5V, I_SOURCE= 80 A

V_DD= 3V, I_SOURCE= 20 A

I_SINK= 8 mA, SCLOCK, MOSI/SDATA

I_SINK= 10 mA, P1.0 and P1.1

I_SINK= 1.6 mA, All Other Outputs

V min

V max

A max

pF typ

V_OL, Output LowVoltage¹⁴

Floating State Leakage Current²

Floating State Output Capacitance

POWER SUPPLY MONITOR (PSM)

AV_DDTrip Point Selection Range

2.63

4.63

±3.0

±4.0

2.63

4.63

±3.0

±4.0

FourTrip Points Selectable inThis Range

Programmed viaTPA1–0 in PSMCON

T_MAX= 85°C

V min

V max

% max

V min

V max

% max

AV_DDPower SupplyTrip Point Accuracy

DV_DDTrip Point Selection Range

T_MAX= 125°C

FourTrip Points Selectable inThis Range

Programmed viaTPD1–0 in PSMCON

T_MAX= 85C

DV_DDPower SupplyTrip Point Accuracy

T_MAX= 125C

WATCHDOGTIMER (WDT)

Timeout Period

0

2000

NineTimeout Periods inThis Range

Programmed via PRE3–0 inWDCON

ms min

ms max

MCU CORE CLOCK RATE

MCU Clock Rate²

Clock Rate Generated via On-Chip PLL

Programmable via CD2–0 Bits in

PLLCON SFR

98.3

kHz min

12.58

MHz max

START-UPTIME

At Power-On

300

3

ms typ

s typ

After External RESET in Normal Mode

AfterWDT Reset in Normal Mode

From Idle Mode

Controlled viaWDCON SFR

10

From Power-Down Mode

Oscillator Running

OSC_PD Bit = 0 in PLLCON SFR

Wake-Up with INT0 Interrupt

Wake-Up with SPI Interrupt

Wake-Up withTIC Interrupt

Wake-Up with External RESET

Oscillator Powered Down

Wake-Up with INT0 Interrupt

Wake-Up with SPI Interrupt

Wake-Up with External RESET

20

3

s typ

ms typ

OSC_PD Bit = 1 in PLLCON SFR

20

5

s typ

ms typ

FLASH/EE MEMORY RELIABILITY CHARACTERISTICS¹⁵

Endurance¹⁶

100,000

100

Cycles min

Years min

Data Retention¹⁷

–6–

REV. A

ADuC836

Parameter

ADuC836

Test Conditions/Comments

Unit

POWER REQUIREMENTS

Power SupplyVoltages

DV_DDand AV_DDCan Be Set Independently

AV_DD, 3V Nominal Operation

2.7

3.6

4.75

5.25

2.7

3.6

4.75

5.25

V min

V max

V min

V max

V min

V max

V min

V max

AV_DD, 5V Nominal Operation

DV_DD, 3V Nominal Operation

DV_DD, 5V Nominal Operation

5V POWER CONSUMPTION

Power Supply Currents Normal Mode^{18, 19}

DV_DDCurrent

DV_DD= 4.75V to 5.25V, AV_DD= 5.25V

4

Core CLK = 1.57 MHz

Core CLK = 12.58 MHz

mA max

mA typ

mA max

A max

DV_DDCurrent

13

16

180

AV_DDCurrent

Core CLK = 1.57 MHz or 12.58 MHz

T_MAX= 85°C; Osc. On,TIC On

T_MAX= 125°C; Osc. On,TIC On

T_MAX= 85°C; Osc. Off

T_MAX= 125°C; Osc. Off

T_MAX= 85°C; Osc. On or Osc. Off

T_MAX= 125°C; Osc. On or Osc. Off

Power Supply Currents Power-Down Mode^{18, 19}

DV_DDCurrent

AV_DDCurrent

53

100

30

80

1

A max

3

Typical Additional Power Supply Currents

Core CLK = 1.57 MHz

(AI_DDand DI_DD

PSM Peripheral

Primary ADC

Auxiliary ADC

DAC

)

50

1

500

150

400

A typ

mA typ

A typ

Dual Current Sources

3V POWER CONSUMPTION

Power Supply Currents Normal Mode^{18, 19}

DV_DDCurrent

DV_DD= 2.7V to 3.6V

2.3

8

10

180

Core CLK = 1.57 MHz

mA max

mA typ

mA max

DV_DDCurrent

Core CLK = 12.58 MHz

AV_DD= 5.25V, Core CLK = 1.57 MHz

or 12.58 MHz

Core CLK = 1.57 MHz or 12.58 MHz

T_MAX= 85°C; Osc. On,TIC On

T_MAX= 125°C; Osc. On,TIC On

Osc. Off

AV_DD= 5.25V;T_MAX= 85°C;

Osc. On or Osc. Off

AV_DD= 5.25V;T_MAX= 125°C;

Osc. On or Osc. Off

AV_DDCurrent

A max

Power Supply Currents Power-Down Mode^{18, 19}

DV_DDCurrent

20

40

10

1

A max

A typ

DV_DDCurrent

AV_DDCurrent

A max

3

REV. A

–7–

ADuC836

NOTES

¹Temperature range for ADuC836BS (MQFP package) is –40°C to +125°C.Temperature range for ADuC836BCP (CSP package) is –40°C to +85°C.

²These numbers are not production tested but are guaranteed by design and/or characterization data on production release.

³System Zero-Scale Calibration can remove this error.

⁴The primary ADC is factory calibrated at 25°C with AV_DD= DV_DD= 5V yielding this full-scale error of 10 V. If user power supply or temperature conditions are signiﬁcantly

different from these, an Internal Full-Scale Calibration will restore this error to 10 V. A system zero-scale and full-scale calibration will remove this error altogether.

⁵Gain Error Drift is a span drift.To calculate Full-Scale Error Drift, add the Offset Error Drift to the Gain Error Drift times the full-scale input.

⁶The auxiliary ADC is factory calibrated at 25°C with AV_DD= DV_DD= 5V yielding this full-scale error of –2.5 LSB. A system zero-scale and full-scale calibration

will remove this error altogether.

⁷DAC linearity and ac speciﬁcations are calculated using: reduced code range of 48 to 4095, 0 toV_REF; reduced code range of 100 to 3950, 0 toV_DD

.

⁸Gain Error is a measurement of the span error of the DAC.

⁹In general terms, the bipolar input voltage range to the primary ADC is given by Range_ADC= ±(V_REF2^RN)/125, where:

V_REF= REFIN(+) to REFIN(–) voltage andV_REF= 1.25V when internal ADCV_REFis selected. RN = decimal equivalent of RN2, RN1, RN0, e.g.,

V_REF= 2.5V and RN2, RN1, RN0 = 1, 1, 0 the Range_ADC= ±1.28V. In Unipolar mode, the effective range is 0V to 1.28V in our example.

¹⁰1.25V is used as the reference voltage to the auxiliary ADC when internalV_REFis selected via XREF0 and XREF1 bits in ADC0CON and ADC1CON, respectively.

¹¹In Bipolar mode, the auxiliary ADC can only be driven to a minimum of AGND – 30 mV as indicated by the auxiliary ADC absolute AIN voltage limits.The bipolar

range is still –V_REFto +V_REF; however, the negative voltage is limited to –30 mV.

¹²The ADuC836BCP (CSP package) has been qualiﬁed and tested with the base of the CSP package ﬂoating.

¹³Pins conﬁgured in SPI mode, pins conﬁgured as digital inputs during this test.

¹⁴Pins conﬁgured in I²C mode only.

¹⁵Flash/EE Memory Reliability Characteristics apply to both the Flash/EE program memory and Flash/EE data memory.

¹⁶Endurance is qualiﬁed to 100 Kcycles as per JEDEC Std. 22 method A117 and measured at –40°C, +25°C, +85°C, and +125°C.Typical endurance at 25°C is 700 Kcycles.

¹⁷Retention lifetime equivalent at junction temperature (T_J) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV will

derate with junction temperature as shown in Figure 16 in the Flash/EE Memory section.

¹⁸Power Supply current consumption is measured in Normal, Idle, and Power-Down modes under the following conditions:

Normal mode: Reset = 0.4V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, Core Executing internal software loop.

Idle mode: Reset = 0.4V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, PCON.0 = 1, Core Execution suspended in idle mode.

Power-Down mode: Reset = 0.4V, All P0 pins and P1.2–P1.7 pins = 0.4V, all other digital I/O pins are open circuit, Core Clk changed via CD bits in PLLCON,

PCON.1 = 1, Core Execution suspended in Power-Down mode, OSC turned on or off via OSC_PD bit (PLLCON.7) in PLLCON SFR.

¹⁹DV_DDpower supply current will increase typically by 3 mA (3V operation) and 10 mA (5V operation) during a Flash/EE memory program or erase cycle.

Speciﬁcations subject to change without notice.

–8–

REV. A

ADuC836

PIN CONFIGURATIONS

52-Lead MQFP

ABSOLUTE MAXIMUM RATINGS¹

(T_A= 25°C, unless otherwise noted.)

AV_DDto AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V

AV_DDto DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V

DV_DDto AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V

DV_DDto DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V

AGND to DGND². . . . . . . . . . . . . . . . . . . . . . –0.3V to +0.3V

AV_DDto DV_DD. . . . . . . . . . . . . . . . . . . . . . . . . . . . –2V to +5V

Analog InputVoltage to AGND³. . . . . . –0.3V to AV_DD+ 0.3V

Reference InputVoltage to AGND . . . . –0.3V to AV_DD+ 0.3V

AIN/REFIN Current (Indeﬁnite) . . . . . . . . . . . . . . . . . . 30 mA

Digital InputVoltage to DGND . . . . . . –0.3V to DV_DD+ 0.3V

Digital OutputVoltage to DGND . . . . . –0.3V to DV_DD+ 0.3V

OperatingTemperature Range . . . . . . . . . . . . –40°C to +125°C

StorageTemperature Range . . . . . . . . . . . . . . –65°C to +150°C

JunctionTemperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

_JAThermal Impedance (MQFP) . . . . . . . . . . . . . . . . . 90°C/W

_JAThermal Impedance (LFCSP Base Floating) . . . . . . 52°C/W

LeadTemperature, Soldering

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ꢍꢎꢏꢐꢑꢒꢓꢔ

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56-Lead LFCSP

ꢊꢏ

ꢉꢎ

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

�ꢀꢁꢂꢃꢂ

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ꢉꢋ

NOTES

¹Stresses above those listed under Absolute Maximum Ratings may cause permanent

damage to the device.This is a stress rating only; functional operation of the device

at these or any other conditions above those listed in the operational sections of this

speciﬁcation is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

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ꢖꢁꢗꢘꢂꢆꢗꢂꢙꢚꢛꢜꢝꢞ

²AGND and DGND are shorted internally on the ADuC836.

³Applies to P1.2 to P1.7 pins operating in analog or digital input modes.

ꢃꢉ

ꢋꢍ

ꢋꢌ

ꢃꢊ

ORDERING GUIDE

Package Description

Model

Temperature Range

Package Option

ADuC836BS

ADuC836BCP

EVAL-ADuC836QS

–40°C to +125°C

–40°C to +85°C

52-Lead Metric Quad Flat Package

56-Lead Lead Frame Chip Scale Package

QuickStart Development System

S-52

CP-56

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate

on the human body and test equipment and can discharge without detection. Although the ADuC836

features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high

energy electrostatic discharges.Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

REV. A

–9–

ADuC836

2

4

9

12

38

19 22

24 25

BUF

44 45 46 49 50 51 52

1

3

10 11

28 29 30 31 36

39

16 17 18

23

43

37

ADuC836

12-BIT

VOLTAGE

OUTPUT DAC

DAC

CONTROL

3

DAC

ADC

CONTROL

AND

AIN1

PRIMARY ADC

16-BIT

- ADC

BUF

AIN

MUX

PGA

AIN2

CALIBRATION

DUAL

16-BIT

- DAC

1

PWM0

PWM1

PWM

CONTROL

AIN3

AIN4

AIN5

MUX

AUXILIARY ADC

16-BIT

ADC CONTROL

AND

CALIBRATION

DUAL

16-BIT

PWM

AIN

MUX

2

- ADC

22 T0

23 T1

2304 BYTES

TEMP

SENSOR

BAND GAP

62 KBYTES PROGRAM/

FLASH/EE

USER RAM

REFERENCE

16-BIT

COUNTER

TIMERS

1

2

T2

WATCHDOG

TIMER

4 KBYTES DATA

FLASH/EE

T2EX

REFIN

REFIN

V

8052

REF

POWER SUPPLY

MONITOR

DETECT

MCU

CORE

2  DATA POINTERS

11-BIT STACK POINTER

PLL WITH PROG.

CLOCK DIVIDER

18

19

200A

INT0

INT1

200A

DOWNLOADER

DEBUGGER

WAKE-UP/

RTC TIMER

IEXC 1

IEXC 2

CURRENT

SOURCE

MUX

2

UART

SERIAL PORT

UART

TIMER

SPI/I C SERIAL

INTERFACE

OSC

POR

32

33

5

6

20 34

48

47

21 35

15

16 17

41

42

26

27

14

13

40

*PIN NUMBERS REFER TO THE 52-LEAD MQFP PACKAGE

SHADED AREAS REPRESENT THE NEW FEATURES OF THE ADuC836 OVER THE ADuC816

Figure 1. Detailed Block Diagram

PIN FUNCTION DESCRIPTIONS

Pin No. Pin No.

52-Lead 56-Lead

MQFP CSP

Mnemonic

Type* Description

1, 2

56, 1

P1.0/P1.1

I/O

P1.0 and P1.1 can function as digital inputs or digital outputs and have a pull-up

conﬁguration as described for Port 3. P1.0 and P1.1 have an increased current drive

sink capability of 10 mA.

P1.0/T2/PWM0

I/O

P1.0 and P1.1 also have various secondary functions as described below. P1.0 can be

used to provide a clock input toTimer 2.When enabled, Counter 2 is incremented

in response to a negative transition on theT2 input pin. If the PWM is enabled, the

PWM0 output will appear at this pin.

P1.1/T2EX/PWM1 I/O

P1.1 can also be used to provide a control input toTimer 2.When enabled, a PWM1

negative transition on theT2EX input pin will cause aTimer 2 capture or reload event.

If the PWM is enabled, the PWM1 output will appear at this pin.

3–4,

9–12

2–3,

11–14

P1.2–P1.7

I

Port 1.2 to Port 1.7 have no digital output driver; they can function as a digital input

for which 0 must be written to the port bit. As a digital input, these pins must be

driven high or low externally.These pins also have the following analog functionality:

The voltage output from the DAC or one or both current sources (200 µA or

2  200 µA) can be conﬁgured to appear at this pin.

P1.2/DAC/IEXC1 I/O

P1.3/AIN5/IEXC2 I/O

Auxiliary ADC input or one or both current sources can be conﬁgured at this pin.

–10–

REV. A

ADuC836

PIN FUNCTION DESCRIPTIONS (continued)

Pin No. Pin No.

52-Lead 56-Lead

MQFP CSP

Mnemonic

Type* Description

P1.4/AIN1

P1.5/AIN2

I

Primary ADC, Positive Analog Input

Primary ADC, Negative Analog Input

P1.6/AIN3

P1.7/AIN4/DAC

I

I/O

Auxiliary ADC Input or Muxed Primary ADC, Positive Analog Input

Auxiliary ADC Input or Muxed Primary ADC, Negative Analog Input.The voltage

output from the DAC can also be conﬁgured to appear at this pin.

5

4, 5

6, 7, 8

9

AV_DD

S

I

Analog SupplyVoltage, 3V or 5V

6

AGND

REFIN(–)

REFIN(+)

SS

Analog Ground. Ground reference pin for the analog circuitry.

Reference Input, NegativeTerminal

7

8

10

I

Reference Input, PositiveTerminal

13

14

15

I

Slave Select Input for the SPI Interface. A weak pull-up is present on this pin.

Master Input/Slave Output for the SPI Interface.A weak pull-up is present on this input pin.

16

MISO

I/O

I

17

RESET

Reset Input. A high level on this pin for 16 core clock cycles while the oscillator is

running resets the device.There is an internal weak pull-down and a Schmitt trigger

input stage on this pin.

16–19,

22–25

18–21,

24–27

P3.0–P3.7

I/O

P3.0–P3.7 are bidirectional port pins with internal pull-up resistors. Port 3 pins that

have 1s written to them are pulled high by the internal pull-up resistors, and in that

state can be used as inputs. As inputs, Port 3 pins being pulled externally low will

source current because of the internal pull-up resistors.When driving a 0-to-1 output

transition, a strong pull-up is active for two core clock periods of the instruction

cycle. Port 3 pins also have various secondary functions including:

Receiver Data for UART Serial Port

P3.0/RXD

P3.1/TXD

P3.2/INT0

P3.3/INT1

I/O

Transmitter Data for UART Serial Port

External Interrupt 0.This pin can also be used as a gate control input toTimer 0.

External Interrupt 1.This pin can also be used as a gate control input toTimer 1.

Timer/Counter 0 External Input. If the PWM is enabled, an external clock may be

input at this pin.

P3.4/T0/PWMCLK I/O

P3.5/T1

P3.6/WR

I/O

Timer/Counter 1 External Input

External Data MemoryWrite Strobe. Latches the data byte from Port 0 into an

external data memory.

P3.7/RD

I/O

External Data Memory Read Strobe. Enables the data from an external data memory

to Port 0.

20, 34, 48 22, 36, 51, DV_DD

S

Digital Supply, 3V or 5V

21, 35, 47 23, 37, 38, DGND

50

Digital Ground. Ground reference point for the digital circuitry.

26

SCLOCK

I/O

Serial Interface Clock for either the I²C or SPI Interface. As an input, this pin is a

Schmitt-triggered input, and a weak internal pull-up is present on this pin unless it is

outputting logic low.This pin can also be directly controlled in software as a digital

output pin.

27

MOSI/SDATA

I/O

Serial Data I/O for the I²C Interface or Master Output/Slave Input for the

SPI Interface. A weak internal pull-up is present on this pin unless it is outputting

logic low.This pin can also be directly controlled in software as a digital output pin.

28–31

36–39

30–33

39–42

P2.0–P2.7

(A8–A15)

(A16–A23)

Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s

written to them are pulled high by the internal pull-up resistors, and in that state can

be used as inputs. As inputs, Port 2 pins being pulled externally low will source current

because of the internal pull-up resistors.

Port 2 emits the high order address bytes during fetches from external program memory

and middle and high order address bytes during accesses to the 24-bit external data

memory space.

32

33

34

35

XTAL1

XTAL2

I

Input to the Crystal Oscillator Inverter

O

Output from the Crystal Oscillator Inverter. (See the Hardware Design Considerations

section for description.)

REV. A

–11–

ADuC836

PIN FUNCTION DESCRIPTIONS (continued)

Pin No. Pin No.

52-Lead 56-Lead

MQFP CSP

Mnemonic

Type* Description

40

43

EA

I/O

External Access Enable, Logic Input.When held high, this input enables the device to

fetch code from internal program memory locations 0000h to F7FFh.When held low,

this input enables the device to fetch all instructions from external program memory.

To determine the mode of code execution, i.e., internal or external, the EA pin is

sampled at the end of an external RESET assertion or as part of a device power cycle.

EA may also be used as an external emulation I/O pin, and therefore the voltage level

at this pin must not be changed during normal mode operation as it may cause an

emulation interrupt that will halt code execution.

41

42

44

45

PSEN

O

Program Store Enable, Logic Output.This output is a control signal that enables the

external program memory to the bus during external fetch operations. It is active every

six oscillator periods except during external data memory accesses.This pin remains

high during internal program execution. PSEN can also be used to enable Serial

Download mode when pulled low through a resistor at the end of an external RESET

assertion or as part of a device power cycle.

ALE

O

Address Latch Enable, Logic Output.This output is used to latch the low byte (and

page byte for 24-bit data address space accesses) of the address to external memory

during external code or data memory access cycles. It is activated every six oscillator

periods except during an external data memory access. It can be disabled by setting

the PCON.4 bit in the PCON SFR.

43–46

49–52

46–49

52–55

P0.0–P0.7

(AD0–AD3)

I/O

These pins are part of Port 0, which is an 8-bit, open-drain, bidirectional

I/O port. Port 0 pins that have 1s written to them ﬂoat and in that state can be used

(AD4–AD7)as high impedance inputs. An external pull-up resistor will be required

on P0 outputs to force a valid logic high level externally. Port 0 is also the multiplexed

low order address and data bus during accesses to external program or data memory.

In this application, it uses strong internal pull-ups when emitting 1s.

*I = Input, O = Output, S = Supply.

–12–

REV. A

ADuC836

MEMORY ORGANIZATION

The ADuC836 contains four different memory blocks:

Reset initializes the stack pointer to location 07H. Any call or push

pre-increments the SP before loading the stack.Therefore, loading

the stack starts from location 08H, which is also the ﬁrst register

(R0) of register bank 1.Thus, if one is going to use more than one

register bank, the stack pointer should be initialized to an area of

RAM not used for data storage.



62 Kbytes of On-Chip Flash/EE Program Memory



4 Kbytes of On-Chip Flash/EE Data Memory



256 bytes of General-Purpose RAM



2 Kbytes of Internal XRAM

7FH

(1) Flash/EE Program Memory

GENERAL-PURPOSE

AREA

The ADuC836 provides 62 Kbytes of Flash/EE program mem-

ory to run user code.The user can choose to run code from this

internal memory or run code from an external program memory.

30H

2FH

BANKS

SELECTED

BIT-ADDRESSABLE

VIA

If the user applies power or resets the device while the EA pin is

pulled low externally, the part will execute code from the external

program space; otherwise, if EA is pulled high externally, the part

defaults to code execution from its internal 62 Kbytes of Flash/EE

program memory.

(BIT ADDRESSES)

BITS IN PSW

20H

1FH

11

18H

17H

10

Unlike the ADuC816, where code execution can overﬂow from the

internal code space to external code space once the PC becomes

greater than 1FFFH, the ADuC836 does not support the rollover

from F7FFH in internal code space to F800H in external code

space. Instead, the 2048 bytes between F800H and FFFFH will

appear as NOP instructions to user code.

FOUR BANKS OF EIGHT

REGISTERS

10H

0FH

07H

R0–R7

01

00

08H

00H

RESET VALUE OF

STACK POINTER

Permanently embedded ﬁrmware allows code to be serially down-

loaded to the 62 Kbytes of internal code space via the UART serial

port while the device is in-circuit. No external hardware is required.

Figure 2. Lower 128 Bytes of Internal Data Memory

(4) Internal XRAM

The ADuC836 contains 2 Kbytes of on-chip extended data mem-

ory.This memory, although on-chip, is accessed via the MOVX

instruction.The 2 Kbytes of internal XRAM are mapped into the

bottom 2 Kbytes of the external address space if the CFG836.0

bit is set. Otherwise, access to the external data memory will occur

just like a standard 8051.

56 Kbytes of the program memory can be reprogrammed during

runtime; thus the code space can be upgraded in the ﬁeld using a

user deﬁned protocol or it can be used as a data memory.This

is discussed in more detail in the Flash/EE Memory section.

(2) Flash/EE Data Memory

4 Kbytes of Flash/EE Data Memory are available to the user and

can be accessed indirectly via a group of registers mapped into the

Special Function Register (SFR) area. Access to the Flash/EE Data

memory is discussed in detail in the Flash/EE Memory section.

Even with the CFG836.0 bit set, access to the external XRAM

will occur once the 24-bit DPTR is greater than 0007FFH.

FFFFFFH

(3) General-Purpose RAM

The general-purpose RAM is divided into two separate memories:

the upper and lower 128 bytes of RAM.The lower 128 bytes of

RAM can be accessed through direct or indirect addressing; the

upper 128 bytes of RAM can only be accessed through indirect

addressing as it shares the same address space as the SFR space,

which can only be accessed through direct addressing.

EXTERNAL

DATA

MEMORY

SPACE

(24-BIT

ADDRESS

SPACE)

EXTERNAL

DATA

MEMORY

SPACE

(24-BIT

ADDRESS

SPACE)

The lower 128 bytes of internal data memory are mapped as shown

in Figure 2.The lowest 32 bytes are grouped into four banks of

eight registers addressed as R0 through R7.The next 16 bytes

(128 bits), locations 20H through 2FH above the register banks,

form a block of directly addressable bit locations at bit addresses

00H through 7FH.The stack can be located anywhere in the inter-

nal memory address space, and the stack depth can be expanded

up to 2048 bytes.

000800H

0007FFH

2 KBYTES

ON-CHIP

XRAM

000000H

CFG836.0 = 0

CFG836.0 = 1

Figure 3. Internal and External XRAM

GENERAL NOTES PERTAININGTOTHIS DATA SHEET

1. SET implies a Logic 1 state and CLEARED implies a Logic 0 state, unless

otherwise stated.

2. SET and CLEARED also imply that the bit is set or automatically cleared by

the ADuC836 hardware, unless otherwise stated.

3. User software should not write 1s to reserved or unimplemented bits as they

may be used in future products.

4. Any pin numbers used throughout this data sheet refer to the 52-lead MQFP

package, unless otherwise stated.

REV. A

–13–

ADuC836

SPECIAL FUNCTION REGISTERS (SFRS)

When accessing the internal XRAM, the P0 and P2 port pins, as

well as the RD and WR strobes, will not be output as per a stan-

dard 8051 MOVX instruction.This allows the user to use these

port pins as standard I/O.

The SFR space is mapped into the upper 128 bytes of internal

data memory space and accessed by direct addressing only. It

provides an interface between the CPU and all on-chip periph-

erals. A block diagram showing the programming model of the

ADuC836 via the SFR area is shown in Figure 5.

The upper 1792 bytes of the internal XRAM can be conﬁgured

to be used as an extended 11-bit stack pointer. By default, the

stack will operate exactly like an 8052 in that it will roll over from

FFH to 00H in the general-purpose RAM. On the ADuC836

however, it is possible (by setting CFG836.7) to enable the 11-bit

extended stack pointer. In this case, the stack will roll over from

FFH in RAM to 0100H in XRAM.The 11-bit stack pointer is

visible in the SP and SPH SFRs.The SP SFR is located at 81H

as with a standard 8052.The SPH SFR is located at B7H.The

3 LSBs of this SFR contain the three extra bits necessary to

extend the 8-bit stack pointer into an 11-bit stack pointer.

4 KBYTE

62 KBYTE ELECTRICALLY

ELECTRICALLY

REPROGRAMMABLE

NONVOLATILE FLASH/EE

NONVOLATILE

PROGRAM MEMORY

FLASH/EE DATA

MEMORY

128-BYTE

SPECIAL

FUNCTION

REGISTER

AREA

8051

COMPATIBLE

CORE

DUAL - ADCs

OTHER ON-CHIP

PERIPHERALS

07FFH

256 BYTES RAM

2K XRAM

TEMP SENSOR

CURRENT SOURCES

12-BIT DAC

SERIAL I/O

WDT, PSM

TIC, PLL

UPPER 1792

BYTES OF

ON-CHIP XRAM

(DATA + STACK

FOR EXSP = 1,

DATA ONLY

Figure 5. Programming Model

All registers, except the Program Counter (PC) and the four

general-purpose register banks, reside in the SFR area.The SFR

registers include control, conﬁguration, and data registers that

provide an interface between the CPU and all on-chip peripherals.

FOR EXSP = 0)

CFG836.7 = 1

CFG836.7 = 0

FFH

100H

00H

Accumulator SFR (ACC)

256 BYTES OF

ON-CHIP DATA

RAM

(DATA +

STACK)

LOWER 256

BYTES OF

ON-CHIP XRAM

(DATA ONLY)

ACC is the Accumulator Register, which is used for math

operations including addition, subtraction, integer multiplication,

and division, and Boolean bit manipulations.The mnemonics for

accumulator-speciﬁc instructions, refer to the Accumulator as A.

00H

B SFR (B)

Figure 4. Extended Stack Pointer Operation

The B Register is used with the ACC for multiplication and

division operations. For other instructions, it can be treated as a

general-purpose scratch pad register.

External Data Memory (External XRAM)

Just like a standard 8051 compatible core, the ADuC836 can

access external data memory using a MOVX instruction.The

MOVX instruction automatically outputs the various control

strobes required to access the data memory.

Data Pointer (DPTR)

The Data Pointer is made up of three 8-bit registers, named DPP

(page byte), DPH (high byte), and DPL (low byte).These are

used to provide memory addresses for internal and external code

access and external data access. It may be manipulated as a 16-bit

register (DPTR = DPH, DPL), although INC DPTR instructions

will automatically carry over to DPP, or as three independent 8-bit

registers (DPP, DPH, DPL).

The ADuC836, however, can access up to 16 Mbytes of external

data memory.This is an enhancement of the 64 Kbytes external

data memory space available on a standard 8051 compatible core.

The external data memory is discussed in more detail in the

ADuC836 Hardware Design Considerations section.

The ADuC836 supports dual data pointers. For more information,

refer to the Dual Data Pointer section.

–14–

REV. A

ADuC836

Stack Pointer (SP and SPH)

Table II. PCON SFR Bit Designations

The SP SFR is the stack pointer and is used to hold an internal

RAM address that is called the “top of the stack.”The SP Register

is incremented before data is stored, during PUSH and CALL

executions.While the Stack may reside anywhere in on-chip RAM,

the SP Register is initialized to 07H after a reset.This causes the

stack to begin at location 08H.

Bit

Name

Description

7

6

5

4

3

2

1

0

SMOD

SERIPD

INT0PD

ALEOFF

GF1

GF0

PD

Double UART Baud Rate

SPI Power-Down Interrupt Enable

INT0 Power-Down Interrupt Enable

Disable ALE Output

General-Purpose Flag Bit

Power-Down Mode Enable

Idle Mode Enable

As mentioned earlier, the ADuC836 offers an extended 11-bit

stack pointer. The three extra bits that make up the 11-bit stack

pointer are the 3 LSBs of the SPH byte located at B7H.

IDL

Program StatusWord (PSW)

The PSW SFR contains several bits reﬂecting the current status

of the CPU as detailed inTable I.

ADuC836 CONFIGURATION SFR (CFG836)

The CFG836 SFR contains the necessary bits to conﬁgure the

internal XRAM and the extended SP. By default it conﬁgures

the user into 8051 mode, i.e., extended SP is disabled, internal

XRAM is disabled.

SFR Address

D0H

00H

Yes

Power-On DefaultValue

Bit Addressable

SFR Address

Power-On DefaultValue

Bit Addressable

AFH

00H

No

Table I. PSW SFR Bit Designations

Bit

Name

Description

7

6

5

4

3

CY

AC

F0

RS1

RS0

Carry Flag

Table III. CFG836 SFR Bit Designations

Auxiliary Carry Flag

General-Purpose Flag

Register Bank Select Bits

Bit Name

Description

7

EXSP

Extended SP Enable. If this bit is set, the

stack will roll over from SPH/SP = 00FFH to

0100H. If this bit is clear, the SPH SFR will

be disabled and the stack will roll over from

SP = FFH to SP = 00H.

RS1

0

RS0

0

1

Selected Bank

0

1

2

3

1

0

1

6

5

4

3

2

1

0

–––

Reserved for Future Use

2

1

0

OV

F1

P

Overﬂow Flag

General-Purpose Flag

Parity Bit

Power Control SFR (PCON)

The PCON SFR contains bits for power saving options and

general-purpose status ﬂags, as shown inTable II.

XRAMEN XRAM Enable Bit. If this bit is set, the in-

ternal XRAM will be mapped into the lower

2 Kbytes of the external address space. If this

bit is clear, the internal XRAM will not be

accessible and the external data memory will

be mapped into the lower 2 Kbytes of external

data memory (see Figure 3).

TheTIC (Wake-Up/RTC timer) can be used to accurately wake

up the ADuC836 from power-down at regular intervals.To use

theTIC to wake up the ADuC836 from power-down, the OSC_PD

bit in the PLLCON SFR must be clear and theTIC must be

enabled.

SFR Address

Power-On DefaultValue

Bit Addressable

87H

00H

No

REV. A

–15–

ADuC836

COMPLETE SFR MAP

not implemented, i.e., no register exists at this location. If an

unoccupied location is read, an unspeciﬁed value is returned.

SFR locations that are reserved for future use are shaded

(RESERVED) and should not be accessed by user software.

Figure 6 shows a full SFR memory map and the SFR con-

tents after RESET. NOT USED indicates unoccupied SFR

locations. Unoccupied locations in the SFR address space are

SPICON

F8H

DACL

FBH

DACH

FCH

DACCON

FDH

00H

ISPI

FFH

WCOL

FEH

SPE

FDH

SPIM

FCH

CPOL

FBH

CPHA

FAH

SPR1

F9H

SPR0

F8H

BITS

RESERVED RESERVED

SPIDAT

0

1

0

04H

00H

B

RESERVED RESERVED NOT USED RESERVED RESERVED RESERVED

BITS

F7H

F6H

F5H

F4H

F3H

F2H

F1H

I2CTX

F0H

I2CI

F0H

I2CCON

F7H

00H

GN0M ¹

GN0H ¹

GN1L ¹

GN1H¹

I2CM

EBH

I2CRS

MDO

MDE

EEH

MCO

MDI

ECH

RESERVED

RESERVED RESERVED

EFH

EDH

EAH

0

E9H

E1H

D9H

E8H

E0H

D8H

E8H

EAH

OF0M

EBH

OF0H

ECH

OF1L

EDH

OF1H

00H

55H

53H

9AH

59H

ACC

RESERVED

BITS

E7H

E6H

E5H

E4H

E3H

E2H

0

E0H

ADCSTAT

E2H

ADC0M

E3H

ADC0H

E4H

ADC1L

E5H

ADC1H

00H

80H

00H

80H

PSMCON

ERR0

DBH

RDY0

DFH

RDY1

DEH

CAL

DDH

NOXREF

ERR1

RESERVED

0

DCH

0

DAH

0

D8H

PSW

D0H

DAH

DBH

DCH

DDH

DFH

00H

DEH

ADCMODE ADC0CON ADC1CON

SF

ICON

PLLCON

CY

D7H

AC

D6H

F0

D5H

RSI

D4H

RS0

D3H

OV

D2H

FI

D1H

P

RESERVED

0

D0H

D1H

D2H

D3H

D4H

TL2

D5H

TH2

D7H

00H

07H

00H

2H

00H

45H

00H

03H

T2CON

RCAP2L

RCAP2H

TF2

CFH

EXF2

CEH

RCLK

CDH

TCLK

CCH

EXEN2

CBH

TR2

CAH

CNT2

C9H

CAP2

C8H

RESERVED

RESERVED RESERVED

0

C8H

C0H

CAH

CBH

CCH

CDH

00H

WDCON

CHIPID

EADRL

EADRH

PRE3

PRE2

C6H

PRE1

C5H

PRE0

C4H

WDIR

C3H

WDS

C2H

WDE

C1H

WDWR

C0H 0

RESERVED

ECON

RESERVED RESERVED RESERVED

C7H

0

1

0

10H

C2H

C6H

EDATA3

00H

C7H

EDATA4

00H

IP

P3

IE

EDATA1

BCH

EDATA2

BDH

PADC

BEH

PT2

BDH

PS

BCH

PT1

BBH

PX1

BAH

PT0

B9H

PX0

B8H

RESERVED RESERVED

BFH

0

1

0

1

0

1

0

1

B8H

B0H

B9H

BEH

BFH

SPH

B7H

00H

PWM0L

PWM0H

PWM1L

00H

PWM1H

B4H

00H

TXD

B1H

RXD

B0H

T1

B5H

T0

B4H

WR

B6H

INT1

B3H

INT0

B2H

RD

B7H

RESERVED

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

FFH B1H

00H B2H

00H B3H

00H

IEIP2

PWMCON

CFG836

AFH

EA

EADC

AEH

ET2

ES

ET1

EX1

ET0

EX0

RESERVED RESERVED RESERVED RESERVED

AFH

A7H

ADH

A5H

ACH

A4H

ABH

A3H

AAH

A2H

A9H

A1H

A8H

A0H

AEH

00H

A8H

A0H

A9H

TIMECON

00H

FFH

A0H

P2

HTHSEC²

A2H

SEC ²

A3H

MIN ²

A4H

HOUR ²

A5H

INTVAL

DPCON

A7H

BITS

A6H

00H

A1H

A6H

00H

SCON

98H

SBUF

T3CON

T3FD

9DH

SM0

SM1

9EH

SM2

REN

TB8

RB8

T1

99H

R1

98H

RESERVED

RESERVED RESERVED NOT USED

9EH

00H

9FH

97H

9DH

95H

9CH

94H

9BH

93H

9AH

92H

00H

99H

00H

P1

T2EX

91H

T2

90H

RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED

96H

90H

FFH

TCON

TMOD

89H

TL0

8AH

DPL

82H

TL1

8BH

DPH

83H

TH0

8CH

DPP

84H

TH1

8DH

00H

TF1

TR1

8EH

TF0

TR0

IE1

IT1

IE0

IT0

RESERVED RESERVED

PCON

8FH

87H

8DH

85H

8CH

84H

8BH

83H

8AH

82H

89H

81H

88H

80H

88H

00H

P0

SP

RESERVED RESERVED

86H

80H

81H

87H

FFH

07H

00H

NOTES

¹CALIBRATION COEFFICIENTS ARE PRECONFIGURED AT POWER-UP TO FACTORY CALIBRATED VALUES.

²THESE SFRs MAINTAIN THEIR PRERESET VALUES AFTER A RESET IF TIMECON.0 = 1.

SFR MAP KEY:

THESE BITS ARE CONTAINED IN THIS BYTE.

TCON

MNEMONIC

BIT MNEMONIC

BIT BIT ADDRESS

IE0

89H

IT0

88H

0

88H

00H

RESET DEFAULT VALUE

RESET DEFAULT

BIT VALUE

SFR ADDRESS

SFR NOTE:

SFRs WHOSE ADDRESSES END IN 0H OR 8H ARE BIT ADDRESSABLE.

Figure 6. Special Function Register Locations andTheir Reset Default Values

–16–

REV. A

ADuC836

ADC SFR INTERFACE

Both ADCs are controlled and conﬁgured via a number of SFRs that are summarized here and described in more detail in the

following sections.

ADCSTAT

ADC Status Register. Holds general status of the

primary and auxiliary ADCs.

ADC0M/H

ADC1L/H

OF0M/H

OF1L/H

Primary ADC 16-bit conversion result is held in

these two 8-bit registers.

ADCMODE ADC Mode Register. Controls general modes of

operation for primary and auxiliary ADCs

Auxiliary ADC 16-bit conversion result is held in

these two 8-bit registers.

ADC0CON Primary ADC Control Register. Controls speciﬁc

conﬁguration of primary ADC.

Primary ADC 16-bit Offset Calibration Coefﬁcient

is held in these two 8-bit registers.

ADC1CON Auxiliary ADC Control Register. Controls

speciﬁc conﬁguration of auxiliary ADC.

Auxiliary ADC 16-bit Offset Calibration Coefﬁcient

is held in these two 8-bit registers.

SF

Sinc Filter Register. Conﬁgures the decimation

factor for the Sinc³ﬁlter and thus the primary

and auxiliary ADC update rates.

GN0M/H

GN1L/H

Primary ADC 16-bit Gain Calibration Coefﬁcient

is held in these two 8-bit registers.

Auxiliary ADC 16-bit Gain Calibration Coefﬁcient

is held in these two 8-bit registers.

ICON

Current Source Control Register. Allows the user

to control of the various on-chip current source

options.

ADCSTAT (ADC Status Register)

This SFR reﬂects the status of both ADCs including data ready, calibration, and various (ADC related) error and warning conditions

such as reference detect and conversion overﬂow/underﬂow ﬂags.

SFR Address

Power-On DefaultValue

Bit Addressable

D8H

00H

Yes

Table IV. ADCSTAT SFR Bit Designations

Bit

Name

Description

7

RDY0

Ready Bit for Primary ADC.

Set by hardware on completion of ADC conversion or calibration cycle.

Cleared directly by the user or indirectly by writing to the mode bits to start another primary ADC conversion

or calibration.The primary ADC is inhibited from writing further results to its data or calibration registers

until the RDY0 bit is cleared.

6

5

RDY1

CAL

Ready Bit for Auxiliary ADC. Same deﬁnition as RDY0 referred to the auxiliary ADC.

Calibration Status Bit.

Set by hardware on completion of calibration.

Cleared indirectly by a write to the mode bits to start another ADC conversion or calibration.

4

3

NOXREF

ERR0

No External Reference Bit (only active if primary or auxiliary ADC is active).

Set to indicate that one or both of the REFIN pins is ﬂoating or the applied voltage is below a speciﬁed threshold.

When set, conversion results are clamped to all ones, if using external reference.

Cleared to indicate validV_REF

.

Primary ADC Error Bit.

Set by hardware to indicate that the result written to the primary ADC data registers has been clamped to all

zeros or all ones. After a calibration, this bit also ﬂags error conditions that caused the calibration registers not

to be written.

Cleared by a write to the mode bits to initiate a conversion or calibration.

2

1

0

ERR1

–––

Auxiliary ADC Error Bit. Same deﬁnition as ERR0 referred to the auxiliary ADC.

Reserved for Future Use

–––

Reserved for Future Use

REV. A

–17–

ADuC836

ADCMODE (ADC Mode Register)

Used to control the operational mode of both ADCs.

SFR Address

Power-On DefaultValue

Bit Addressable

D1H

00H

No

TableV. ADCMODE SFR Bit Designations

Bit

7

Name

–––

Description

Reserved for Future Use

6

–––

5

ADC0EN Primary ADC Enable.

Set by the user to enable the primary ADC and place it in the mode selected in MD2–MD0, below.

Cleared by the user to place the primary ADC in power-down mode.

4

ADC1EN Auxiliary ADC Enable.

Set by the user to enable the auxiliary ADC and place it in the mode selected in MD2–MD0, below.

Cleared by the user to place the auxiliary ADC in power-down mode.

3

2

1

0

–––

Reserved for Future Use

MD2

MD1

MD0

Primary and Auxiliary ADC Mode bits.

These bits select the operational mode of the enabled ADC as follows:

MD2

0

MD1

0

MD0

0

1

ADC Power-Down Mode (Power-On Default)

Idle Mode.The ADC ﬁlter and modulator are held in a reset state although the

modulator clocks are still provided.

0

1

0

Single Conversion Mode. A single conversion is performed on the enabled ADC.

On completion of the conversion, the ADC data registers (ADC0H/M and/or ADC1H/L)

are updated, the relevant ﬂags in the ADCSTAT SFR are written, and power-down is

re-entered with the MD2–MD0 accordingly being written to 000.

Continuous Conversion.The ADC data registers are regularly updated at the selected

update rate (see SF Register).

Internal Zero-Scale Calibration. Internal short automatically connected to the enabled

ADC input(s).

Internal Full-Scale Calibration. Internal or externalV_REF(as determined by XREF0

and XREF1 bits in ADC0/1CON) is automatically connected to the enabled ADC

input(s) for this calibration.

0

1

0

1

0

1

0

1

System Zero-Scale Calibration. User should connect system zero-scale input to the

enabled ADC input(s) as selected by CH1/CH0 and ACH1/ACH0 bits in the

ADC0/1CON Register.

System Full-Scale Calibration. User should connect system full-scale input to the

enabled ADC input(s) as selected by the CH1/CH0 and ACH1/ACH0 bits in the

ADC0/1CON Register.

NOTES

1. Any change to the MD bits will immediately reset both ADCs. A write to the MD2–0 bits with no change is also treated as a reset. (See exception to this in Note 3.)

2. If ADC0CON is written when ADC0EN = 1, or if ADC0EN is changed from 0 to 1, then both ADCs are also immediately reset. In other words, the primary ADC is

given priority over the auxiliary ADC, and any change requested on the primary ADC is immediately responded to.

3. On the other hand, if ADC1CON is written or if ADC1EN is changed from 0 to 1, only the auxiliary ADC is reset. For example, if the primary ADC is continuously converting

when the auxiliary ADC change or enable occurs, the primary ADC continues undisturbed. Rather than allow the auxiliary ADC to operate with a phase difference from

the primary ADC, the auxiliary ADC will fall into step with the outputs of the primary ADC.The result is that the ﬁrst conversion time for the auxiliary ADC will be

delayed up to three outputs while the auxiliary ADC update rate is synchronized to the primary ADC.

4. Once ADCMODE has been written with a calibration mode, the RDY0/1 bits (ADCSTAT) are immediately reset and the calibration commences. On completion, the appropriate

calibration registers are written, the relevant bits in ADCSTAT are written, and the MD2–0 bits are reset to 000 to indicate the ADC is back in Power-Down mode.

5. Any calibration request of the auxiliary ADC while the temperature sensor is selected will fail to complete. Although the RDY1 bit will be set at the end of the calibration

cycle, no update of the calibration SFRs will take place and the ERR1 bit will be set.

6. Calibrations are performed at maximum SF (see SF SFR) value, guaranteeing optimum calibration operation.

–18–

REV. A

ADuC836

ADC0CON (Primary ADC Control Register) and ADC1CON (Auxiliary ADC Control Register)

The ADC0CON and ADC1CON SFRs are used to conﬁgure the primary and auxiliary ADC for reference and channel selection,

unipolar or bipolar coding and, in the case of the primary ADC, range (the auxiliary ADC operates on a ﬁxed input range of ±V_REF).

ADC0CON

SFR Address

Power-On DefaultValue 07H

Bit Addressable

Primary ADC Control SFR

D2H

ADC1CON

SFR Address

Power-On DefaultValue

Bit Addressable

Auxiliary ADC Control SFR

D3H

00H

No

TableVI. ADC0CON SFR Bit Designations

Bit

Name

Description

7

6

–––

XREF0

Reserved for Future Use

Primary ADC External Reference Select Bit.

Set by user to enable the primary ADC to use the external reference via REFIN(+)/REFIN(–).

Cleared by user to enable the primary ADC to use the internal band gap reference (V_REF= 1.25V).

5

4

CH1

CH0

Primary ADC Channel Selection Bits.

Written by the user to select the differential input pairs used by the primary ADC as follows:

CH1

CH0

Positive Input

AIN1

AIN3

AIN2

AIN3

Negative Input

AIN2

AIN4

AIN2 (Internal Short)

AIN2

0

1

0

1

0

1

3

UNI0

Primary ADC Unipolar Bit.

Set by user to enable unipolar coding, i.e., zero differential input will result in 000000H output.

Cleared by user to enable bipolar coding, i.e., zero differential input will result in 800000H output.

2

1

0

RN2

RN1

RN0

Primary ADC Range Bits.

Written by the user to select the primary ADC input range as follows:

RN2

RN1

RN0

Selected Primary ADC Input Range (V_REF= 2.5 V)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

±20 mV

±40 mV

±80 mV

±160 mV

±320 mV

±640 mV

±1.28 V

±2.56 V

(0 mV–20 mV in Unipolar Mode)

(0 mV–40 mV in Unipolar Mode)

(0 mV–80 mV in Unipolar Mode)

(0 mV–160 mV in Unipolar Mode)

(0 mV–320 mV in Unipolar Mode)

(0 mV–640 mV in Unipolar Mode)

(0V–1.28V in Unipolar Mode)

(0V–2.56V in Unipolar Mode)

TableVII. ADC1CON SFR Bit Designations

Bit

Name

Description

7

6

–––

XREF1

Reserved for Future Use

Auxiliary ADC External Reference Bit.

Set by user to enable the auxiliary ADC to use the external reference via REFIN(+)/REFIN(–).

Cleared by user to enable the auxiliary ADC to use the internal band gap reference.

5

4

ACH1

ACH0

Auxiliary ADC Channel Selection Bits.

Written by the user to select the single-ended input pins used to drive the auxiliary ADC as follows:

ACH1 ACH0 Positive Input

Negative Input

0

1

0

1

0

1

AIN3

AIN4

Temp Sensor

AIN5

AGND

AGND (Temp Sensor routed to the ADC input)

AGND

3

UNI1

Auxiliary ADC Unipolar Bit.

Set by user to enable unipolar coding, i.e., zero input will result in 0000H output.

Cleared by user to enable bipolar coding, i.e., zero input will result in 8000H output.

2

1

0

–––

Reserved for Future Use

NOTES

1.When the temperature sensor is selected, user code must select internal reference via XREF1 bit above and clear the UNI1 bit (ADC1CON.3) to select bipolar coding.

2.The temperature sensor is factory calibrated to yield conversion results 8000H at 0°C.

3. A +1°C change in temperature will result in a +1 LSB change in the ADC1H Register ADC conversion result.

REV. A

–19–

ADuC836

ADC0H/ADC0M (Primary ADC Conversion Result Registers)

These two 8-bit registers hold the 16-bit conversion result from the primary ADC.

SFR Address

ADC0H

ADC0M

00H

High Data Byte

DBH

DAH

Middle Data Byte

ADC0H, ADC0M

Power-On DefaultValue

Bit Addressable

No

ADC1H/ADC1L (Auxiliary ADC Conversion Result Registers)

These two 8-bit registers hold the 16-bit conversion result from the auxiliary ADC.

SFR Address

ADC1H

ADC1L

00H

High Data Byte

Low Data Byte

ADC1H, ADC1L

DDH

DCH

Power-On DefaultValue

Bit Addressable

No

OF0H/OF0M (Primary ADC Offset Calibration Registers*)

These two 8-bit registers hold the 16-bit offset calibration coefﬁcient for the primary ADC.These registers are conﬁgured at power-on

with a factory default value of 800000H. However, these bytes will be automatically overwritten if an internal or system zero-scale

calibration of the primary ADC is initiated by the user via MD2–0 bits in the ADCMODE Register.

SFR Address

OF0H

OF0M

80000H

No

Primary ADC Offset Coefﬁcient High Byte

Primary ADC Offset Coefﬁcient Middle Byte

OF0H, OF0M respectively

E3H

E2H

Power-On DefaultValue

Bit Addressable

OF0H, OF0M

OF1H/OF1L (Auxiliary ADC Offset Calibration Registers*)

These two 8-bit registers hold the 16-bit offset calibration coefﬁcient for the auxiliary ADC.These registers are conﬁgured at power-on

with a factory default value of 8000H. However, these bytes will be automatically overwritten if an internal or system zero-scale calibration

of the auxiliary ADC is initiated by the user via the MD2–0 bits in the ADCMODE Register.

SFR Address

OF1H

OF1L

8000H

No

Auxiliary ADC Offset Coefﬁcient High Byte

Auxiliary ADC Offset Coefﬁcient Low Byte

OF1H and OF1L, respectively

OF1H, OF1L

E5H

E4H

Power-On DefaultValue

Bit Addressable

GN0H/GN0M (Primary ADC Gain Calibration Registers*)

These two 8-bit registers hold the 16-bit gain calibration coefﬁcient for the primary ADC.These registers are conﬁgured at power-on

with a factory-calculated internal full-scale calibration coefﬁcient. Every device will have an individual coefﬁcient. However, these bytes

will be automatically overwritten if an internal or system full-scale calibration of the primary ADC is initiated by the user via MD2–0

bits in the ADCMODE Register.

SFR Address

GN0H

GN0M

Primary ADC Gain Coefﬁcient High Byte

Primary ADC Gain Coefﬁcient Middle Byte

Conﬁgured at Factory FinalTest; See Notes above.

GN0H, GN0M

EBH

EAH

Power-On DefaultValue

Bit Addressable

No

GN1H/GN1L (Auxiliary ADC Gain Calibration Registers*)

These two 8-bit registers hold the 16-bit gain calibration coefﬁcient for the auxiliary ADC.These registers are conﬁgured at power-on

with a factory-calculated internal full-scale calibration coefﬁcient. Every device will have an individual coefﬁcient. However, these bytes

will be automatically overwritten if an internal or system full-scale calibration of the auxiliary ADC is initiated by the user via MD2–0

bits in the ADCMODE Register.

SFR Address

GN1H

GN1L

Auxiliary ADC Gain Coefﬁcient High Byte

Auxiliary ADC Gain Coefﬁcient Low Byte

Conﬁgured at Factory FinalTest; see notes above.

GN1H, GN1L

EDH

ECH

Power-On DefaultValue

Bit Addressable

No

*These registers can be overwritten by user software only if Mode bits MD0–2 (ADCMODE SFR) are zero.

–20–

REV. A

ADuC836

SF (Sinc Filter Register)

value for the SF Register is 45H, resulting in a default ADC update

rate of just under 20 Hz. Both ADC inputs are chopped to mini-

mize offset errors, which means that the settling time for a single

conversion, or the time to a ﬁrst conversion result in Continuous

Conversion mode, is 2  t_ADC. As mentioned earlier, all calibra-

tion cycles will be carried out automatically with a maximum, i.e.,

FFH, SF value to ensure optimum calibration performance. Once

a calibration cycle has completed, the value in the SF Register will

be that programmed by user software.

The number in this register sets the decimation factor and thus

the output update rate for the primary and auxiliary ADCs.This

SFR cannot be written by user software while either ADC is active.

The update rate applies to both primary and auxiliary ADCs and

is calculated as follows:

1

3

1

f_ADC

=

×

× f_MO

8 × SF

where:

f

_ADC= ADC Output Update Rate

TableVIII. SF SFR Bit Designations

f_MOD= Modulator Clock Frequency = 32.768 kHz

SF(dec)

SF(hex)

f_ADC(Hz)

t_ADC(ms)

SF = DecimalValue of SF Register

13

69

255

0D

45

FF

105.3

19.79

5.35

9.52

50.34

186.77

The allowable range for SF is 0DH to FFH. Examples of SF

values and corresponding conversion update rates (f_ADC) and con-

version times (t_ADC) are shown inTableVIII.The power-on default

ICON (Current Sources Control Register)

The icon SFR is used to control and conﬁgure the various excitation and burnout current source options available on-chip.

SFR Address

Power-On DefaultValue

Bit Addressable

D5H

00H

No

Table IX. ICON SFR Bit Designations

Bit

7

Name

–––

Description

Reserved for Future Use

6

BO

Burnout Current Enable Bit.

Set by user to enable both transducer burnout current sources in the primary ADC signal paths.

Cleared by the user to disable both transducer burnout current sources.

5

4

3

ADC1IC

ADC0IC

I2PIN*

Auxiliary ADC Current Correction Bit. Set by user to allow scaling of the auxiliary ADC by an internal current

source calibration word.

Primary ADC Current Correction Bit.

Set by user to allow scaling of the primary ADC by an internal current source calibration word.

Current Source-2 Pin Select Bit.

Set by user to enable current source-2 (200 A) to external Pin 3 (P1.2/DAC/IEXC1).

Cleared by user to enable current source-2 (200 A) to external Pin 4 (P1.3/AIN5/IEXC2).

2

1

0

I1PIN*

I2EN

Current Source-1 Pin Select Bit.

Set by user to enable current source-1 (200 A) to external Pin 4 (P1.3/AIN5/IEXC2).

Cleared by user to enable current source-1 (200 A) to external Pin 3 (P1.2/DAC/IEXC1).

Current Source-2 Enable Bit.

Set by user to turn on excitation current source-2 (200 A).

Cleared by user to turn off excitation current source-2 (200 A).

I1EN

Current Source-1 Enable Bit.

Set by user to turn on excitation current source-1 (200 A).

Cleared by user to turn off excitation current source-1 (200 A).

*Both current sources can be enabled to the same external pin, yielding a 400 A current source.

REV. A

–21–

ADuC836

PRIMARY AND AUXILIARY ADC NOISE PERFORMANCE

Tables X, XI, and XII show the output rms noise in mV and output

peak-to-peak resolution in bits (rounded to the nearest 0.5 LSB)

for some typical output update rates on both the primary and

auxiliary ADCs.The numbers are typical and are generated at a

differential input voltage of 0V.The output update rate is selected

via the Sinc Filter (SF) SFR. It is important to note that the

peak-to-peak resolution ﬁgures represent the resolution for which

there will be no code ﬂicker within a six-sigma limit.

The QuickStart Development system PC software comes com-

plete with an ADC noise evaluation tool.This tool can be easily

used with the evaluation board to see these ﬁgures from silicon.

Table X. Primary ADC,Typical Output RMS Noise (V)

Typical Output RMS Noise vs. Input Range and Update Rate; Output RMS Noise in V

Input Range

160 mV

SF

Word

Data Update

Rate (Hz)

20 mV

40 mV

80 mV

320 mV

640 mV

1.28V 2.56 V

13

69

255

105.3

19.79

5.35

1.50

0.60

0.35

1.50

0.65

0.35

1.60

0.65

0.37

1.75

0.65

0.37

3.50

0.65

0.37

4.50

0.95

0.51

6.70

1.40

0.82

11.75

2.30

1.25

Table XI. Primary ADC, Peak-to-Peak Resolution (Bits)

Peak-to-Peak Resolution vs. Input Range and Update Rate; Peak-to-Peak Resolution in Bits

Input Range

160 mV

SF

Word

Data Update

Rate (Hz)

20 mV

40 mV

80 mV

320 mV

640 mV

1.28V 2.56V

13

69

255

105.3

19.79

5.35

12

13.5

14

13

14

15

14

15

16

15

16

15

16

15.5

16

Typical RMS Resolution vs. Input Range and Update Rate: RMS Resolution in Bits*

Input Range

160 mV

SF

Word

Data Update

Rate (Hz)

20 mV

40 mV

80 mV

320 mV

640 mV

1.28V 2.56V

13

69

255

105.3

19.79

5.35

14.7

16

15.7

16

*Based on a six-sigma limit, the rms resolution is 2.7 bits greater than the peak-to-peak resolution.

Table XII. Auxiliary ADC

Typical Output RMS Noise vs. Update Rate*

Output RMS Noise in V

Peak-to-Peak Resolution vs. Update Rate¹

Peak-to-Peak Resolution in Bits

SF

Word

Data Update

ate (Hz)

Input Range

2.5V

SF

Word

Data Update

Rate (Hz)

Input Range

2.5V

R

13

69

255

105.3

19.79

5.35

10.75

2.00

1.15

13

69

255

105.3

19.79

5.35

16²

16

*ADC converting in Bipolar mode

NOTES

¹ADC converting in Bipolar mode

²In Unipolar mode, peak-to-peak resolution at 105 Hz is 15 bits.

–22–

REV. A

ADuC836

PRIMARY AND AUXILIARY ADC CIRCUIT DESCRIPTION

Overview

allowing R/C ﬁltering (for noise rejection or RFI reduction) to be

placed on the analog inputs if required. On-chip burnout currents

can also be turned on.These currents can be used to check that

a transducer on the selected channel is still operational before

attempting to take measurements.

The ADuC836 incorporates two independent - ADCs (primary

and auxiliary) with on-chip digital ﬁltering intended for the mea-

surement of wide dynamic range, low frequency signals such as

those in weigh-scale, strain gage, pressure transducer, or tempera-

ture measurement applications.

The ADC employs a - conversion technique to realize up to

16 bits of no missing codes performance.The - modulator

converts the sampled input signal into a digital pulse train whose

duty cycle contains the digital information. A Sinc³programmable

low-pass ﬁlter is then employed to decimate the modulator output

data stream to give a valid data conversion result at programmable

output rates from 5.35 Hz (186.77 ms) to 105.03 Hz (9.52 ms). A

chopping scheme is also employed to minimize ADC offset errors.

A block diagram of the primary ADC is shown in Figure 7.

Primary ADC

This ADC is intended to convert the primary sensor input.The

input is buffered and can be programmed for one of eight input

ranges from ±20 mV to ±2.56V being driven from one of three

differential input channel options AIN1/2, AIN3/4, or AIN3/2.

The input channel is internally buffered, allowing the part to

handle signiﬁcant source impedances on the analog input and

DIFFERENTIAL

REFERENCE

PROGRAMMABLE GAIN

AMPLIFIER

THE EXTERNAL REFERENCE

INPUT TO THE ADuC836 IS

DIFFERENTIAL AND

ANALOG INPUT CHOPPING

THE PROGRAMMABLE

GAIN AMPLIFIER ALLOWS

EIGHT UNIPOLAR AND

EIGHT BIPOLAR INPUT

RANGES FROM 20mV TO

- ADC

OUTPUT AVERAGE

THE INPUTS ARE

ALTERNATELY REVERSED

THROUGH THE

FACILITATES RATIOMETRIC

OPERATION. THE EXTERNAL

REFERENCE VOLTAGE IS

SELECTED VIA THE XREF0 BIT

IN ADC0CON.

THE - ARCHITECTURE

ENSURES 24 BITS NO

MISSING CODES. THE

ENTIRE- ADC IS

CHOPPED TO REMOVE

DRIFT ERROR.

AS PART OF THE CHOPPING

IMPLEMENTATION, EACH

DATA-WORD OUTPUT

FROM THE FILTER IS

SUMMED AND AVERAGED

WITH ITS PREDECESSOR

TO NULL ADC CHANNEL

OFFSET ERRORS.

CONVERSION CYCLE.

CHOPPING YIELDS

BURNOUT CURRENTS

2.56V (EXT V

= 2.5V).

REF

EXCELLENT ADC OFFSET

AND OFFSET DRIFT

PERFORMANCE.

TWO 100nA BURNOUT

CURRENTS ALLOW THE

USER TO EASILY DETECT

IF A TRANSDUCER HAS

BURNED OUT OR GONE

OPEN-CIRCUIT.

REFERENCE DETECT

CIRCUITRY TESTS FOR OPEN OR

SHORTED REFERENCE INPUTS.

REFIN(–)

REFIN(+)

AV

DD

DIGTAL OUTPUT

RESULT WRITTEN

TO ADC0H/M/L

SFRS

- ADC

AIN1

AIN2

AIN3

AIN4

BUFFER

PROGRAMMABLE

OUTPUT

AVERAGE

OUTPUT

SCALING

-

MODULATOR

DIGITAL

FILTER

MUX

PGA

CHOP

AGND

OUTPUT SCALING

THE OUPUT WORD FROM THE

DIGITAL FILTER IS SCALED

BY THE CALIBRATION

ANALOG MULTIPLEXER

A DIFFERENTIAL MULTIPLEXER

ALLOWS SELECTION OF THREE

FULLY DIFFERENTIAL PAIR OPTIONS AND

ADDITIONAL INTERNAL SHORT OPTION

(AIN2–AIN2). THE MULTIPLEXER IS

CONTROLLED VIA THE CHANNEL

SELECTION BITS IN ADC0CON.

COEFFICIENTS BEFORE

BEING PROVIDED AS

PROGRAMMABLE

DIGITAL FILTER

- MODULATOR

BUFFER AMPLIFIER

THE CONVERSION RESULT.

THE MODULATOR PROVIDES

A HIGH FREQUENCY 1-BIT

DATA STREAM (THE OUTPUT

3

THE SINC FILTER REMOVES

QUANTIZATION NOISE INTRODUCED

BY THE MODULATOR. THE UPDATE

RATE AND BANDWIDTH OF THIS

FILTER ARE PROGRAMMABLE

VIA THE SF SFR.

THE BUFFER AMPLIFIER

PRESENTS A HIGH

OF WHICH IS ALSO CHOPPED)

TO THE DIGITAL FILTER,

IMPEDANCE INPUT STAGE

FOR THE ANALOG INPUTS,

ALLOWING SIGNIFICANT

EXTERNAL SOURCE

THE DUTY CYCLE OF WHICH

REPRESENTS THE SAMPLED

ANALOG INPUT VOLTAGE.

IMPEDANCES.

Figure 7. Primary ADC Block Diagram

REV. A

–23–

ADuC836

Auxiliary ADC

The auxiliary ADC has three external input pins (labeled AIN3

to AIN5) as well as an internal connection to the on-chip tem-

perature sensor. All inputs to the auxiliary ADC are single-ended

inputs referenced to the AGND on the part. Channel selection

bits in the ADC1CON SFR detailed inTableVII allow selection

of one of four inputs.

The auxiliary ADC is intended to convert supplementary inputs

such as those from a cold junction diode or thermistor.This ADC

is not buffered and has a ﬁxed input range of 0V to 2.5V (assuming

an external 2.5V reference).The single-ended inputs can be driven

from AIN3, AIN4, or AIN5 pins, or directly from the on-chip

temperature sensor voltage. A block diagram of the auxiliary ADC

is shown in Figure 8.

Two input multiplexers switch the selected input channel to the

on-chip buffer ampliﬁer in the case of the primary ADC and

directly to the - modulator input in the case of the auxiliary

ADC.When the analog input channel is switched, the settling

time of the part must elapse before a new valid word is available

from the ADC.

Analog Input Channels

The primary ADC has four associated analog input pins (labeled

AIN1 to AIN4) that can be conﬁgured as two fully differential input

channels. Channel selection bits in the ADC0CON SFR detailed

inTableVI allow three combinations of differential pair selection

as well as an additional shorted input option (AIN2–AIN2).

DIFFERENTIAL REFERENCE

THE EXTERNAL REFERENCE INPUT

TO THE ADuC836 IS DIFFERENTIAL

AND FACILITATES RATIOMETRIC

OPERATION. THE EXTERNAL

OUTPUT AVERAGE

- ADC

REFERENCE VOLTAGE IS SELECTED

VIA THE XREF1 BIT IN ADC1CON.

AS PART OF THE CHOPPING

ANALOG INPUT CHOPPING

THE - ARCHITECTURE

REFERENCE DETECT

IMPLEMENTATION, EACH

ENSURES 16 BITS NO MISSING

CIRCUITRY TESTS FOR OPEN OR

DATA-WORD OUTPUT

THE INPUTS ARE ALTERNATELY

CODES. THE ENTIRE- ADC

SHORTED REFERENCE INPUTS.

REVERSED THROUGH THE

FROM THE FILTER IS

IS CHOPPED TO REMOVE

SUMMED AND AVERAGED

CONVERSION CYCLE. CHOPPING

YIELDS EXCELLENT ADC

OFFSET AND OFFSET DRIFT

PERFORMANCE.

DRIFT ERRORS.

WITH ITS PREDECESSOR

TO NULL ADC CHANNEL

OFFSET ERRORS.

REFIN(–)

REFIN(+)

DIGTAL OUTPUT

RESULT WRITTEN

TO ADC1H/L SFRs

- ADC

AIN3

AIN4

PROGRAMMABLE

DIGITAL FILTER

OUTPUT

SCALING

-

MODULATOR

OUTPUT

AVERAGE

MU

MUX

X

AIN5

CHOP

ON-CHIP

TEMPERATURE

SENSOR

CHOP

OUTPUT SCALING

THE OUPUT WORD FROM THE

DIGITAL FILTER IS SCALED BY

THE CALIBRATION

ANALOG MULTIPLEXER

COEFFICIENTS BEFORE

BEING PROVIDED AS

PROGRAMMABLE DIGITAL

FILTER

A DIFFERENTIAL MULTIPLEXER

ALLOWS SELECTION OF THREE

EXTERNAL SINGLE ENDED INPUTS

OR THE ON-CHIP TEMP. SENSOR.

THE MULTIPLEXER IS CONTROLLED

VIA THE CHANNEL SELECTION

BITS IN ADC1CON.

- MODULATOR

THE CONVERSION RESULT.

3

THE MODULATOR PROVIDES A

HIGH FREQUENCY 1-BIT DATA

STREAM (THE OUTPUT OF WHICH

IS ALSO CHOPPED) TO THE

DIGITAL FILTER,

THE DUTY CYCLE OF WHICH

REPRESENTS THE SAMPLED

ANALOG INPUT VOLTAGE.

THE SINC FILTER REMOVES

QUANTIZATION NOISE INTRODUCED

BY THE MODULATOR. THE UPDATE

RATE AND BANDWIDTH OF THIS

FILTER ARE PROGRAMMABLE

VIA THE SF SFR.

Figure 8. Auxiliary ADC Block Diagram

–24–

REV. A

ADuC836

19.372

19.371

19.370

19.369

Primary and Auxiliary ADC Inputs

The output of the Primary ADC multiplexer feeds into a high

impedance input stage of the buffer ampliﬁer. As a result, the

primary ADC inputs can handle signiﬁcant source impedances

and are tailored for direct connection to external resistive-type sen-

sors like strain gages or ResistanceTemperature Detectors (RTDs).

The auxiliary ADC, however, is unbuffered, resulting in higher

analog input current on the auxiliary ADC. It should be noted

that this unbuffered input path provides a dynamic load to the

driving source.Therefore, resistor/capacitor combinations on the

input pins can cause dc gain errors depending on the output

impedance of the source that is driving the ADC inputs.

19.368

19.367

19.366

19.365

Analog Input Ranges

19.364

SAMPLE COUNT

0

100

200

300

400

500

600

700

800

The absolute input voltage range on the primary ADC is restricted

to between AGND + 100 mV to AV_DD– 100 mV. Care must be

taken in setting up the common-mode voltage and input voltage

range so that these limits are not exceeded; otherwise there will

be a degradation in linearity performance.

ADC RANGE

Figure 9. Primary ADC Range Matching

Bipolar/Unipolar Inputs

The analog inputs on the ADuC836 can accept either unipolar

or bipolar input voltage ranges. Bipolar input ranges do not imply

that the part can handle negative voltages with respect to system

AGND.

The absolute input voltage range on the auxiliary ADC is restricted

to between AGND – 30 mV to AV_DD+ 30 mV.The slightly negative

absolute input voltage limit does allow the possibility of monitor-

ing small signal bipolar signals using the single-ended auxiliary

ADC front end.

Programmable Gain Ampliﬁer

Unipolar and bipolar signals on the AIN(+) input on the primary

ADC are referenced to the voltage on the respective AIN(–)

input. For example, if AIN(–) is 2.5V and the primary ADC is

conﬁgured for an analog input range of 0 mV to 20 mV, the input

voltage range on the AIN(+) input is 2.5V to 2.52V. If AIN(–) is

2.5V and the ADuC836 is conﬁgured for an analog input range

of 1.28V, the analog input range on the AIN(+) input is 1.22V to

3.78V (i.e., 2.5V ± 1.28V).

The output from the buffer on the primary ADC is applied to the

input of the on-chip programmable gain ampliﬁer (PGA).The

PGA can be programmed through eight different unipolar input

ranges and bipolar ranges.The PGA gain range is programmed

via the range bits in the ADC0CON SFR.With the external

reference select bit set in the ADC0CON SFR and an external

2.5V reference, the unipolar ranges are 0 mV to 20 mV, 0 mV to

40 mV, 0 mV to 80 mV, 0 mV to 160 mV, 0 mV to 320 mV, 0 mV

to 640 mV, 0V to 1.28V, and 0 to 2.56V; the bipolar ranges

are ±20 mV, ±40 mV, ±80 mV, ±160 mV, ±320 mV, ±640 mV,

±1.28V, and ±2.56V.These are the nominal ranges that should

appear at the input to the on-chip PGA. An ADC range matching

speciﬁcation of 2 µV (typ) across all ranges means that calibration

need only be carried out at a single gain range and does not have

to be repeated when the PGA gain range is changed.

As mentioned earlier, the auxiliary ADC input is a single-ended

input with respect to the system AGND. In this context, a bipolar

signal on the auxiliary ADC can only span 30 mV negative with

respect to AGND before violating the voltage input limits for

this ADC.

Bipolar or unipolar options are chosen by programming the pri-

mary and auxiliary Unipolar enable bits in the ADC0CON and

ADC1CON SFRs, respectively.This programs the relevant ADC

for either unipolar or bipolar operation. Programming for either

unipolar or bipolar operation does not change any of the input

signal conditioning; it simply changes the data output coding

and the points on the transfer function where calibrations occur.

When an ADC is conﬁgured for unipolar operation, the output

coding is natural (straight) binary with a zero differential input

voltage resulting in a code of 000 . . . 000, a midscale voltage

resulting in a code of 100 . . . 000, and a full-scale input voltage

resulting in a code of 111 . . . 111.When an ADC is conﬁgured

for bipolar operation, the coding is offset binary with a negative

full-scale voltage resulting in a code of 000 . . . 000, a zero dif-

ferential voltage resulting in a code of 100 . . . 000, and a positive

full-scale voltage resulting in a code of 111 . . . 111.

Typical matching across ranges is shown in Figure 9. Here, the

primary ADC is conﬁgured in bipolar mode with an external 2.5V

reference, while just greater than 19 mV is forced on its inputs.

The ADC continuously converts the dc input voltage at an update

rate of 5.35 Hz, i.e., SF = FFH. In total, 800 conversion results are

gathered.The ﬁrst 100 results are gathered with the primary ADC

operating in the ±20 mV range.The ADC range is then switched

to ±40 mV, 100 more conversion results are gathered, and so on,

until the last group of 100 samples is gathered with the ADC con-

ﬁgured in the ±2.56V range. From Figure 9, the variation in the

sample mean through each range, i.e., the range matching, is seen

to be of the order of 2 V.

The auxiliary ADC does not incorporate a PGA and is conﬁgured

for a ﬁxed single input range of 0 toV_REF

.

REV. A

–25–

ADuC836

Reference Input

Excitation Currents

The ADuC836’s reference inputs, REFIN(+) and REFIN(–),

provide a differential reference input capability.The common-

mode range for these differential inputs is from AGND to AV_DD

The nominal reference voltage,V_REF(REFIN(+) – REFIN(–)),

for speciﬁed operation is 2.5V with the primary and auxiliary

reference enable bits set in the respective ADC0CON and/or

ADC1CON SFRs.

The ADuC836 also contains two identical, 200 µA constant current

sources. Both source current from AV_DDto Pin 3 (IEXC1) or Pin 4

(IEXC2).These current sources are controlled via bits in the ICON

SFR shown inTable IX.They can be conﬁgured to source 200 µA

individually to both pins or a combination of both currents, i.e.,

400 µA, to either of the selected pins.These current sources can be

used to excite external resistive bridge or RTD sensors.

.

The part is also functional (although not speciﬁed for perfor-

mance) when the XREF0 or XREF1 bits are 0, which enables the

on-chip internal band gap reference. In this mode, the ADCs will see

the internal reference of 1.25V, therefore halving all input ranges.

As a result of using the internal reference voltage, a noticeable

degradation in peak-to-peak resolution will result.Therefore, for

best performance, operation with an external reference is strongly

recommended.

Reference Detect

The ADuC836 includes on-chip circuitry to detect if the part has

a valid reference for conversions or calibrations. If the voltage

between the external REFIN(+) and REFIN(–) pins goes below

0.3V or either the REFIN(+) or REFIN(–) inputs is open circuit,

the ADuC836 detects that it no longer has a valid reference. In this

case, the NOXREF bit of the ADCSTAT SFR is set to a 1. If the

ADuC836 is performing normal conversions and the NOXREF

bit becomes active, the conversion results revert to all 1s. It is not

necessary to continuously monitor the status of the NOXREF bit

when performing conversions. It is only necessary to verify its status

if the conversion result read from the ADC Data Register is all 1s.

In applications where the excitation (voltage or current) for the

transducer on the analog input also drives the reference voltage

for the part, the effect of the low frequency noise in the excitation

source will be removed as the application is ratiometric. If the

ADuC836 is not used in a ratiometric application, a low noise

reference should be used. Recommended reference voltage sources

for the ADuC836 include the AD780, REF43, and REF192.

If the ADuC836 is performing either an offset or gain calibration

and the NOXREF bit becomes active, the updating of the respec-

tive calibration registers is inhibited to avoid loading incorrect

coefﬁcients to these registers, and the appropriate ERR0 or ERR1

bits in the ADCSTAT SFR are set. If the user is concerned about

verifying that a valid reference is in place every time a calibration is

performed, the status of the ERR0 or ERR1 bit should be checked

at the end of the calibration cycle.

It should also be noted that the reference inputs provide a high

impedance, dynamic load. Because the input impedance of each

reference input is dynamic, resistor/capacitor combinations on these

inputs can cause dc gain errors depending on the output imped-

ance of the source that is driving the reference inputs. Reference

voltage sources, like those recommended above (e.g., AD780),

will typically have low output impedances and therefore decoupling

capacitors on the REFIN(+) input would be recommended.

Deriving the reference input voltage across an external resistor,

as shown in Figure 66, will mean that the reference input sees a

signiﬁcant external source impedance. External decoupling on

the REFIN(+) and REFIN(–) pins would not be recommended

in this type of circuit conﬁguration.

- Modulator

A -ADC generally consists of two main blocks, an analog modu-

lator and a digital ﬁlter. In the case of the ADuC836 ADCs, the

analog modulators consist of a difference ampliﬁer, an integrator

block, a comparator, and a feedback DAC, as illustrated in Figure 10.

DIFFERENCE

AMP

ANALOG

INPUT

COMPARATOR

HIGH

FREQUENCY

BIT STREAM

TO DIGITAL

FILTER

INTEGRATOR

DAC

Burnout Currents

The primary ADC on the ADuC836 contains two 100 nA con-

stant current generators: one sourcing current from AV_DDto

AIN(+) and one sinking from AIN(–) to AGND.The currents

are switched to the selected analog input pair. Both currents are

either on or off, depending on the Burnout Current Enable

(BO) bit in the ICON SFR (seeTable IX).These currents can

be used to verify that an external transducer is still operational

before attempting to take measurements on that channel. Once

the burnout currents are turned on, they will ﬂow in the external

transducer circuit, and a measurement of the input voltage on

the analog input channel can be taken. If the resultant voltage

measured is full-scale, it indicates that the transducer has gone

open-circuit. If the voltage measured is 0V, it indicates that the

transducer has short circuited. For normal operation, these burn-

out currents are turned off by writing a 0 to the BO bit in the

ICON SFR.The current sources work over the normal absolute

input voltage range speciﬁcations.

Figure 10. - Modulator Simpliﬁed Block Diagram

In operation, the analog signal sample is fed to the difference

ampliﬁer along with the output of the feedback DAC.The dif-

ference between these two signals is integrated and fed to the

comparator.The output of the comparator provides the input to

the feedback DAC so the system functions as a negative feedback

loop that tries to minimize the difference signal.The digital data

that represents the analog input voltage is contained in the duty

cycle of the pulse train appearing at the output of the comparator.

This duty cycle data can be recovered as a data-word using a sub-

sequent digital ﬁlter stage.The sampling frequency of the modulator

loop is many times higher than the bandwidth of the input signal.

The integrator in the modulator shapes the quantization noise

(which results from the analog-to-digital conversion) so that the

noise is pushed toward one-half of the modulator frequency.

–26–

REV. A

ADuC836

0

–10

Digital Filter

The output of the - modulator feeds directly into the digital

ﬁlter.The digital ﬁlter then band-limits the response to a frequency

signiﬁcantly lower than one-half of the modulator frequency. In

this manner, the 1-bit output of the comparator is translated into

a band-limited, low noise output from the ADuC836 ADCs.

–20

–30

–40

–50

The ADuC836 ﬁlter is a low-pass, SIN³or (SINx/x)3 ﬁlter whose

primary function is to remove the quantization noise introduced

at the modulator.The cutoff frequency and decimated output

data rate of the ﬁlter are programmable via the SF (Sinc Filter)

SFR, as described inTableVIII.

–60

–70

–80

–90

–100

–110

–120

Figure 11 shows the frequency response of the ADC channel at

the default SF word of 69 dec or 45H, yielding an overall output

update rate of just under 20 Hz.

0

10

20

30

40

50

60

70

80

90

110

FREQUENCY – Hz

It should be noted that this frequency response allows frequency

components higher than the ADC Nyquist frequency to pass

through the ADC, in some cases without signiﬁcant attenuation.

These components may, therefore, be aliased and appear in-band

after the sampling process.

Figure 12. Filter Response, SF = 255 dec

Figures 13 and 14 show the NMR for 50 Hz and 60 Hz across

the full range of SF word, i.e., SF = 13 dec to SF = 255 dec.

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

It should also be noted that rejection of mains related frequency

components, i.e., 50 Hz and 60 Hz, is seen to be at a level of

>65 dB at 50 Hz and >100 dB at 60 Hz.This conﬁrms the data

sheet speciﬁcations for 50 Hz/60 Hz Normal Mode Rejection

(NMR) at a 20 Hz update rate.

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–120

10 30 50 70 90 110 130 150 170 190 210 230 250

SF – Decimal

Figure 13. 50 Hz Normal Mode Rejection vs. SF

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

0

10

20

30

40

50

60

70

80

90 100 110

FREQUENCY – Hz

Figure 11. Filter Response, SF = 69 dec

The response of the ﬁlter, however, will change with SF word, as

can be seen in Figure 12, which shows >90 dB NMR at 50 Hz

and >70 dB NMR at 60 Hz when SF = 255 dec.

–120

10 30 50 70 90 110 130 150 170 190 210 230 250

SF – Decimal

Figure 14. 60 Hz Normal Mode Rejection vs. SF

REV. A

–27–

ADuC836

ADC Chopping

present at power-on an internal full-scale calibration will only be

required if the part is being operated at 3V or at temperatures

signiﬁcantly different from 25°C.

Both ADCs on the ADuC836 implement a chopping scheme

whereby the ADC repeatedly reverses its inputs.The decimated

digital output words from the Sinc³ﬁlters therefore have a positive

offset and negative offset term included.

The ADuC836 offers internal or system calibration facilities. For

full calibration to occur on the selected ADC, the calibration

logic must record the modulator output for two different input

conditions: zero-scale and full-scale points.These points are

derived by performing a conversion on the different input volt-

ages provided to the input of the modulator during calibration.

The result of the zero-scale calibration conversion is stored in the

Offset Calibration Registers for the appropriate ADC.The result

of the full-scale calibration conversion is stored in the Gain Cali-

bration Registers for the appropriate ADC.With these readings,

the calibration logic can calculate the offset and the gain slope for

the input-to-output transfer function of the converter.

As a result, a ﬁnal summing stage is included in each ADC so that

each output word from the ﬁlter is summed and averaged with

the previous ﬁlter output to produce a new valid output result

to be written to the ADC data SFRs. In this way, while the ADC

throughput or update rate is as discussed earlier and illustrated in

TableVIII, the full settling time through the ADC (or the time to

a ﬁrst conversion result) will actually be given by 2  t_ADC

.

The chopping scheme incorporated in the ADuC836 ADC results

in excellent dc offset and offset drift speciﬁcations and is extremely

beneﬁcial in applications where drift, noise rejection, and optimum

EMI rejection are important factors.

During an internal zero-scale or full-scale calibration, the respective

zero-scale input and full-scale inputs are automatically connected to

the ADC input pins internally to the device. A system calibration,

however, expects the system zero-scale and system full-scale volt-

ages to be applied to the external ADC pins before the calibration

mode is initiated. In this way, external ADC errors are taken into

account and minimized as a result of system calibration. It should

also be noted that to optimize calibration accuracy, all ADuC836

ADC calibrations are carried out automatically at the slowest

update rate.

Calibration

The ADuC836 provides four calibration modes that can be pro-

grammed via the mode bits in the ADCMODE SFR detailed in

TableV. In fact, every ADuC836 has already been factory cali-

brated.The resultant Offset and Gain calibration coefﬁcients

for both the primary and auxiliary ADCs are stored on-chip in

manufacturing-speciﬁc Flash/EE memory locations. At power-on

or after reset, these factory calibration coefﬁcients are automati-

cally downloaded to the calibration registers in the ADuC836

SFR space. Each ADC (primary and auxiliary) has dedicated

calibration SFRs, which have been described earlier as part of the

general ADC SFR description. However, the factory calibration

values in the ADC calibration SFRs will be overwritten if any

one of the four calibration options are initiated and that ADC is

enabled via the ADC enable bits in ADCMODE.

Internally in the ADuC836, the coefﬁcients are normalized before

being used to scale the words coming out of the digital ﬁlter.The

offset calibration coefﬁcient is subtracted from the result prior to

the multiplication by the gain coefﬁcient.

From an operational point of view, a calibration should be treated

like another ADC conversion. A zero-scale calibration (if required)

should always be carried out before a full-scale calibration. System

software should monitor the relevant ADC RDY0/1 bit in the

ADCSTAT SFR to determine end of calibration via a polling

sequence or interrupt driven routine.

Even though an internal offset calibration mode is described

below, it should be recognized that both ADCs are chopped.This

chopping scheme inherently minimizes offset and means that an

internal offset calibration should never be required. Also, because

factory 5V/25°C gain calibration coefﬁcients are automatically

–28–

REV. A

ADuC836

ADuC836 Flash/EE Memory Reliability

NONVOLATILE FLASH/EE MEMORY

Flash/EE Memory Overview

The Flash/EE program and data memory arrays on the ADuC836

are fully qualiﬁed for two key Flash/EE memory characteristics:

Flash/EE Memory Cycling Endurance and Flash/EE Memory

Data Retention.

The ADuC836 incorporates Flash/EE memory technology

on-chip to provide the user with nonvolatile, in-circuit, repro-

grammable code and data memory space. Flash/EE memory is

a relatively recent type of nonvolatile memory technology and is

based on a single transistor cell architecture.This technology is

basically an outgrowth of EPROM technology and was devel-

oped through the late 1980s. Flash/EE memory takes the ﬂexible

in-circuit reprogrammable features of EEPROM and combines

them with the space efﬁcient/density features of EPROM (see

Figure 15).

Endurance quantiﬁes the ability of the Flash/EE memory to be

cycled through many program, read, and erase cycles. In real

terms, a single endurance cycle is composed of four independent,

sequential events, which are deﬁned as:

a. Initial page erase sequence

A Single Flash/EE

Memory Endurance

Cycle

b. Read/verify sequence

Because Flash/EE technology is based on a single transistor cell

architecture, a Flash memory array, like EPROM, can be im-

plemented to achieve the space efﬁciencies or memory densities

required by a given design.

c. Byte program sequence

d. Second read/verify sequence

In reliability qualiﬁcation, every byte in both the program and

data Flash/EE memory is cycled from 00H to FFH until a ﬁrst

fail is recorded, signifying the endurance limit of the on-chip

Flash/EE memory.

Like EEPROM, ﬂash memory can be programmed in-system

at a byte level, although it must ﬁrst be erased; the erase being

performed in page blocks.Thus, ﬂash memory is often and more

correctly referred to as Flash/EE memory.

As indicated in the Speciﬁcation tables, the ADuC836 Flash/EE

Memory Endurance qualification has been carried out in

accordance with JEDEC Speciﬁcation A117 over the industrial

temperature range of –40°C, +25°C, +85°C, and +125°C.The

results allow the speciﬁcation of a minimum endurance ﬁgure

over supply and temperature of 100,000 cycles, with an endur-

ance ﬁgure of 700,000 cycles being typical of operation at 25°C.

EPROM

TECHNOLOGY

EEPROM

TECHNOLOGY

SPACE EFFICIENT/

DENSITY

IN-CIRCUIT

REPROGRAMMABLE

FLASH/EE MEMORY

TECHNOLOGY

Retention quantiﬁes the ability of the Flash/EE memory to retain

its programmed data over time. Again, the ADuC836 has been

qualiﬁed in accordance with the formal JEDEC Retention Life-

time Speciﬁcation (A117) at a speciﬁc junction temperature

(T_J= 55°C). As part of this qualiﬁcation procedure, the Flash/EE

memory is cycled to its speciﬁed endurance limit described above,

before data retention is characterized.This means that the Flash/EE

memory is guaranteed to retain its data for its full speciﬁed reten-

tion lifetime every time the Flash/EE memory is reprogrammed.

It should also be noted that retention lifetime, based on an activa-

tion energy of 0.6 eV, will derate withT_J, as shown in Figure 16.

Figure 15. Flash/EE Memory Development

Overall, Flash/EE memory represents a step closer to the ideal

memory device that includes nonvolatility, in-circuit programma-

bility, high density, and low cost. Incorporated into the ADuC836,

Flash/EE memory technology allows the user to update program

code space in-circuit, without the need to replace one-time pro-

grammable (OTP) devices at remote operating nodes.

Flash/EE Memory and the ADuC836

The ADuC836 provides two arrays of Flash/EE memory for user

applications. 62 Kbytes of Flash/EE program space are provided

on-chip to facilitate code execution without any external dis-

crete ROM device requirements.The program memory can be

programmed in-circuit, using the serial download mode provided,

using conventional third party memory programmers, or via any

user deﬁned protocol in User Download (ULOAD) mode.

300

250

200

ADI SPECIFICATION

100 YEARS MIN.

AT T = 55C

J

150

100

A 4 Kbyte Flash/EE data memory space is also provided on-chip.

This may be used as a general-purpose, nonvolatile scratch pad

area. User access to this area is via a group of seven SFRs.This

space can be programmed at a byte level, although it must ﬁrst be

erased in 4-byte pages.

50

0

40

50

60

70

80

90

100

110

T

JUNCTION TEMPERATURE – C

J

Figure 16. Flash/EE Memory Data Retention

REV. A

–29–

ADuC836

Flash/EE Program Memory

(2) Parallel Programming

The ADuC836 contains a 64 Kbyte array of Flash/EE program

memory. The lower 62 Kbytes of this program memory are avail-

able to the user, and can be used for program storage or indeed

as additional NV data memory.

The Parallel Programming mode is fully compatible with con-

ventional third party Flash or EEPROM device programmers.

A block diagram of the external pin conﬁguration required to

support parallel programming is shown in Figure 18. In this mode,

Ports 0 and 2 operate as the external address bus interface, P3

operates as the external data bus interface, and P1.0 operates as

theWrite Enable strobe. Port 1.1, P1.2, P1.3, and P1.4 are used

as a general conﬁguration port that conﬁgures the device for vari-

ous program and erase operations during parallel programming.

The upper 2 Kbytes of this Flash/EE program memory array con-

tain permanently embedded ﬁrmware, allowing in-circuit serial

download, serial debug, and nonintrusive single pin emulation.

These 2 Kbytes of embedded ﬁrmware also contain a power-on

conﬁguration routine that downloads factory calibrated coefﬁ-

cients to the various calibrated peripherals (ADC, temperature

sensor, current sources, band gap references, and so on).

Table XIII. Flash/EE Memory Parallel Programming Modes

Port 1 Pins

This 2 Kbyte embedded ﬁrmware is hidden from user code.

Attempts to read this space will read 0s, i.e., the embedded ﬁrm-

ware appears as NOP instructions to user code.

P1.4 P1.3 P1.2 P1.1

Programming Mode

0

Erase Flash/EE Program,

Data, and Security Modes

Read Device Signature/ID

Program Code Byte

Program Data Byte

Read Code Byte

Read Data Byte

Program Security Modes

Read/Verify Security Modes

Redundant

In normal operating mode (power-up default), the 62 Kbytes of

user Flash/EE program memory appear as a single block. This

block is used to store the user code, as shown in Figure 17.

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

EMBEDDED DOWNLOAD/DEBUG KERNEL

FFFFH

2 KBYTE

F800H

PERMANENTLY EMBEDDED FIRMWARE ALLOWS CODE

TO BE DOWNLOADED TO ANY OF THE 62 KBYTES OF

ON-CHIP PROGRAM MEMORY. THE KERNEL PROGRAM

APPEARS AS ‘NOP’ INSTRUCTIONS TO USER CODE.

F7FFH

All other codes

USER PROGRAM MEMORY

62 KBYTES OF FLASH/EE PROGRAM MEMORY IS

AVAILABLE TO THE USER. ALL OF THIS SPACE CAN

BE PROGRAMMED FROM THE PERMANENTLY

EMBEDDED DOWNLOAD/DEBUG KERNEL OR IN

PARALLEL PROGRAMMING MODE.

5V

62 KBYTE

ADuC836

V

PROGRAM

DD

DATA

P3

P0

P2

GND

(D0–D7)

PROGRAM MODE

(SEE TABLE XIII)

PROGRAM

ADDRESS

(A0–A13)

(P2.0 = A0)

(P1.7 = A13)

P1.1 -> P1.4

P1.0

0000H

COMMAND

ENABLE

Figure 17. Flash/EE Program Memory Map in Normal Mode

GND

EA

ENTRY

SEQUENCE

In Normal mode, the 62 Kbytes of Flash/EE program memory

can be programmed by serial downloading or parallel processing:

GND

P1.5 -> P1.7

TIMING

PSEN

V

RESET

DD

(1) Serial Downloading (In-Circuit Programming)

The ADuC836 facilitates code download via the standard UART

serial port.The ADuC836 will enter Serial Download mode after

a reset or power cycle if the PSEN pin is pulled low through an

external 1 k resistor. Once in serial download mode, the hidden

embedded download kernel will execute.This allows the user to

download code to the full 62 Kbytes of Flash/EE program memo-

ry while the device is in circuit in its target application hardware.

Figure 18. Flash/EE Memory Parallel Programming

A PC serial download executable is provided as part of the

ADuC836 QuickStart development system. Application Note

uC004 fully describes the serial download protocol that is used

by the embedded download kernel. This Application Note is

available at www.analog.com/microconverter.

–30–

REV. A

ADuC836

Flash/EE Program Memory Security

User Download Mode (ULOAD)

The ADuC836 facilitates three modes of Flash/EE program memory

security.These modes can be independently activated, restrict-

ing access to the internal code space.These security modes can

be enabled as part of serial download protocol, as described

in Application Note uC004, or via parallel programming.The

ADuC836 offers the following security modes:

In Figure 17 we can see that it was possible to use the 62 Kbytes

of Flash/EE program memory available to the user as one single

block of memory. In this mode, all of the Flash/EE memory is

read only to user code.

However, the Flash/EE program memory can also be written to

during runtime simply by entering ULOAD mode. In ULOAD

mode, the lower 56 Kbytes of program memory can be erased

and reprogrammed by user software, as shown in Figure 19.

ULOAD mode can be used to upgrade your code in the ﬁeld via

any user deﬁned download protocol. Conﬁguring the SPI port on

the ADuC836 as a slave, it is possible to completely reprogram

the 56 Kbytes of Flash/EE program memory in only 5 seconds

(see Application Note uC007).

Lock Mode

This mode locks the code memory, disabling parallel program-

ming of the program memory. However, reading the memory in

Parallel mode and reading the memory via a MOVC command

from external memory is still allowed.This mode is deactivated

by initiating an “erase code and data” command in Serial Down-

load or Parallel Programming modes.

Secure Mode

Alternatively, ULOAD mode can be used to save data to the

56 Kbytes of Flash/EE memory.This can be extremely useful in

data logging applications where the ADuC836 can provide up to

60 Kbytes of NV data memory on-chip (4 Kbytes of dedicated

Flash/EE data memory also exist).

This mode locks the code memory, disabling parallel program-

ming of the program memory. Reading/verifying the memory

in Parallel mode and reading the internal memory via a MOVC

command from external memory is also disabled.This mode is

deactivated by initiating an “erase code and data” command in

Serial Download or Parallel Programming modes.

The upper 6 Kbytes of the 62 Kbytes of Flash/EE program memory

are only programmable via serial download or parallel program-

ming.This means that this space appears as read-only to user

code.Therefore, it cannot be accidently erased or reprogrammed

by erroneous code execution.This makes it very suitable to use

the 6 Kbytes as a bootloader. A Bootload Enable option exists in

the serial downloader to “Always RUN from E000h after Reset.”

If using a bootloader, this option is recommended to ensure that

the bootloader always executes correct code after reset.

Serial Safe Mode

This mode disables serial download capability on the device.

If Serial Safe mode is activated and an attempt is made to reset

the part into Serial Download mode, i.e., RESET asserted and

deasserted with PSEN low, the part will interpret the serial down-

load reset as a normal reset only. It will therefore not enter Serial

Download mode, but only execute a normal reset sequence.

Serial Safe mode can only be disabled by initiating an “erase code

and data” command in parallel programming mode.

Programming the Flash/EE program memory via ULOAD mode

is described in more detail in the description of ECON and also

in Application Note uC007.

EMBEDDED DOWNLOAD/DEBUG KERNEL

PERMANENTLY EMBEDDED FIRMWARE ALLOWS CODE

TO BE DOWNLOADED TO ANY OF THE 62 KBYTES OF

ON-CHIP PROGRAM MEMORY. THE KERNEL PROGRAM

APPEARS AS ‘NOP’ INSTRUCTIONS TO USER CODE.

FFFFH

2 KBYTE

F800H

F7FFH

USER BOOTLOADER SPACE

THE USER BOOTLOADER SPACE

CAN BE PROGRAMMED IN

DOWNLOAD/DEBUG MODE VIA THE

KERNEL BUT IS READ ONLY WHEN

EXECUTING USER CODE

6 KBYTE

E000H

DFFFH

62 KBYTES

OF USER

CODE

USER DOWNLOAD SPACE

EITHER THE DOWNLOAD/DEBUG KERNEL

OR USER CODE (IN ULOAD MODE) CAN

PROGRAM THIS SPACE.

MEMORY

56 KBYTE

0000H

Figure 19. Flash/EE Program Memory Map in

ULOAD Mode

REV. A

–31–

ADuC836

Using the Flash/EE Data Memory

BYTE 1

BYTE 2

BYTE 3

(0FFEH)

BYTE 4

(0FFFH)

3FFH

3FEH

(0FFCH)

(0FFDH)

The 4 Kbytes of Flash/EE data memory are conﬁgured as

1024 pages, each of four bytes. As with the other ADuC836

peripherals, the interface to this memory space is via a group of

registers mapped in the SFR space. A group of four data regis-

ters (EDATA1–A4) is used to hold the four bytes of data at each

page.The page is addressed via the two registers EADRH and

EADRL. Finally, ECON is an 8-bit control register that may be

written with one of nine Flash/EE memory access commands to

trigger various read, write, erase, and verify functions.

BYTE 1

(0FF8H)

BYTE 3

(0FFAH)

BYTE 2

(0FF9H)

BYTE 4

(0FFBH)

BYTE 1

(000CH)

BYTE 3

(000EH)

BYTE 2

(000DH)

BYTE 4

(000FH)

03H

02H

01H

00H

BYTE 1

(0008H)

BYTE 2

(0009H)

BYTE 3

(000AH)

BYTE 4

(000BH)

BYTE 1

(0004H)

BYTE 2

(0005H)

BYTE 3

(0006H)

BYTE 4

(0007H)

BYTE 1

(0000H)

BYTE 3

(0002H)

BYTE 2

(0001H)

BYTE 4

(0003H)

A block diagram of the SFR interface to the Flash/EE data

memory array is shown in Figure 20.

ECON—Flash/EE Memory Control SFR

BYTE

ADDRESSES

ARE GIVEN IN

BRACKETS

Programming of either the Flash/EE data memory or the Flash/EE

program memory is done through the Flash/EE Memory Control

SFR (ECON).This SFR allows the user to read, write, erase, or

verify the 4 Kbytes of Flash/EE data memory or the 56 Kbytes of

Flash/EE program memory.

Figure 20. Flash/EE Data Memory Control and Conﬁguration

Table XIV. ECON—Flash/EE Memory Commands

Command Description

(Normal Mode) (Power-On Default)

Command Description

(ULOAD Mode)

ECONValue

01H

READ

Results in four bytes in the Flash/EE data memory,

addressed by the page address EADRH/L, being read

into EDATA 1 to 4.

Not Implemented. Use the MOVC instruction.

02H

WRITE

Results in four bytes in EDATA1–A4 being written to the Results in bytes 0–255 of internal XRAM being written

Flash/EE data memory, at the page address given by

EADRH/L (0  EADRH/L < 0400H)

Note:The four bytes in the page being addressed must

be pre-erased.

to the 256 bytes of Flash/EE program memory at the

page address given by EADRH. (0  EADRH < E0H)

Note:The 256 bytes in the page being addressed must

be pre-erased.

03H

Reserved Command

04H

VERIFY

Veriﬁes if the data in EDATA1–4 is contained in the

page address given by EADRH/L. A subsequent read

of the ECON SFR will result in a 0 being read if the

veriﬁcation is valid, or a nonzero value being read

to indicate an invalid veriﬁcation.

Not Implemented. Use the MOVC and MOVX

instructions to verify theWRITE in software.

05H

ERASE PAGE

Results in the erase of the 4-bytes page of Flash/EE

data memory addressed by the page address EADRH/L

Results in the 64-byte page of Flash/EE program

memory, addressed by the byte address EADRH/L

being erased. EADRL can equal any of 64 locations

within the page. A new page starts whenever EADRL

is equal to 00H, 40H, 80H, or C0H.

06H

ERASE ALL

Results in the erase of entire four Kbytes of Flash/EE

data memory.

Results in the erase of the entire 56 Kbytes of ULOAD

Flash/EE program memory.

81H

READBYTE

Results in the byte in the Flash/EE data memory,

addressed by the byte address EADRH/L, being read

into EDATA1. (0  EADRH/L  0FFFH).

Not Implemented. Use the MOVC command.

82H

WRITEBYTE

Results in the byte in EDATA1 being written into

Flash/EE data memory, at the byte address EADRH/L.

Results in the byte in EDATA1 being written into

Flash/EE program memory at the byte address

EADRH/L (0  EADRH/L  DFFFH).

0FH

EXULOAD

Leaves the ECON instructions to operate on the

Flash/EE data memory.

Enters Normal mode, directing subsequent ECON

instructions to operate on the Flash/EE data memory.

F0H

ULOAD

Enters ULOAD mode, directing subsequent ECON

instructions to operate on the Flash/EE program memory. program memory.

Leaves the ECON instructions to operate on the Flash/EE

–32–

REV. A

ADuC836

Programming the Flash/EE Data Memory

A user wishes to program F3H into the second byte on Page 03H

of the Flash/EE data memory space while preserving the other

three bytes already in this page.

set to FFH, it is nonetheless good programming practice to

include an erase-all routine as part of any conﬁguration/setup

code running on the ADuC836. An ERASE-ALL command

consists of writing 06H to the ECON SFR, which initiates an

erase of the 4-Kbyte Flash/EE array.This command coded in

8051 assembly would appear as:

A typical program of the Flash/EE Data array will involve:

1. Setting EADRH/L with the page address

2.Writing the data to be programmed to the EDATA1–4

3.Writing the ECON SFR with the appropriate command

MOV ECON,#06H;Erase all Command

; 2 ms Duration

Step 1: Set Up the Page Address

Flash/EE MemoryTiming

The two address registers, EADRH and EADRL, hold the high

byte address and the low byte address of the page to be addressed.

The assembly language to set up the address may appear as:

MOVEADRH,#0; Set Page Address Pointer

MOVEADRL,#03H

Typical program and erase times for the ADuC836 are as follows:

Normal Mode (operating on Flash/EE data memory)

READPAGE (4 bytes)

WRITEPAGE (4 bytes)

VERIFYPAGE (4 bytes)

ERASEPAGE (4 bytes)

ERASEALL (4 Kbytes)

READBYTE (1 byte)

WRITEBYTE (1 byte)

– 5 machine cycles

– 380 s

– 5 machine cycles

– 2 ms

– 3 machine cycles

– 200 s

Step 2: Set Up the EDATA Registers

The four values to be written into the page into the four SFRs

EDATA1–4. Since we do not know three of them, it is necessary

to read the current page and overwrite the second byte.

MOVECON,#1;Read Page into EDATA1-4

MOVEDATA2,#0F3H;Overwrite byte 2

ULOAD Mode (operating on Flash/EE program memory)

WRITEPAGE (256 bytes)

ERASEPAGE (64 bytes)

ERASEALL (56 Kbytes)

WRITEBYTE (1 byte)

– 15 ms

– 2 ms

Step 3: Program Page

A byte in the Flash/EE array can be programmed only if it has

previously been erased.To be more speciﬁc, a byte can only be

programmed if it already holds the value FFH. Because of the

Flash/EE architecture, this erase must happen at a page level.

Therefore, a minimum of four bytes (1 page) will be erased when

an erase command is initiated. Once the page is erased, we can

program the four bytes in-page and then perform a veriﬁcation of

the data.

– 200 s

It should be noted that a given mode of operation is initiated as

soon as the command word is written to the ECON SFR.The

core microcontroller operation on the ADuC836 is idled until the

requested Program/Read or Erase mode is completed.

In practice, this means that even though the Flash/EE memory

mode of operation is typically initiated with a two-machine

cycle MOV instruction (to write to the ECON SFR), the next

instruction will not be executed until the Flash/EE operation is

complete.This means that the core will not respond to interrupt

requests until the Flash/EE operation is complete, although the

core peripheral functions like counter/timers will continue to

count and time as conﬁgured throughout this period.

MOV ECON,#5;ERASE Page

MOV ECON,#2;WRITE Page

MOV ECON,#4;VERIFY Page

MOV A,ECON;Check if ECON=0 (OK!)

JNZ ERROR

Note that although the four Kbytes of Flash/EE data memory

is shipped from the factory pre-erased, i.e., Byte locations

REV. A

–33–

ADuC836

DAC

programmed to appear at Pin 3 or Pin 12. It should be noted

that in 12-bit mode, the DAC voltage output will be updated

as soon as the DACL data SFR has been written; therefore, the

DAC data registers should be updated as DACH ﬁrst, followed

by DACL.The 12-bit DAC data should be written into DACH/L

right-justiﬁed such that DACL contains the lower eight bits, and

the lower nibble of DACH contains the upper four bits.

The ADuC836 incorporates a 12-bit voltage output DAC

on-chip. It has a rail-to-rail voltage output buffer capable of driving

10 k/100 pF. It has two selectable ranges, 0V toV_REF(the inter-

nal band gap 2.5 V reference) and 0 V to AV_DD. It can operate

in 12-bit or 8-bit mode.The DAC has a control register, DACCON,

and two data registers, DACH/L. The DAC output can be

Table XV. DACCON SFR Bit Designations

Bit

7

Name

–––

Description

Reserved for Future Use

DAC Output Pin Select.

6

–––

5

–––

4

DACPIN

Set by user to direct the DAC output to Pin 12 (P1.7/AIN4/DAC).

Cleared by user to direct the DAC output to Pin 3 (P1.2/DAC/IEXC1).

3

DAC8

DAC 8-bit Mode Bit.

Set by user to enable 8-bit DAC operation. In this mode, the 8 bits in DACL SFR are routed to the 8 MSBs

of the DAC, and the 4 LSBs of the DAC are set to zero.

Cleared by user to operate the DAC in its normal 12-bit mode of operation.

2

1

0

DACRN

DACCLR

DACEN

DAC Output Range Bit.

Set by user to conﬁgure DAC range of 0 to AV_DD

Cleared by user to conﬁgure DAC range of 0V to 2.5V (V_REF).

.

DAC Clear Bit.

Set to 1 by user to enable normal DAC operation.

Cleared to 0 by user to reset DAC data registers DACL/H to zero.

DAC Enable Bit.

Set to 1 by user to enable normal DAC operation.

Cleared to 0 by user to power down the DAC.

DACH/L

DAC Data Registers

Function

SFR Address

DAC Data Registers, written by user to update the DAC output.

DACL (DAC Data Low Byte)

FBH

DACH (DAC Data High Byte) FCH

Power-On DefaultValue 00H

Both Registers

Bit Addressable

No

Using the D/A Converter

Features of this architecture include inherent guaranteed monoto-

The on-chip D/A converter architecture consists of a resistor

string DAC followed by an output buffer ampliﬁer, the functional

equivalent of which is illustrated in Figure 21.

nicity and excellent differential linearity. As illustrated in Figure 21,

the reference source for the DAC is user selectable in software. It

can be either AV_DDorV_REF. In 0-to-AV_DDmode, the DAC output

transfer function spans from 0V to the voltage at the AV_DDpin.

In 0-to-V_REFmode, the DAC output transfer function spans from

0V to the internalV_REF(2.5V).The DAC output buffer ampliﬁer

features a true rail-to-rail output stage implementation.This means

that, unloaded, each output is capable of swinging to within less than

100 mV of both AV_DDand ground. Moreover, the DAC’s linear-

ity speciﬁcation (when driving a 10 k resistive load to ground)

is guaranteed through the full transfer function except codes 0

to 48 in 0-to-V_REFmode and 0 to 100 and 3950 to 4095 in 0-to-

V_DDmode.

AV

DD

ADuC836

V

R

REF

OUTPUT

BUFFER

DAC

12

HIGH-Z

DISABLE

(FROM MCU)

Linearity degradation near ground andV_DDis caused by saturation

of the output ampliﬁer, and a general representation of its effects

(neglecting offset and gain error) is illustrated in Figure 22.The

dotted line in Figure 22 indicates the ideal transfer function, and

the solid line represents what the transfer function might look

like with endpoint nonlinearities due to saturation of the output

ampliﬁer.

R

Figure 21. Resistor String DAC Functional Equivalent

–34–

REV. A

ADuC836

V

4

3

1

0

DD

V

–50mV

DD

DAC LOADED WITH 0FFFH

V

–100mV

DD

100mV

DAC LOADED WITH 0000H

50mV

0mV

0

5

10

15

FFFH

000H

SOURCE/SINK CURRENT – mA

Figure 22. Endpoint Nonlinearities Due to

Ampliﬁer Saturation

Figure 24. Source and Sink Current Capability with

V_REF= V_DD= 3 V

Note that Figure 22 represents a transfer function in 0-to-V_DDmode

only. In 0-to-V_REFmode (withV_REF<V_DD), the lower nonlinearity

would be similar, but the upper portion of the transfer function

would follow the “ideal” line right to the end, showing no signs of

endpoint linearity errors.

For larger loads, the current drive capability may not be sufﬁcient

To increase the source and sink current capability of the DAC, an

external buffer should be added, as shown in Figure 25.

The endpoint nonlinearities conceptually illustrated in Figure 22

get worse as a function of output loading. Most of the ADuC836

data sheet speciﬁcations assume a 10 k resistive load to ground

at the DAC output. As the output is forced to source or sink more

current, the nonlinear regions at the top or bottom (respectively)

of Figure 22 become larger.With larger current demands, this

can signiﬁcantly limit output voltage swing. Figures 23 and 24

illustrate this behavior. It should be noted that the upper trace in

each of these ﬁgures is valid only for an output range selection of

0-to-AV_DD. In 0-to-V_REFmode, DAC loading will not cause high

side voltage drops as long as the reference voltage remains below

the upper trace in the corresponding ﬁgure. For example, if AV_DD

= 3V andV_REF= 2.5V, the high side voltage will not be affected by

loads less than 5 mA. But somewhere around 7 mA, the upper curve

in Figure 24 drops below 2.5V (V_REF), indicating that at these

ADuC836

12

Figure 25. Buffering the DAC Output

The DAC output buffer also features a high impedance disable func-

tion. In the chip’s default power-on state, the DAC is disabled and

its output is in a high impedance state (or “three-state”) where

they remain inactive until enabled in software.

This means that if a zero output is desired during power-up or

power-down transient conditions, a pull-down resistor must be

added to each DAC output. Assuming this resistor is in place, the

DAC output will remain at ground potential whenever the DAC

is disabled.

higher currents, the output will not be capable of reachingV_REF

.

5

4

3

2

1

0

DAC LOADED WITH 0FFFH

DAC LOADED WITH 0000H

10

0

5

15

SOURCE/SINK CURRENT – mA

Figure 23. Source and Sink Current Capability

with V_REF= AV_DD= 5 V

REV. A

–35–

ADuC836

PULSEWIDTH MODULATOR (PWM)

The PWM uses ﬁve SFRs: the control SFR, PWMCON, and

four data SFRs: PWM0H, PWM0L, PWM1H, and PWM1L.

The PWM on the ADuC836 is a highly ﬂexible PWM offering

programmable resolution and input clock, and can be conﬁgured

for any one of six different modes of operation.Two of these modes

allow the PWM to be conﬁgured as a - DAC with up to 16 bits

of resolution. A block diagram of the PWM is shown in Figure 26.

PWMCON (as described inTable XVI) controls the different

modes of operation of the PWM as well as the PWM clock fre-

quency. PWM0H/L and PWM1H/L are the data registers that

determine the duty cycles of the PWM outputs at P1.0 and P1.1.

12.583MHz

To use the PWM user software, ﬁrst write to PWMCON to select

the PWM mode of operation and the PWM input clock.Writing

to PWMCON also resets the PWM counter. In any of the 16-bit

modes of operation (modes 1, 3, 4, 6), user software should write

to the PWM0L or PWM1L SFRs ﬁrst.This value is written to a

hidden SFR.Writing to the PWM0H or PWM1H SFRs updates

both the PWMxH and the PWMxL SFRs but does not change

the outputs until the end of the PWM cycle in progress.The

values written to these 16-bit registers are then used in the next

PWM cycle.

PWM

CLOCK

SELECT

CLK

PROGRAMMABLE

DIVIDER

32.768kHz

32.768kHz/15

16-BIT PWM COUNTER

COMPARE

P1.0

P1.1

PWMCON

PWM Control SFR

SFR Address

Power-On DefaultValue

Bit Addressable

AEH

00H

No

Figure 26. PWM Block Diagram

Table XVI. PWMCON SFR Bit Designations

Description

Bit

7

Name

–––

Reserved for Future Use

6

MD2

MD1

MD0

PWM Mode Bits

5

The MD2/1/0 bits choose the PWM mode as follows:

4

MD2

MD1

MD0

Mode

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Mode 0: PWM Disabled

Mode 1: SingleVariable Resolution PWM

Mode 2:Twin 8-bit PWM

Mode 3:Twin 16-bit PWM

Mode 4: Dual NRZ 16-bit - DAC

Mode 5: Dual 8-bit PWM

Mode 6: Dual RZ 16-bit - DAC

Reserved for Future Use

3

2

CDIV1

CDIV0

PWM Clock Divider.

Scale the clock source for the PWM counter as follows:

CDIV1 CDIV0 Description

0

1

0

1

0

1

PWM Counter = Selected Clock/1

PWM Counter = Selected Clock 4

PWM Counter = Selected Clock/16

PWM Counter = Selected Clock/64

1

0

CSEL1

CSEL0

PWM Clock Divider.

Select the clock source for the PWM as follows:

CSEL1 CSEL0 Description

0

1

0

1

0

1

PWM Clock = f_XTAL/15

PWM Clock = f_XTAL

PWM Clock = External Input at P3.4/T0/PWMCLK

PWM Clock = f_VCO(12.58 MHz)

–36–

REV. A

ADuC836

PWM1L

PWM MODES OF OPERATION

Mode 0: PWM Disabled

PWM COUNTER

PWM0H

PWM0L

The PWM is disabled, allowing P1.0 and P1.1 to be used as normal.

Mode 1: SingleVariable Resolution PWM

In Mode 1, both the pulse length and the cycle time (period) are

programmable in user code, allowing the resolution of the PWM

to be variable.

PWM1H

0

P1.0

P1.1

PWM1H/L sets the period of the output waveform. Reducing

PWM1H/L reduces the resolution of the PWM output but

increases the maximum output rate of the PWM (e.g., setting

PWM1H/L to 65536 gives a 16-bit PWM with a maximum

output rate of 192 Hz (12.583 MHz/65536). Setting PWM1H/L

to 4096 gives a 12-bit PWM with a maximum output rate of

3072 Hz (12.583 MHz/4096)).

Figure 28. PWM Mode 2

Mode 3:Twin 16-Bit PWM

In Mode 3, the PWM counter is ﬁxed to count from 0 to 65536,

giving a ﬁxed 16-bit PWM. Operating from the 12.58 MHz core

clock results in a PWM output rate of 192 Hz.The duty cycle of the

PWM outputs at P1.0 and P1.1 is independently programmable.

PWM0H/L sets the duty cycle of the PWM output waveform, as

shown in Figure 27.

PWM1H/L

PWM COUNTER

As in Figure 29, while the PWM counter is less than PWM0H/L,

the output of PWM0 (P1.0) is high. Once the PWM counter

equals PWM0H/L, PWM0 (P1.0) goes low and remains low until

the PWM counter rolls over.

PWM0H/L

Similarly, while the PWM counter is less than PWM1H/L, the

output of PWM1 (P1.1) is high. Once the PWM counter equals

PWM1H/L, PWM1 (P1.1) goes low and remains low until the

PWM counter rolls over.

0

P1.0

In this mode, both PWM outputs are synchronized (i.e., once the

PWM counter rolls over to 0, both PWM0 (P1.0) and PWM1

(P1.1) will go high).

Figure 27. PWM in Mode 1

Mode 2:Twin 8-Bit PWM

In Mode 2, the duty cycle of the PWM outputs and the resolution

of the PWM outputs are both programmable.The maximum

resolution of the PWM output is eight bits.

65536

PWM COUNTER

PWM1H/L

PWM1L sets the period for both PWM outputs.Typically this will

be set to 255 (FFH) to give an 8-bit PWM, although it is possible

to reduce this as necessary. A value of 100 could be loaded here

to give a percentage PWM (i.e., the PWM is accurate to 1%).

PWM0H/L

0

The outputs of the PWM at P1.0 and P1.1 are shown in Figure 28.

As can be seen, the output of PWM0 (P1.0) goes low when the

PWM counter equals PWM0L.The output of PWM1 (P1.1)

goes high when the PWM counter equals PWM1H and goes low

again when the PWM counter equals PWM0H. Setting PWM1H

to 0 ensures that both PWM outputs start simultaneously.

P1.0

P1.1

Figure 29. PWM Mode 3

REV. A

–37–

ADuC836

Mode 4: Dual NRZ 16-Bit - DAC

Mode 4 provides a high speed PWM output similar to that of a

- DAC.Typically, this mode will be used with the PWM clock

equal to 12.58 MHz.

PWM1L

PWM COUNTERS

PWM1H

PWM0L

In this mode, P1.0 and P1.1 are updated every PWM clock

(80 ns in the case of 12.58 MHz). Over any 65536 cycles (16-bit

PWM), PWM0 (P1.0) is high for PWM0H/L cycles and low for

(65536 – PWM0H/L) cycles. Similarly, PWM1 (P1.1) is high for

PWM1H/L cycles and low for (65536 – PWM1H/L) cycles.

PWM0H

0

P1.0

P1.1

If PWM1H is set to 4010H (slightly above one quarter of FS),

then typically P1.1 will be low for three clocks and high for one

clock (each clock is approximately 80 ns). Over every 65536

clocks, the PWM will compromise for the fact that the output

should be slightly above one quarter of full scale by having a high

cycle followed by only two low cycles.

Figure 31. PWM Mode 5

Mode 6: Dual RZ 16-Bit - DAC

Mode 6 provides a high speed PWM output similar to that of a

- DAC. Mode 6 operates very similarly to Mode 4. However,

the key difference is that Mode 6 provides return to zero (RZ)

- DAC output. Mode 4 provides non-return-to-zero -

DAC outputs.The RZ mode ensures that any difference in the

rise and fall times will not affect the - DAC INL. However,

the RZ Mode halves the dynamic range of the - DAC outputs

from 0AV_DDto 0AV_DD/2. For best results, this mode should

be used with a PWM clock divider of 4.

PWM0H/L = C000H

CARRY OUT AT P1.0

0

1

16-BIT

80s

16-BIT

If PWM1H is set to 4010H (slightly above one quarter of FS)

then P1.1 will typically be low for three full clocks (3  80 ns),

high for half a clock (40 ns) and then low again for half a clock

(40 ns) before repeating itself. Over every 65536 clocks, the

PWM will compromise for the fact that the output should be

slightly above one quarter of full scale by leaving the output high

for two half clocks in four every so often.

12.583MHz

16-BIT

LATCH

16-BIT

0

1

CARRY OUT AT P1.1

For faster DAC outputs (at lower resolution), write 0s to the

LSBs that are not required with a 1 in the LSB position. If, for

example, only 12-bit performance is required, write 0001 to the

4 LSBs.This means that a 12-bit accurate - DAC output can

occur at 3 kHz. Similarly, writing 00000001 to the 8 LSBs gives

an 8-bit accurate - DAC output at 49 kHz.

16-BIT

80s

PWM1H/L = 4000H

Figure 30. PWM Mode 4

For faster DAC outputs (at lower resolution), write 0s to the

LSBs that are not required with a 1 in the LSB position. If, for

example, only 12-bit performance is required, write 0001 to the

4 LSBs.This means that a 12-bit accurate - DAC output can

occur at 3 kHz. Similarly, writing 00000001 to the 8 LSBs gives

an 8-bit accurate - DAC output at 49 kHz.

PWM0H/L = C000H

CARRY OUT AT P1.0

0

1

16-BIT

318s

Mode 5: Dual 8-Bit PWM

16-BIT

In Mode 5, the duty cycle of the PWM outputs and the resolution

of the PWM outputs are individually programmable.The max-

imum resolution of the PWM output is 8 bits.

3.146MHz

16-BIT

LATCH

The output resolution is set by the PWM1L and PWM1H SFRs

for the P1.0 and P1.1 outputs, respectively. PWM0L and

PWM0H set the duty cycles of the PWM outputs at P1.0 and

P1.1, respectively. Both PWMs have the same clock source and

clock divider.

16-BIT

0

1

0

CARRY OUT AT P1.1

16-BIT

318s

PWM1H/L = 4000H

Figure 32. PWM Mode 6

–38–

REV. A

ADuC836

ON-CHIP PLL

required.The default core clock is the PLL clock divided by

8 or 1.572864 MHz.The ADC clocks are also derived from the

PLL clock, with the modulator rate being the same as the crystal

oscillator frequency.This choice of frequencies ensures that the

modulators and the core will be synchronous, regardless of the

core clock rate.The PLL control register is PLLCON.

The ADuC836 is intended for use with a 32.768 kHz watch

crystal. A PLL locks onto a multiple (384) of this to provide a

stable 12.582912 MHz clock for the system. The core can

operate at this frequency, or at binary submultiples of it, to allow

power saving in cases where maximum core performance is not

PLLCON

PLL Control Register

SFR Address

Power-On DefaultValue

Bit Addressable

D7H

03H

No

Table XVII. PLLCON SFR Bit Designations

Bit

Name

Description

Oscillator Power-Down Bit.

7

OSC_PD

Set by user to halt the 32 kHz oscillator in Power-Down mode.

Cleared by user to enable the 32 kHz oscillator in Power-Down mode.

This feature allows theTIC to continue counting even in Power-Down mode.

6

LOCK

PLL Lock Bit.This is a read-only bit.

Set automatically at power-on to indicate the PLL loop is correctly tracking the crystal clock. After

power-down, this bit can be polled to wait for the PLL to lock.

Cleared automatically at power-on to indicate the PLL is not correctly tracking the crystal clock.This may

be due to the absence of a crystal clock or an external crystal at power-on. In this mode, the PLL output

can be 12.58 MHz ± 20%. After the ADuC836 wakes up from power-down, user code may poll this bit

to wait for the PLL to lock. If LOCK = 0, then the PLL is not locked.

5

4

3

–––

Reserved for Future Use. Should be written with 0.

LTEA

FINT

Reading this bit returns the state of the external EA pin latched at reset or power-on.

Fast Interrupt Response Bit.

Set by user enabling the response to any interrupt to be executed at the fastest core clock frequency,

regardless of the conﬁguration of the CD2–0 bits (see below). After user code has returned from an interrupt,

the core resumes code execution at the core clock selected by the CD2–0 bits. Cleared by user to disable

the fast interrupt response feature.

2

1

0

CD2

CD1

CD0

CPU (Core Clock) Divider Bits.

This number determines the frequency at which the microcontroller core will operate.

CD2

CD1

CD0

Core Clock Frequency (MHz)

12.582912

6.291456

3.145728

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.572864 (Default Core Clock Frequency)

0.786432

0.393216

0.196608

0.098304

REV. A

–39–

ADuC836

TIME INTERVAL COUNTER (WAKE-UP/RTCTIMER)

A time interval counter (TIC) is provided on-chip for:

If the ADuC836 is in Power-Down mode, again withTIC inter-

rupt enabled, theTII bit will wake up the device and resume

code execution by vectoring directly to theTIC interrupt service

vector address at 0053H.TheTIC-related SFRs are described in

Table XVIII with a block diagram of theTIC shown in Figure 33.



Periodically waking up the part from power-down

Implementing a real-time clock

Counting longer intervals than the standard 8051 compatible



timers are capable of

TCEN

32.768kHz EXTERNAL CRYSTAL

TheTIC is capable of timeout intervals ranging from 1/128th

second to 255 hours. Furthermore, this counter is clocked by the

crystal oscillator rather than the by PLL, and thus has the ability to

remain active in Power-Down mode and time long power-down

intervals.This has obvious applications for remote battery-powered

sensors where regular widely, spaced readings are required.

ITS0, 1

8-BIT

PRESCALER

HUNDREDTHS COUNTER

HTHSEC

TheTIC counter can easily be used to generate a real-time

clock.The hardware will count in seconds, minutes, and hours;

however, user software will have to count in days, months, and

years.The current time can be written to the timebase SFRs

(HTHSEC, SEC, MIN, and HOUR) whileTCEN is low.When

the RTC timer is enabled (TCEN is set), theTCEN bit itself and

the HTHSEC, SEC, MIN, and HOUR Registers are not reset to

00H after a hardware or watchdog timer reset.This is to prevent

the need to recalibrate the real-time clock after a reset. However,

these registers will be reset to 00H after a power cycle (indepen-

dent ofTCEN) or after any reset ifTCEN is clear.

INTERVAL

TIMEBASE

SELECTION

MUX

TIEN

SECOND COUNTER

SEC

MINUTE COUNTER

MIN

HOUR COUNTER

HOUR

8-BIT

INTERVAL COUNTER

Six SFRs are associated with the time interval counter,TIMECON

being its control register. Depending on the conﬁguration of the

IT0 and IT1 bits inTIMECON, the selected time counter register

overﬂow will clock the interval counter.When this counter is equal

to the time interval value loaded in the INTVAL SFR, theTII

bit (TIMECON.2) is set and generates an interrupt if enabled.

(See IEIP2 SFR description under the Interrupt System section.)

INTERVAL TIMEOUT

EQUAL?

TIME INTERVAL COUNTER INTERRUPT

INTVAL SFR

Figure 33.TIC, Simpliﬁed Block Diagram

Table XVIII. TIMECON SFR Bit Designations

Bit

7

Name

–––

Description

Reserved for Future Use

6

–––

Reserved for Future Use. For future product code compatibility, this bit should be written as a 1.

IntervalTimebase Selection Bits.

5

ITS1

ITS0

4

Written by user to determine the interval counter update rate.

ITS1

ITS0

IntervalTimebase

1/128 Second

Seconds

Minutes

Hours

0

1

0

1

0

1

3

STI

SingleTime Interval Bit.

Set by user to generate a single interval timeout. If set, a timeout will clear theTIEN bit.

Cleared by user to allow the interval counter to be automatically reloaded and start counting again at each interval

timeout.

2

1

TII

TIC Interrupt Bit.

Set when the 8-bit interval counter matches the value in the INTVAL SFR.

Cleared by user software.

TIEN

Time Interval Enable Bit.

Set by user to enable the 8-bit time interval counter.

Cleared by user to disable and clear the contents of the 8-bit interval counter.To ensure that the 8-bit interval

counter is cleared,TIEN must be held low for at least 30.5 s (32 kHz).

0

TCEN

Time Clock Enable Bit.

Set by user to enable the time clock to the time interval counters.

Cleared by user to disable the 32 kHz clock to theTIC and clear the 8-bit prescaler and the HTHSEC, SEC,

MIN, and HOURS SFRs.To ensure that these registers are cleared,TCEN must be held low for at least 30.5 s

(32 kHz).The time registers (HTHSEC, SEC, MIN, and HOUR) can be written only whileTCEN is low.

–40–

REV. A

ADuC836

INTVAL

UserTime Interval Select Register

Function

User code writes the required time interval to this register.When the 8-bit interval counter is equal

to the time interval value loaded in the INTVAL SFR, theTII bit (TIMECON.2) is set and generates

an interrupt if enabled. (See IEIP2 SFR description under the Interrupt System section.)

A6H

SFR Address

Power-On DefaultValue

Reset DefaultValue

Bit Addressable

ValidValue

00H

No

0 to 255 decimal

HTHSEC

Hundredths SecondsTime Register

Function

This register is incremented in 1/128 second intervals onceTCEN inTIMECON is active.

The HTHSEC SFR counts from 0 to 127 before rolling over to increment the SEC time register.

SFR Address

A2H

00H

Power-On DefaultValue

Reset DefaultValue

Bit Addressable

ValidValue

00H if TCEN = 0, previous value before reset if TCEN = 1

No

0 to 127 decimal

SEC

SecondsTime Register

Function

This register is incremented in 1-second intervals onceTCEN inTIMECON is active.

The SEC SFR counts from 0 to 59 before rolling over to increment the MIN time register.

SFR Address

A3H

00H

Power-On DefaultValue

Reset DefaultValue

Bit Addressable

ValidValue

00H if TCEN = 0, previous value before reset if TCEN = 1

No

0 to 59 decimal

MIN

MinutesTime Register

Function

This register is incremented in 1-minute intervals onceTCEN inTIMECON is active.

The MIN counts from 0 to 59 before rolling over to increment the HOUR time register.

SFR Address

A4H

00H

Power-On DefaultValue

Reset DefaultValue

Bit Addressable

ValidValue

00H if TCEN = 0, previous value before reset if TCEN = 1

No

0 to 59 decimal

HOUR

HoursTime Register

Function

This register is incremented in 1-hour intervals onceTCEN inTIMECON is active.The HOUR SFR

counts from 0 to 23 before rolling over to 0.

SFR Address

A5H

00H

Power-On DefaultValue

Reset DefaultValue

Bit Addressable

ValidValue

00H if TCEN = 0, previous value before reset if TCEN = 1

No

0 to 23 decimal

REV. A

–41–

ADuC836

WATCHDOGTIMER

amount of time (see PRE3–0 bits inWDCON).The watchdog

timer itself is a 16-bit counter that is clocked at 32.768 kHz.The

watchdog timeout interval can be adjusted via the PRE3–0 bits in

WDCON. Full control and status of the watchdog timer function

can be controlled via theWatchdogTimer Control SFR (WDCON).

TheWDCON SFR can only be written by user software if the

double write sequence described inWDWR below is initiated on

every write access to theWDCON SFR.

The purpose of the watchdog timer is to generate a device reset

or interrupt within a reasonable amount of time if the ADuC836

enters an erroneous state, possibly due to a programming error,

electrical noise, or RFI.The watchdog function can be disabled

by clearing theWDE (Watchdog Enable) bit in theWatchdog

Control (WDCON) SFR.When enabled, the watchdog circuit will

generate a system reset or interrupt (WDS) if the user program

fails to set the watchdog (WDE) bit within a predetermined

WDCON

SFR Address

Power-On DefaultValue

Bit Addressable

WatchdogTimer Control Register

C0H

10H

Yes

Table XIX. WDCON SFR Bit Designations

Bit

7

Name

PRE3

PRE2

PRE1

PRE0

Description

WatchdogTimer Prescale Bits.

TheWatchdog timeout period is given by the equation t_WD= (2^PRE (2⁹/f_PLL))

6

5

(0  PRE  7; f_PLL= 32.768 kHz)

4

Timeout

PRE3 PRE2 PRE1 PRE0 Period (ms)

Action

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

15.6

31.2

62.5

125

250

500

1000

2000

0.0

Reset or Interrupt

Immediate Reset

Reserved

PRE3–0 > 1001

3

WDIR

Watchdog Interrupt Response Enable Bit. If this bit is set by the user, the watchdog will generate an interrupt

response instead of a system reset when the watchdog timeout period has expired.This interrupt is not disabled by

the CLR EA instruction, and it is also a ﬁxed, high priority interrupt. If the watchdog is not being used to monitor

the system, it can alternatively be used as a timer.The prescaler is used to set the timeout period in which an

interrupt will be generated. (See also Note 1,Table XXXIX in the Interrupt System section.)

2

1

WDS

WDE

Watchdog Status Bit.

Set by the watchdog controller to indicate that a watchdog timeout has occurred.

Cleared by writing a 0 or by an external hardware reset. It is not cleared by a watchdog reset.

Watchdog Enable Bit.

Set by user to enable the watchdog and clear its counters. If a 1 is not written to this bit within the watchdog timeout

period, the watchdog will generate a reset or interrupt, depending onWDIR.

Cleared under the following conditions: User writes 0, watchdog reset (WDIR = 0); hardware reset; PSM interrupt.

0

WDWR

WatchdogWrite Enable Bit.

To write data into theWDCON SFR involves a double instruction sequence.TheWDWR bit must be set and the

very next instruction must be a write instruction to theWDCON SFR. For example:

CLR

EA

; disable interrupts while writing

; to WDT

SETB

MOV

SETB

WDWR

WDCON, #72h

EA

; allow write to WDCON

; enable WDT for 2.0s timeout

; enable interrupts again (if rqd)

–42–

REV. A

ADuC836

POWER SUPPLY MONITOR

will interrupt the core using the PSMI bit in the PSMCON SFR.

This bit will not be cleared until the failing power supply has

returned above the trip point for at least 250 ms.This monitor

function allows the user to save working registers to avoid possible

data loss due to the low supply condition, and also ensures that

normal code execution will not resume until a safe supply level

has been well established.The supply monitor is also protected

against spurious glitches triggering the interrupt circuit.

As its name suggests, the Power Supply Monitor, once enabled,

monitors both supplies (AV_DDor DV_DD) on the ADuC836. It will

indicate when any of the supply pins drops below one of four

user-selectable voltage trip points from 2.63V to 4.63V. For cor-

rect operation of the Power Supply Monitor function, AV_DDmust

be equal to or greater than 2.7V. Monitor function is controlled via

the PSMCON SFR. If enabled via the IEIP2 SFR, the monitor

PSMCON

Power Supply Monitor Control Register

SFR Address

Power-On DefaultValue

Bit Addressable

DFH

DEH

No

Table XX. PSMCON SFR Bit Designations

Bit

Name

Description

DV_DDComparator Bit.

7

CMPD

This is a read-only bit and directly reﬂects the state of the DV_DDcomparator.

Read 1 indicates the DV_DDsupply is above its selected trip point.

Read 0 indicates the DV_DDsupply is below its selected trip point.

6

5

CMPA

PSMI

AV_DDComparator Bit.

This is a read-only bit and directly reﬂects the state of the AVDD comparator.

Read 1 indicates the AV_DDsupply is above its selected trip point.

Read 0 indicates the AV_DDsupply is below its selected trip point.

Power Supply Monitor Interrupt Bit.

This bit will be set high by the MicroConverter if either CMPA or CMPD are low, indicating low analog or digital

supply.The PSMI Bit can be used to interrupt the processor. Once CMPD and/or CMPA return (and remain)

high, a 250 ms counter is started.When this counter times out, the PSMI interrupt is cleared. PSMI can also be

written by the user. However, if either comparator output is low, it is not possible for the user to clear PSMI.

4

3

TPD1

TPD0

DV_DDTrip Point Selection Bits.

These bits select the DV_DDtrip point voltage as follows:

TPD1

TPD0

Selected DV_DDTrip Point (V)

0

1

0

1

0

1

4.63

3.08

2.93

2.63

2

1

TPA1

TPA0

AVDDTrip Point Selection Bits.

These bits select the AV_DDtrip point voltage as follows:

TPA1

TPA0

Selected AV_DDTrip Point (V)

0

1

0

1

0

1

4.63

3.08

2.93

2.63

0

PSMEN

Power Supply Monitor Enable Bit.

Set to 1 by the user to enable the Power Supply Monitor Circuit.

Cleared to 0 by the user to disable the Power Supply Monitor Circuit.

REV. A

–43–

ADuC836

SERIAL PERIPHERAL INTERFACE

MISO (Master In, Slave Out Data I/O Pin), Pin 14

The MISO (master in slave out) pin is conﬁgured as an input line

in Master mode and an output line in Slave mode.The MISO

line on the master (data in) should be connected to the MISO

line in the slave device (data out).The data is transferred as byte-

wide (8-bit) serial data, MSB ﬁrst.

The ADuC836 integrates a complete hardware Serial Peripheral

Interface (SPI) interface on-chip. SPI is an industry-standard

synchronous serial interface that allows eight bits of data to be

synchronously transmitted and received simultaneously, i.e., full-

duplex. It should be noted that the SPI pins SCLOCK and MOSI

are multiplexed with the I²C pins SCLOCK and SDATA.The pins

are controlled via the I2CCON SFR only if SPE is clear. SPI can

be conﬁgured for master or slave operation and typically consists of

four pins:

MOSI (Master Out, Slave In Pin), Pin 27

The MOSI (master out slave in) pin is conﬁgured as an output

line in Master mode and an input line in Slave mode.The MOSI

line on the master (data out) should be connected to the MOSI

line in the slave device (data in).The data is transferred as byte-

wide (8-bit) serial data, MSB ﬁrst.

SCLOCK (Serial Clock I/O Pin), Pin 26

The master clock (SCLOCK) is used to synchronize the data

being transmitted and received through the MOSI and MISO

data lines. A single data bit is transmitted and received in each

SCLOCK period.Therefore, a byte is transmitted/received after

eight SCLOCK periods.The SCLOCK pin is conﬁgured as an

output in master mode and as an input in Slave mode. In Master

mode, the bit rate, polarity, and phase of the clock are controlled

by the CPOL, CPHA, SPR0, and SPR1 bits in the SPICON SFR

(seeTable XXI). In Slave mode, the SPICON register will have

to be conﬁgured with the phase and polarity (CPHA and CPOL)

as the master, as for both Master and Slave modes the data is

transmitted on one edge of the SCLOCK signal and sampled on

the other.

SS (Slave Select Input Pin), Pin 13

The Slave Select (SS) input pin is only used when the ADuC836

is conﬁgured in SPI Slave mode.This line is active low. Data is

only received or transmitted in Slave mode when the SS pin is low,

allowing the ADuC836 to be used in single master, multislave SPI

conﬁgurations. If CPHA = 1, the SS input may be permanently

pulled low.With CPHA = 0, the SS input must be driven low

before the ﬁrst bit in a byte wide transmission or reception and

return high again after the last bit in that byte-wide transmission or

reception. In SPI Slave mode, the logic level on the external SS pin

(Pin 13) can be read via the SPR0 bit in the SPICON SFR.

The following SFR registers are used to control the SPI interface.

Table XXI. SPICON SFR Bit Designations

Bit

Name

Description

7

ISPI

SPI Interrupt Bit.

Set by MicroConverter at the end of each SPI transfer.

Cleared directly by user code or indirectly by reading the SPIDAT SFR.

6

5

4

3

2

WCOL

SPE

Write Collision Error Bit.

Set by MicroConverter if SPIDAT is written to while an SPI transfer is in progress.

Cleared by user code.

SPI Interface Enable Bit.

Set by user to enable the SPI interface.

Cleared by user to enable the I²C interface.

SPIM

SPI Master/Slave Mode Select Bit.

Set by user to enable Master mode operation (SCLOCK is an output).

Cleared by user to enable Slave mode operation (SCLOCK is an input).

CPOL*

CPHA*

Clock Polarity Select Bit.

Set by user if SCLOCK idles high.

Cleared by user if SCLOCK idles low.

Clock Phase Select Bit.

Set by user if leading SCLOCK edge is to transmit data.

Cleared by user if trailing SCLOCK edge is to transmit data.

1

0

SPR1

SPR0

SPI Bit Rate Select Bits.

These bits select the SCLOCK rate (bitrate) in Master mode as follows:

SPR1

SPR0

Selected Bit Rate

f_CORE/2

f_CORE/4

f_CORE/8

f_CORE/16

0

1

0

1

0

1

In SPI Slave mode, i.e., SPIM = 0, the logic level on the external SS pin (Pin 13), can be read via the SPR0 bit.

*The CPOL and CPHA bits should both contain the same values for master and slave devices.

–44–

REV. A

ADuC836

SPIDAT

SPI Data Register

Function

The SPIDAT SFR is written by the user to transmit data over the SPI interface or read by user code to read

data just received by the SPI interface.

SFR Address

Power-On DefaultValue

Bit Addressable

F7H

00H

No

SPI Interface—Master Mode

Depending on the conﬁguration of the bits in the SPICON SFR

shown inTable XXI, the ADuC836 SPI interface will transmit

or receive data in a number of possible modes. Figure 34 shows

all possible ADuC836 SPI conﬁgurations and the timing rela-

tionships and synchronization between the signals involved. Also

shown in this ﬁgure is the SPI Interrupt bit (ISPI) and how it is

triggered at the end of each byte-wide communication.

In Master mode, the SCLOCK pin is always an output and gen-

erates a burst of eight clocks whenever user code writes to the

SPIDAT Register.The SCLOCK bit rate is determined by SPR0

and SPR1 in SPICON. It should also be noted that the SS pin

is not used in Master mode. If the ADuC836 needs to assert

the SS pin on an external slave device, a port digital output pin

should be used.

SCLOCK

(CPOL = 1)

In Master mode, a byte transmission or reception is initiated

by a write to SPIDAT. Eight clock periods are generated via

the SCLOCK pin and the SPIDAT byte being transmitted via

MOSI.With each SCLOCK period, a data bit is also sampled

via MISO. After eight clocks, the transmitted byte will have been

completely transmitted and the input byte will be waiting in the

input shift register.The ISPI ﬂag will be set automatically and an

interrupt will occur if enabled.The value in the shift register will

be latched into SPIDAT.

SCLOCK

(CPOL = 0)

SS

SAMPLE INPUT

?

MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB

DATA OUTPUT

(CPHA = 1)

SPI Interface—Slave Mode

ISPI FLAG

In Slave mode, the SCLOCK is an input.The SS pin must also

be driven low externally during the byte communication.Trans-

mission is also initiated by a write to SPIDAT. In Slave mode,

a data bit is transmitted via MISO and a data bit is received via

MOSI through each input SCLOCK period. After eight clocks,

the transmitted byte will have been completely transmitted and

the input byte will be waiting in the input shift register.The ISPI

ﬂag will be set automatically and an interrupt will occur if enabled.

The value in the shift register will be latched into SPIDAT only

when the transmission/reception of a byte has been completed.

The end of transmission occurs after the eighth clock has been

received, if CPHA = 1 or when SS returns high if CPHA = 0.

SAMPLE INPUT

DATA OUTPUT

MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB

?

(CPHA = 0)

ISPI FLAG

Figure 34. SPITiming, All Modes

REV. A

–45–

ADuC836

I²C SERIAL INTERFACE

the user can enable only one interface or the other at any given

time (see SPE inTable XXI). Application Note uC001 describes

the operation of this interface as implemented and is available from

the MicroConverter website at: www.analog.com/microconverter.

Three SFRs are used to control the I²C interface. These are

described below.

The ADuC836 supports a fully licensed* I²C serial interface. The

I²C interface is implemented as a full hardware slave and soft-

ware master. SDATA (Pin 27) is the data I/O pin and SCLOCK

(Pin 26) is the serial clock. These two pins are shared with the

MOSI and SCLOCK pins of the on-chip SPI interface.Therefore

I2CCON

SFR Address

Power-On DefaultValue

Bit Addressable

I²C Control Register

E8H

00H

Yes

Table XXII. I2CCON SFR Bit Designations

Bit

Name

Description

7

MDO

I²C Software Master Data Output Bit (Master Mode Only).

This data bit is used to implement a master I²C transmitter interface in software. Data written to this bit will

be output on the SDATA pin if the data output enable (MDE) bit is set.

6

5

4

3

2

1

0

MDE

MCO

MDI

I²C Software Master Data Output Enable Bit (Master Mode Only).

Set by user to enable the SDATA pin as an output (Tx).

Cleared by user to enable SDATA pin as an input (Rx).

I²C Software Master Clock Output Bit (Master Mode Only).

This data bit is used to implement a master I²C transmitter interface in software. Data written to this bit will

be output on the SCLOCK pin.

I²C Software Master Data Input Bit (Master Mode Only).

This data bit is used to implement a master I²C receiver interface in software. Data on the SDATA pin is

latched into this bit on SCLOCK if the data output enable (MDE) bit is 0.

I2CM

I2CRS

I2CTX

I2CI

I²C Master/Slave Mode Bit.

Set by user to enable I²C software Master mode.

Cleared by user to enable I²C hardware Slave mode.

I²C Reset Bit (Slave Mode Only).

Set by user to reset the I²C interface.

Cleared by user code for normal I²C operation.

I²C DirectionTransfer Bit (Slave Mode Only).

Set by MicroConverter if the interface is transmitting.

Cleared by the MicroConverter if the interface is receiving.

I²C Interrupt Bit (Slave Mode Only).

Set by the MicroConverter after a byte has been transmitted or received.

Cleared automatically when the user code reads the I2CDAT SFR (see I2CDAT below).

I2CADD

Function

I²C Address Register

Holds the I²C peripheral address for the part. It may be overwritten by the user code. Application Note uC001

at www.analog.com/microconverter describes the format of the I²C standard 7-bit address in detail.

9BH

SFR Address

Power-On DefaultValue 55H

Bit Addressable

No

I2CDAT

Function

I²C Data Register

The I2CDAT SFR is written by the user to transmit data over the I²C interface or read by user code to read

data just received by the I²C interface. Accessing I2CDAT automatically clears any pending I²C interrupt

and the I2CI bit in the I2CCON SFR. User software should access I2CDAT only once per interrupt cycle.

9AH

SFR Address

Power-On DefaultValue 00H

Bit Addressable No

*Purchase of licensed I²C components of Analog Devices or one of its sublicensed associated companies conveys a license for the purchaser under the Philips I²C

Patent Rights to use these components in an I²C system provided that the system conforms to the I²C Standard Speciﬁcation as deﬁned by Philips.

–46–

REV. A

ADuC836

The main features of the MicroConverter I²C interface are:

Once enabled in I²C Slave mode, the slave controller waits for

a START condition. If the ADuC836 detects a valid start con-

dition followed by a valid address, and by the R/W bit, the I2CI

interrupt bit will be automatically set by hardware.



Only two bus lines are required: a serial data line (SDATA)

and a serial clock line (SCLOCK).

An I²C master can communicate with multiple slave devices.



Because each slave device has a unique 7-bit address, single

master/slave relationships can exist at all times even in a

multislave environment (Figure 35).

The I²C peripheral will only generate a core interrupt if the user

has preconﬁgured the I²C interrupt enable bit in the IEIP2 SFR

as well as the global interrupt Bit EA in the IE SFR, i.e.,



On-chip ﬁltering rejects <50 ns spikes on the SDATA and

; Enabling I2C Interrupts for the ADuC836

MOV IEIP2,#01h ; enable I2C interrupt

SETB EA

SCLOCK lines to preserve data integrity.

DV

DD

On the ADuC836, an auto clear of the I2CI bit is implemented

so this bit is cleared automatically on a read or write access to the

I2CDAT SFR.

2

I C

MASTER

SLAVE #1

MOV I2CDAT, A ; I2CI auto-cleared

MOV A, I2CDAT ; I2CI auto-cleared

2

If for any reason the user tries to clear the interrupt more than

once, i.e., access the data SFR more than once per interrupt,

then the I²C controller will halt.The interface will then have to

be reset using the I2CRS bit.

I C

SLAVE #2

Figure 35. Typical I²C System

The user can choose to poll the I2CI bit or enable the interrupt.

In the case of the interrupt, the PC counter will vector to 003BH

at the end of each complete byte. For the ﬁrst byte when the user

gets to the I2CI ISR, the 7-bit address and the R/W bit will appear

in the I2CDAT SFR.

Software Master Mode

The ADuC836 can be used as an I²C master device by conﬁguring

the I²C peripheral in Master mode and writing software to output

the data bit by bit, which is referred to as a software master. Master

mode is enabled by setting the I2CM bit in the I2CCON register.

The I2CTX bit contains the R/W bit sent from the master. If

I2CTX is set, the master would like to receive a byte.Therefore,

the slave will transmit data by writing to the I2CDAT register.

If I2CTX is cleared, the master would like to transmit a byte.

Therefore, the slave will receive a serial byte.The software can

interrogate the state of I2CTX to determine whether it should

write to or read from I2CDAT.

To transmit data on the SDATA line, MDE must be set to enable

the output driver on the SDATA pin. If MDE is set, the SDATA

pin will be pulled high or low depending on whether the MDO

bit is set or cleared. MCO controls the SCLOCK pin and is

always conﬁgured as an output in Master mode. In Master mode,

the SCLOCK pin will be pulled high or low depending on the

whether MCO is set or cleared.

Once the ADuC836 has received a valid address, hardware will

hold SCLOCK low until the I2CI bit is cleared by the software.

This allows the master to wait for the slave to be ready before

transmitting the clocks for the next byte.

To receive data, MDE must be cleared to disable the output driver

on SDATA. Software must provide the clocks by toggling the

MCO bit and reading the SDATA pin via the MDI bit. If MDE

is cleared, MDI can be used to read the SDATA pin.The value of

the SDATA pin is latched into MDI on a rising edge of SCLOCK.

MDI is set if the SDATA pin was high on the last rising edge of

SCLOCK. MDI is clear if the SDATA pin was low on the last

rising edge of SCLOCK.

The I2CI interrupt bit will be set every time a complete data byte

is received or transmitted provided it is followed by a valid ACK.

If the byte is followed by a NACK, an interrupt is generated.The

ADuC836 will continue to issue interrupts for each complete

data byte transferred until a STOP condition is received or the

interface is reset.

Software must control MDO, MCO, and MDE appropriately to

generate the START condition, slave address, acknowledge bits,

data bytes, and STOP conditions.These functions are provided

in Application Note uC001.

When a STOP condition is received, the interface will reset to a

state where it is waiting to be addressed (idle). Similarly, if the

interface receives a NACK at the end of a sequence, it also returns

to the default idle state.The I2CRS bit can be used to reset the

I²C interface.This bit can be used to force the interface back to

the default idle state.

Hardware Slave Mode

After reset, the ADuC836 defaults to hardware Slave mode.The

I²C interface is enabled by clearing the SPE bit in SPICON.

Slave mode is enabled by clearing the I2CM bit in I2CCON.

The ADuC836 has a full hardware slave. In Slave mode, the I²C

address is stored in the I2CADD register. Data received or to be

transmitted is stored in the I2CDAT register.

It should be noted that there is no way (in hardware) to distinguish

between an interrupt generated by a received START + valid

address and an interrupt generated by a received data byte. User

software must be used to distinguish between these interrupts.

REV. A

–47–

ADuC836

DUAL DATA POINTER

DPCON

Data Pointer Control SFR

The ADuC836 incorporates both main and shadow data pointers.

The shadow data pointer is selected via the data pointer control

SFR (DPCON). DPCON also includes features such as automatic

hardware post-increment and post-decrement, as well as automatic

data pointer toggle. DPCON is described inTable XXIII.

SFR Address

Power-On DefaultValue

Bit Addressable

A7H

00H

No

Table XXIII. DPCON SFR Bit Designations

Bit

7

Name

–––

Description

Reserved for Future Use

6

DPT

Data Pointer AutomaticToggle Enable.

Cleared by user to disable auto swapping of the DPTR.

Set in user software to enable automatic toggling of the DPTR after each MOVX or MOVC instruction.

5

4

DP1m1

DP1m0

Shadow Data Pointer Mode.

These two bits enable extra modes of the shadow data pointer operation, allowing for more compact and more

efﬁcient code size and execution.

m1

0

1

m0

0

1

0

1

Behavior of the Shadow Data Pointer

8052 Behavior

DPTR is post-incremented after a MOVX or MOVC instruction.

DPTR is post-decremented after a MOVX or MOVC instruction.

DPTR LSB is toggled after a MOVX or MOVC instruction.

(This instruction can be useful for moving 8-bit blocks to/from 16-bit devices.)

3

2

DP0m1

DP0m0

Main Data Pointer Mode.

These two bits enable extra modes of the main data pointer operation, allowing for more compact and more

efﬁcient code size and execution.

m1

0

1

m0

0

1

0

1

Behavior of the Main Data Pointer

8052 Behavior

DPTR is post-incremented after a MOVX or MOVC instruction.

DPTR is post-decremented after a MOVX or MOVC instruction.

DPTR LSB is toggled aftera MOVX or MOVC instruction.

(This instruction can be useful for moving 8-bit blocks to/from 16-bit devices.)

1

0

–––

This bit is not implemented to allow the INC DPCON instruction to toggle the data pointer without incre-

menting the rest of the SFR.

DPSEL

Data Pointer Select.

Cleared by user to select the main data pointer.This means that the contents of the main 24-bit DPTR appears

in the three SFRs: DPL, DPH, and DPP.

Set by user to select the shadow data pointer.This means that the contents of the shadow 24-bit DPTR

appears in the three SFRs: DPL, DPH, and DPP.

NOTES

1. This is the only place where the main and shadow data pointers are distinguished. Everywhere else in this data sheet, wherever the DPTR is mentioned, operation on the

active DPTR is implied.

2. Only MOVC/MOVX @DPTR instructions are relevant above. MOVC/MOVX PC/@Ri instructions will not cause the DPTR to automatically post increment/decrement,

and so on.To illustrate the operation of DPCON, the following code will copy 256 bytes of code memory at address D000H into XRAM starting from address 0000H.

the code uses 16 bytes and 2054 cycles.To perform this on a standard 8051 requires approximately 33 bytes and 7172 cycles (depending on how it is implemented).

MOV DPTR,#0

MOV DPCON,#55h

; Main DPTR = 0

MOVC A,@A+DPTR

MOVX @DPTR,A

; Get data

; Post Inc DPTR

; Swap to Main DPTR (Data)

; Put ACC in XRAM

; Increment main DPTR

; Swap to Shad DPTR (Code)

; Select shadow DPTR

; DPTR1 increment mode,

; DPTR0 increment mode

; DPTR auto toggling ON

MOV DPTR,#0D000h ; Shadow DPTR = D000h

MOVELOOP:

CLR

MOV A, DPL

JNZ MOVELOOP

A

–48–

REV. A

ADuC836

8052 COMPATIBLE ON-CHIP PERIPHERALS

This section gives a brief overview of the various secondary

peripheral circuits, which are also available to the user on-chip.

These remaining functions are mostly 8052 compatible (with

a few additional features) and are controlled via standard 8052

SFR bit deﬁnitions.

Port 1

Port 1 is also an 8-bit port directly controlled via the P1 SFR.

The Port 1 pins are divided into two distinct pin groupings: P1.0

to P1.1 and P1.2 to P1.7.

P1.0 and P1.1

P1.0 and P1.1 are bidirectional digital I/O pins with internal

pull-ups.

Parallel I/O

The ADuC836 uses four input/output ports to exchange data

with external devices. In addition to performing general-purpose

I/O, some ports are capable of external memory operations while

others are multiplexed with alternate functions for the peripheral

features on the device. In general, when a peripheral is enabled,

that pin may not be used as a general-purpose I/O pin.

If P1.0 and P1.1 have 1s written to them via the P1 SFR, they are

pulled high by the internal pull-up resistors. In this state, they can

also be used as inputs. As input pins being externally pulled low,

they will source current because of the internal pull-ups.With 0s

written to them, both of these pins will drive a logic low output

voltage (V_OL) and will be capable of sinking 10 mA compared to

the standard 1.6 mA sink capability on the other port pins.

Port 0

Port 0 is an 8-bit open-drain bidirectional I/O port that is directly

controlled via the Port 0 SFR. Port 0 is also the multiplexed low

order address and data bus during accesses to external program

or data memory.

These pins also have various secondary functions described in

Table XXIV.TheTimer 2 alternate functions of P1.0 and P1.1

can only be activated if the corresponding bit latch in the P1 SFR

contains a 1. Otherwise, the port pin is stuck at 0. In the case of

the PWM outputs at P1.0 and P1.1, the PWM outputs will over-

write anything written to P1.0 or P1.1.

Figure 36 shows a typical bit latch and I/O buffer for a Port 0

port pin.The bit latch (one bit in the port’s SFR) is represented

as aType D ﬂip-ﬂop, which will clock in a value from the internal

bus in response to a “write to latch” signal from the CPU.The Q

output of the ﬂip-ﬂop is placed on the internal bus in response to

a “read latch” signal from the CPU.The level of the port pin itself

is placed on the internal bus in response to a “read pin” signal

from the CPU. Some instructions that read a port activate the

“read latch” signal, and others activate the “read pin” signal. See

the Read-Modify-Write Instructions section for more details.

Table XXIV. P1.0 and P1.1 Alternate Pin Functions

Alternate Function

P1.0

T2 (Timer/Counter 2 External Input)

PWM0 (PWM0 output at this pin)

P1.1

T2EX (Timer/Counter 2 Capture/ReloadTrigger)

PWM1 (PWM1 output at this pin)

Figure 37 shows a typical bit latch and I/O buffer for a P1.0 or

P1.1 port pin. No external memory access is required from either

of these pins, although internal pull-ups are present.

ADDR/DATA

DV

DD

CONTROL

READ

LATCH

DV

DD

P0.x

ALTERNATE

OUTPUT FUNCTION

INTERNAL

BUS

INTERNAL

PULL-UP*

READ

LATCH

D

Q

P1.x

WRITE

TO LATCH

CL

LATCH

Q

INTERNAL

BUS

D

Q

WRITE

TO LATCH

READ

CL

LATCH

Q

READ

Figure 36. Port 0 Bit Latch and I/O Buffer

*SEE FIGURE 38

FOR DETAILS OF

INTERNAL PULL-UP

ALTERNATE

INPUT

As shown in Figure 36, the output drivers of Port 0 pins are

switchable to an internal ADDR and ADDR/DATA bus by an

internal CONTROL signal for use in external memory accesses.

During external memory accesses, the P0 SFR is written with

1s (i.e., all of its bit latches become 1s).When accessing external

memory, the CONTROL signal in Figure 36 goes high, enabling

push-pull operation of the output pin from the internal address

or data bus (ADDR/DATA line).Therefore, no external pull-ups

are required on Port 0 for it to access external memory.

FUNCTION

Figure 37. P1.0 and P1.1 Bit Latch and I/O Buffer

The internal pull-up consists of active circuitry, as shown in

Figure 38.Whenever a P1.0 or P1.1 bit latch transitions from low

to high, Q1 in Figure 38 turns on for two oscillator periods to

quickly pull the pin to a logic high state. Once there, the weaker

Q3 turns on, thereby latching the pin to a logic high. If the pin

is momentarily pulled low externally, Q3 will turn off, but the

very weak Q2 will continue to source some current into the pin,

attempting to restore it to a logic high.

In general-purpose I/O port mode, Port 0 pins that have 1s writ-

ten to them via the Port 0 SFR will be conﬁgured as open-drain

and therefore will ﬂoat. In this state, Port 0 pins can be used as

high impedance inputs.This is represented in Figure 36 by the

NAND gate whose output remains high as long as the CONTROL

signal is low, thereby disabling the top FET. External pull-up

resistors are therefore required when Port 0 pins are used as

general-purpose outputs. Port 0 pins with 0s written to them will

drive a logic low output voltage (V_OL) and will be capable of sink-

ing 1.6 mA.

DV

DD

Q1

Q2

Q3

2 CLK

DELAY

Px.x

Q

FROM

PORT

Q4

LATCH

Figure 38. Internal Pull-Up Conﬁguration

REV. A

–49–

ADuC836

P1.2 to P1.7

Port 3 pins also have various secondary functions described in

Table XXV.The alternate functions of Port 3 pins can be activated

only if the corresponding bit latch in the P3 SFR contains a 1.

Otherwise, the port pin is stuck at 0.

The remaining Port 1 pins (P1.2 to P1.7) can only be conﬁgured as

analog input (ADC) or digital input pins. By (power-on) default,

these pins are conﬁgured as analog inputs, i.e., 1 written in the

corresponding Port 1 register bit.To conﬁgure any of these pins

as digital inputs, the user should write a 0 to these port bits to

conﬁgure the corresponding pin as a high impedance digital input.

Figure 39 illustrates this function. Note that there are no output

drivers for Port 1 pins, and they therefore cannot be used as

outputs.

Table XXV. Port 3, Alternate Pin Functions

Alternate Function

P3.0

RxD (UART Input Pin)

(or Serial Data I/O in Mode 0)

TxD (UART Output Pin)

P3.1

READ

LATCH

(or Serial Clock Output in Mode 0)

INT0 (External Interrupt 0)

INT1 (External Interrupt 1)

T0 (Timer/Counter 0 External Input)

PWMCLK (PWM External Clock)

T1 (Timer/Counter 1 External Input)

WR (External Data MemoryWrite Strobe)

RD (External Data Memory Read Strobe)

P3.2

P3.3

P3.4

INTERNAL

D

Q

BUS

WRITE

CL

Q

TO LATCH

LATCH

P1.x

P3.5

P3.6

P3.7

READ

TO ADC

Figure 39. P1.2 to P1.7 Bit Latch and I/O Buffer

Port 2

Port 3 pins have the same bit latch and I/O buffer conﬁgurations

as the P1.0 and P1.1, as shown in Figure 41.The internal pull-up

conﬁguration is also deﬁned by the one in Figure 38.

Port 2 is a bidirectional port with internal pull-up resistors directly

controlled via the P2 SFR. Port 2 also emits the high order address

bytes during fetches from external program memory and middle

and high order address bytes during accesses to the 24-bit external

data memory space.

DV

DD

ALTERNATE

OUTPUT

FUNCTION

INTERNAL

PULL-UP*

READ

LATCH

As shown in Figure 40, the output drivers of Port 2 are switchable

to an internal ADDR bus by an internal CONTROL signal for use

in external memory accesses (as for Port 0). In external memory

addressing mode (CONTROL = 1), the port pins feature push/

pull operation controlled by the internal address bus (ADDR line).

However, unlike the P0 SFR during external memory accesses,

the P2 SFR remains unchanged.

P3.x

INTERNAL

BUS

D

Q

WRITE

TO LATCH

CL

Q

LATCH

READ

*SEE FIGURE 38

FOR DETAILS OF

INTERNAL PULL-UP

ALTERNATE

INPUT

FUNCTION

In general-purpose I/O port mode, Port 2 pins that have 1s written

to them are pulled high by the internal pull-ups (Figure 38), and in

that state can be used as inputs. As inputs, Port 2 pins being pulled

externally low will source current because of the internal pull-up

resistors. Port 2 pins with 0s written to them will drive a logic low

output voltage (V_OL) and will be capable of sinking 1.6 mA.

ADDR

Figure 41. Port 3 Bit Latch and I/O Buffer

Additional Digital I/O

In addition to the port pins, the dedicated SPI/I2C pins (SCLOCK

and SDATA/MOSI) also feature both input and output functions.

Their equivalent I/O architectures are illustrated in Figure 42 and

Figure 44, respectively, for SPI operation, and in Figure 43 and

Figure 45 for I²C operation.

Notice that in I²C mode (SPE = 0), the strong pull-up FET (Q1) is

disabled leaving only a weak pull-up (Q2) present. By contrast, in

SPI mode (SPE = 1), the strong pull-up FET (Q1) is controlled

directly by SPI hardware, giving the pin push/pull capability.

READ

LATCH

DV

DD

CONTROL

INTERNAL

PULL-UP*

INTERNAL

BUS

D

Q

P2.x

WRITE

TO LATCH

CL

Q

LATCH

READ

*SEE FIGURE 38 FOR

DETAILS OF INTERNAL PULL-UP

In I²C mode (SPE = 0), two pull-down FETs (Q3 and Q4)

operate in parallel in order to provide an extra 60% or 70% of

current sinking capability. In SPI mode, however, (SPE = 1), only

one of the pull-down FETs (Q3) operates on each pin resulting

in sink capabilities identical to that of Port 0 and Port 2 pins.

Figure 40. Port 2 Bit Latch and I/O Buffer

Port 3

Port 3 is a bidirectional port with internal pull-ups directly controlled

via the P3 SFR.

Port 3 pins that have 1s written to them are pulled high by the

internal pull-ups, and in that state can be used as inputs. As inputs,

Port 3 pins being pulled externally low will source current because

of the internal pull-ups. Port 3 pins with 0s written to them will

drive a logic low output voltage (V_OL) and will be capable of sink-

ing 1.6 mA.

On the input path of SCLOCK, notice that a Schmitt trigger

conditions the signal going to the SPI hardware to prevent false

triggers (double triggers) on slow incoming edges. For incoming

signals from the SCLOCK and SDATA pins going to I²C hardware,

a ﬁlter conditions the signals to reject glitches of up to 50 ns in

duration.

–50–

REV. A

ADuC836

Notice also that direct access to the SCLOCK and SDATA/MOSI

pins is afforded through the SFR interface in I²C master mode.

Therefore, if you are not using the SPI or I²C functions, you can

use these two pins to provide additional high current digital outputs.

As shown in Figure 46, the MISO pin in SPI master/slave opera-

tion offers the exact same pull-up and pull-down conﬁguration as

the MOSI pin in SPI slave/master operation.

The SS pin has a weak internal pull-up permanently enabled to

prevent the SS input from ﬂoating.This pull-up can be easily

overdriven by an external device to drive the SS pin low.

DV

DD

SPE = 1 (SPI ENABLE)

Q1

DV

DD

Q2 (OFF)

Q4 (OFF)

HARDWARE SPI

(MASTER/SLAVE)

SCLOCK

SCHMITT

TRIGGER

HARDWARE SPI

(MASTER/SLAVE)

MISO

Q3

Figure 42. SCLOCK Pin I/O Functional Equivalent

in SPI Mode

Figure 46. MISO Pin I/O Functional Equivalent

DV

DD

2

SPE = 0 (I C ENABLE)

DV

DD

2

HARDWARE I C

Q1

(OFF)

(SLAVE ONLY)

Q2

Q4

50ns GLITCH

REJECTION FILTER

SFR

HARDWARE SPI

(MASTER/SLAVE)

SS

BITS

SCLOCK

MCO

Figure 47. SS Pin I/O Functional Equivalent

Read-Modify-Write Instructions

Q3

2

I CM

Some 8051 instructions that read a port, read the latch and

others read the pin.The instructions that read the latch rather

than the pins are the ones that read a value, possibly change it,

and then rewrite it to the latch.These are called “read-modify-

write” instructions. which are listed below.When the destination

operand is a port or a port bit, these instructions read the latch

rather than the pin.

Figure 43. SCLOCK Pin I/O Functional Equivalent

in I²C Mode

DV

DD

SPE = 1 (SPI ENABLE)

Q1

Q2 (OFF)

Q4 (OFF)

ANL

ORL

XRL

JBC

(Logical AND, e.g., ANL P1, A)

(Logical OR, e.g., ORL P2, A)

(Logical EX-OR, e.g., XRL P3, A)

(Jump If Bit = 1 and Clear Bit,

e.g., JBC P1.1, LABEL

(Complement Bit, e.g., CPL P3.0)

(Increment, e.g., INC P2)

(Decrement, e.g., DEC P2)

SDATA/

MOSI

HARDWARE SPI

(MASTER/SLAVE)

Q3

CPL

INC

DEC

DJNZ

(Decrement and Jump IFf Not Zero,

e.g.,DJNZ P3, LABEL)

Figure 44. SDATA/MOSI Pin I/O Functional Equivalent

in SPI Mode

MOV PX.Y, C* (Move Carry to Bit Y of Port X)

DV

DD

CLR PX.Y*

(Clear Bit Y of Port X)

2

SETB PX.Y*

(Set Bit Y of Port X)

SPE = 0 (I C ENABLE)

Q1

2

HARDWARE I C

(OFF)

*These instructions read the port byte (all eight bytes), modify the addressed bit

and then write the new byte back to the latch.

(SLAVE ONLY)

SFR

Q2

BITS

50ns GLITCH

REJECTION FILTER

SDATA/

The reason that read-modify-write instructions are directed to

the latch rather than to the pin is to avoid a possible misinter-

pretation of the voltage level of a pin. For example, a port pin

might be used to drive the base of a transistor.When a 1 is written

to the bit, the transistor is turned on. If the CPU then reads the

same port bit at the pin rather than the latch, it will read the base

voltage of the transistor and interpret it as a Logic 0. Reading the

latch rather than the pin will return the correct value of 1.

MDI

MOSI

Q4

MDO

MDE

I2CM

Q3

Figure 45. SDATA/MOSI Pin I/O Functional Equivalent

in I²C Mode

REV. A

–51–

ADuC836

TIMERS/COUNTERS

every machine cycle.When the samples show a high in one cycle

and a low in the next cycle, the count is incremented.The new

count value appears in the register during S3P1 of the cycle fol-

lowing the one in which the transition was detected. Since it takes

two machine cycles (16 core clock periods) to recognize a 1-to-0

transition, the maximum count rate is 1/16 of the core clock fre-

quency.There are no restrictions on the duty cycle of the external

input signal, but to ensure that a given level is sampled at least

once before it changes, it must be held for a minimum of one full

machine cycle. Remember that the core clock frequency is pro-

grammed via the CD0–2 selection bits in the PLLCON SFR.

The ADuC836 has three 16-bitTimer/Counters:Timer 0,Timer 1,

andTimer 2.TheTimer/Counter hardware has been included

on-chip to relieve the processor core of the overhead inherent in

implementing timer/counter functionality in software. Each

Timer/Counter consists of two 8-bit registers:THx and TLx

(x = 0, 1, and 2). All three can be conﬁgured to operate either as

timers or event counters.

InTimer function, theTLx Register is incremented every machine

cycle.Thus it can be viewed as counting machine cycles. Since

a machine cycle consists of 12 core clock periods, the maximum

count rate is 1/12 of the core clock frequency.

User conﬁguration and control of the timers is achieved via three

main SFRs:TMOD andTCON control the conﬁguration of

Timers 0 and 1, whileT2CON conﬁguresTimer 2.

In Counter function, theTLx Register is incremented by a 1-to-0

transition at its corresponding external input pin,T0,T1, orT2.

In this function, the external input is sampled during S5P2 of

TMOD

Timer/Counter 0 and 1 Mode Register

SFR Address

Power-On DefaultValue

Bit Addressable

89H

00H

No

Table XXVI. TMOD SFR Bit Designations

Bit

Name

Description

Timer 1 Gating Control.

7

Gate

Set by software to enableTimer/Counter 1 only while INT1 pin is high andTR1 control bit is set.

Cleared by software to enableTimer 1 wheneverTR1 control bit is set.

6

C/T

Timer 1Timer or Counter Select Bit.

Set by software to select counter operation (input fromT1 pin).

Cleared by software to select timer operation (input from internal system clock).

5

4

M1

M0

Timer 1 Mode Select Bit 1 (used with M0 Bit)

Timer 1 Mode Select Bit 0.

M1

0

M0

0

1

TH1 operates as an 8-bit timer/counter.TL1 serves as 5-bit prescaler.

16-BitTimer/Counter.TH1 andTL1 are cascaded; there is no prescaler.

8-Bit AutoreloadTimer/Counter.TH1 holds a value that is to be reloaded intoTL1 each

time it overﬂows.

0

1

0

1

Timer/Counter 1 stopped.

3

2

Gate

Timer 0 Gating Control.

Set by software to enableTimer/Counter 0 only while INT0 pin is high andTR0 control bit is set.

Cleared by software to enableTimer 0 wheneverTR0 control bit is set.

C/T

Timer 0Timer or Counter Select Bit.

Set by software to select counter operation (input fromT0 pin).

Cleared by software to select timer operation (input from internal system clock).

1

0

M1

M0

Timer 0 Mode Select Bit 1

Timer 0 Mode Select Bit 0.

M1

0

M0

0

TH0 operates as an 8-bit timer/counter.TL0 serves as 5-bit prescaler.

16-BitTimer/Counter.TH0 andTL0 are cascaded; there is no prescaler.

8-Bit AutoreloadTimer/Counter.TH0 holds a value that is to be reloaded intoTL0 each time

it overﬂows.

TL0 is an 8-bit timer/counter controlled by the standardTimer 0 control bits.TH0 is an 8-bit

timer only, controlled byTimer 1 control bits.

0

1

0

1

–52–

REV. A

ADuC836

TCON

Timer/Counter 0 and 1 Control Register

SFR Address

Power-On DefaultValue

Bit Addressable

88H

00H

Yes

Table XXVII. TCON SFR Bit Designations

Bit

Name Description

7

TF1

TR1

TF0

TR0

IE1*

Timer 1 Overﬂow Flag.

Set by hardware on aTimer/Counter 1 overﬂow.

Cleared by hardware when the Program Counter (PC) vectors to the interrupt service routine.

6

5

4

3

Timer 1 Run Control Bit.

Set by user to turn onTimer/Counter 1.

Cleared by user to turn offTimer/Counter 1.

Timer 0 Overﬂow Flag.

Set by hardware on aTimer/Counter 0 overﬂow.

Cleared by hardware when the PC vectors to the interrupt service routine.

Timer 0 Run Control Bit.

Set by user to turn onTimer/Counter 0.

Cleared by user to turn offTimer/Counter 0.

External Interrupt 1 (INT1) Flag.

Set by hardware by a falling edge or zero level being applied to external interrupt pin INT1, depending on bit IT1 state.

Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition-

activated. If level-activated, the external requesting source rather than the on-chip hardware, controls the request ﬂag.

2

1

IT1*

IE0*

External Interrupt 1 (IE1)TriggerType.

Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition).

Cleared by software to specify level-sensitive detection (i.e., zero level).

External Interrupt 0 (INT0) Flag.

Set by hardware by a falling edge or zero level being applied to external interrupt pin INT0, depending on bit IT0 state.

Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition-

activated. If level-activated, the external requesting source controls the request ﬂag, rather than the on-chip hardware.

0

IT0*

External Interrupt 0 (IE0)TriggerType.

Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition).

Cleared by software to specify level-sensitive detection (i.e., zero level).

*These bits are not used in the control ofTimer/Counter 0 and 1, but are used instead in the control and monitoring of the external INT0 and INT1 interrupt pins.

Timer/Counter 0 and 1 Data Registers

BothTimer 0 andTimer 1 consist of two 8-bit registers.These can be used as independent registers or combined to be a single 16-bit

register, depending on the timer mode conﬁguration.

TH0 andTL0

Timer 0 high byte and low byte.

SFR Address = 8CH, 8AH, respectively.

TH1 andTL1

Timer 1 high byte and low byte.

SFR Address = 8DH, 8BH, respectively.

REV. A

–53–

ADuC836

TIMER/COUNTER 0 AND 1 OPERATING MODES

Mode 2 (8-BitTimer/Counter with Auto Reload)

The following paragraphs describe the operating modes forTimer/

Counters 0 and 1. Unless otherwise noted, it should be assumed

that these modes of operation are the same for bothTimer 0 and 1.

Mode 2 conﬁgures the timer register as an 8-bit counter (TL0)

with automatic reload, as shown in Figure 50. Overﬂow fromTL0

not only setsTF0, but also reloadsTL0 with the contents ofTH0,

which are preset by software.The reload leavesTH0 unchanged.

Mode 0 (13-BitTimer/Counter)

Mode 0 conﬁgures an 8-bit timer/counter with a divide-by-32

prescaler. Figure 48 shows Mode 0 operation.

CORE

 12

CLK

*

C/T = 0

C/T = 1

INTERRUPT

CORE

 12

TL0

(8 BITS)

TF0

CLK*

C/T = 0

INTERRUPT

TL0

TH0

P3.4/T0

TF0

(5 BITS) (8 BITS)

CONTROL

C/T = 1

TR0

P3.4/T0

CONTROL

RELOAD

TH0

(8 BITS)

GATE

P3.2/INT0

TR0

*THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)

GATE

P3.2/INT0

Figure 50. Timer/Counter 0, Mode 2

*THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)

Mode 3 (Two 8-BitTimer/Counters)

Figure 48. Timer/Counter 0, Mode 0

Mode 3 has different effects onTimer 0 andTimer 1.Timer 1 in

Mode 3 simply holds its count.The effect is the same as setting

TR1 = 0.Timer 0 in Mode 3 establishesTL0 andTH0 as two

separate counters.This conﬁguration is shown in Figure 51.TL0

uses theTimer 0 control bits: C/T, Gate,TR0, INT0, andTF0.

TH0 is locked into a timer function (counting machine cycles)

and takes over the use ofTR1 andTF1 fromTimer 1.Thus,TH0

now controls theTimer 1 interrupt. Mode 3 is provided for appli-

cations requiring an extra 8-bit timer or counter.

In this mode, the timer register is conﬁgured as a 13-bit register.

As the count rolls over from all 1s to all 0s, it sets the timer over-

ﬂow ﬂag.The overﬂow ﬂag,TF0, can then be used to request an

interrupt.The counted input is enabled to the timer whenTR0 = 1

and either Gate = 0 or INT0 = 1. Setting Gate = 1 allows the

timer to be controlled by external input INT0 to facilitate pulse-

width measurements.TR0 is a control bit in the special function

registerTCON; Gate is inTMOD.The 13-bit register consists

of all eight bits ofTH0 and the lower ﬁve bits ofTL0.The upper

three bits ofTL0 are indeterminate and should be ignored. Setting

the run ﬂag (TR0) does not clear the registers.

WhenTimer 0 is in Mode 3,Timer 1 can be turned on and off by

switching it out of and into its own Mode 3, or it can still be used by

the serial interface as a baud rate generator. In fact, it can be used in

any application not requiring an interrupt fromTimer 1 itself.

Mode 1 (16-BitTimer/Counter)

Mode 1 is the same as Mode 0, except that the timer register is

running with all 16 bits. Mode 1 is shown in Figure 49.

CORE

CLK

CORE

CLK/12

 12

*

C/T = 0

C/T = 1

INTERRUPT

CORE

TL0

(8 BITS)

TF0

 12

CLK

*

C/T = 0

C/T = 1

INTERRUPT

TL0

TH0

P3.4/T0

TF0

(8 BITS) (8 BITS)

CONTROL

TR0

P3.4/T0

CONTROL

GATE

TR0

P3.2/INT0

INTERRUPT

GATE

P3.2/INT0

TH0

(8 BITS)

CORE

CLK/12

TF1

TR1

*THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)

Figure 49.Timer/Counter 0, Mode 1

Figure 51.Timer/Counter 0, Mode 3

–54–

REV. A

ADuC836

TIMER/COUNTER 2 OPERATING MODES

16-Bit Capture Mode

The following paragraphs describe the operating modes for

Timer/Counter 2.The operating modes are selected by bits in the

T2CON SFR, as shown inTable XXIX.

Capture Mode has two options, which are selected by bit EXEN2

inT2CON. If EXEN2 = 0,Timer 2 is a 16-bit timer or counter

that, upon overﬂowing, sets bitTF2, theTimer 2 overﬂow bit,

which can be used to generate an interrupt. If EXEN2 = 1,Timer 2

still performs the above, but a l-to-0 transition on external input

T2EX causes the current value in the Timer 2 registers,TL2

andTH2, to be captured into registers RCAP2L and RCAP2H,

respectively. In addition, the transition atT2EX causes bit EXF2

inT2CON to be set; EXF2, likeTF2, can generate an interrupt.

Capture mode is illustrated in Figure 53.

Table XXVIII. Timer 2 Operating Modes

RCLK (or)TCLK

CAP2

TR2

MODE

0

1

X

0

1

X

1

0

16-Bit Autoreload

16-Bit Capture

Baud Rate

OFF

The baud rate generator mode is selected by RCLK = 1 and/or

TCLK = 1.

16-Bit Autoreload Mode

Autoreload mode has two options, which are selected by bit

EXEN2 inT2CON. If EXEN2 = 0, whenTimer 2 rolls over,

it not only setsTF2 but also causes theTimer 2 registers to be

reloaded with the 16-bit value in registers RCAP2L and RCAP2H,

which are preset by software. If EXEN2 = 1,Timer 2 still

performs the above, but with the added feature that a 1-to-0 tran-

sition at external inputT2EX will also trigger the 16-bit reload

and set EXF2.The Autoreload mode is illustrated in Figure 52.

In either case, if Timer 2 is being used to generate the baud rate,

theTF2 interrupt ﬂag will not occur.ThereforeTimer 2 inter-

rupts will not occur so they do not have to be disabled. However,

in this mode, the EXF2 ﬂag can still cause interrupts and this can

be used as a third external interrupt.

Baud rate generation will be described as part of the UART serial

port operation.

CORE

12

CLK

*

C/T2 = 0

C/T2 = 1

TL2

(8 BITS)

TH2

(8 BITS)

T2

CONTROL

RELOAD

TR2

TRANSITION

DETECTOR

RCAP2L

RCAP2H

TF2

TIMER

INTERRUPT

T2EX

EXF2

CONTROL

EXEN2

*THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)

Figure 52.Timer/Counter 2, 16-Bit Autoreload Mode

CORE

12

CLK

*

C/T2 = 0

C/T2 = 1

TL2

(8 BITS)

TH2

(8 BITS)

TF2

T2

CONTROL

TR2

TIMER

INTERRUPT

CAPTURE

TRANSITION

DETECTOR

RCAP2L

RCAP2H

T2EX

EXF2

CONTROL

EXEN2

*THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)

Figure 53.Timer/Counter 2, 16-Bit Capture Mode

REV. A

–55–

ADuC836

T2CON

Timer/Counter 2 Control Register

SFR Address

Power-On DefaultValue

Bit Addressable

C8H

00H

Yes

Table XXIX. T2CON SFR Bit Designations

Bit

Name

Description

Timer 2 Overﬂow Flag.

7

TF2

Set by hardware on aTimer 2 overﬂow.TF2 will not be set when either RCLK orTCLK = 1.

Cleared by user software.

6

5

4

3

EXF2

Timer 2 External Flag.

Set by hardware when either a capture or a reload is caused by a negative transition inT2EX and EXEN2 = 1.

Cleared by user software.

RCLK

TCLK

EXEN2

Receive Clock Enable Bit.

Set by user to enable the serial port to useTimer 2 overﬂow pulses for its receive clock in serial port Modes 1 and 3.

Cleared by user to enableTimer 1 overﬂow to be used for the receive clock.

Transmit Clock Enable Bit.

Set by user to enable the serial port to useTimer 2 overﬂow pulses for its transmit clock in serial port Modes 1 and 3.

Cleared by user to enableTimer 1 overﬂow to be used for the transmit clock.

Timer 2 External Enable Flag.

Set by user to enable a capture or reload to occur as a result of a negative transition onT2EX if Timer 2 is not

being used to clock the serial port.

Cleared by user forTimer 2 to ignore events atT2EX.

2

1

0

TR2

Timer 2 Start/Stop Control Bit.

Set by user to startTimer 2.

Cleared by user to stopTimer 2.

CNT2

CAP2

Timer 2Timer or Counter Function Select Bit.

Set by user to select counter function (input from externalT2 pin).

Cleared by user to select timer function (input from on-chip core clock).

Timer 2 Capture/Reload Select Bit.

Set by user to enable captures on negative transitions inT2EX when EXEN2 = 1.

Cleared by user to enable auto reloads withTimer 2 overﬂows or negative transitions inT2EX when EXEN2 = 1.

When either RCLK = 1 orTCLK = 1, this bit is ignored and the timer is forced to autoreload onTimer 2 overﬂow.

Timer/Counter 2 Data Registers

Timer/Counter 2 also has two pairs of 8-bit data registers associated with it.These are used as both timer data registers and timer

capture/reload registers.

TH2 andTL2

Timer 2, data high byte and low byte.

SFR Address = CDH, CCH, respectively.

RCAP2H and RCAP2L

Timer 2, Capture/Reload byte and low byte.

SFR Address = CBH, CAH, respectively.

–56–

REV. A

ADuC836

SBUF

UART SERIAL INTERFACE

The serial port receive and transmit registers are both accessed

through the SBUF SFR (SFR address = 99H).Writing to SBUF

loads the transmit register, and reading SBUF accesses a physi-

cally separate receive register.

The serial port is full-duplex, meaning it can transmit and receive

simultaneously. It is also receive-buffered, meaning it can com-

mence reception of a second byte before a previously received byte

has been read from the receive register. However, if the ﬁrst byte

still has not been read by the time reception of the second byte is

complete, the ﬁrst byte will be lost.The physical interface to the

serial data network is via pins RxD(P3.0) andTxD(P3.1), while

the SFR interface to the UART comprises the following registers:

SCON

UART Serial Port Control Registers

SFR Address

98H

Power-On DefaultValue 00H

Bit Addressable

Yes

Table XXX. SCON SFR Bit Designations

Bit

7

Name

SM0

Description

UART Serial Mode Select Bits.

6

SM1

These bits select the Serial Port operating mode as follows:

SM0

SM1

Selected Operating Mode

0

1

0

1

0

1

Mode 0: Shift Register, ﬁxed baud rate (f_CORE/12)

Mode 1: 8-bit UART, variable baud rate

Mode 2: 9-bit UART, ﬁxed baud rate (f_CORE/64) or (f_CORE/32)

Mode 3: 9-bit UART, variable baud rate

5

4

SM2

REN

Multiprocessor Communication Enable Bit.

Enables multiprocessor communication in Modes 2 and 3. In Mode 0, SM2 should be cleared. In Mode 1, if

SM2 is set, RI will not be activated if a valid stop bit was not received. If SM2 is cleared, RI will be set as soon

as the byte of data has been received. In Modes 2 or 3, if SM2 is set, RI will not be activated if the received ninth

data bit in RB8 is 0. If SM2 is cleared, RI will be set as soon as the byte of data has been received.

Serial Port Receive Enable Bit.

Set by user software to enable serial port reception.

Cleared by user software to disable serial port reception.

3

2

1

TB8

RB8

TI

Serial PortTransmit (Bit 9).

The data loaded intoTB8 will be the ninth data bit that will be transmitted in Modes 2 and 3.

Serial Port Receiver Bit 9.

The ninth data bit received in Modes 2 and 3 is latched into RB8. For Mode 1, the stop bit is latched into RB8.

Serial PortTransmit Interrupt Flag.

Set by hardware at the end of the eighth bit in Mode 0, or at the beginning of the stop bit in Modes 1, 2, and 3.

TI must be cleared by user software.

0

RI

Serial Port Receive Interrupt Flag.

Set by hardware at the end of the eighth bit in Mode 0, or halfway through the stop bit in Modes 1, 2, and 3.

RI must be cleared by software.

MACHINE

CYCLE 1

MACHINE

CYCLE 2

MACHINE

CYCLE 7

MACHINE

CYCLE 8

UART OPERATING MODES

Mode 0: 8-Bit Shift Register Mode

S1 S2 S3 S4 S5 S6 S1 S2 S3 S4

S4 S5 S6 S1 S2 S3 S4 S5 S6

Mode 0 is selected by clearing both the SM0 and SM1 bits in

the SFR SCON. Serial data enters and exits through RxD.TxD

outputs the shift clock. Eight data bits are transmitted or received.

Transmission is initiated by any instruction that writes to SBUF.

The data is shifted out of the RxD line.The 8 bits are transmitted

with the least signiﬁcant bit (LSB) ﬁrst, as shown in Figure 54.

CORE

CLK

ALE

RxD

(DATA OUT)

DATA BIT 0

DATA BIT 1

DATA BIT 6

DATA BIT 7

TxD

(SHIFT CLOCK)

Reception is initiated when the Receive Enable bit (REN) is 1 and

the Receive Interrupt bit (RI) is 0.When RI is cleared, the data

is clocked into the RxD line and the clock pulses are output from

theTxD line.

Figure 54. UART Serial PortTransmission, Mode 0

REV. A

–57–

ADuC836

Mode 1: 8-Bit UART,Variable Baud Rate

To transmit, the eight data bits must be written into SBUF.The

ninth bit must be written toTB8 in SCON.When transmission

is initiated, the eight data bits (from SBUF) are loaded onto the

transmit shift register (LSB ﬁrst).The contents ofTB8 are loaded

into the ninth bit position of the transmit shift register.

Mode 1 is selected by clearing SM0 and setting SM1. Each data

byte (LSB ﬁrst) is preceded by a start bit (0) and followed by a

stop bit (1).Therefore 10 bits are transmitted onTxD or received

on RxD.The baud rate can be set byTimer 1 orTimer 2 (or both).

Alternatively, a dedicated baud rate generator,Timer 3, is pro-

vided on-chip to generate high speed, very accurate baud rates.

The transmission will start at the next valid baud rate clock.The

TI ﬂag is set as soon as the stop bit appears onTxD.

Transmission is initiated by writing to SBUF.The “write to

SBUF” signal also loads a 1 (stop bit) into the ninth bit position

of theTransmit Shift Register.The data is output bit by bit until

the stop bit appears onTxD and the transmit interrupt ﬂag (TI)

is automatically set, as shown in Figure 55.

Reception for Mode 2 is similar to that of Mode 1.The eight data

bytes are input at RxD (LSB ﬁrst) and loaded onto the Receive

Shift Register.When all eight bits have been clocked in, the fol-

lowing events occur:



The eight bits in the Receive Shift Register are latched into

STOP BIT

START

BIT

SBUF.

D0

D1 D2

D3 D4 D5

D6 D7

TxD



The ninth data bit is latched into RB8 in SCON.

TI



(SCON.1)

The Receiver Interrupt ﬂag (RI) is set.

SET INTERRUPT

i.e., READY FOR MORE

DATA

If, and only if, the following conditions are met at the time the

ﬁnal shift pulse is generated:



RI = 0, and

Figure 55. UART Serial PortTransmission, Mode 0



Either SM2 = 0, or SM2 = 1 and the received stop bit = 1.

Reception is initiated when a 1-to-0 transition is detected on

RxD. Assuming a valid start bit was detected, character reception

continues.The start bit is skipped and the eight data bits are

clocked into the serial port shift register.When all eight bits have

been clocked in, the following events occur:

If either of these conditions is not met, the received frame is

irretrievably lost and RI is not set.

Mode 3: 9-Bit UART withVariable Baud Rate

Mode 3 is selected by setting both SM0 and SM1. In this mode,

the 8051 UART serial port operates in 9-bit mode with a variable

baud rate determined by eitherTimer 1 orTimer 2.The operation

of the 9-bit UART is the same as for Mode 2, but the baud rate

can be varied as for Mode 1.



The eight bits in the Receive Shift Register are latched into

SBUF.



The ninth bit (stop bit) is clocked into RB8 in SCON.



The Receiver Interrupt ﬂag (RI) is set.

In all four modes, transmission is initiated by any instruction

that uses SBUF as a destination register. Reception is initiated in

Mode 0 by the condition RI = 0 and REN = 1. Reception is initi-

ated in the other modes by the incoming start bit if REN = 1.

If, and only if, the following conditions are met at the time, the

ﬁnal shift pulse is generated:



RI = 0, and

UART Serial Port Baud Rate Generation

Mode 0 Baud Rate Generation

The baud rate in Mode 0 is ﬁxed:



Either SM2 = 0, or SM2 = 1 and the Received Stop Bit = 1.

If either of these conditions is not met, the received frame is

irretrievably lost and RI is not set.

f_CORE*

Mode 0 Baud Rate =

12

Mode 2: 9-Bit UART with Fixed Baud Rate

Mode 2 is selected by setting SM0 and clearing SM1. In this mode,

the UART operates in 9-bit mode with a ﬁxed baud rate.The baud

rate is ﬁxed at Core_Clk/64 by default, although by setting the

SMOD bit in PCON, the frequency can be doubled to Core_Clk/32.

Eleven bits are transmitted or received, a start bit (0), eight data

bits, a programmable ninth bit, and a stop bit (1).The ninth bit

is most often used as a parity bit, although it can be used for any-

thing, including a ninth data bit if required.

Mode 2 Baud Rate Generation

The baud rate in Mode 2 depends on the value of the SMOD bit

in the PCON SFR. If SMOD = 0, the baud rate is 1/64 of the

core clock. If SMOD = 1, the baud rate is 1/32 of the core clock:

f_CORE*× 2^SMOD

Mode 2 Baud Rate =

64

Mode 1 and 3 Baud Rate Generation

Traditionally, the baud rates in Modes 1 and 3 are determined by

the overﬂow rate inTimer 1 or Timer 2, or both (one for transmit

and the other for receive). On the ADuC836, however, the baud

rate can also be generated via a separate baud rate generator to

achieve higher baud rates and allow all three to be used for other

functions.

*f_CORErefers to the output of the PLL as described in the On-Chip PLL section.

–58–

REV. A

ADuC836

BAUD RATE GENERATION USINGTIMER 1 ANDTIMER 2

Timer 1 Generated Baud Rates

WhenTimer 1 is used as the baud rate generator, the baud rates

in Modes 1 and 3 are determined by theTimer 1 overﬂow rate

and the value of SMOD as follows:

Timer 2 Generated Baud Rates

Baud rates can also be generated usingTimer 2. UsingTimer 2 is

similar to usingTimer 1 in that the timer must overﬂow 16 times

before a bit is transmitted/received. BecauseTimer 2 has a 16-bit

Autoreload mode, a wider range of baud rates is possible.

Modes 1 and 3 Baud Rate = 2^SMOD⁄ 32 × Timer 1 Overflow Rate

Mode 1 and Mode 3 Baud Rate = 1 16 × Timer 2 Overflow Rate

(

)

(

)

(

)

(

)

TheTimer 1 interrupt should be disabled in this application.

The timer itself can be conﬁgured for either timer or counter

operation, and in any of its three running modes. In the most

typical application, it is conﬁgured for timer operation, in the

Autoreload mode (high nibble ofTMOD = 0100 binary). In this

case, the baud rate is given by the formula:

Therefore whenTimer 2 is used to generate baud rates, the timer

increments every two clock cycles and not every core machine

cycle as before.Thus, it increments six times faster thanTimer 1,

and therefore baud rates six times faster are possible. Because

Timer 2 has a 16-bit autoreload capability, very low baud rates

are still possible.

2^SMOD× f_CORE

Mode 1 and Mode 3 Baud Rate =

32 × 12 256 − TH1

Timer 2 is selected as the baud rate generator by setting theTCLK

and/or RCLK inT2CON.The baud rates for transmit and receive

can be simultaneously different. Setting RCLK and/orTCLK puts

Timer 2 into its baud rate generator mode, as shown in Figure 56.

In this case, the baud rate is given by the formula:

(

)

A very low baud rate can also be achieved withTimer 1 by leaving

theTimer 1 interrupt enabled, conﬁguring the timer to run as a

16-bit timer (high nibble ofTMOD = 0100 binary), and using

theTimer 1 interrupt to do a 16-bit software reload.Table XXXI

shows some commonly used baud rates and how they might

be calculated from a core clock frequency of 1.5728 MHz and

12.58 MHz usingTimer 1. Generally speaking, a 5% error is

tolerable using asynchronous (start/stop) communications.

f_CORE

Mode 1 and Mode 3 Baud Rate =

32 × 65536 − RCAP2H L

(

)

Table XXXII shows some commonly used baud rates and

how they might be calculated from a core clock frequency of

1.5728 MHz and 12.5829 MHz usingTimer 2.

Table XXXI. Commonly Used Baud Rates,Timer 1

Table XXXII. Commonly Used Baud Rates,Timer 2

Ideal

Baud

Core

CLK

SMOD TH1-Reload

Actual

Baud

%

Error

Ideal

Baud

Core

CLK

RCAP2H RCAP2L

Value Value

Actual

Baud

%

Error

Value

9600

1600

1200

12.58

1.57

1

–7 (F9H)

–27 (E5H)

–55 (C9H)

–7 (F9H)

9362

1627

1192

1170

2.5

1.1

0.7

2.5

19200

9600

1600

1200

9600

1600

1200

12.58

1.57

–1 (FFH) –20 (ECH) 19661

–1 (FFH) –41 (D7H) 9591

–1 (FFH) –164 (5CH) 2398

–2 (FEH) –72 (B8H) 1199

2.4

0.1

2.4

0.1

–1 (FFH) –5 (FBH)

9830

–1 (FFH) –20 (ECH) 1658

–1 (FFH) –41 (D7H) 1199

TIMER 1

OVERFLOW

2

OSC. FREQ. IS DIVIDED BY 2, NOT 12.

0

1

SMOD

CONTROL

CORE

2

C/T2 = 0

C/T2 = 1

CLK

*

TIMER 2

OVERFLOW

1

0

TL2

(8 BITS)

TH2

(8 BITS)

RCLK

16

T2

RX

CLOCK

TR2

TCLK

16

NOTE AVAILABILITY OF ADDITIONAL

EXTERNAL INTERRUPT

RELOAD

TX

CLOCK

RCAP2H

RCAP2L

TIMER 2

INTERRUPT

T2EX

EXF 2

CONTROL

TRANSITION

DETECTOR

EXEN2

*THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)

Figure 56.Timer 2, UART Baud Rates

REV. A

–59–

ADuC836

BAUD RATE GENERATION USINGTIMER 3

The appropriate value to write to the DIV2-1-0 bits can be cal-

culated using the following formula where f_COREis the output of

the PLL, as described in the On-Chip PLL section. Note that the

DIV value must be rounded down.

The high integer dividers in a UART block means that high

speed baud rates are not always possible using some particular

crystals, e.g., using a 12 MHz crystal, a baud rate of 115200 is

not possible.To address this problem, the ADuC836 has added

a dedicated baud rate timer (Timer 3) speciﬁcally for generating

highly accurate baud rates.





f_CORE

32 × Baud Rate

log









DIV =

log 2

( )

Timer 3 can be used instead of Timer 1 orTimer 2 for generating

very accurate high speed UART baud rates including 115200 and

230400.Timer 3 also allows a much wider range of baud rates to

be obtained. In fact, every desired bit rate from 12 bits to 393216

bits can be generated to within an error of ±0.8%.Timer 3 also

frees up the other three timers allowing them to be used for dif-

ferent applications. A block diagram of Timer 3 is shown in

Figure 57.

T3FD is the fractional divider ratio required to achieve the

required baud rate.We can calculate the appropriate value for

T3FD using the following formula. Note that the T3FD should

be rounded to the nearest integer.

2 × f_CORE

2^DIV× Baud Rate

T3FD =

− 64

CORE

2

Once the values for DIV and T3FD are calculated, the actual

baud rate can be calculated using the following formula:

CLK

*

TIMER 1/TIMER 2

TX CLOCK (FIG 44)

2 × f_CORE

Actual Baud Rate =

FRACTIONAL

DIVIDER

(1 + T3FD/64)

TIMER 1/TIMER 2

RX CLOCK (FIG 44)

2^DIV× T3FD + 64

(

)

1

0

2^DIV

For a baud rate of 115200 while operating from the maximum

core frequency (CD = 0), we have:

RX

CLOCK

1

0

DIV = log 12582912/32 × 115200 / log 2 = 1.77 = 1

16

(

)

T3EN

T3 RX/TX

CLOCK

TX CLOCK

1

T3FD = 2 × 12.582912 2 × 115200 − 64 = 45.22 = 2Dh

(

)

(

*

THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)

Therefore, the actual baud rate is 115439 bits.

Figure 57. Timer 3, UART Baud Rates

Table XXXIV. Commonly Used Baud Rates UsingTimer 3

Two SFRs (T3CON andT3FD) are used to controlTimer 3.

T3CON is the baud rate control SFR, allowingTimer 3 to be

used to set up the UART baud rate, and setting up the binary

divider (DIV).

Ideal

Baud

%

Error

CD

DIV

T3CON

T3FD

230400

0

80H

2DH

0.2

Table XXXIII. T3CON SFR Bit Designations

115200

0

1

0

81H

80H

2DH

0.2

Bit Name

Description

7

T3EN

Set to enableTimer 3 to generate the baud rate.

When set PCON.7,T2CON.4 andT2CON.5

are ignored. Cleared to let the baud rate be

generated as per a standard 8052.

57600

0

1

2

1

0

82H

81H

80H

2DH

0.2

6

5

4

3

2

1

0

–––

Reserved for Future Use

Binary Divider Factor

38400

0

1

2

3

2

1

0

83H

82H

81H

80H

12H

0.1

–––

19200

0

1

2

3

4

3

2

1

0

84H

83H

82H

81H

80H

12H

0.1

DIV2

DIV1

DIV0

DIV2 DIV1 DIV0 Bin Divider

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

8

16

32

64

128

9600

38400

0

1

2

3

4

5

0

5

4

3

2

1

0

3

85H

84H

83H

82H

81H

80H

83H

12H

0.1

–60–

REV. A

ADuC836

INTERRUPT SYSTEM

The ADuC836 provides a total of 11 interrupt sources with two priority levels.The control and conﬁguration of the interrupt system

are carried out through three interrupt-related SFRs: the IE (Interrupt Enable) Register, IP (Interrupt Priority Register), and IEIP2

(Secondary Interrupt Enable/Priority SFR) Registers.Their bit deﬁnitions are given in theTables XXXV to XXXVII.

IE

Interrupt Enable Register

SFR Address

Power-On DefaultValue

Bit Addressable

A8H

00H

Yes

Table XXXV. IE SFR Bit Designations

Bit

Name

Description

7

6

5

4

3

2

1

0

EA

Written by User to Enable 1 or Disable 0 All Interrupt Sources

Written by User to Enable 1 or Disable 0 ADC Interrupt

Written by User to Enable 1 or Disable 0Timer 2 Interrupt

Written by User to Enable 1 or Disable 0 UART Serial Port Interrupt

Written by User to Enable 1 or Disable 0Timer 1 Interrupt

Written by User to Enable 1 or Disable 0 External Interrupt 1

Written by User to Enable 1 or Disable 0Timer 0 Interrupt

Written by User to Enable 1 or Disable 0 External Interrupt 0

EADC

ET2

ES

ET1

EX1

ET0

EX0

IP

Interrupt Priority Register

SFR Address

Power-On DefaultValue

Bit Addressable

B8H

00H

Yes

Table XXXVI. IP SFR Bit Designations

Description

Bit

Name

7

6

5

4

3

2

1

0

–––

Reserved for Future Use

PADC

PT2

PS

PT1

PX1

PT0

PX0

Written by User to Select ADC Interrupt Priority (1 = High; 0 = Low)

Written by User to SelectTimer 2 Interrupt Priority (1 = High; 0 = Low)

Written by User to Select UART Serial Port Interrupt Priority (1 = High; 0 = Low)

Written by User to SelectTimer 1 Interrupt Priority (1 = High; 0 = Low)

Written by User to Select External Interrupt 1 Priority (1 = High; 0 = Low)

Written by User to SelectTimer 0 Interrupt Priority (1 = High; 0 = Low)

Written by User to Select External Interrupt 0 Priority (1 = High; 0 = Low)

IEIP2

Secondary Interrupt Enable and

Priority Register

SFR Address

Power-On DefaultValue

Bit Addressable

A9H

A0H

No

Table XXXVII. IEIP2 SFR Bit Designations

Description

Bit

Name

7

6

5

4

3

2

1

0

–––

PTI

PPSM

PSI

–––

ETI

EPSM

ESI

Reserved for Future Use

Written by User to SelectTIC Interrupt Priority (1 = High; 0 = Low)

Written by User to Select Power Supply Monitor Interrupt Priority (1 = High; 0 = Low)

Written by User to Select SPI/I²C Serial Port Interrupt Priority (1 = High; 0 = Low)

Reserved.This bit must be 0.

Written by User to Enable 1 or Disable 0TIC Interrupt

Written by User to Enable 1 or Disable 0 Power Supply Monitor Interrupt

Written by User to Enable 1 or Disable 0 SPI/I²C Serial Port Interrupt

REV. A

–61–

ADuC836

Interrupt Priority

InterruptVectors

The Interrupt Enable registers are written by the user to enable

individual interrupt sources, while the Interrupt Priority registers

allow the user to select one of two priority levels for each inter-

rupt. An interrupt of a high priority may interrupt the service

routine of a low priority interrupt, and if two interrupts of differ-

ent priority occur at the same time, the higher level interrupt will

be serviced ﬁrst. An interrupt cannot be interrupted by another

interrupt of the same priority level. If two interrupts of the same

priority level occur simultaneously, a polling sequence is used to

determine which interrupt is serviced ﬁrst.The polling sequence

is shown inTable XXXVIII.

When an interrupt occurs, the program counter is pushed onto

the stack and the corresponding interrupt vector address is loaded

into the program counter.The interrupt vector addresses are

shown inTable XXXIX.

Table XXXIX. InterruptVector Addresses

Source

Vector Address

IE0

TF0

IE1

TF1

0003H

000BH

0013H

001BH

0023H

002BH

0033H

003BH

0043H

0053H

005BH

RI +TI

Table XXXVIII. Priority within an Interrupt Level

TF2 + EXF2

RDY0/RDY1 (ADC)

ISPI/I2CI

PSMI

Source

Priority

Description

PSMI

WDS

1 (Highest)

2

Power Supply Monitor Interrupt

Watchdog Interrupt

IE0

RDY0/RDY1

TF0

IE1

TF1

ISPI/I2CI

RI +TI

TF2 + EXF2

TII

3

4

5

6

7

8

9

10

External Interrupt 0

ADC Interrupt

Timer/Counter 0 Interrupt

External Interrupt 1

Timer/Counter 1 Interrupt

SPI Interrupt

TII

WDS (WDIR = 1)*

*The watchdog can be conﬁgured to generate an interrupt instead of

a reset when it times out.This is used for logging errors or examining

the internal status of the microcontroller core to understand, from

a software debug point of view, why a watchdog timeout occurred.

The watchdog interrupt is slightly different from the normal inter-

rupts in that its priority level is always set to 1 and it is not possible

to disable the interrupt via the global disable bit (EA) in the IE SFR.

This is done to ensure that the interrupt will always be responded

to if a watchdog timeout occurs.The watchdog will only produce an

interrupt if the watchdog timeout is greater than zero.

Serial Interrupt

Timer/Counter 2 Interrupt

11 (Lowest) Time Interval Counter Interrupt

–62–

REV. A

ADuC836

ADuC836 HARDWARE DESIGN CONSIDERATIONS

This section outlines some of the key hardware design consider-

ations that must be addressed when integrating the ADuC836

into any hardware system.

Though both external program memory and external data memory

are accessed using some of the same pins, the two are completely

independent of each other from a software point of view. For

example, the chip can read/write external data memory while

executing from external program memory.

External Memory Interface

In addition to its internal program and data memories, the

ADuC836 can access up to 64 Kbytes of external program memory

(ROM, PROM, and so on) and up to 16 Mbytes of external data

memory (SRAM).

Figure 59 shows a hardware conﬁguration for accessing up to

64 Kbytes of external data memory.This interface is standard to

any 8051 compatible MCU.

SRAM

ADuC836

To select from which code space (internal or external program

memory) to begin executing code, tie the EA (external access)

pin high or low, respectively.When EA is high (pulled up toV_DD),

user program execution will start at Address 0 in the internal

62 Kbytes Flash/EE code space.When EA is low (tied to ground)

user program execution will start at Address 0 in the external

code space.When executing from internal code space, accesses

to the program space above F7FFH (62 Kbytes) will be read as

NOP instructions.

D0–D7

(DATA)

P0

LATCH

A0–A7

ALE

A8–A15

P2

RD

OE

WR

WE

Note that a second very important function of the EA pin is

described in the Single Pin Emulation Mode section.

External program memory (if used) must be connected to the

ADuC836, as illustrated in Figure 58. Sixteen I/O lines (Ports 0

and 2) are dedicated to bus functions during external program

memory fetches. Port 0 (P0) serves as a multiplexed address/data

bus. It emits the low byte of the program counter (PCL) as

an address, and then goes into a high impedance input state

awaiting the arrival of the code byte from the program memory.

During the time that the low byte of the program counter is valid

on P0, the signal ALE (Address Latch Enable) clocks this byte

into an external address latch. Meanwhile, Port 2 (P2) emits the

high byte of the program counter (PCH), and PSEN strobes the

EPROM and the code byte is read into the ADuC836.

Figure 59. External Data Memory Interface

(64 Kbytes Address Space)

If access to more than 64 Kbytes of RAM is desired, a feature

unique to the MicroConverter allows addressing up to 16 Mbytes

of external RAM simply by adding an additional latch, as illus-

trated in Figure 60.

SRAM

ADuC836

D0–D7

(DATA)

P0

LATCH

A0–A7

ALE

EPROM

ADuC836

A8–A15

P2

D0–D7

(INSTRUCTION)

P0

LATCH

A16–A23

LATCH

A0–A7

ALE

OE

RD

WE

WR

A8–A15

P2

PSEN

OE

Figure 60. External Data Memory Interface

(16 Mbytes Address Space)

In either implementation, Port 0 (P0) serves as a multiplexed

address/data bus. It emits the low byte of the data pointer (DPL)

as an address, which is latched by ALE prior to data being placed

on the bus by the ADuC836 (write operation) or by the external

data memory (read operation). Port 2 (P2) provides the data

pointer page byte (DPP) to be latched by ALE, followed by the

data pointer high byte (DPH). If no latch is connected to P2,

DPP is ignored by the SRAM, and the 8051 standard of 64 Kbyte

external data memory access is maintained.

Figure 58. External Program Memory Interface

Note that program memory addresses are always 16 bits wide,

even in cases where the actual amount of program memory used

is less than 64 Kbytes. External program execution sacriﬁces

two of the 8-bit ports (P0 and P2) to the function of addressing

the program memory.While executing from external program

memory, Ports 0 and 2 can be used simultaneously for read/write

access to external data memory, but not for general-purpose I/O.

Detailed timing diagrams of external program and data memory

read and write access can be found in theTiming Speciﬁcations

section.

REV. A

–63–

ADuC836

Power Supplies

Notice that in Figures 61 and 62, a large value (10 F) reservoir

capacitor sits on DV_DDand a separate 10 F capacitor sits on

AV_DD. Also, local decoupling capacitors (0.1 F) are located at

eachV_DDpin of the chip. As per standard design practice, be sure

to include all of these capacitors and ensure the smaller capacitors

are closest to eachV_DDpin with lead lengths as short as possible.

Connect the ground terminal of each of these capacitors directly to

the underlying ground plane. Finally, it should also be noticed that,

at all times, the analog and digital ground pins on the ADuC836

should be referenced to the same system ground reference point.

The ADuC836’s operational power supply voltage range is 2.7V

to 5.25V. Although the guaranteed data sheet speciﬁcations are

given only for power supplies within 2.7V to 3.6V or +5% of the

nominal 5V level, the chip will function equally well at any power

supply level between 2.7V and 5.25V.

Separate analog and digital power supply pins (AV_DDand DV_DD

,

respectively) allow AV_DDto be kept relatively free of noisy digital

signals that are often present on the system DV_DDline. In this mode,

the part can also operate with split supplies, that is, using different

voltage supply levels for each supply. For example, this means that

the system can be designed to operate with a DV_DDvoltage level of

3V while the AV_DDlevel can be at 5V, or vice-versa if required. A

typical split-supply conﬁguration is shown in Figure 61.

Power-On Reset (POR) Operation

An internal POR (Power-On Reset) is implemented on the

ADuC836. For DV_DDbelow 2.45V, the internal POR will hold

the ADuC836 in reset. As DV_DDrises above 2.45V, an internal

timer will time out for typically 128 ms before the part is

released from reset.The user must ensure that the power supply

has reached a stable 2.7V minimum level by this time. Likewise

on power-down, the internal POR will hold the ADuC836 in

reset until the power supply has dropped below 1V. Figure 63

illustrates the operation of the internal POR in detail.

ANALOG SUPPLY

DIGITAL SUPPLY

10F

+

–

+

–

ADuC836

20

34

48

AV

DD

5

6

DD

DV

0.1F

2.45V TYP

DV

DD

21

35

47

128ms TYP

1.0V TYP

AGND

DGND

INTERNAL

CORE RESET

Figure 61. External Dual-Supply Connections

As an alternative to providing two separate power supplies, AV_DD

can be kept quiet by placing a small series resistor and/or ferrite

bead between it and DV_DD, and then decoupling AV_DDseparately

to ground. An example of this conﬁguration is shown in Figure 62.

In this conﬁguration, other analog circuitry (such as op amps,

voltage reference, and so on) can be powered from the AV_DD

supply line as well.

Figure 63. Internal Power-on-Reset Operation

Power Consumption

The DV_DDpower supply current consumption is speciﬁed in

normal, idle, and power-down modes.The AV_DDpower supply

current is speciﬁed with the analog peripherals disabled.The

normal mode power consumption represents the current drawn

from DV_DDby the digital core.The other on-chip peripherals

(watchdog timer, power supply monitor, and so on) consume

negligible current and are therefore lumped in with the normal

operating current here. Of course, the user must add any currents

sourced by the parallel and serial I/O pins, and those sourced

by the DAC in order to determine the total current needed at the

ADuC836’s DV_DDand AV_DDsupply pins. Also, current drawn

from the DV_DDsupply will increase by approximately 5 mA during

Flash/EE erase and program cycles.

DIGITAL SUPPLY

10F

1.6

BEAD

10F

+

–

ADuC836

20

34

48

AV

DD

5

DV

DD

0.1F

21

35 DGND

47

6

AGND

Figure 62. External Single-Supply Connections

–64–

REV. A

ADuC836

Power Saving Modes

Wake-Up from Power-Down Latency

Setting the Idle and Power-Down Mode Bits, PCON.0 and

PCON.1, respectively, in the PCON SFR described inTable II

allows the chip to be switched from Normal mode into Idle

mode, and also into full Power-Down mode.

Even with the 32 kHz crystal enabled during power-down, the PLL

will take some time to lock after a wake-up from power-down.Typ-

ically, the PLL will take about 1 ms to lock. During this time, code

will execute, but not at the speciﬁed frequency. Some operations

require an accurate clock, for example, UART communications,

to achieve speciﬁed 50 Hz/60 Hz rejection from the ADCs.The

following code may be used to wait for the PLL to lock:

In Idle mode, the oscillator continues to run, but the core clock

generated from the PLL is halted.The on-chip peripherals

continue to receive the clock and remain functional.The CPU

status is preserved with the stack pointer, program counter, and

all other internal registers maintain their data during Idle mode.

Port pins and DAC output pins also retain their states, and ALE

and PSEN outputs go high in this mode.The chip will recover

from Idle mode upon receiving any enabled interrupt, or upon

receiving a hardware reset.

WAITFORLOCK:

MOV A, PLLCON

JNB ACC.6, WAITFORLOCK

If the crystal has been powered down during power-down, there

is an additional delay associated with the startup of the crystal

oscillator before the PLL can lock. 32 kHz crystals are inherently

slow to oscillate, typically taking about 150 ms. Once again, during

this time before lock, code will execute, but the exact frequency

of the clock cannot be guaranteed. Again for any timing sensitive

operations, it is recommended to wait for lock using the lock bit

in PLLCON, as shown in the code above.

In Power-Down mode, both the PLL and the clock to the core are

stopped.The on-chip oscillator can be halted or can continue to

oscillate, depending on the state of the oscillator power-down bit

(OSC_PD) in the PLLCON SFR.TheTIC, being driven directly

from the oscillator, can also be enabled during power-down. All

other on-chip peripherals, however, are shut down. Port pins retain

their logic levels in this mode, but the DAC output goes to a high

impedance state (three-state) while ALE and PSEN outputs are

held low. During full Power-Down mode with the oscillator and

wake-up timer running, the ADuC836 typically consumes a total

of 15 A.There are ﬁve ways of terminating Power-Down mode:

Grounding and Board Layout Recommendations

As with all high resolution data converters, special attention must

be paid to grounding and PC board layout of ADuC836 based

designs in order to achieve optimum performance from the ADCs

and DAC.

Although the ADuC836 has separate pins for analog and digital

ground (AGND and DGND), the user must not tie these to two

separate ground planes unless the two ground planes are con-

nected together very close to the ADuC836, as illustrated in the

simpliﬁed example of Figure 64a. In systems where digital and

analog ground planes are connected together somewhere else

(at the system’s power supply, for example), they cannot be con-

nected again near the ADuC836 since a ground loop would result.

In these cases, tie the ADuC836’s AGND and DGND pins all to

the analog ground plane, as illustrated in Figure 64b. In systems

with only one ground plane, ensure that the digital and analog com-

ponents are physically separated onto separate halves of the board

such that digital return currents do not ﬂow near analog circuitry

and vice versa.The ADuC836 can then be placed between the

digital and analog sections, as illustrated in Figure 64c.

Asserting the RESET Pin (Pin 15)

Returns to Normal mode. All registers are set to their reset default

value and program execution starts at the reset vector once the

RESET pin is deasserted.

Cycling Power

All registers are set to their default state and program execution

starts at the reset vector approximately 128 ms later.

Time Interval Counter (TIC) Interrupt

If the OSC_PD bit in the PLLCON SFR is clear, the 32 kHz

oscillator will remain powered up even in Power-Down mode.

If theTime Interval Counter (Wakeup/RTC timer) is enabled,

aTIC interrupt will wake the ADuC836 up from Power-Down

mode.The CPU services theTIC interrupt.The RETI at the end

of theTIC ISR will return the core to the instruction after the

one that enabled power-down.

In all of these scenarios, and in more complicated real-life appli-

cations, keep in mind the ﬂow of current from the supplies and

back to ground. Make sure the return paths for all currents are as

close as possible to the paths the currents took to reach their des-

tinations. For example, do not power components on the analog

side of Figure 64b with DV_DDsince that would force return cur-

rents from DV_DDto ﬂow through AGND. Also, try to avoid digital

currents ﬂowing under analog circuitry, which could happen if

the user placed a noisy digital chip on the left half of the board

in Figure 64c.Whenever possible, avoid large discontinuities in

the ground plane(s) (such as those formed by a long trace on the

same layer), since they force return signals to travel a longer path.

And of course, make all connections directly to the ground plane

with little or no trace separating the pin from its via to ground.

SPI Interrupt

If the SERIPD bit in the PCON SFR is set, then an SPI interrupt,

if enabled, will wake up the ADuC836 from Power-Down mode.

The CPU services the SPI interrupt.The RETI at the end of the

ISR will return the core to the instruction after the one that enabled

power-down.

INT0 Interrupt

If the INT0PD bit in the PCON SFR is set, an external interrupt 0,

if enabled, will wake up the ADuC836 from power-down.The

CPU services the SPI interrupt.The RETI at the end of the ISR

will return the core to the instruction after the one that enabled

power-down.

REV. A

–65–

ADuC836

The CHIPID SFR is a read-only register located at SFR address

C2H.The upper nibble of this SFR designates the MicroConverter

within the - ADC family. User software can read this SFR to

identify the host MicroConverter and thus execute slightly differ-

ent code if required.The CHIPID SFR reads as follows for the

- ADC family of MicroConverter products.

PLACE ANALOG

COMPONENTS

HERE

PLACE DIGITAL

COMPONENTS

HERE

a.

AGND

DGND

ADuC836

ADuC834

ADuC824

ADuC816

CHIPID = 3xH

CHIPID = 2xH

CHIPID = 0xH

CHIPID = 1xH

Clock Oscillator

PLACE ANALOG

COMPONENTS

PLACE DIGITAL

COMPONENTS

HERE

b.

As described earlier, the core clock frequency for the ADuC836

is generated from an on-chip PLL that locks onto a multiple (384

times) of 32.768 kHz.The latter is generated from an internal

clock oscillator.To use the internal clock oscillator, connect a

32.768 kHz parallel resonant crystal between the XTAL1 and

XTAL2 pins (32 and 33), as shown in Figure 65.

HERE

AGND

DGND

As shown in the typical external crystal connection diagram in

Figure 65, two internal 12 pF capacitors are provided on-chip.

These are connected internally, directly to the XTAL1 and

XTAL2 pins, and the total input capacitances at both pins is

detailed in the Speciﬁcations table.The value of the total load

capacitance required for the external crystal should be the value

recommended by the crystal manufacturer for use with that

speciﬁc crystal. In many cases, because of the on-chip capacitors,

additional external load capacitors will not be required.

PLACE ANALOG

COMPONENTS

HERE

PLACE DIGITAL

COMPONENTS

HERE

c.

GND

Figure 64. System Grounding Schemes

If the user plans to connect fast logic signals (rise/fall time < 5 ns)

to any of the ADuC836’s digital inputs, add a series resistor to

each relevant line to keep rise and fall times longer than 5 ns at the

ADuC836 input pins. A value of 100  or 200  is usually suf-

ﬁcient to prevent high speed signals from coupling capacitively into

the ADuC836 and affecting the accuracy of ADC conversions.

ADuC836

XTAL1

32

12pF

32.768kHz

TO INTERNAL

PLL

33

XTAL2

12pF

ADuC836 System Self-Identiﬁcation

In some hardware designs, it may be an advantage for the software

running on the ADuC836 target to identify the host MicroCon-

verter. For example, code running on the ADuC836 may also

be used with the ADuC824 or the ADuC816, and is required to

operate differently.

Figure 65. External Parallel Resonant Crystal

Connections Other Hardware Considerations

To facilitate in-circuit programming plus in-circuit debug and

emulation options, users will want to implement some simple

connection points in their hardware that will allow easy access to

Download, Debug, and Emulation modes.

–66–

REV. A

ADuC836

OTHER HARDWARE CONSIDERATIONS

In-Circuit Serial Download Access

that no external signals are capable of pulling the PSEN pin low,

except for the external PSEN jumper itself.

Nearly all ADuC836 designs will want to take advantage of the

in-circuit reprogrammability of the chip. This is accomplished

by a connection to the ADuC836’s UART, which requires an

external RS-232 chip for level translation if downloading code

from a PC. Basic conﬁguration of an RS-232 connection is illus-

trated in Figure 66 with a simple ADM3202 based circuit. If users

would rather not include an RS-232 chip onto the target board,

refer to the application note, uC006–A 4-Wire UART-to-PC Interface

available at www.analog.com/microconverter, for a simple (and

zero-cost-per-board) method of gaining in-circuit serial download

access to the ADuC836.

Embedded Serial Port Debugger

From a hardware perspective, entry to Serial Port Debug mode is

identical to the serial download entry sequence described above.

In fact, both Serial Download and Serial Port Debug modes can

be thought of as essentially one mode of operation used in two

different ways.

Note that the serial port debugger is fully contained on the

ADuC836 device, (unlike ROM monitor type debuggers) and

therefore no external memory is needed to enable in-system

debug sessions.

Single-Pin Emulation Mode

In addition to the basic UART connections, users will also need

a way to trigger the chip into Download mode. This is accom-

plished via a 1 k pull-down resistor that can be jumpered onto

the PSEN pin, as shown in Figure 66. To get the ADuC836 into

Download mode, simply connect this jumper and power-cycle the

device (or manually reset the device, if a manual reset button is

available), and it will be ready to receive a new program serially.

With the jumper removed, the device will power on in Normal

mode (and run the program) whenever power is cycled or RESET

is toggled.

Also built into the ADuC836 is a dedicated controller for single-pin

in-circuit emulation (ICE) using standard production ADuC836

devices. In this mode, emulation access is gained by connection to

a single pin, the EA pin. Normally, this pin is hard-wired either

high or low to select execution from internal or external program

memory space, as described earlier.To enable single-pin emu-

lation mode, however, users will need to pull the EA pin high

through a 1 k resistor, as shown in Figure 66.The emulator

will then connect to the 2-pin header also shown in Figure 66.

To be compatible with the standard connector that comes

with the single-pin emulator available from Accutron Limited

(www.accutron.com), use a 2-pin 0.1-inch pitch Friction Lock

header from Molex (www.molex.com) such as their part number

22-27-2021. Be sure to observe the polarity of this header. As

represented in Figure 66, when the Friction Lock tab is at the

right, the ground pin should be the lower of the two pins (when

viewed from the top).

Note that PSEN is normally an output (as described in the Exter-

nal Memory Interface section) and that it is sampled as an input

only on the falling edge of RESET (i.e., at power-up or upon an

external manual reset). Note also that if any external circuitry

unintentionally pulls PSEN low during power-up or reset events,

it could cause the chip to enter Download mode and therefore fail

to begin user code execution as it should.To prevent this, ensure

REV. A

–67–

ADuC836

Typical System Conﬁguration

its resistance.This differential voltage is routed directly to the

positive and negative inputs of the primary ADC (AIN1, AIN2,

respectively).The same current that excited the RTD also ﬂows

through a series resistance R_REF, generating a ratiometric voltage

referenceV_REF.The ratiometric voltage reference ensures that

variations in the excitation current do not affect the measurement

system as the input voltage from the RTD and reference voltage

across R_REFvary ratiometrically with the excitation current. Resis-

tor R_REFmust, however, have a low temperature coefﬁcient to

avoid errors in the reference voltage over temperature. R_REFmust

also be large enough to generate at least a 1V voltage reference.

A typical ADuC836 conﬁguration is shown in Figure 66. It sum-

marizes some of the hardware considerations discussed in the

previous paragraphs.

Figure 66 also includes connections for a typical analog mea-

surement application of the ADuC836, namely an interface to an

RTD (ResistiveTemperature Device).The arrangement shown is

commonly referred to as a 4-wire RTD conﬁguration.

Here, the on-chip excitation current sources are enabled to

excite the sensor.The excitation current ﬂows directly through

the RTD, generating a voltage across the RTD proportional to

DOWNLOAD/DEBUG

ENABLE JUMPER

(NORMALLY OPEN)

DV

DD

1k

DV

DD

1k

2-PIN HEADER FOR

EMULATION ACCESS

(NORMALLY OPEN)

44 43 42 41 40

47 46 45

52 51 50 49 48

39

38

P1.2/I

1/DAC

37

EXC

200A/400A

EXCITATION

CURRENT

AV

DV

DD

P1.3/AIN5/DAC

36

35

34

DD

AV

DD

DGND

DV

DD

AGND

ADuC836

RTD

REFIN–

XTAL2 33

XTAL1

32

31

30

29

28

27

REFIN+

32.768kHz

R

P1.4/AIN1

P1.5/AIN2

REF

5.6k

NOT CONNECTED IN THIS EXAMPLE

DV

DD

ALL CAPACITORS IN THIS EXAMPLE ARE

0.1F CERAMIC CAPACITORS.

DV

DD

RS232 INTERFACE*

STANDARD D-TYPE

SERIAL COMMS

CONNECTOR TO

PC HOST

ADM3202

C1+

V+

V

CC

GND

1

2

3

4

5

6

7

8

9

C1–

C2+

C2–

V–

T1OUT

R1IN

R1OUT

T1IN

T2OUT

R2IN

T2IN

R2OUT

*EXTERNAL UART TRANSCEIVER INTEGRATED IN SYSTEM OR AS

PART OF AN EXTERNAL DONGLE AS DESCRIBED IN uC006.

Figure 66. Typical System Conﬁguration

–68–

REV. A

ADuC836

QUICKSTART DEVELOPMENT SYSTEM

Download—In Circuit Downloader

The QuickStart Development System is a full featured, low cost

development tool suite supporting the ADuC836. The system

consists of the following PC based (Windows^®compatible) hard-

ware and software development tools:

The Serial Downloader is a software program that allows the user

to serially download an assembled program (Intel Hex format ﬁle)

to the on-chip program Flash memory via the serial COM1 port on

a standard PC. Application Note uC004 details this serial download

protocol and is available from www.analog.com/microconverter.

Hardware:

ADuC836 Evaluation Board

and Serial Port Cable

Debugger/Emulator—In-Circuit Debugger/Emulator

The Debugger/Emulator is aWindows application that allows the

user to debug code execution on silicon using the MicroConverter

UART serial port or via a single pin to provide nonintrusive

debug. The debugger provides access to all on-chip peripherals

during a typical debug session, including single-step and multiple

break-point code execution control. C source and assembly level

debug are both possible with the emulator.

Code Development:

Code Functionality:

8051 Assembler

ADSIM, Windows

MicroConverter Code

Simulator

In-Circuit Code Download:

Serial Downloader

In-Circuit Debugger/Emulator: Serial Port/Single Pin

ADSIM—Windows Simulator

Debugger/Emulator with

Assembly and C Source

Debug

The Simulator is aWindows application that fully simulates the

MicroConverter functionality including ADC and DAC periph-

erals.The simulator provides an easy-to-use, intuitive, interface to

the MicroConverter functionality and integrates many standard

debug features including multiple breakpoints, single stepping,

and code execution trace capability. This tool can be used both

as a tutorial guide to the part as well as an efﬁcient way to prove

code functionality before moving to a hardware platform.

Miscellaneous Other:

CD-ROM Documentation

andTwo Additional

Prototype Devices

Figure 67 shows the typical components of a QuickStart Devel-

opment System while Figure 68 shows a typical debug session. A

brief description of some of the software tools’ components in the

QuickStart Development System follows.

Figure 68. Typical Debug Session

Figure 67. Components of the QuickStart Development

System

REV. A

–69–

ADuC836

TIMING SPECIFICATIONS^{1, 2, 3}

(AV_DD= 2.7 V to 3.6 V or 4.75 V to 5.25 V, DV_DD= 2.7 V to 3.6 V or 4.75 V to 5.25 V;

all speciﬁcations T_MINto T_MAX, unless otherwise noted.)

32.768 kHz External Crystal

Parameter

Min

Typ

Max

Unit

CLOCK INPUT (External Clock Driven XTAL1)

t_CK

t_CKL

XTAL1 Period

XTAL1Width Low

30.52

6.26

9

s

MHz

s

t_CKH

t_CKR

t_CKF

1/t_CORE

t_CORE

t_CYC

XTAL1Width High

XTAL1 RiseTime

XTAL1 FallTime

9

ADuC836 Core Clock Frequency⁴

ADuC836 Core Clock Period⁵

ADuC836 Machine CycleTime⁶

0.098

0.95

12.58

0.636

7.6

122.45

s

NOTES

¹AC inputs during testing are driven at DV_DD– 0.5V for a Logic 1, and 0.45V for a Logic 0.Timing measurements are made atV_IHmin for a Logic 1, andV_ILmax for a

Logic 0, as shown in Figure 70.

²For timing purposes, a port pin is no longer ﬂoating when a 100 mV change from load voltage occurs. A port pin begins to ﬂoat when a 100 mV change from the loaded

V_OH/V_OLlevel occurs, as shown in Figure 70.

³C_LOADfor Port 0, ALE, PSEN outputs = 100 pF; C_LOADfor all other outputs = 80 pF, unless otherwise noted.

⁴ADuC836 internal PLL locks onto a multiple (384 times) the external crystal frequency of 32.768 kHz to provide a stable 12.583 MHz internal clock for the system.

The core can operate at this frequency or at a binary submultiple called Core_Clk, selected via the PLLCON SFR.

⁵This number is measured at the default Core_Clk operating frequency of 1.57 MHz.

⁶ADuC836 Machine CycleTime is nominally deﬁned as 12/Core_Clk.

t_CKR

t_CKH

t_CKL

t_CKF

t_CK

Figure 69. XTAL1 Input

DV – 0.5V

DD

V

– 0.1V

+ 0.1V

V

– 0.1V

LOAD

0.2DV + 0.9V

DD

TIMING

REFERENCE

POINTS

V

LOAD

TEST POINTS

LOAD

0.2DV

– 0.1V

DD

V

+ 0.1V

LOAD

0.45V

Figure 70.Timing Waveform Characteristics

–70–

REV. A

ADuC836

12.58 MHz Core_Clk

Variable Core_Clk

Max

Parameter

Min

Max

Min

Unit

EXTERNAL PROGRAM MEMORY

t_LHLL

t_AVLL

t_LLAX

t_LLIV

t_LLPL

t_PLPH

t_PLIV

t_PXIX

t_PXIZ

t_AVIV

t_PLAZ

t_PHAX

ALE Pulsewidth

119

39

49

2t_CORE– 40

t_CORE– 40

t_CORE– 30

ns

AddressValid to ALE Low

Address Hold after ALE Low

ALE Low toValid Instruction In

ALE Low to PSEN Low

218

133

4t_CORE– 100

ns

49

193

t_CORE– 30

3t_CORE– 45

PSEN Pulsewidth

PSEN Low toValid Instruction In

Input Instruction Hold after PSEN

Input Instruction Float after PSEN

Address toValid Instruction In

PSEN Low to Address Float

Address Hold after PSEN High

3t_CORE– 105

0

54

292

25

t_CORE– 25

5t_CORE– 105

25

0

CORE_CLK

t_LHLL

ALE (O)

t_PLPH

t_AVLL

t_LLPL

t_LLIV

t_PLIV

PSEN (O)

t_PXIZ

t_PLAZ

t_LLAX

t_PXIX

PCL

(OUT)

INSTRUCTION

(IN)

PORT 0 (I/O)

t_AVIV

t_PHAX

PORT 2 (O)

PCH

Figure 71. External Program Memory Read Cycle

REV. A

–71–

ADuC836

12.58 MHz Core_Clk

Variable Core_Clk

Max

Parameter

Min

Max

Min

Unit

EXTERNAL DATA MEMORY READ CYCLE

t_RLRH

t_AVLL

t_LLAX

t_RLDV

t_RHDX

t_RHDZ

t_LLDV

t_AVDV

t_LLWL

t_AVWL

t_RLAZ

t_WHLH

RD Pulsewidth

377

39

44

6t_CORE– 100

t_CORE– 40

t_CORE– 35

ns

AddressValid after ALE Low

Address Hold after ALE Low

RD Low toValid Data In

Data and Address Hold after RD

Data Float after RD

ALE Low toValid Data In

Address toValid Data In

ALE Low to RD Low

232

5t_CORE– 165

0

89

2t_CORE– 70

8t_CORE– 150

9t_CORE– 165

3t_CORE+ 50

486

550

288

188

3t_CORE– 50

4t_CORE– 130

AddressValid to RD Low

RD Low to Address Float

RD High to ALE High

0

119

0

39

t_CORE– 40

t_CORE+ 40

CORE_CLK

ALE (O)

t_WHLH

PSEN (O)

t_LLDV

t_LLWL

t_RLRH

RD (O)

t_AVWL

t_LLAX

t_RLDV

t_RHDZ

t_RHDX

t_AVLL

t_RLAZ

A0–A7

(OUT)

PORT 0 (I/O)

DATA (IN)

t_AVDV

A16–A23

PORT 2 (O)

A8–A15

Figure 72. External Data Memory Read Cycle

–72–

REV. A

ADuC836

12.58 MHz Core_Clk

Variable Core_Clk

Max

Parameter

Min

Max

Min

Unit

EXTERNAL DATA MEMORYWRITE CYCLE

t_WLWH

t_AVLL

WR Pulsewidth

377

39

44

188

29

406

29

6t_CORE– 100

t_CORE– 40

t_CORE– 35

3t_CORE– 50

4t_CORE– 130

t_CORE– 50

7t_CORE– 150

t_CORE– 50

t_CORE– 40

ns

AddressValid after ALE Low

Address Hold after ALE Low

ALE Low to WR Low

t_LLAX

t_LLWL

t_AVWL

t_QVWX

t_QVWH

t_WHQX

t_WHLH

288

119

3t_CORE+ 50

AddressValid to WR Low

DataValid to WR Transition

Data Setup before WR

Data and Address Hold after WR

WR High to ALE High

39

t_CORE+ 40

CORE_CLK

ALE (O)

t_WHLH

PSEN (O)

WR (O)

t_LLWL

t_WLWH

t_AVWL

t_LLAX

t_QVWX

t_WHQX

t_AVLL

t_QVWH

PORT 0 (O)

PORT 2 (O)

A0–A7

DATA

A16–A23

A8–A15

Figure 73. External Data Memory Write Cycle

REV. A

–73–

ADuC836

12.58MHz Core_Clk

Variable Core_Clk

Typ

Parameter

Min

Typ

Max

Min

Max

Unit

UARTTIMING (Shift Register Mode)

t_XLXL

t_QVXH

t_DVXH

t_XHDX

t_XHQX

Serial Port Clock CycleTime

0.95

12t_CORE

s

ns

Output Data Setup to Clock

Input Data Setup to Clock

Input Data Hold after Clock

Output Data Hold after Clock

662

292

0

10t_CORE– 133

2t_CORE+ 133

0

42

2t_CORE– 117

ALE (O)

t_XLXL

TxD

01

67

(OUTPUT CLOCK)

SET RI

OR

SET TI

t_QVXH

t_XHQX

RxD

MSB

BIT 6

BIT 1

(OUTPUT DATA)

t_DVXH

t_XHDX

RxD

(INPUT DATA)

MSB

BIT 6

BIT 1

LSB

Figure 74. UART Timing in Shift Register Mode

–74–

REV. A

ADuC836

Parameter

Min

Typ

Max

Unit

SPI MASTER MODETIMING (CPHA = 1)

t_SL

t_SH

SCLOCK Low Pulsewidth*

SCLOCK High Pulsewidth*

Data OutputValid after SCLOCK Edge

Data Input SetupTime before SCLOCK Edge

Data Input HoldTime after SCLOCK Edge

Data Output FallTime

630

ns

t_DAV

t_DSU

t_DHD

t_DF

t_DR

t_SR

50

100

10

25

Data Output RiseTime

SCLOCK RiseTime

t_SF

SCLOCK FallTime

*Characterized under the following conditions:

Core clock divider bits CD2, CD1, and CD0 in PLLCON SFR set to 0, 1, and 1, respectively, i.e., core clock frequency = 1.57 MHz, and SPI bit rate selection bits

SPR1 and SPR0 in SPICON SFR are both set to 0.

SCLOCK

(CPOL = 0)

t_SH

t_SL

t_SR

t_SF

SCLOCK

(CPOL = 1)

t_DAV

t_DOSU

t_DF

t_DR

MOSI

MISO

MSB

BITS 6–1

LSB

LSB IN

MSB IN

BITS 6–1

t_DSUt_DHD

Figure 75. SPI Master ModeTiming (CPHA = 1)

REV. A

–75–

ADuC836

Parameter

Min

Typ

Max

Unit

SPI MASTER MODETIMING (CPHA = 0)

t_SL

t_SH

SCLOCK Low Pulsewidth*

SCLOCK High Pulsewidth*

630

ns

t_DAV

t_DOSU

t_DSU

t_DHD

t_DF

Data OutputValid after SCLOCK Edge

Data Output Setup before SCLOCK Edge

Data Input SetupTime before SCLOCK Edge

Data Input HoldTime after SCLOCK Edge

Data Output FallTime

50

150

100

10

25

t_DR

Data Output RiseTime

t_SR

t_SF

SCLOCK RiseTime

SCLOCK FallTime

*Characterized under the following conditions:

1. Core clock divider bits CD2, CD1, and CD0 in PLLCON SFR set to 0, 1, and 1 respectively, i.e., core clock frequency = 1.57 MHz.

2. SPI bit rate selection bits SPR1 and SPR0 in SPICON SFR are both set to 0.

SCLOCK

(CPOL = 0)

t_SH

t_SL

t_SF

t_SR

SCLOCK

(CPOL = 1)

t_DAV

t_DF

t_DR

MOSI

MISO

BITS 6–1

MSB

LSB

MSB IN

LSB IN

t_DSU

t_DHD

Figure 76. SPI Master ModeTiming (CPHA = 0)

–76–

REV. A

ADuC836

Parameter

Min

Typ

Max

Unit

SPI SLAVE MODETIMING (CPHA = 1)

t_SS

t_SL

t_SH

t_DAV

t_DSU

t_DHD

t_DF

t_DR

t_SR

SS to SCLOCK Edge

0

ns

SCLOCK Low Pulsewidth

SCLOCK High Pulsewidth

Data OutputValid after SCLOCK Edge

Data Input SetupTime before SCLOCK Edge

Data Input HoldTime after SCLOCK Edge

Data Output FallTime

330

50

100

10

25

Data Output RiseTime

SCLOCK RiseTime

t_SF

t_SFS

SCLOCK FallTime

SS High after SCLOCK Edge

0

SS

t_SFS

t_SS

SCLOCK

(CPOL = 0)

t_SL

t_SH

t_SF

t_SR

SCLOCK

(CPOL = 1)

t_DAV

t_DF

t_DR

MISO

MOSI

BITS 6–1

MSB

LSB

BITS 6–1

LSB IN

MSB IN

t_DSU

t_DHD

Figure 77. SPI Slave ModeTiming (CPHA = 1)

REV. A

–77–

ADuC836

Parameter

Min

Typ

Max

Unit

SPI SLAVE MODETIMING (CPHA = 0)

t_SS

t_SL

t_SH

t_DAV

t_DSU

t_DHD

t_DF

SS to SCLOCK Edge

0

ns

SCLOCK Low Pulsewidth

SCLOCK High Pulsewidth

Data OutputValid after SCLOCK Edge

Data Input SetupTime before SCLOCK Edge

Data Input HoldTime after SCLOCK Edge

Data Output FallTime

330

50

100

10

25

50

20

t_DR

t_SR

Data Output RiseTime

SCLOCK RiseTime

t_SF

SCLOCK FallTime

SS to SCLOCK Edge

Data OutputValid after SS Edge

SS High after SCLOCK Edge

t_SSR

t_DOSS

t_SFS

0

SS

t_SFS

t_SS

SCLOCK

(CPOL = 0)

t_SH

t_SL

t_SF

t_SR

SCLOCK

(CPOL = 1)

t_DAV

t_DOSS

t_DF

t_DR

MISO

MOSI

BITS 6–1

MSB

LSB

BITS 6–1

LSB IN

MSB IN

t_DSU

t_DHD

Figure 78. SPI Slave ModeTiming (CPHA = 0)

–78–

REV. A

ADuC836

Parameter

Min

Max

Unit

I²C-SERIAL INTERFACETIMING

t_L

t_H

SCLOCK Low Pulsewidth

4.7

4.0

0.6

100

µs

ns

µs

SCLOCK High Pulsewidth

Start Condition HoldTime

Data SetupTime

t_SHD

t_DSU

t_DHD

t_RSU

t_PSU

t_BUF

Data HoldTime

0.9

SetupTime for Repeated Start

Stop Condition SetupTime

Bus FreeTime between a STOP

Condition and a START Condition

RiseTime of Both SCLOCK and SDATA

FallTime of Both SCLOCK and SDATA

Pulsewidth of Spike Suppressed

0.6

1.3

t_R

t_F

t_SUP

300

50

ns

*

*Input ﬁltering on both the SCLOCK and SDATA inputs surpresses noise spikes less than 50 ns.

t_BUF

t_SUP

t_R

SDATA (I/O)

MSB

LSB

ACK

MSB

t_DSU

t_F

t_DHD

t_R

t_RSU

t_H

t_PSU

t_SHD

SCLK (I)

1

2-7

8

9

1

t_L

t_SUP

S(R)

PS

t_F

STOP

START

REPEATED

START

CONDITION CONDITION

Figure 79. I²C Compatible InterfaceTiming

REV. A

–79–

ADuC836

OUTLINE DIMENSIONS

52-Lead Metric Quad Flat Package [MQFP]

(S-52)

Dimensions shown in millimeters

14.15

1.03

0.88

0.73

13.90 SQ

13.65

2.45

MAX

39

27

40

26

SEATING

PLANE

10.20

10.00 SQ

9.80

7.80

REF

TOP VIEW

(PINS DOWN)

VIEW A

PIN 1

52

14

1

13

0.23

0.11

0.65 BSC

0.38

0.22

2.10

2.00

1.95

7

0

0.10 MIN

COPLANARITY

VIEW A

ROTATED 90 CCW

COMPLIANT TO JEDEC STANDARDS MO-022-AC-1

56-Lead Lead Frame Chip Scale Package [LFCSP]

8  8 mm Body

(CP-56)

Dimensions shown in millimeters

0.30

8.00

BSC SQ

0.23

0.18

0.60 MAX

PIN 1

INDICATOR

0.60 MAX

43

56

1

42

PIN 1

INDICATOR

6.25

6.10 SQ

5.95

7.75

BSC SQ

BOTTOM

VIEW

TOP

VIEW

0.50

0.40

0.30

29

28

14

15

6.50

REF

0.70 MAX

0.65 NOM

1.00

0.90

0.80

12 MAX

0.05 MAX

0.02 NOM

0.20

REF

COPLANARITY

0.08

0.50 BSC

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2

Revision History

Location

Page

4/03—Data Sheet changed from REV. 0 to REV. A.

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

–80–

REV. A


型号：	ADUC836BCPZ
厂家：	ADI
描述：	MicroConverter® , Dual 16-Bit Sigma-Delta ADCs with Embedded 62 kB Flash MCU 转换器闪存微控制器
文件：	总80页 (文件大小：5171K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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