ADuM131E0BRWZ_技术文档

3.0 kV RMS/3.75 kV RMS Triple-Channel

Digital Isolators

Data Sheet

ADuM130D/ADuM130E/ADuM131D/ADuM131E

FEATURES

FUNCTIONAL BLOCK DIAGRAMS

V

1

2

3

4

5

6

7

8

16

DD1

DD2

High common-mode transient immunity: 100 kV/μs

High robustness to radiated and conducted noise

Low propagation delay: 13 ns maximum for 5 V operation,

15 ns maximum for 1.8 V operation

150 Mbps maximum guaranteed data rate

Safety and regulatory approvals (pending)

UL recognition

ADuM130D

GND

V

15 GND

1

2

V

14

13

12

11

10

9

ENCODE

DECODE

IA

IB

IC

OA

OB

OC

V

ENCODE

NIC

DISABLE

NIC

GND

1

GND

1

2

NIC = NO INTERNAL CONNECTION. LEAVE THIS PIN FLOATING.

Figure 1. ADuM130D Functional Block Diagram

3000 V rms/3750 V rms for 1 minute per UL 1577

CSA Component Acceptance Notice 5A

VDE certificate of conformity

V

1

2

3

4

5

6

7

8

16

DD1

DD2

2

ADuM130E

GND

V

15 GND

1

V

14

13

12

11

10

9

ENCODE

DECODE

IA

OA

OB

OC

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12

V

IB

IC

ENCODE

V

_IORM= 849 V peak

CQC certification per GB4943.1-2011

Backward compatibility

NIC

GND

NIC

V

E2

GND

1

2

ADuM130E1/ADuM131E1 pin-compatible with

ADuM1300/ADuM1301

Low dynamic power consumption

1.8 V to 5 V level translation

High temperature operation: 125°C

Fail-safe high or low options

16-lead, RoHS compliant, SOIC package

NIC = NO INTERNAL CONNECTION. LEAVE THIS PIN FLOATING.

Figure 2. ADuM130E Functional Block Diagram

V

DD2

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

DD1

ADuM131D

GND

V

GND

1

2

V

ENCODE

DECODE

ENCODE

IA

IB

OA

V

OB

ENCODE

DECODE

V

IC

OC

NIC

DISABLE

NIC

DISABLE

2

1

APPLICATIONS

GND

2

GND

1

NIC = NO INTERNAL CONNECTION. LEAVE THIS PIN FLOATING.

General-purpose multichannel isolation

Serial peripheral interface (SPI)/data converter isolation

Industrial field bus isolation

Figure 3. ADuM131D Functional Block Diagram

V

1

2

3

4

5

6

7

8

16

DD1

DD2

ADuM131E

GND

V

15 GND

1

2

GENERAL DESCRIPTION

V

14

13

12

11

10

9

ENCODE

DECODE

ENCODE

IA

IB

OA

OB

IC

The ADuM130D/ADuM130E/ADuM131D/ADuM131E¹are

triple-channel digital isolators based on Analog Devices, Inc.,

iCoupler® technology. Combining high speed, complementary

metal-oxide semiconductor (CMOS) and monolithic air core

transformer technology, these isolation components provide

outstanding performance characteristics superior to alternatives

such as optocoupler devices and other integrated couplers. The

maximum propagation delay is 13 ns with a pulse width distortion

of less than 3 ns at 5 V operation. Channel matching is tight at

3.0 ns maximum.

V

ENCODE

DECODE

V

OC

NIC

V

GND

V

E1

E2

GND

1

2

NIC = NO INTERNAL CONNECTION. LEAVE THIS PIN FLOATING.

Figure 4. ADuM131E Functional Block Diagram

Unlike other optocoupler alternatives, dc correctness is ensured

in the absence of input logic transitions. Two different fail-safe

options are available, in which the outputs transition to a pre-

determined state when the input power supply is not applied or

the inputs are disabled. The ADuM130E1/ADuM131E1 are pin-

compatible with the ADuM1300/ADuM1301.

The ADuM130D/ADuM130E/ADuM131D/ADuM131E data

channels are independent and are available in a variety of config-

urations with a withstand voltage rating of 3.0 kV rms or

3.75 kV rms (see the Ordering Guide). The devices operate with

the supply voltage on either side ranging from 1.8 V to 5 V, prov-

iding compatibility with lower voltage systems as well as enabling

voltage translation functionality across the isolation barrier.

¹Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.

Rev. A Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

ADuM130D/ADuM130E/ADuM131D/ADuM131E

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Recommended Operating Conditions .................................... 12

Absolute Maximum Ratings ......................................................... 13

ESD Caution................................................................................ 13

Truth Tables................................................................................. 14

Pin Configurations and Function Descriptions......................... 15

Typical Performance Characteristics ........................................... 17

Applications Information.............................................................. 18

Overview ..................................................................................... 18

Printed Circuit Board (PCB) Layout ....................................... 18

Propagation Delay Related Parameters ................................... 19

Jitter Measurement..................................................................... 19

Insulation Lifetime..................................................................... 19

Outline Dimensions....................................................................... 21

Ordering Guide .......................................................................... 22

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagrams............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics—5 V Operation................................ 3

Electrical Characteristics—3.3 V Operation ............................ 4

Electrical Characteristics—2.5 V Operation ............................ 6

Electrical Characteristics—1.8 V Operation ............................ 7

Insulation and Safety Related Specifications ............................ 9

Package Characteristics ............................................................... 9

Regulatory Information............................................................. 10

DIN V VDE V 0884-10 (VDE V 0884-10) Insulation

Characteristics ............................................................................ 11

REVISION HISTORY

11/15—Rev. 0 to Rev. A

Added 16-Lead, Narrow Body SOIC Package ................Universal

Changes to Title, Features Section, and General Description

Section................................................................................................ 1

Added Table 9; Renumbered Sequentially .................................... 9

Changes to Table 10 and Table 11 .................................................. 9

Added Table 12 ............................................................................... 10

Changes to Table 13........................................................................ 10

Changes to Table 15 Title............................................................... 12

Added Figure 5; Renumbered Sequentially ................................ 12

Changes to Table 17 and Table 19 ................................................ 13

Added Table 18 ............................................................................... 13

Updated Outline Dimensions....................................................... 21

Changes to Ordering Guide .......................................................... 22

7/15—Revision 0: Initial Version

Rev. A | Page 2 of 22

Data Sheet

ADuM130D/ADuM130E/ADuM131D/ADuM131E

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

All typical specifications are at T_A= 25°C, V_DD1= V_DD2= 5 V. Minimum/maximum specifications apply over the entire recommended

operation range of 4.5 V ≤ V_DD1≤ 5.5 V, 4.5 V ≤ V_DD2≤ 5.5 V, and −40°C ≤ T_A≤ +125°C, unless otherwise noted. Switching specifications

are tested with C_L= 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.

Table 1.

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions/Comments

SWITCHING SPECIFICATIONS

Pulse Width

PW

6.6

150

4.8

ns

Mbps

ns

ps/°C

ns

Within pulse width distortion (PWD) limit

Within PWD limit

50% input to 50% output

Data Rate¹

Propagation Delay

Pulse Width Distortion

Change vs. Temperature

Propagation Delay Skew

t_PHL, t_PLH

PWD

7.2

0.5

1.5

13

3

|t_PLH− t_PHL|

t_PSK

6.1

Between any two devices at the same

temperature, voltage, and load

Channel Matching

Codirectional

Opposing Direction

Jitter

t_PSKCD

t_PSKOD

0.5

630

80

3.0

ns

ps p-p

ps rms

See the Jitter Measurement section

DC SPECIFICATIONS

Input Threshold

Logic High

V_IH

V_IL

0.7 × V_DDx

V

Logic Low

0.3 × V_DDx

Output Voltage

Logic High

3

V_OH

V_DDx− 0.1 V_DDx

V_DDx− 0.4 V_DDx

0.2

V

I_Ox²= −20 µA, V_Ix= V_IxH

3

−

I_Ox²= −4 mA, V_Ix= V_IxH

4

Logic Low

V_OL

0.0

0.2

0.1

0.4

V

I_Ox²= 20 µA, V_Ix= V_IxL

4

I_Ox²= 4 mA, V_Ix= V_IxL

Input Current per Channel

I_I

−10

+0.01

−3

9

+10

µA

0 V ≤ V_Ix≤ V_DDx

V_E2= 0 V

DISABLE₁= V_DDx

0 V ≤ V_Ox≤ V_DDx

V_E2Enable Input Pull-Up Current

DISABLE₁Input Pull-Down Current

Tristate Output Current per Channel

Quiescent Supply Current

I_PU

I_PD

I_OZ

15

+10

−10

+0.01

ADuM130D/ADuM130E

I_{DD1 (Q)}

I_{DD2 (Q)}

I_{DD1 (Q)}

I_{DD2 (Q)}

1.35

1.73

9.7

2.6

2.9

15.2

3.0

mA

V_I⁵= 0 (E0, D0), 1 (E1, D1)⁶

V_I⁵= 1 (E0, D0), 0 (E1, D1)⁶

1.87

ADuM131D/ADuM131E

I_{DD1 (Q)}

I_{DD2 (Q)}

I_{DD1 (Q)}

I_{DD2 (Q)}

1.62

1.61

7.4

2.7

2.8

11.4

7.2

mA

V_I⁵= 0 (E0, D0), 1 (E1, D1)⁶

V_I⁵= 1 (E0, D0), 0 (E1, D1)⁶

5.34

Dynamic Supply Current

Dynamic Input

Dynamic Output

Undervoltage Lockout

Positive V_DDxThreshold

Negative V_DDxThreshold

V_DDxHysteresis

I_{DDI (D)}

0.01

0.02

mA/Mbps Inputs switching, 50% duty cycle

I_{DDO (D)}

UVLO

V_DDxUV+

V_DDxUV−

V_DDxUVH

1.6

1.5

0.1

V

Rev. A | Page 3 of 22

ADuM130D/ADuM130E/ADuM131D/ADuM131E

Data Sheet

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions/Comments

AC SPECIFICATIONS

Output Rise/Fall Time

t_R/t_F

2.5

ns

10% to 90%

Common-Mode Transient

Immunity⁷

|CM_H|

75

100

kV/µs

V_Ix= V_DDx, V_CM= 1000 V,

transient magnitude = 800 V

V_Ix= 0 V, V_CM= 1000 V,

|CM_L|

100

kV/µs

transient magnitude = 800 V

¹150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.

²I_Oxis the Channel x output current, where x = A, B, or C.

³V_IxHis the input side logic high.

⁴V_IxLis the input side logic low.

⁵V_Iis the voltage input.

⁶E0 refers to the ADuM130E0/ADuM131E0 models, D0 refers to the ADuM130D0/ADuM131D0 models, E1 refers to the ADuM130E1/ADuM131E1 models, and D1 refers

to the ADuM130D1/ADuM131D1 models. See the Ordering Guide section.

⁷|CM_H| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (V_O) > 0.8 V_DDx. |CM_L| is the maximum common-

mode voltage slew rate that can be sustained while maintaining V_Ox> 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode

voltage edges.

Table 2. Total Supply Current vs. Data Throughput

1 Mbps

Typ

25 Mbps

Typ

100 Mbps

Typ

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Unit

SUPPLY CURRENT

ADuM130D/ADuM130E

Supply Current Side 1

Supply Current Side 2

ADuM131D/ADuM131E

Supply Current Side 1

Supply Current Side 2

I_DD1

I_DD2

5.6

1.9

9.0

3.7

6.3

3.1

9.8

4.9

9.4

6.8

14.3

10

mA

I_DD1

I_DD2

4.6

3.6

7.2

5.8

5.5

4.6

8.3

6.8

8.8

8.0

11.9

11.3

mA

ELECTRICAL CHARACTERISTICS—3.3 V OPERATION

All typical specifications are at T_A= 25°C, V_DD1= V_DD2= 3.3 V. Minimum/maximum specifications apply over the entire recommended

operation range: 3.0 V ≤ V_DD1≤ 3.6 V, 3.0 V ≤ V_DD2≤ 3.6 V, and −40°C ≤ T_A≤ +125°C, unless otherwise noted. Switching specifications

are tested with C_L= 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.

Table 3.

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions/Comments

SWITCHING SPECIFICATIONS

Pulse Width

PW

6.6

150

4.8

ns

Mbps

ns

ps/°C

ns

Within PWD limit

50% input to 50% output

|t_PLH− t_PHL|

Data Rate¹

Propagation Delay

Pulse Width Distortion

Change vs. Temperature

Propagation Delay Skew

t_PHL, t_PLH

PWD

6.8

0.7

1.5

14

3

t_PSK

7.5

Between any two devices at the

same temperature, voltage, and

load

Channel Matching

Codirectional

Opposing Direction

Jitter

t_PSKCD

t_PSKOD

0.7

640

75

3.0

ns

ps p-p

ps rms

See the Jitter Measurement section

DC SPECIFICATIONS

Input Threshold

Logic High

V_IH

V_IL

0.7 × V_DDx

V

Logic Low

0.3 × V_DDx

Rev. A | Page 4 of 22

Data Sheet

ADuM130D/ADuM130E/ADuM131D/ADuM131E

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions/Comments

Output Voltage

Logic High

3

V_OH

V_OL

V_DDx− 0.1 V_DDx

V_DDx− 0.4 V_DDx− 0.2

V

I_Ox²= −20 µA, V_Ix= V_IxH

3

I_Ox²= −2 mA, V_Ix= V_IxH

4

Logic Low

0.0

0.2

0.1

0.4

I_Ox²= 20 µA, V_Ix= V_IxL

4

I_Ox²= 2 mA, V_Ix= V_IxL

Input Current per Channel

I_I

−10

+0.01

−3

9

+10

µA

0 V ≤ V_Ix≤ V_DDx

V_E2= 0 V

DISABLE₁= V_DDx

0 V ≤ V_Ox≤ V_DDx

V_E2Enable Input Pull-Up Current

DISABLE₁Input Pull-Down Current

Tristate Output Current per Channel

I_PU

I_PD

I_OZ

15

+10

−10

+0.01

Quiescent Supply Current

ADuM130D/ADuM130E

I_{DD1 (Q)}

I_{DD2 (Q)}

I_{DD1 (Q)}

I_{DD2 (Q)}

1.25

1.65

9.57

1.79

2.5

2.8

15.0

2.9

mA

V_I⁵= 0 (E0, D0), 1 (E1, D1)⁶

V_I⁵= 1 (E0, D0), 0 (E1, D1)⁶

ADuM131D/ADuM131E

I_{DD1 (Q)}

I_{DD2 (Q)}

I_{DD1 (Q)}

I_{DD2 (Q)}

1.52

7.28

5.24

2.6

11.3

7.1

mA

V_I⁵= 0 (E0, D0), 1 (E1, D1)⁶

V_I⁵= 1 (E0, D0), 0 (E1, D1)⁶

Dynamic Supply Current

Dynamic Input

Dynamic Output

Undervoltage Lockout

Positive V_DDxThreshold

Negative V_DDxThreshold

V_DDxHysteresis

I_{DDI (D)}

0.01

mA/Mbps Inputs switching, 50% duty cycle

I_{DDO (D)}

UVLO

V_DDxUV+

V_DDxUV−

V_DDxUVH

1.6

1.5

0.1

V

AC SPECIFICATIONS

Output Rise/Fall Time

t_R/t_F

2.5

100

ns

kV/µs

10% to 90%

V_Ix= V_DDx, V_CM= 1000 V,

transient magnitude = 800 V

V_Ix= 0 V, V_CM= 1000 V,

Common-Mode Transient Immunity⁷|CM_H|

75

|CM_L|

100

kV/µs

transient magnitude = 800 V

¹150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.

²I_Oxis the Channel x output current, where x = A, B, or C.

³V_IxHis the input side logic high.

⁴V_IxLis the input side logic low.

⁵V_Iis the voltage input.

⁶E0 refers to the ADuM130E0/ADuM131E0 models, D0 refers to the ADuM130D0/ADuM131D0 models, E1 refers to the ADuM130E1/ADuM131E1 models, and D1 refers

to the ADuM130D1/ADuM131D1 models. See the Ordering Guide section.

⁷|CM_H| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (V_O) > 0.8 V_DDx. |CM_L| is the maximum common-

mode voltage slew rate that can be sustained while maintaining V_Ox> 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode

voltage edges.

Table 4. Total Supply Current vs. Data Throughput

1 Mbps

Typ

25 Mbps

Typ

100 Mbps

Typ

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Unit

SUPPLY CURRENT

ADuM130D/ADuM130E

Supply Current Side 1

Supply Current Side 2

ADuM131D/ADuM131E

Supply Current Side 1

Supply Current Side 2

I_DD1

I_DD2

5.4

1.8

8.8

3.6

6.0

2.9

9.4

4.7

8.5

6.2

12.7

8.4

mA

I_DD1

I_DD2

4.4

3.4

7.1

5.6

5.2

4.3

8.0

6.5

8.1

7.4

10.7

9.5

mA

Rev. A | Page 5 of 22

ADuM130D/ADuM130E/ADuM131D/ADuM131E

Data Sheet

ELECTRICAL CHARACTERISTICS—2.5 V OPERATION

All typical specifications are at T_A= 25°C, V_DD1= V_DD2= 2.5 V. Minimum/maximum specifications apply over the entire recommended

operation range: 2.25 V ≤ V_DD1≤ 2.75 V, 2.25 V ≤ V_DD2≤ 2.75 V, −40°C ≤ T_A≤ +125°C, unless otherwise noted. Switching specifications

are tested with C_L= 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.

Table 5.

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions/Comments

SWITCHING SPECIFICATIONS

Pulse Width

PW

6.6

150

5.0

ns

Mbps

ns

ps/°C

ns

Within PWD limit

50% input to 50% output

|t_PLH− t_PHL|

Data Rate¹

Propagation Delay

Pulse Width Distortion

Change vs. Temperature

Propagation Delay Skew

t_PHL, t_PLH

PWD

7.0

0.7

1.5

14

3

t_PSK

6.8

Between any two devices at the

same temperature, voltage, load

Channel Matching

Codirectional

Opposing Direction

Jitter

t_PSKCD

t_PSKOD

0.7

770

160

3.0

ns

ps p-p

ps rms

See the Jitter Measurement section

DC SPECIFICATIONS

Input Threshold

Logic High

Logic Low

Output Voltage

Logic High

V_IH

V_IL

0.7 × V_DDx

V_DDx− 0.1

V

0.3 × V_DDx

3

V_OH

V_OL

V_DDx

V

I_Ox²= −20 µA, V_Ix= V_IxH

3

V_DDx− 0.4 V_DDx− 0.2

I_Ox²= −2 mA, V_Ix= V_IxH

4

Logic Low

0.0

0.2

0.1

0.4

I_Ox²= 20 µA, V_Ix= V_IxL

4

I_Ox²= 2 mA, V_Ix= V_IxL

Input Current per Channel

I_I

−10

+0.01

−3

9

+10

µA

0 V ≤ V_Ix≤ V_DDx

V_E2= 0 V

DISABLE₁= V_DDx

0 V ≤ V_Ox≤ V_DDx

V_E2Enable Input Pull-Up Current

DISABLE₁Input Pull-Down Current

Tristate Output Current per Channel

Quiescent Supply Current

I_PU

I_PD

I_OZ

15

+10

−10

+0.01

ADuM130D/ADuM130E

I_{DD1 (Q)}

I_{DD2 (Q)}

I_{DD1 (Q)}

I_{DD2 (Q)}

1.2

2.4

2.7

14.9

2.8

mA

V_I⁵= 0 (E0, D0), 1 (E1, D1)⁶

V_I⁵= 1 (E0, D0), 0 (E1, D1)⁶

1.61

9.52

1.76

ADuM131D/ADuM131E

I_{DD1 (Q)}

I_{DD2 (Q)}

I_{DD1 (Q)}

I_{DD2 (Q)}

1.47

1.48

7.23

5.19

2.5

11.2

7.0

mA

V_I⁵= 0 (E0, D0), 1 (E1, D1)⁶

V_I⁵= 1 (E0, D0), 0 (E1, D1)⁶

Dynamic Supply Current

Dynamic Input

Dynamic Output

I_{DDI (D)}

I_{DDO (D)}

0.01

mA/Mbps Inputs switching, 50% duty cycle

Undervoltage Lockout

Positive V_DDxThreshold

Negative V_DDxThreshold

V_DDxHysteresis

V_DDxUV+

V_DDxUV−

V_DDxUVH

1.6

1.5

0.1

V

Rev. A | Page 6 of 22

Data Sheet

ADuM130D/ADuM130E/ADuM131D/ADuM131E

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions/Comments

AC SPECIFICATIONS

Output Rise/Fall Time

Common-Mode Transient Immunity⁷

t_R/t_F

|CM_H|

2.5

100

ns

kV/µs

10% to 90%

V_Ix= V_DDx, V_CM= 1000 V,

transient magnitude = 800 V

V_Ix= 0 V, V_CM= 1000 V,

75

|CM_L|

100

kV/µs

transient magnitude = 800 V

¹150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.

²I_Oxis the Channel x output current, where x = A, B, or C.

³V_IxHis the input side logic high.

⁴V_IxLis the input side logic low.

⁵V_Iis the voltage input.

⁶E0 refers to the ADuM130E0/ADuM131E0 models, D0 refers to the ADuM130D0/ADuM131D0 models, E1 refers to the ADuM130E1/ADuM131E1 models, and D1 refers

to the ADuM130D1/ADuM131D1 models. See the Ordering Guide section.

⁷|CM_H| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (V_O) > 0.8 V_DDx. |CM_L| is the maximum common-

mode voltage slew rate that can be sustained while maintaining V_Ox> 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode

voltage edges.

Table 6. Total Supply Current vs. Data Throughput

1 Mbps

Typ

25 Mbps

Typ

100 Mbps

Typ

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Unit

SUPPLY CURRENT

ADuM130E/ADuM130D

Supply Current Side 1

Supply Current Side 2

ADuM131E/ADuM131D

Supply Current Side 1

Supply Current Side 2

I_DD1

I_DD2

5.3

1.8

8.7

3.6

5.9

2.6

9.3

4.4

8.2

5.2

12.3

7.4

mA

I_DD1

I_DD2

4.4

3.4

7.1

5.6

5.0

4.1

7.8

6.3

7.5

6.6

10.1

8.7

mA

ELECTRICAL CHARACTERISTICS—1.8 V OPERATION

All typical specifications are at T_A= 25°C, V_DD1= V_DD2= 1.8 V. Minimum/maximum specifications apply over the entire recommended

operation range: 1.7 V ≤ V_DD1≤ 1.9 V, 1.7 V ≤ V_DD2≤ 1.9 V, and −40°C ≤ T_A≤ +125°C, unless otherwise noted. Switching specifications

are tested with C_L= 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.

Table 7.

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions/Comments

SWITCHING SPECIFICATIONS

Pulse Width

PW

6.6

150

5.8

ns

Mbps

ns

ps/°C

ns

Within PWD limit

50% input to 50% output

|t_PLH− t_PHL|

Data Rate¹

Propagation Delay

Pulse Width Distortion

Change vs. Temperature

Propagation Delay Skew

t_PHL, t_PLH

PWD

8.7

0.7

1.5

15

3

t_PSK

7.0

Between any two devices at the

same temperature, voltage, and

load

Channel Matching

Codirectional

Opposing Direction

Jitter

t_PSKCD

t_PSKOD

0.7

600

90

3.0

ns

ps p-p

ps rms

See the Jitter Measurement section

DC SPECIFICATIONS

Input Threshold

Logic High

Logic Low

Output Voltage

Logic High

V_IH

V_IL

0.7 × V_DDx

V_DDx− 0.1

V

0.3 × V_DDx

3

V_OH

V_DDx

V

I_Ox²= −20 µA, V_Ix= V_IxH

3

V_DDx− 0.4 V_DDx− 0.2

I_Ox²= −2 mA, V_Ix= V_IxH

Rev. A | Page 7 of 22

ADuM130D/ADuM130E/ADuM131D/ADuM131E

Data Sheet

Parameter

Logic Low

Symbol Min

Typ

0.0

0.2

+0.01

−3

9

Max

0.1

0.4

Unit

V

µA

Test Conditions/Comments

I_Ox²= 20 µA, V_Ix= V_IxL

4

V_OL

4

I_Ox²= 2 mA, V_Ix= V_IxL

0 V ≤ V_Ix≤ V_DDx

V_E2= 0 V

Input Current per Channel

I_I

−10

+10

V_E2Enable Input Pull-Up Current

DISABLE₁Input Pull-Down Current

Tristate Output Current per Channel

Quiescent Supply Current

I_PU

I_PD

I_OZ

15

+10

DISABLE₁= V_DDx

0 V ≤ V_Ox≤ V_DDx

−10

+0.01

ADuM130D/ADuM130E

I_{DD1 (Q)}

I_{DD2 (Q)}

I_{DD1 (Q)}

I_{DD2 (Q)}

1.15

1.58

9.41

1.72

2.3

2.6

14.8

2.7

mA

V_I⁵= 0 (E0, D0), 1 (E1, D1)⁶

V_I⁵= 1 (E0, D0), 0 (E1, D1)⁶

ADuM131D/ADuM131E

I_{DD1 (Q)}

I_{DD2 (Q)}

I_{DD1 (Q)}

I_{DD2 (Q)}

1.42

1.44

7.15

5.13

2.4

11.1

6.9

mA

V_I⁵= 0 (E0, D0), 1 (E1, D1)⁶

V_I⁵= 1 (E0, D0), 0 (E1, D1)⁶

Dynamic Supply Current

Dynamic Input

Dynamic Output

Undervoltage Lockout

Positive V_DDxThreshold

Negative V_DDxThreshold

V_DDxHysteresis

I_{DDI (D)}

0.01

mA/Mbps Inputs switching, 50% duty cycle

I_{DDO (D)}

UVLO

V_DDxUV+

V_DDxUV−

V_DDxUVH

1.6

1.5

0.1

V

AC SPECIFICATIONS

Output Rise/Fall Time

t_R/t_F

2.5

100

ns

kV/µs

10% to 90%

V_Ix= V_DDx, V_CM= 1000 V,

transient magnitude = 800 V

V_Ix= 0 V, V_CM= 1000 V,

Common-Mode Transient Immunity⁷|CM_H|

75

|CM_L|

100

kV/µs

transient magnitude = 800 V

¹150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.

²I_Oxis the Channel x output current, where x = A, B, or C.

³V_IxHis the input side logic high.

⁴V_IxLis the input side logic low.

⁵V_Iis the voltage input.

⁶E0 refers to the ADuM130E0/ADuM131E0 models, D0 refers to the ADuM130D0/ADuM131D0 models, E1 refers to the ADuM130E1/ADuM131E1 models, and D1 refers

to the ADuM130D1/ADuM131D1 models. See the Ordering Guide section.

⁷|CM_H| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (V_O) > 0.8 V_DDx. |CM_L| is the maximum common-

mode voltage slew rate that can be sustained while maintaining V_Ox> 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode

voltage edges.

Table 8. Total Supply Current vs. Data Throughput

1 Mbps

Typ

25 Mbps

Typ

100 Mbps

Typ

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Unit

SUPPLY CURRENT

ADuM130D/ADuM130E

Supply Current Side 1

Supply Current Side 2

ADuM131D/ADuM131E

Supply Current Side 1

Supply Current Side 2

I_DD1

I_DD2

5.2

1.7

8.6

3.5

5.8

2.5

9.3

4.3

8.1

5.2

12.2

7.3

mA

I_DD1

I_DD2

4.3

3.3

7.0

5.5

4.9

4.0

7.7

6.2

7.26

6.5

10.0

8.6

mA

Rev. A | Page 8 of 22

Data Sheet

ADuM130D/ADuM130E/ADuM131D/ADuM131E

INSULATION AND SAFETY RELATED SPECIFICATIONS

For additional information, see www.analog.com/icouplersafety.

Table 9. R-16 Narrow Body [SOIC_N] Package

Parameter

Symbol Value Unit

Test Conditions/Comments

Rated Dielectric Insulation Voltage

Minimum External Air Gap (Clearance)

3000

4.0

V rms

1-minute duration

L (I01)

L (I02)

L (PCB)

mm min Measured from input terminals to output terminals,

shortest distance through air

mm min Measured from input terminals to output terminals,

shortest distance path along body

mm min Measured from input terminals to output terminals,

shortest distance through air, line of sight, in the PCB

mounting plane

Minimum External Tracking (Creepage)

4.0

4.5

Minimum Clearance in the Plane of the Printed

Circuit Board (PCB Clearance)

Minimum Internal Gap (Internal Clearance)

Tracking Resistance (Comparative Tracking Index)

Material Group

25.5

>400

II

μm min

V

Insulation distance through insulation

DIN IEC 112/VDE 0303 Part 1

Material Group (DIN VDE 0110, 1/89, Table 1)

CTI

Table 10. RW-16 Wide Body [SOIC_W] Package

Parameter

Symbol Value Unit

Test Conditions/Comments

Rated Dielectric Insulation Voltage

Minimum External Air Gap (Clearance)

3750

7.8

V rms

1-minute duration

L (I01)

L (I02)

L (PCB)

mm min Measured from input terminals to output terminals,

shortest distance through air

mm min Measured from input terminals to output terminals,

shortest distance path along body

mm min Measured from input terminals to output terminals,

shortest distance through air, line of sight, in the PCB

mounting plane

Minimum External Tracking (Creepage)

7.8

8.1

Minimum Clearance in the Plane of the Printed

Circuit Board (PCB Clearance)

Minimum Internal Gap (Internal Clearance)

Tracking Resistance (Comparative Tracking Index)

Material Group

25.5

>400

II

μm min

V

Insulation distance through insulation

DIN IEC 112/VDE 0303 Part 1

Material Group (DIN VDE 0110, 1/89, Table 1)

CTI

PACKAGE CHARACTERISTICS

Table 11.

Parameter

Symbol Min Typ Max Unit Test Conditions/Comments

Resistance (Input to Output)¹

Capacitance (Input to Output)¹

Input Capacitance²

R_I-O

C_I-O

C_I

10¹³

2.2

4.0

Ω

pF

f = 1 MHz

IC Junction to Ambient Thermal Resistance

R-16 Narrow Body [SOIC_N] Package

RW-16 Wide Body [SOIC_W] Package

θ_JA

76

45

°C/W Thermocouple located at center of package underside

¹The device is considered a 2-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.

²Input capacitance is from any input data pin to ground.

Rev. A | Page 9 of 22

ADuM130D/ADuM130E/ADuM131D/ADuM131E

Data Sheet

REGULATORY INFORMATION

See Table 19 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-

isolation waveforms and insulation levels.

Table 12. R-16 Narrow Body [SOIC_N] Package

UL (Pending)

CSA (Pending)

VDE (Pending)

CQC (Pending)

Recognized Under UL 1577

Component Recognition

Program¹

Approved under CSA Component

Acceptance Notice 5A

Certified according to DIN V VDE V

0884-10 (VDE V 0884-10):2006-12²

Certified under

CQC11-471543-2012

Single Protection, 3000 V rms

Isolation Voltage

CSA 60950-1-07+A1+A2 and IEC

60950-1, second edition, +A1+A2:

Reinforced insulation, V_IORM

565 V peak, V_IOSM= 6000 V peak

=

GB4943.1-2011:

Double Protection, 3000 V rms Basic insulation at 400 V rms

Basic insulation, V_IORM= 565 V peak,

Basic insulation at

Isolation Voltage

(565 V peak)

V

_IOSM= 10 kV peak

770 V rms (1089 V peak)

Reinforced insulation at 200 V rms

(283 V peak)

Reinforced insulation at

385 V rms (545 V peak)

IEC 60601-1 Edition 3.1: Basic

insulation (one means of patient

protection (1 MOPP)), 250 V rms

(354 V peak)

Tropical climate, altitude

≤5000 m

CSA 61010-1-12 and IEC 61010-1

third edition:

Basic insulation at 300 V rms mains,

400 V rms secondary (565 V peak)

Reinforced insulation at 300 V rms

mains, 200 V secondary (282 V peak)

File E214100

File 205078

File 2471900-4880-0001

File (pending)

¹In accordance with UL 1577, each ADuM130D/ADuM130E/ADuM131D/ADuM131E in the R-16 narrow body [SOIC_N] package is proof tested by applying an insulation

test voltage ≥ 3600 V rms for 1 sec.

²In accordance with DIN V VDE V 0884-10, each ADuM130D/ADuM130E/ADuM131D/ADuM131E in the R-16 narrow body [SOIC_N] package is proof tested by applying an

insulation test voltage ≥ 1059 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.

Table 13. RW-16 Wide Body [SOIC_W] Package

UL (Pending)

CSA (Pending)

VDE (Pending)

CQC (Pending)

Recognized Under UL 1577

Component Recognition

Program¹

Approved under CSA Component

Acceptance Notice 5A

Certified according to DIN V VDE V

0884-10 (VDE V 0884-10):2006-12²

Certified under

CQC11-471543-2012

Single Protection, 3750 V rms

Isolation Voltage

CSA 60950-1-07+A1+A2 and IEC 60950-1,

second edition, +A1+A2:

Reinforced insulation, V_IORM

849 V peak, V_IOSM= 6000 V peak

=

GB4943.1-2011

Double Protection, 3750 V rms Basic insulation at 780 V rms

Basic insulation, V_IORM= 849 V peak,

V_IOSM= 10 kV peak

Basic insulation at

780 V rms (1103 V peak)

Isolation Voltage

(1103 V peak)

Reinforced insulation at 390 V rms

(552 V peak)

Reinforced insulation at

390 V rms (552 V peak)

IEC 60601-1 Edition 3.1: basic insulation

(1 means of patient protection (MOPP)),

490 V rms (693 V peak)

Tropical climate,

altitude ≤5000 m

CSA 61010-1-12 and IEC 61010-1 third

edition:

Basic insulation at 300 V rms mains, 780V

secondary (1103 V peak)

Reinforced insulation at 300 V rms mains,

390 V secondary (552 V peak)

File E214100

File 205078

File 2471900-4880-0001

File (pending)

¹In accordance with UL 1577, each ADuM130D/ADuM130E/ADuM131D/ADuM131E in the RW-16 wide body [SOIC_W] package is proof tested by applying an insulation

test voltage ≥ 4500 V rms for 1 sec.

²In accordance with DIN V VDE V 0884-10, each ADuM130D/ADuM130E/ADuM131D/ADuM131E in the RW-16 wide body [SOIC_W] package is proof tested by applying an

insulation test voltage ≥ 1592 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.

Rev. A | Page 10 of 22

Data Sheet

ADuM130D/ADuM130E/ADuM131D/ADuM131E

DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS

These isolators are suitable for reinforced electrical isolation only within the safety limit data. Protective circuits ensure the maintenance

of the safety data. The * marking on packages denotes DIN V VDE V 0884-10 approval.

Table 14. R-16 Narrow Body [SOIC_N] Package

Description

Test Conditions/Comments

Symbol

Characteristic Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 150 V rms

For Rated Mains Voltage ≤ 300 V rms

For Rated Mains Voltage ≤ 600 V rms

Climatic Classification

Pollution Degree per DIN VDE 0110, Table 1

Maximum Working Insulation Voltage

Input to Output Test Voltage, Method B1

I to IV

I to III

40/125/21

2

V_IORM

V_{pd (m)}

565

1059

V peak

V_IORM× 1.875 = V_{pd (m)}, 100% production test,

t

_ini= t_m= 1 sec, partial discharge < 5 pC

Input to Output Test Voltage, Method A

After Environmental Tests Subgroup 1

V_{pd (m)}

V_IORM× 1.5 = V_{pd (m)}, t_ini= 60 sec, t_m= 10 sec,

partial discharge < 5 pC

V_IORM× 1.2 = V_{pd (m)}, t_ini= 60 sec, t_m= 10 sec,

partial discharge < 5 pC

848

678

V peak

After Input and/or Safety Test Subgroup 2

and Subgroup 3

Highest Allowable Overvoltage

Surge Isolation Voltage Basic

V_IOTM

V_IOSM

4200

10000

V peak

V peak = 10 kV, 1.2 µs rise time, 50 µs,

50% fall time

Surge Isolation Voltage Reinforced

V peak = 10 kV, 1.2 µs rise time, 50 µs,

50% fall time

V_IOSM

6000

V peak

Safety Limiting Values

Maximum value allowed in the event of a failure

(see Figure 5)

Maximum Junction Temperature

Total Power Dissipation at 25°C

Insulation Resistance at T_S

T_S

P_S

R_S

150

1.64

>10⁹

°C

W

Ω

V_IO= 500 V

Rev. A | Page 11 of 22

ADuM130D/ADuM130E/ADuM131D/ADuM131E

Data Sheet

Table 15. RW-16 Wide Body [SOIC_W] Package

Description

Test Conditions/Comments

Symbol Characteristic Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 150 V rms

For Rated Mains Voltage ≤ 300 V rms

For Rated Mains Voltage ≤ 600 V rms

Climatic Classification

Pollution Degree per DIN VDE 0110, Table 1

Maximum Working Insulation Voltage

Input to Output Test Voltage, Method B1

I to IV

I to III

40/125/21

2

V_IORM

V_{pd (m)}

849

1592

V peak

V_IORM× 1.875 = V_{pd (m)}, 100% production test,

t

_ini= t_m= 1 sec, partial discharge < 5 pC

Input to Output Test Voltage, Method A

After Environmental Tests Subgroup 1

V_{pd (m)}

V_IORM× 1.5 = V_{pd (m)}, t_ini= 60 sec, t_m= 10 sec,

partial discharge < 5 pC

V_IORM× 1.2 = V_{pd (m)}, t_ini= 60 sec, t_m= 10 sec,

partial discharge < 5 pC

1274

1019

5300

V peak

After Input and/or Safety Test Subgroup 2

and Subgroup 3

Highest Allowable Overvoltage

Surge Isolation Voltage

Basic

V_IOTM

V_PEAK= 12.8 kV, 1.2 µs rise time, 50 µs, 50% fall time

V_PEAK= 10 kV, 1.2 µs rise time, 50 µs, 50% fall time

V_IOSM

12,000

6000

V peak

Reinforced

Safety Limiting Values

Maximum value allowed in the event of a failure

(see Figure 6)

Maximum Junction Temperature

Total Power Dissipation at 25°C

Insulation Resistance at T_S

T_S

P_S

R_S

150

2.78

>10⁹

°C

W

Ω

V_IO= 500 V

3.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

2.5

2.0

1.5

1.0

0.5

0

50

100

150

200

0

50

100

150

200

AMBIENT TEMPERATURE (°C)

Figure 6. Thermal Derating Curve, Dependence of Safety Limiting Values

with Ambient Temperature per DIN V VDE V 0884-10

Figure 5. Thermal Derating Curve for R-16 Narrow Body [SOIC_N] Package,

Dependence of Safety Limiting Values with Ambient Temperature per

DIN V VDE V 0884-10

RECOMMENDED OPERATING CONDITIONS

Table 16.

Parameter

Symbol

T_A

V_DD1, V_DD2

Rating

Operating Temperature

Supply Voltages

Input Signal Rise and Fall Times

−40°C to +125°C

1.7 V to 5.5 V

1.0 ms

Rev. A | Page 12 of 22

Data Sheet

ADuM130D/ADuM130E/ADuM131D/ADuM131E

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Table 17.

Parameter

Rating

Storage Temperature (T_ST) Range

Ambient Operating Temperature

(T_A) Range

−65°C to +150°C

−40°C to +125°C

Supply Voltages (V_DD1, V_DD2

Input Voltages (V_IA, V_IB, V_IC, V_E1, V_E2,

DISABLE₁, DISABLE₂)

Output Voltages (V_OA, V_OB, V_OC)

Average Output Current per Pin³

Side 1 Output Current (I_O1)

Side 2 Output Current (I_O2)

Common-Mode Transients⁴

)

−0.5 V to +7.0 V

−0.5 V to V_DDI¹+ 0.5 V

ESD CAUTION

−0.5 V to V_DDO²+ 0.5 V

−10 mA to +10 mA

−150 kV/μs to +150 kV/μs

¹V_DDIis the input side supply voltage.

²V_DDOis the output side supply voltage.

³See Figure 5 for the R-16 narrow body [SOIC_N] package or Figure 6 for the

RW-16 wide body [SOIC_W] package for the maximum rated current values

for various ambient temperatures.

⁴Refers to the common-mode transients across the insulation barrier.

Common-mode transients exceeding the absolute maximum ratings may

cause latch-up or permanent damage.

Table 18. Maximum Continuous Working Voltage R-16 Narrow Body [SOIC_N] Package¹

Parameter

Rating

Constraint²

AC Voltage

Bipolar Waveform

Basic Insulation

Reinforced Insulation

Unipolar Waveform

Basic Insulation

Reinforced Insulation

DC Voltage

789 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1

403 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1

909 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1

469 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1

Basic Insulation

Reinforced Insulation

558 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1

285 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1

¹Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.

²Insulation lifetime for the specified test condition is greater than 50 years.

Table 19. Maximum Continuous Working Voltage RW-16 Wide Body [SOIC_W] Package¹

Parameter

Rating

Constraint²

AC Voltage

Bipolar Waveform

Basic Insulation

Reinforced Insulation

Unipolar Waveform

Basic Insulation

Reinforced Insulation

DC Voltage

849 V peak

768 V peak

50-year minimum insulation lifetime

Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1

1698 V peak 50-year minimum insulation lifetime

768 V peak

Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1

Basic Insulation

Reinforced Insulation

1092 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1

543 V peak

Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1

¹Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.

²Insulation lifetime for the specified test condition is greater than 50 years.

Rev. A | Page 13 of 22

ADuM130D/ADuM130E/ADuM131D/ADuM131E

Data Sheet

TRUTH TABLES

Table 20. ADuM130D/ADuM131D Truth Table (Positive Logic)

Default Low (D0), Default High (D1),

V_IxInput^{1, 2}V_DISABLExInput^{1, 2}

V_DDIState²

Powered

Unpowered

Powered

V_DDOState²

Powered

Unpowered

V_OxOutput^{1, 2, 3}

Test Conditions/Comments

Normal operation

Inputs disabled, fail-safe output

Fail-safe output

L

H

X

L or NC

H

L

H

L

H

X⁴

L

H

X⁴

Indeterminate

¹L means low, H means high, X means don’t care, and NC means not connected.

²V_Ixand V_Oxrefer to the input and output signals of a given channel (A, B, or C). V_DISABLExrefers to the input disable signal on the same side as the V_Ixinputs. V_DDIand V_DDO

refer to the supply voltages on the input and output sides of the given channel, respectively.

³E0 refers to the ADuM130E0/ADuM131E0 models, D0 refers to the ADuM130D0/ADuM131D0 models, E1 refers to the ADuM130E1/ADuM131E1 models, and D1 refers

to the ADuM130D1/ADuM131D1 models. See the Ordering Guide section.

⁴Input pins (V_Ix, DISABLE₁, and DISABLE₂) on the same side as an unpowered supply must be in a low state to avoid powering the device through its ESD protection

circuitry.

Table 21. ADuM130E/ADuM131E Truth Table (Positive Logic)

Default Low (E0),

Default High (E1),

V_OxOutput^{1, 2, 3}

V_IxInput^{1, 2}

V_ExInput^{1, 2}

H or NC

L

H or NC

L⁴

X⁴

V_DDIState²

Powered

Unpowered

Powered

V_DDOState²

Powered

Unpowered

V_OxOutput^{1, 2, 3}

Test Conditions/Comments

Normal operation

Outputs disabled

Fail-safe output

L

H

X

L

X⁴

L

H

Z

L

H

Z

H

Z

Outputs disabled

Indeterminate

¹L means low, H means high, X means don’t care, and NC means not connected, and Z means high impedance.

²V_Ixand V_Oxrefer to the input and output signals of a given channel (A, B, C, or D). V_Exrefers to the output enable signal on the same side as the V_Oxoutputs. V_DDIand

V

_DDOrefer to the supply voltages on the input and output sides of the given channel, respectively.

³E0 refers to the ADuM130E0/ADuM131E0 models, D0 refers to the ADuM130D0/ADuM131D0 models, E1 refers to the ADuM130E1/ADuM131E1 models, and D1 refers

to the ADuM130D1/ADuM131D1 models. See the Ordering Guide section.

⁴Input pins (V_Ix, V_E1, and V_E2) on the same side as an unpowered supply must be in a low state to avoid powering the device through its ESD protection circuitry.

Rev. A | Page 14 of 22

Data Sheet

ADuM130D/ADuM130E/ADuM131D/ADuM131E

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

16

15 GND

V

1

2

3

4

5

6

7

8

16

15 GND

V

DD1

DD2

DD1

DD2

GND

V

GND

V

1

2

1

2

14

13

12

V

14

13

12

V

IA

IB

IC

OA

OB

OC

IA

IB

IC

OA

OB

OC

ADuM130E

ADuM130D

V

TOP VIEW

(Not to Scale)

11 NIC

NIC

11 NIC

V

10

9

10

E2

DISABLE

NIC

1

GND

2

GND

9 GND

2

1

NIC = NO INTERNAL CONNECTION.

LEAVE THIS PIN FLOATING.

NIC = NO INTERNAL CONNECTION.

LEAVE THIS PIN FLOATING.

Figure 8. ADuM130E Pin Configuration

Figure 7. ADuM130D Pin Configuration

Table 22. Pin Function Descriptions

Pin No.¹

ADuM130E

ADuM130D

Mnemonic Description

1

2, 8

3

1

2, 8

3

V_DD1

GND₁

V_IA

Supply Voltage for Isolator Side 1.

Ground 1. Ground reference for Isolator Side 1.

Logic Input A.

4

V_IB

Logic Input B.

5

V_IC

Logic Input C.

6, 10, 11

7

6, 7, 11

Not applicable DISABLE₁

NIC

No Internal Connection. Leave these pins floating.

Input Disable 1. This pin disables the isolator inputs. Outputs take on the logic state

determined by the fail-safe option shown in the Ordering Guide.

9, 15

Not applicable

9, 15

10

GND₂

V_E2

Ground 2. Ground reference for Isolator Side 2.

Output Enable 2. Active high logic input. When V_E2is high or disconnected, the V_OA, V_OB,

and V_OCoutputs are enabled. When V_E2is low, the V_OA, V_OB, and V_OCoutputs are disabled

to the high-Z state.

12

13

14

16

12

13

14

16

V_OC

V_OB

V_OA

V_DD2

Logic Output C.

Logic Output B.

Logic Output A.

Supply Voltage for Isolator Side 2.

¹Reference the AN-1109 Application Note for specific layout guidelines.

Rev. A | Page 15 of 22

ADuM130D/ADuM130E/ADuM131D/ADuM131E

Data Sheet

V

1

2

3

4

5

6

7

8

16

V

1

2

3

4

5

6

7

8

16

V

DD1

DD2

DD1

DD2

2

GND

V

15 GND

GND

V

15 GND

1

2

14

13

12

V

14

13

12

11

10

9

V

IA

IB

OA

OB

IC

IA

IB

OA

OB

IC

ADuM131E

ADuM131D

V

TOP VIEW

V

(Not to Scale)

OC

(Not to Scale)

OC

NIC

11 NIC

NIC

V

10

9

V

E2

DISABLE

E1

1

2

GND

2

GND

2

1

NIC = NO INTERNAL CONNECTION.

LEAVE THIS PIN FLOATING.

NIC = NO INTERNAL CONNECTION.

LEAVE THIS PIN FLOATING.

Figure 10. ADuM131E Pin Configuration

Figure 9. ADuM131D Pin Configuration

Table 23. Pin Function Descriptions

Pin No.¹

ADuM131E

ADuM131D

Mnemonic Description

1

2, 8

3

1

2, 8

3

V_DD1

GND₁

V_IA

Supply Voltage for Isolator Side 1.

Ground 1. Ground reference for Isolator Side 1.

Logic Input A.

4

V_IB

Logic Input B.

5

V_OC

Logic Output C.

6, 11

7

6, 11

NIC

No Internal Connection. Leave this pin floating.

Input Disable 1. This pin disables the isolator inputs. Outputs take on the logic state

determined by the fail-safe option shown in the Ordering Guide.

Not applicable DISABLE₁

Not applicable

7

V_E1

Output Enable 1. Active high logic input. When V_E1is high or disconnected, the V_OC

output is enabled. When V_E1is low, the V_OCoutput is disabled to the high-Z state.

9, 15

10

9, 15

GND₂

Ground 2. Ground reference for Isolator Side 2.

Input Disable 2. This pin disables the isolator inputs. Outputs take on the logic state

determined by the fail-safe option shown in the Ordering Guide.

Not applicable DISABLE₂

Not applicable

10

V_E2

Output Enable 2. Active high logic input. When V_E2is high or disconnected, the V_OAand

V

_OBoutputs are enabled. When V_E2is low, the V_OAand V_OBoutputs are disabled to the

high-Z state.

12

13

14

16

12

13

14

16

V_IC

Logic Input C.

Logic Output B.

Logic Output A.

Supply Voltage for Isolator Side 2.

V_OB

V_OA

V_DD2

¹Reference the AN-1109 Application Note for specific layout guidelines.

Rev. A | Page 16 of 22

Data Sheet

ADuM130D/ADuM130E/ADuM131D/ADuM131E

TYPICAL PERFORMANCE CHARACTERISTICS

16

5.0V

3.3V

5.0V

3.3V

2.5V

1.8V

14

12

10

8

2.5V

1.8V

12

10

8

6

4

2

0

20

40

60

80

100

120

140

160

0

20

40

60

80

100

120

140

160

DATA RATE (Mbps)

Figure 11. ADuM130D/ADuM130E I_DD1Supply Current vs. Data Rate at

Various Voltages

Figure 14. ADuM131D/ADuM131E I_DD2Supply Current vs. Data Rate at

Various Voltages

16

14

5.0V

3.3V

5.0V

3.3V

14

12

10

8

2.5V

1.8V

12

1.8V

10

8

6

4

2

0

6

4

2

0

–40

–20

0

20

40

60

80

100

120

140

0

20

40

60

80

100

120

140

160

TEMPERATURE (°C)

DATA RATE (Mbps)

Figure 15. Propagation Delay (t_PLH) vs. Temperature at Various Voltages

Figure 12. ADuM130D/ADuM130E I_DD2Supply Current vs. Data Rate at

Various Voltages

14

16

5.0V

3.3V

5.0V

3.3V

2.5V

14

12

10

8

2.5V

1.8V

12

1.8V

10

8

6

4

2

0

6

4

2

0

20

40

60

80

100

120

140

160

–40

–20

0

20

40

60

80

100

120

140

DATA RATE (Mbps)

TEMPERATURE (°C)

Figure 13. ADuM131D/ADuM131E I_DD1Supply Current vs. Data Rate at

Various Voltages

Figure 16. Propagation Delay( t_PHL) vs. Temperature at Various Voltages

Rev. A | Page 17 of 22

ADuM130D/ADuM130E/ADuM131D/ADuM131E

Data Sheet

APPLICATIONS INFORMATION

OVERVIEW

PRINTED CIRCUIT BOARD (PCB) LAYOUT

The ADuM130D/ADuM130E/ADuM131D/ADuM131E use a

high frequency carrier to transmit data across the isolation barrier

using iCoupler chip scale transformer coils separated by layers of

polyimide isolation. Using an on/off keying (OOK) technique

and the differential architecture shown in Figure 18 and Figure 19,

the ADuM130D/ADuM130E/ADuM131D/ADuM131E have very

low propagation delay and high speed. Internal regulators and

input/output design techniques allow logic and supply voltages

over a wide range from 1.7 V to 5.5 V, offering voltage translation

of 1.8 V, 2.5 V, 3.3 V, and 5 V logic. The architecture is designed

for high common-mode transient immunity and high immunity to

electrical noise and magnetic interference. Radiated emissions

are minimized with a spread spectrum OOK carrier and other

techniques.

The ADuM130D/ADuM130E/ADuM131D/ADuM131E digital

isolators require no external interface circuitry for the logic

interfaces. Power supply bypassing is strongly recommended at

the input and output supply pins (see Figure 17). Bypass capacitors

are most conveniently connected between Pin 1 and Pin 2 for

V_DD1and between Pin 15 and Pin 16 for V_DD2. The recommended

bypass capacitor value is between 0.01 µF and 0.1 µF. The total

lead length between both ends of the capacitor and the input

power supply pin must not exceed 10 mm. Bypassing between

Pin 1 and Pin 8 and between Pin 9 and Pin 16 must also be

considered, unless the ground pair on each package side is

connected close to the package.

V

DD2

DD1

GND

V

GND

1

IA

IB

2

V

OA

OB

/V

IC OC

Figure 18 illustrates the waveforms for models of the ADuM130D/

ADuM130E/ADuM131D/ADuM131E that have the condition of

the fail-safe output state equal to low, where the carrier waveform is

off when the input state is low. If the input side is off or not

operating, the fail-safe output state of low (the ADuM130D0,

ADuM131D0, ADuM130E0, and ADuM131E0 models) sets the

output to low. For the ADuM130D/ADuM130E/ADuM131D/

ADuM131E that have a fail-safe output state of high, Figure 19

illustrates the conditions where the carrier waveform is off

when the input state is high. When the input side is off or not

operating, the fail-safe output state of high (the ADuM130D1,

ADuM131D1, ADuM130E1, and ADuM131E1 models) sets the

output to high. See the Ordering Guide for the model numbers

that have the fail-safe output state of low or the fail-safe output

state of high.

V

/V

IC OC

NIC

DISABLE /V

E2

DISABLE /V

1

E1

2

GND

2

1

NIC = NO INTERNAL CONNECTION. LEAVE THIS PIN FLOATING.

Figure 17. Recommended PCB Layout

In applications involving high common-mode transients, ensure

that board coupling across the isolation barrier is minimized.

Furthermore, design the board layout such that any coupling that

does occur equally affects all pins on a given component side.

Failure to ensure this can cause voltage differentials between pins

exceeding the Absolute Maximum Ratings of the device, thereby

leading to latch-up or permanent damage.

See the AN-1109 Application Note for board layout guidelines.

REGULATOR

RECEIVER

TRANSMITTER

V

OUT

IN

GND

2

1

Figure 18. Operational Block Diagram of a Single Channel with a Low Fail-Safe Output State

REGULATOR

TRANSMITTER

RECEIVER

V

OUT

IN

GND

2

1

Figure 19. Operational Block Diagram of a Single Channel with a High Fail-Safe Output State

Rev. A | Page 18 of 22

Data Sheet

ADuM130D/ADuM130E/ADuM131D/ADuM131E

PROPAGATION DELAY RELATED PARAMETERS

INSULATION LIFETIME

Propagation delay is a parameter that describes the time it takes

a logic signal to propagate through a component. The propagation

delay to a Logic 0 output may differ from the propagation delay

to a Logic 1 output.

All insulation structures eventually break down when subjected to

voltage stress over a sufficiently long period. The rate of insulation

degradation is dependent on the characteristics of the voltage

waveform applied across the insulation as well as on the materials

and material interfaces.

INPUT (V

)

50%

Ix

The two types of insulation degradation of primary interest are

breakdown along surfaces exposed to the air and insulation wear

out. Surface breakdown is the phenomenon of surface tracking

and the primary determinant of surface creepage requirements

in system level standards. Insulation wear out is the phenomenon

where charge injection or displacement currents inside the

insulation material cause long-term insulation degradation.

t_PLH

t_PHL

OUTPUT (V

)

50%

Ox

Figure 20. Propagation Delay Parameters

Pulse width distortion is the maximum difference between these

two propagation delay values and is an indication of how accurately

the timing of the input signal is preserved.

Surface Tracking

Channel matching is the maximum amount the propagation

delay differs between channels within a single ADuM130D/

ADuM130E/ADuM131D/ADuM131E component.

Surface tracking is addressed in electrical safety standards by

setting a minimum surface creepage based on the working voltage,

the environmental conditions, and the properties of the insulation

material. Safety agencies perform characterization testing on the

surface insulation of components that allows the components to be

categorized in different material groups. Lower material group

ratings are more resistant to surface tracking and, therefore, can

provide adequate lifetime with smaller creepage. The minimum

creepage for a given working voltage and material group is in each

system level standard and is based on the total rms voltage across

the isolation, pollution degree, and material group. The material

group and creepage for the ADuM130D/ADuM130E/

Propagation delay skew is the maximum amount the propagation

delay differs between multiple ADuM130D/ADuM130E/

ADuM131D/ADuM131E components operating under the

same conditions.

JITTER MEASUREMENT

Figure 21 shows the eye diagram for the ADuM130D/ADuM130E/

ADuM131D/ADuM131E. The measurement was taken using an

Agilent 81110A pulse pattern generator at 150 Mbps with pseudo-

random bit sequences (PRBS), 2(n − 1), n = 14, for 5 V supplies.

Jitter was measured with the Tektronix Model 5104B oscilloscope,

at 1 GHz, 10 GSPS with the DPOJET jitter and eye diagram

analysis tools. The result shows a typical measurement on the

ADuM130D/ADuM130E/ADuM131D/ADuM131E with

630 ps p-p jitter.

ADuM131D/ADuM131E isolators are presented in Table 9.

Insulation Wear Out

The lifetime of insulation caused by wear out is determined by

its thickness, material properties, and the voltage stress applied.

It is important to verify that the product lifetime is adequate at

the application working voltage. The working voltage supported

by an isolator for wear out may not be the same as the working

voltage supported for tracking. It is the working voltage applicable

to tracking that is specified in most standards.

5

4

3

2

1

0

Testing and modeling have shown that the primary driver of

long-term degradation is displacement current in the polyimide

insulation causing incremental damage. The stress on the insula-

tion can be broken down into broad categories, such as dc stress,

which causes very little wear out because there is no displacement

current, and an ac component time varying voltage stress, which

causes wear out.

–10

–5

0

5

10

TIME (ns)

Figure 21. Eye Diagram

Rev. A | Page 19 of 22

ADuM130D/ADuM130E/ADuM131D/ADuM131E

Data Sheet

The ratings in certification documents are usually based on

60 Hz sinusoidal stress because this reflects isolation from line

voltage. However, many practical applications have combinations

of 60 Hz ac and dc across the barrier as shown in Equation 1.

Because only the ac portion of the stress causes wear out, the

equation can be rearranged to solve for the ac rms voltage, as

shown in Equation 2. For insulation wear out with the polyimide

materials used in these products, the ac rms voltage determines

the product lifetime.

The working voltage across the barrier from Equation 1 is

2

V_RMS= V_{AC RMS}²+V_DC

V_RMS= 240²+ 400²

V_RMS= 466 V

This V_RMSvalue is the working voltage used together with the

material group and pollution degree when looking up the

creepage required by a system standard.

2

V_RMS= V_{AC RMS}²+V_DC

(1)

To determine if the lifetime is adequate, obtain the time varying

portion of the working voltage. To obtain the ac rms voltage,

use Equation 2.

or

2

V_{AC RMS}= V_RMS²−V_DC

(2)

2

V_{AC RMS}= V_RMS²−V_DC

where:

V_{AC RMS}

_{AC RMS}= 240 V rms

=

466²− 400²

V

_{AC RMS}is the time varying portion of the working voltage.

_RMSis the total rms working voltage.

_DCis the dc offset of the working voltage.

V

In this case, the ac rms voltage is simply the line voltage of

240 V rms. This calculation is more relevant when the waveform is

not sinusoidal. The value is compared to the limits for working

voltage in Table 19 for the expected lifetime, less than a 60 Hz

sine wave, and it is well within the limit for a 50-year service life.

Calculation and Use of Parameters Example

The following example frequently arises in power conversion

applications. Assume that the line voltage on one side of the

isolation is 240 V ac rms and a 400 V dc bus voltage is present

on the other side of the isolation barrier. The isolator material is

polyimide. To establish the critical voltages in determining the

creepage, clearance, and lifetime of a device, see Figure 22 and

the following equations.

Note that the dc working voltage limit in Table 19 is set by the

creepage of the package as specified in IEC 60664-1. This value

can differ for specific system level standards.

V

AC RMS

V

DC

PEAK

RMS

TIME

Figure 22. Critical Voltage Example

Rev. A | Page 20 of 22

Data Sheet

ADuM130D/ADuM130E/ADuM131D/ADuM131E

OUTLINE DIMENSIONS

10.00 (0.3937)

9.80 (0.3858)

9

8

16

1

6.20 (0.2441)

5.80 (0.2283)

4.00 (0.1575)

3.80 (0.1496)

1.27 (0.0500)

BSC

0.50 (0.0197)

45°

0.25 (0.0098)

1.75 (0.0689)

0.25 (0.0098)

0.10 (0.0039)

8°

0°

1.35 (0.0531)

COPLANARITY

0.10

SEATING

PLANE

1.27 (0.0500)

0.40 (0.0157)

0.51 (0.0201)

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

COMPLIANT TO JEDEC STANDARDS MS-012-AC

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 23. 16-Lead Standard Small Outline Package [SOIC_N]

Narrow Body (R-16)

Dimensions shown in millimeters and (inches)

10.50 (0.4134)

10.10 (0.3976)

16

1

9

8

7.60 (0.2992)

7.40 (0.2913)

10.65 (0.4193)

10.00 (0.3937)

0.75 (0.0295)

0.25 (0.0098)

1.27 (0.0500)

BSC

45°

2.65 (0.1043)

2.35 (0.0925)

0.30 (0.0118)

0.10 (0.0039)

8°

0°

COPLANARITY

0.10

SEATING

PLANE

0.51 (0.0201)

0.31 (0.0122)

1.27 (0.0500)

0.40 (0.0157)

0.33 (0.0130)

0.20 (0.0079)

COMPLIANT TO JEDEC STANDARDS MS-013-AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 24. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body

(RW-16)

Dimensions shown in millimeters and (inches)

Rev. A | Page 21 of 22

ADuM130D/ADuM130E/ADuM131D/ADuM131E

Data Sheet

ORDERING GUIDE

No. of

Withstand

Inputs, Inputs, Voltage

Fail-Safe

Output

State

Temperature

Range

V_DD1

Side

V_DD2

Side

Rating

(kV rms)

Input

Disable Enable Description

16-Lead SOIC_N R-16

Output Package

Package

Option

Model¹

ADuM130D1BRZ

−40°C to +125°C

3

2

0

1

3.0

High

Low

High

Low

High

Low

High

Low

High

Low

High

Low

High

Low

High

Low

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

ADuM130D1BRZ-RL7 −40°C to +125°C

ADuM130D0BRZ −40°C to +125°C

ADuM130D0BRZ-RL7 −40°C to +125°C

ADuM130E1BRZ −40°C to +125°C

ADuM130E1BRZ-RL7 −40°C to +125°C

ADuM130E0BRZ −40°C to +125°C

ADuM130E0BRZ-RL7 −40°C to +125°C

ADuM130D1BRWZ −40°C to +125°C

ADuM130D1BRWZ-RL −40°C to +125°C

ADuM130D0BRWZ −40°C to +125°C

ADuM130D0BRWZ-RL −40°C to +125°C

ADuM130E1BRWZ −40°C to +125°C

ADuM130E1BRWZ-RL −40°C to +125°C

ADuM130E0BRWZ −40°C to +125°C

ADuM130E0BRWZ-RL −40°C to +125°C

ADuM131D1BRZ −40°C to +125°C

ADuM131D1BRZ-RL7 −40°C to +125°C

ADuM131D0BRZ −40°C to +125°C

ADuM131D0BRZ-RL7 −40°C to +125°C

ADuM131E1BRZ −40°C to +125°C

ADuM131E1BRZ-RL7 −40°C to +125°C

ADuM131E0BRZ −40°C to +125°C

ADuM131E0BRZ-RL7 −40°C to +125°C

ADuM131D1BRWZ −40°C to +125°C

ADuM131D1BRWZ-RL −40°C to +125°C

ADuM131D0BRWZ −40°C to +125°C

ADuM131D0BRWZ-RL −40°C to +125°C

ADuM131E1BRWZ −40°C to +125°C

ADuM131E1BRWZ-RL −40°C to +125°C

ADuM131E0BRWZ −40°C to +125°C

3.0

3.75

3.0

16-Lead SOIC_N R-16

16-Lead SOIC_W RW-16

16-Lead SOIC_N R-16

16-Lead SOIC_W RW-16

3.0

3.75

ADuM131E0BRWZ-RL −40°C to +125°C

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D13348-0-11/15(A)

Rev. A | Page 22 of 22


型号：	ADuM131E0BRWZ
厂家：	ADI
描述：	3.0 kV RMS/3.75 kV RMS Triple-Channel Digital Isolators
文件：	总22页 (文件大小：649K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADuM131E0BRWZ [ADI]

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ADuM131E1BRZ

ADuM131E1BRZ-RL7

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