EVAL-ADF7021-NDBZ51_技术文档

High Performance

Narrow-Band Transceiver IC

ADF7021-N

On-chip VCO and fractional-N PLL

FEATURES

On-chip, 7-bit ADC and temperature sensor

Fully automatic frequency control loop (AFC)

Digital received signal strength indication (RSSI)

Integrated Tx/Rx switch

Low power, narrow-band transceiver

Frequency bands using dual VCO

80 MHz to 650 MHz

842 MHz to 916 MHz

Programmable IF filter bandwidths of

9 kHz, 13.5 kHz, and 18.5 kHz

Modulation schemes: 2FSK, 3FSK, 4FSK, MSK

Spectral shaping: Gaussian and raised cosine filtering

Data rates supported: 0.05 kbps to 24 kbps

2.3 V to 3.6 V power supply

0.1 μA leakage current in power-down mode

APPLICATIONS

Narrow-band, short range device (SRD) standards

ARIB STD-T67, ETSI EN 300 220, Korean SRD standard,

FCC Part 15, FCC Part 90, FCC Part 95

Low cost, wireless data transfer

Remote control/security systems

Wireless metering

Wireless medical telemetry service (WMTS)

Home automation

Process and building control

Programmable output power

−16 dBm to +13 dBm in 63 steps

Automatic power amplifier (PA) ramp control

Receiver sensitivity

−130 dBm at 100 bps, 2FSK

−122 dBm at 1 kbps, 2FSK

Pagers

Patent pending, on-chip image rejection calibration

FUNCTIONAL BLOCK DIAGRAM

CE

RSET

MUXOUT

CREG(1:4)

TEMP

SENSOR

MUX

7-BIT ADC

R

LDO(1:4)

TEST MUX

LNA

2FSK

3FSK

4FSK

LNA

TxRxCLK

CLOCK

AND DATA

RECOVERY

R

FIN

RSSI/

LOG AMP

TxRxDATA

Tx/Rx

CONTROL

IF FILTER

R

FINB

DEMODULATOR

SWD

GAIN

AGC

CONTROL

SLE

SERIAL

PORT

SDATA

SREAD

SCLK

AFC

CONTROL

PA RAMP

2FSK

3FSK

4FSK

GAUSSIAN/

RAISED COSINE

FILTER

Σ-Δ

MODULATOR

÷1/÷2

DIV P

N/N + 1

RFOUT

MOD CONTROL

÷2

VCO1

3FSK

ENCODING

MUX

CP

PFD

VCO2

CLK

DIV

DIV R

OSC

L1 L2

VCOIN CPOUT

OSC1 OSC2

CLKOUT

Figure 1.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADF7021-N

TABLE OF CONTENTS

Features .............................................................................................. 1

Demodulation, Detection, and CDR....................................... 32

Receiver Setup............................................................................. 34

Demodulator Considerations................................................... 36

AFC Operation ........................................................................... 36

Automatic Sync Word Detection (SWD)................................ 37

Applications Information.............................................................. 38

IF Filter Bandwidth Calibration............................................... 38

LNA/PA Matching...................................................................... 39

Image Rejection Calibration..................................................... 40

Packet Structure and Coding.................................................... 42

Programming After Initial Power-Up ..................................... 42

Applications Circuit................................................................... 45

Serial Interface ................................................................................ 46

Readback Format........................................................................ 46

Interfacing to a Microcontroller/DSP ..................................... 48

Register 0—N Register............................................................... 49

Register 1—VCO/Oscillator Register...................................... 50

Register 2—Transmit Modulation Register ............................ 51

Register 3—Transmit/Receive Clock Register........................ 52

Register 4—Demodulator Setup Register ............................... 53

Register 5—IF Filter Setup Register......................................... 54

Register 6—IF Fine Cal Setup Register ................................... 55

Register 7—Readback Setup Register...................................... 56

Register 8—Power-Down Test Register .................................. 57

Register 9—AGC Register......................................................... 58

Register 10—AFC Register ....................................................... 59

Register 11—Sync Word Detect Register................................ 60

Register 12—SWD/Threshold Setup Register........................ 60

Register 13—3FSK/4FSK Demod Register ............................. 61

Register 14—Test DAC Register............................................... 62

Register 15—Test Mode Register ............................................. 63

Outline Dimensions....................................................................... 64

Ordering Guide .......................................................................... 64

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description......................................................................... 3

Specifications..................................................................................... 4

RF and PLL Specifications........................................................... 4

Transmission Specifications........................................................ 5

Receiver Specifications ................................................................ 6

Digital Specifications ................................................................... 9

General Specifications ............................................................... 10

Timing Characteristics .............................................................. 11

Timing Diagrams........................................................................ 12

Absolute Maximum Ratings.......................................................... 15

ESD Caution................................................................................ 15

Pin Configuration and Function Descriptions........................... 16

Typical Performance Characteristics ........................................... 18

Frequency Synthesizer ................................................................... 22

Reference Input........................................................................... 22

MUXOUT.................................................................................... 23

Voltage Controlled Oscillator (VCO)...................................... 24

Choosing Channels for Best System Performance................. 25

Transmitter ...................................................................................... 26

RF Output Stage.......................................................................... 26

Modulation Schemes.................................................................. 26

Spectral Shaping ......................................................................... 28

Modulation and Filtering Options........................................... 29

Transmit Latency........................................................................ 29

Test Pattern Generator............................................................... 29

Receiver Section.............................................................................. 30

RF Front End............................................................................... 30

IF Filter......................................................................................... 30

RSSI/AGC.................................................................................... 30

REVISION HISTORY

2/08—Revision 0: Initial Version

Rev. 0 | Page 2 of 64

ADF7021-N

GENERAL DESCRIPTION

The ADF7021-N is a high performance, low power, narrow-

band transceiver based on the ADF7021. The ADF7021-N has

IF filter bandwidths of 9 kHz, 13.5 kHz, and 18.5 kHz, making

it ideally suited to worldwide narrowband standards and

particularly those that stipulate 12.5 kHz channel separation.

The frequency-agile PLL allows the ADF7021-N to be used in

frequency-hopping, spread spectrum (FHSS) systems. Both

VCOs operate at twice the fundamental frequency to reduce

spurious emissions and frequency pulling problems.

The transmitter output power is programmable in 63 steps from

−16 dBm to +13 dBm and has an automatic power ramp control

to prevent spectral splatter and help meet regulatory standards.

The transceiver RF frequency, channel spacing, and modulation

are programmable using a simple 3-wire interface. The device

operates with a power supply range of 2.3 V to 3.6 V and can be

powered down when not in use.

It is designed to operate in the narrow-band, license-free ISM

bands and in the licensed bands with frequency ranges of 80

MHz to 650 MHz and 842 MHz to 916 MHz. The part has both

Gaussian and raised cosine transmit data filtering options to

improve spectral efficiency for narrow-band applications. It is

suitable for circuit applications targeted at the Japanese ARIB

STD-T67, the European ETSI EN 300 220, the Korean short

range device regulations, the Chinese short range device

regulations, and the North American FCC Part 15, Part 90, and

Part 95 regulatory standards. A complete transceiver can be

built using a small number of external discrete components,

making the ADF7021-N very suitable for price-sensitive and

area-sensitive applications.

A low IF architecture is used in the receiver (100 kHz), which

minimizes power consumption and the external component

count yet avoids dc offset and flicker noise at low frequencies.

The IF filter has programmable bandwidths of 9 kHz, 13.5 kHz,

and 18.5 kHz. The ADF7021-N supports a wide variety of pro-

grammable features including Rx linearity, sensitivity, and IF

bandwidth, allowing the user to trade off receiver sensitivity

and selectivity against current consumption, depending on the

application. The receiver also features a patent-pending automatic

frequency control (AFC) loop with programmable pull-in range

that allows the PLL to track out the frequency error in the

incoming signal.

The range of on-chip FSK modulation and data filtering options

allows users greater flexibility in their choice of modulation

schemes while meeting the tight spectral efficiency requirements.

The ADF7021-N also supports protocols that dynamically

switch among 2FSK, 3FSK, and 4FSK to maximize communica-

tion range and data throughput.

The receiver achieves an image rejection performance of 56 dB

using a patent-pending IR calibration scheme that does not

require the use of an external RF source.

The transmit section contains two voltage controlled oscillators

(VCOs) and a low noise fractional-N PLL with an output

resolution of <1 ppm. The ADF7021-N has a VCO using an

internal LC tank (421 MHz to 458 MHz, 842 MHz to 916 MHz)

and a VCO using an external inductor as part of its tank circuit

(80 MHz to 650 MHz). The dual VCO design allows dual-band

operation where the user can transmit and/or receive at any

frequency supported by the internal inductor VCO and can also

transmit and/or receive at a particular frequency band

supported by the external inductor VCO.

An on-chip ADC provides readback of the integrated tempera-

ture sensor, external analog input, battery voltage, and RSSI

signal, which provides savings on an ADC in some applications.

The temperature sensor is accurate to 10ꢀC over the full oper-

ating temperature range of −40ꢀC to +85ꢀC. This accuracy can

be improved by performing a 1-point calibration at room

temperature and storing the result in memory.

Rev. 0 | Page 3 of 64

ADF7021-N

SPECIFICATIONS

V_DD= 2.3 V to 3.6 V, GND = 0 V, T_A= T_MINto T_MAX, unless otherwise noted. Typical specifications are at V_DD= 3 V, T_A= 25ꢀC.

All measurements are performed with the EVAL-ADF7021-NDBxx using the PN9 data sequence, unless otherwise noted.

RF AND PLL SPECIFICATIONS

Table 1.

Parameter

Min

Typ

Max Unit

Test Conditions/Comments

RF CHARACTERISTICS

See Table 9 for required VCO_BIAS and

VCO_ADJUST settings

Frequency Ranges (Direct Output)

160

842

80

650

916

325

458

24

MHz

External inductor VCO

Internal inductor VCO

External inductor VCO, RF divide-by-2 enabled

Internal inductor VCO, RF divide-by-2 enabled

Frequency Ranges (RF Divide-by-2 Mode)

421

Phase Frequency Detector (PFD) Frequency¹RF/256

PHASE-LOCKED LOOP (PLL)

VCO Gain²

868 MHz, Internal Inductor VCO

426 MHz, Internal Inductor VCO

426 MHz, External Inductor VCO

160 MHz, External Inductor VCO

Phase Noise (In-Band)

67

45

27

6

MHz/V VCO_ADJUST = 0, VCO_BIAS = 8

MHz/V VCO_ADJUST = 0, VCO_BIAS = 3

MHz/V VCO_ADJUST = 0, VCO_BIAS = 2

868 MHz, Internal Inductor VCO

−97

dBc/Hz 10 kHz offset, PA = 10 dBm, V_DD= 3.0 V,

PFD = 19.68 MHz, VCO_BIAS = 8

433 MHz, Internal Inductor VCO

426 MHz, External Inductor VCO

Phase Noise (Out-of-Band)

−103

−95

dBc/Hz 10 kHz offset, PA = 10 dBm, V_DD= 3.0 V,

PFD = 19.68 MHz, VCO_BIAS = 8

dBc/Hz 10 kHz offset, PA = 10 dBm, V_DD= 3.0 V,

PFD = 9.84 MHz, VCO_BIAS = 3

dBc/Hz 1 MHz offset, f_RF= 433 MHz, PA = 10 dBm,

V_DD= 3.0 V, PFD = 19.68 MHz, VCO_BIAS = 8

−124

Normalized In-Band Phase Noise Floor³

PLL Settling

−203

40

dBc/Hz

μs

Measured for a 10 MHz frequency step to within

5 ppm accuracy, PFD = 19.68 MHz, loop bandwidth

(LBW) = 100 kHz

REFERENCE INPUT

Crystal Reference⁴

External Oscillator^{4, 5}

Crystal Start-Up Time⁶

XTAL Bias = 20 μA

XTAL Bias = 35 μA

Input Level for External Oscillator⁷

OSC1

3.625

24

MHz

0.930

0.438

ms

10 MHz XTAL, 33 pF load capacitors, V_DD= 3.0 V

0.8

CMOS levels

V p-p

V

Clipped sine wave

OSC2

ADC PARAMETERS

INL

DNL

0.4

LSB

V_DD= 2.3 V to 3.6 V, T_A= 25°C

¹The maximum usable PFD at a particular RF frequency is limited by the minimum N divide value.

²VCO gain measured at a VCO tuning voltage of 0.7 V. The VCO gain varies across the tuning range of the VCO. The software package ADIsimPLL™ can be used to model this

variation.

³This value can be used to calculate the in-band phase noise for any operating frequency. Use the following equation to calculate the in-band phase noise performance

as seen at the power amplifier (PA) output: −203 + 10 log(f_PFD) + 20 logN.

⁴Guaranteed by design. Sample tested to ensure compliance.

⁵A TCXO, VCXO, or OCXO can be used as an external oscillator.

⁶Crystal start-up time is the time from chip enable (CE) being asserted to correct clock frequency on the CLKOUT pin.

⁷Refer to the Reference Input section for details on using an external oscillator.

Rev. 0 | Page 4 of 64

ADF7021-N

TRANSMISSION SPECIFICATIONS

Table 2.

Parameter

Min

Typ

Max

Unit Test Conditions/Comments

DATA RATE

2FSK, 3FSK

4FSK

0.05

18.5¹kbps IF_FILTER_BW = 18.5 kHz

24 kbps IF_FILTER_BW = 18.5 kHz

MODULATION

Frequency Deviation (f_DEV

2

)

0.056

0.306

56

28.26 kHz

PFD = 3.625 MHz

PFD = 20 MHz

PFD = 3.625 MHz

156

kHz

Hz

Deviation Frequency Resolution

Gaussian Filter BT

0.5

Raised Cosine Filter Alpha

0.5/0.7

Programmable

TRANSMIT POWER

Maximum Transmit Power³

Transmit Power Variation vs.

Temperature

+13

1

dBm V_DD= 3.0 V, T_A= 25°C

dB

−40°C to +85°C

Transmit Power Variation vs. V_DD

Transmit Power Flatness

Programmable Step Size

1

dB

2.3 V to 3.6 V at 915 MHz, T_A= 25°C

902 MHz to 928 MHz, 3 V, T_A= 25°C

−16 dBm to +13 dBm

0.3125

ADJACENT CHANNEL POWER (ACP)

426 MHz, External Inductor VCO

12.5 kHz Channel Spacing

PFD = 9.84 MHz

−50

dBc

Gaussian 2FSK modulation, measured in a 4.25 kHz bandwidth

at 12.5 kHz offset, 2.4 kbps PN9 data, 1.2 kHz frequency deviation,

compliant with ARIB STD-T67

Gaussian 2FSK modulation, measured in a 8 kHz bandwidth at

25 kHz offset, 9.6 kbps PN9 data, 2.4 kHz frequency deviation,

compliant with ARIB STD-T67

25 kHz Channel Spacing

868 MHz, Internal Inductor VCO

12.5 kHz Channel Spacing

PFD = 19.68 MHz

−46

−43

dBm Gaussian 2FSK modulation, 10 dBm output power, measured in

a 6.25 kHz bandwidth at 12.5 kHz offset, 2.4 kbps PN9 data,

1.2 kHz frequency deviation, compliant with ETSI EN 300 220

dBm Gaussian 2FSK modulation, 10 dBm output power, measured in

a 12.5 kHz bandwidth at 25 kHz offset, 9.6 kbps PN9 data,

2.4 kHz frequency deviation, compliant with ETSI EN 300 220

25 kHz Channel Spacing

433 MHz, Internal Inductor VCO

12.5 kHz Channel Spacing

PFD = 19.68 MHz

−50

−47

dBm Gaussian 2FSK modulation, 10 dBm output power, measured in

a 6.25 kHz bandwidth at 12.5 kHz offset, 2.4 kbps PN9 data,

1.2 kHz frequency deviation, compliant with ETSI EN 300 220

dBm Gaussian 2FSK modulation, 10 dBm output power, measured in

a 12.5 kHz bandwidth at 25 kHz offset, 9.6 kbps PN9 data,

2.4 kHz frequency deviation, compliant with ETSI EN 300 220

25 kHz Channel Spacing

OCCUPIED BANDWIDTH

99.0% of total mean power; 12.5 kHz channel spacing (2.4 kbps

PN9 data, 1.2 kHz frequency deviation); 25 kHz channel spacing

(9.6 kbps PN9 data, 2.4 kHz frequency deviation)

2FSK Gaussian Data Filtering

12.5 kHz Channel Spacing

25 kHz Channel Spacing

2FSK Raised Cosine Data Filtering

12.5 kHz Channel Spacing

25 kHz Channel Spacing

3FSK Raised Cosine Filtering

12.5 kHz Channel Spacing

25 kHz Channel Spacing

4FSK Raised Cosine Filtering

25 kHz Channel Spacing

3.9

9.9

kHz

4.4

10.2

kHz

3.9

9.5

kHz

19.2 kbps PN9 data, 1.2 kHz frequency deviation

kHz

13.2

Rev. 0 | Page 5 of 64

ADF7021-N

Parameter

Min

Typ

Max

Unit Test Conditions/Comments

SPURIOUS EMISSIONS

Reference Spurs

HARMONICS⁴

−65

dBc

100 kHz loop bandwidth

13 dBm output power, unfiltered conductive/filtered conductive

Second Harmonic

Third Harmonic

All Other Harmonics

OPTIMUM PA LOAD IMPEDANCE⁵

f_RF= 915 MHz

f_RF= 868 MHz

f_RF= 450 MHz

f_RF= 426 MHz

f_RF= 315 MHz

−35/−52

−43/−60

−36/−65

dBc

39 + j61

48 + j54

98 + j65

100 + j65

129 + j63

173 + j49

Ω

f_RF= 175 MHz

¹Using Gaussian or raised cosine filtering. The frequency deviation should be chosen to ensure that the transmit-occupied signal bandwidth is within the receiver

IF filter bandwidth.

²For the definition of frequency deviation, refer to the Register 2—Transmit Modulation Register section.

³Measured as maximum unmodulated power.

⁴Conductive filtered harmonic emissions measured on the EVAL-ADF7021-NDBxx, which includes a T-stage harmonic filter (two inductors and one capacitor).

⁵For matching details, refer to the LNA/PA Matching section.

RECEIVER SPECIFICATIONS

Table 3.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Bit error rate (BER) = 10⁻³, low noise amplifier (LNA)

and power amplifier (PA) matched separately

SENSITIVITY

2FSK

Sensitivity at 0.1 kbps

−130

−127

−122

−115

dBm

f_DEV= 1 kHz, high sensitivity mode, IF_FILTER_BW =

13.5 kHz

f_DEV= 1 kHz, high sensitivity mode, IF_FILTER_BW =

13.5 kHz

f_DEV= 1 kHz, high sensitivity mode, IF_FILTER_BW =

13.5 kHz

f_DEV= 4 kHz, high sensitivity mode, IF_FILTER_BW =

18.5 kHz

Sensitivity at 0.25 kbps

Sensitivity at 1 kbps

Sensitivity at 9.6 kbps

Gaussian 2FSK

Sensitivity at 0.1 kbps

−129

−127

−121

−114

dBm

f_DEV= 1 kHz, high sensitivity mode, IF_FILTER_BW =

13.5 kHz

f_DEV= 1 kHz, high sensitivity mode, IF_FILTER_BW =

13.5 kHz

f_DEV= 1 kHz, high sensitivity mode, IF_FILTER_BW =

13.5 kHz

f_DEV= 4 kHz, high sensitivity mode, IF_FILTER_BW =

18.5 kHz

Sensitivity at 0.25 kbps

Sensitivity at 1 kbps

Sensitivity at 9.6 kbps

GMSK

Sensitivity at 9.6 kbps

−113

dBm

f_DEV= 2.4 kHz, high sensitivity mode, IF_FILTER_BW =

18.5 kHz

Raised Cosine 2FSK

Sensitivity at 0.25 kbps

−127

−121

−114

dBm

f_DEV= 1 kHz, high sensitivity mode, IF_FILTER_BW =

13.5 kHz

f_DEV= 1 kHz, high sensitivity mode, IF_FILTER_BW =

13.5 kHz

f_DEV= 4 kHz, high sensitivity mode, IF_FILTER_BW =

18.5 kHz

Sensitivity at 1 kbps

Sensitivity at 9.6 kbps

Rev. 0 | Page 6 of 64

ADF7021-N

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

3FSK

Sensitivity at 9.6 kbps

−110

dBm

f_DEV= 2.4 kHz, high sensitivity mode, IF_FILTER_BW =

18.5 kHz, Viterbi detection on

Raised Cosine 3FSK

Sensitivity at 9.6 kbps

−110

−112

−109

dBm

f_DEV= 2.4 kHz, high sensitivity mode, IF_FILTER_BW =

13.5 kHz, alpha = 0.5, Viterbi detection on

4FSK

Sensitivity at 9.6 kbps

f_DEV(inner) = 1.2 kHz, high sensitivity mode,

IF_FILTER_BW = 13.5 kHz

Raised Cosine 4FSK

Sensitivity at 9.6 kbps

f_DEV(inner) = 1.2 kHz, high sensitivity mode,

IF_FILTER_BW = 13.5 kHz, alpha = 0.5

INPUT IP3

Two-tone test, f_LO= 860 MHz, F1 = f_LO+ 100 kHz,

F2 = f_LO− 800 kHz

Low Gain Enhanced Linearity

Mode

−3

dBm

LNA_GAIN = 3, MIXER_LINEARITY = 1

Medium Gain Mode

High Sensitivity Mode

ADJACENT CHANNEL REJECTION

868 MHz

−13.5

−24

dBm

LNA_GAIN = 10, MIXER_LINEARITY = 0

LNA_GAIN = 30, MIXER_LINEARITY = 0

Wanted signal is 3 dB above the sensitivity point

(BER = 10⁻³); unmodulated interferer is at the center

of the adjacent channel; rejection measured as the

difference between the interferer level and the

wanted signal level in dB

12.5 kHz Channel Spacing

25 kHz Channel Spacing

426 MHz

40

39

dB

9 kHz IF_FILTER_BW

18.5 kHz IF_FILTER_BW

Wanted signal is 3 dB above the reference sensitivity

point (BER = 10⁻²); modulated interferer (same

modulation as wanted signal) at the center of the

adjacent channel; rejection measured as the

difference between the interferer level and reference

sensitivity level in dB

12.5 kHz Channel Spacing

25 kHz Channel Spacing

40

39

dB

9 kHz IF_FILTER_BW, compliant with ARIB STD-T67

18.5 kHz IF_FILTER_BW, compliant with ARIB STD-T67

CO-CHANNEL REJECTION

Wanted signal (2FSK, 9.6 kbps, 4 kHz deviation) is

3 dB above the sensitivity point (BER = 10⁻³), modu-

lated interferer

868 MHz

−5

dB

IMAGE CHANNEL REJECTION

Wanted signal (2FSK, 9.6 kbps, 4 kHz deviation) is

10 dB above the sensitivity point (BER = 10⁻³); modu-

lated interferer (2FSK, 9.6 kbps, 4 kHz deviation) is

placed at the image frequency of f_RF− 200 kHz; the

interferer level is increased until BER = 10⁻³

868 MHz

450 MHz, Internal Inductor

VCO

26/39

29/50

dB

Uncalibrated/calibrated¹, V_DD= 3.0 V, T_A= 25°C

BLOCKING

Wanted signal is 10 dB above the input sensitivity

level; CW interferer level is increased until BER = 10⁻³

1 MHz

2 MHz

5 MHz

10 MHz

69

75

78

78.5

12

dB

SATURATION

dBm

2FSK mode, BER = 10⁻³

(MAXIMUM INPUT LEVEL)

Rev. 0 | Page 7 of 64

ADF7021-N

Parameter

RSSI

Min

Typ

Max

Unit

Test Conditions/Comments

Range at Input²

−120 to −47

2

3

dBm

dB

Linearity

Input power range = −100 dBm to −47 dBm

See the RSSI/AGC section

Absolute Accuracy

Response Time

AFC

390

μs

Pull-In Range

0.5

1.5 × IF_

FILTER_BW

kHz

The range is programmable in Register 10

(R10_DB[24:31])

Response Time

Accuracy

64

0.5

Bits

kHz

Input power range = −100 dBm to +12 dBm

Rx SPURIOUS EMISSIONS³

Internal Inductor VCO

−91/−91

−52/−70

−62/−72

−64/−85

dBm

<1 GHz at antenna input, unfiltered conductive/filtered

conductive

>1 GHz at antenna input, unfiltered conductive/filtered

conductive

<1 GHz at antenna input, unfiltered conductive/filtered

conductive

>1 GHz at antenna input, unfiltered conductive/filtered

conductive

External Inductor VCO

LNA INPUT IMPEDANCE

f_RF= 915 MHz

f_RF= 868 MHz

f_RF= 450 MHz

f_RF= 426 MHz

RFIN to RFGND

24 − j60

26 − j63

63 − j129

68 − j134

96 − j160

178 − j190

Ω

f_RF= 315 MHz

f_RF= 175 MHz

¹Calibration of the image rejection used an external RF source.

²For received signal levels < −100 dBm, it is recommended to average the RSSI readback value over a number of samples to improve the RSSI accuracy at low input powers.

³Filtered conductive receive spurious emissions are measured on the EVAL-ADF7021-NDBxx, which includes a T-stage harmonic filter (two inductors and one

capacitor).

Rev. 0 | Page 8 of 64

ADF7021-N

DIGITAL SPECIFICATIONS

Table 4.

Parameter

Min

Typ

Max

Unit Test Conditions/Comments

TIMING INFORMATION

Chip Enabled to Regulator Ready

Chip Enabled to Tx Mode

TCXO Reference

10

μs

CREG (1:4) = 100 nF

32-bit register write time = 50 μs

1

2

ms

XTAL

Chip Enabled to Rx Mode

32-bit register write time = 50 μs, IF filter coarse

calibration only

TCXO Reference

XTAL

1.2

2.2

ms

Tx-to-Rx Turnaround Time

390 μs + (5 × t_BIT)

Time to synchronized data out, includes AGC

settling (three AGC levels)and CDR synchronization;

see the AGC Information and Timing section for

more details; t_BIT= data bit period

LOGIC INPUTS

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_INH/I_INL

Input Capacitance, C_IN

Control Clock Input

LOGIC OUTPUTS

0.7 × V_DD

V

μA

pF

MHz

0.2 × V_DD

1

10

50

Output High Voltage, V_OH

Output Low Voltage, V_OL

CLKOUT Rise/Fall

DV_DD− 0.4

V

ns

pF

I_OH= 500 μA

I_OL= 500 μA

0.4

5

10

CLKOUT Load

Rev. 0 | Page 9 of 64

ADF7021-N

GENERAL SPECIFICATIONS

Table 5.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

TEMPERATURE RANGE (T_A)

POWER SUPPLIES

Voltage Supply, V_DD

TRANSMIT CURRENT CONSUMPTION¹

868 MHz

−40

+85

°C

2.3

3.6

V

All VDD pins must be tied together

V_DD= 3.0 V, PA is matched into 50 Ω

VCO_BIAS = 8

0 dBm

5 dBm

10 dBm

20.2

24.7

32.3

mA

450 MHz, Internal Inductor VCO

0 dBm

5 dBm

VCO_BIAS = 8

VCO_BIAS = 2

19.9

23.2

29.2

mA

10 dBm

426 MHz, External Inductor VCO

0 dBm

5 dBm

13.5

17

23.3

mA

10 dBm

RECEIVE CURRENT CONSUMPTION

868 MHz

V_DD= 3.0 V

VCO_BIAS = 8

Low Current Mode

High Sensitivity Mode

433MHz, Internal Inductor VCO

Low Current Mode

High Sensitivity Mode

426 MHz, External Inductor VCO

Low Current Mode

High Sensitivity Mode

POWER-DOWN CURRENT CONSUMPTION

Low Power Sleep Mode

22.7

24.6

mA

VCO_BIAS = 8

VCO_BIAS = 2

24.5

26.4

mA

17.5

19.5

mA

0.1

1

μA

CE low

¹The transmit current consumption tests used the same combined PA and LNA matching network as that used on the EVAL-ADF7021-NDBxx evaluation boards.

Improved PA efficiency is achieved by using a separate PA matching network.

Rev. 0 | Page 10 of 64

ADF7021-N

TIMING CHARACTERISTICS

V_DD= 3 V 10%, DGND = AGND = 0 V, T_A= 25ꢀC, unless otherwise noted. Guaranteed by design but not production tested.

Table 6.

Parameter

Limit at T_MINto T_MAX

Unit

ns

μs

Test Conditions/Comments

SDATA to SCLK setup time

SDATA to SCLK hold time

SCLK high duration

SCLK low duration

t₁

t₂

t₃

t₄

t₅

t₆

t₈

t₉

t₁₀

t₁₁

t₁₂

t₁₃

t₁₄

t₁₅

>10

>25

>10

>20

<25

SCLK to SLE setup time

SLE pulse width

SCLK to SREAD data valid, readback

SREAD hold time after SCLK, readback

SCLK to SLE disable time, readback

TxRxCLK negative edge to SLE

TxRxDATA to TxRxCLK setup time (Tx mode)

TxRxCLK to TxRxDATA hold time (Tx mode)

TxRxCLK negative edge to SLE

SLE positive edge to positive edge of TxRxCLK

>10

5 < t₁₁< (¼ × t_BIT)

>5

>¼ × t_BIT

Rev. 0 | Page 11 of 64

ADF7021-N

TIMING DIAGRAMS

Serial Interface

t₃

t₄

SCLK

t₁

t₂

DB1

DB0 (LSB)

(CONTROL BIT C1)

SDATA

SLE

DB31 (MSB)

DB30

DB2

(CONTROL BIT C2)

t₆

t₅

Figure 2. Serial Interface Timing Diagram

t₁

t₂

SCLK

SDATA

SLE

REG7 DB0

(CONTROL BIT C1)

t₃

t₁₀

RV2

RV1

X

RV16

RV15

SREAD

t₉

t₈

Figure 3. Serial Interface Readback Timing Diagram

2FSK/3FSK Timing

±1 × DATA RATE/32

1/DATA RATE

TxRxCLK

TxRxDATA

DATA

Figure 4. TxRxDATA/TxRxCLK Timing Diagram in Receive Mode

1/DATA RATE

TxRxCLK

TxRxDATA

DATA

FETCH

SAMPLE

Figure 5. TxRxDATA/TxRxCLK Timing Diagram in Transmit Mode

Rev. 0 | Page 12 of 64

ADF7021-N

4FSK Timing

In 4FSK receive mode, MSB/LSB synchronization should be guaranteed by SWD in the receive bit stream.

REGISTER 0 WRITE

SWITCH FROM Rx TO Tx

t_SYMBOL

t₁₃

t₁₂

t₁₁

t_BIT

SLE

TxRxCLK

Rx SYMBOL

LSB

Rx SYMBOL

LSB

Tx SYMBOL

MSB

Rx SYMBOL

MSB

Rx SYMBOL

MSB

Tx SYMBOL

LSB

Tx SYMBOL

MSB

TxRxDATA

Tx/Rx MODE

Rx MODE

Tx MODE

Figure 6. Receive-to-Transmit Timing Diagram in 4FSK Mode

REGISTER 0 WRITE

SWITCH FROM Tx TO Rx

t₁₅

t_SYMBOL

t₁₄

t_BIT

SLE

TxRxCLK

Tx SYMBOL

LSB

Tx SYMBOL

LSB

Tx SYMBOL

MSB

Tx SYMBOL

MSB

Rx SYMBOL

MSB

Rx SYMBOL

LSB

TxRxDATA

Tx/Rx MODE

Tx MODE

Rx MODE

Figure 7. Transmit-to-Receive Timing Diagram in 4FSK Mode

Rev. 0 | Page 13 of 64

ADF7021-N

UART/SPI Mode

UART mode is enabled by setting R0_DB28 to 1. SPI mode is enabled by setting R0_DB28 to 1 and setting R15_DB[17:19] to 0x7.

The transmit/receive data clock is available on the CLKOUT pin.

t_BIT

CLKOUT

(TRANSMIT/RECEIVE DATA

CLOCK IN SPI MODE.

NOT USED IN UART MODE.)

FETCH SAMPLE

TxRxCLK

(TRANSMIT DATA INPUT

IN UART/SPI MODE.)

Tx BIT

TxRxDATA

(RECEIVE DATA OUTPUT

IN UART/SPI MODE.)

HIGH-Z

Tx/Rx MODE

Tx MODE

Figure 8. Transmit Timing Diagram in UART/SPI Mode

t_BIT

CLKOUT

(TRANSMIT/RECEIVE DATA

CLOCK IN SPI MODE.

FETCH SAMPLE

NOT USED IN UART MODE.)

TxRxCLK

(TRANSMIT DATA INPUT

IN UART/SPI MODE.)

HIGH-Z

TxRxDATA

(RECEIVE DATA OUTPUT

IN UART/SPI MODE.)

Rx BIT

Tx/Rx MODE

Rx MODE

Figure 9. Receive Timing Diagram in UART/SPI Mode

Rev. 0 | Page 14 of 64

ADF7021-N

ABSOLUTE MAXIMUM RATINGS

T_A= 25ꢀC, unless otherwise noted.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 7.

Parameter

V_DDto GND¹

Rating

−0.3 V to +5 V

Analog I/O Voltage to GND

Digital I/O Voltage to GND

Operating Temperature Range

Industrial (B Version)

Storage Temperature Range

Maximum Junction Temperature

MLF θ_JAThermal Impedance

Reflow Soldering

−0.3 V to AV_DD+ 0.3 V

−0.3 V to DV_DD+ 0.3 V

This device is a high performance RF integrated circuit with an

ESD rating of <2 kV and it is ESD sensitive. Proper precautions

should be taken for handling and assembly.

−40°C to +85°C

−65°C to +125°C

150°C

26°C/W

ESD CAUTION

Peak Temperature

Time at Peak Temperature

260°C

40 sec

¹GND = CPGND = RFGND = DGND = AGND = 0.

Rev. 0 | Page 15 of 64

ADF7021-N

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

1

36

35

34

33

32

31

30

29

28

27

26

25

CLKOUT

TxRxCLK

TxRxDATA

SWD

VCOIN

2

CREG1

3

VDD1

4

RFOUT

5

VDD2

RFGND

ADF7021-N

TOP VIEW

(Not to Scale)

6

7

RFIN

CREG2

ADCIN

GND2

RFINB

8

R

LNA

9

SCLK

VDD4

RSET

10

11

12

SREAD

SDATA

SLE

CREG4

GND4

Figure 10. Pin Configuration

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

VCOIN

The tuning voltage on this pin determines the output frequency of the voltage controlled oscillator (VCO).

The higher the tuning voltage, the higher the output frequency.

2

3

4

CREG1

VDD1

Regulator Voltage for PA Block. Place a series 3.9 Ω resistor and a 100 nF capacitor between this pin and

ground for regulator stability and noise rejection.

Voltage Supply for PA Block. Place decoupling capacitors of 0.1 μF and 100 pF as close as possible to this pin.

Tie all VDD pins together.

The modulated signal is available at this pin. Output power levels are from −16 dBm to +13 dBm. The output

should be impedance matched to the desired load using suitable components (see the Transmitter section).

RFOUT

5

6

RFGND

RFIN

Ground for Output Stage of Transmitter. All GND pins should be tied together.

LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA

input to ensure maximum power transfer (see the LNA/PA Matching section).

7

8

RFINB

R_LNA

Complementary LNA Input. (See the LNA/PA Matching section.)

External Bias Resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance.

9

10

11

VDD4

RSET

CREG4

Voltage Supply for LNA/MIXER Block. This pin should be decoupled to ground with a 10 nF capacitor.

External Resistor. Sets charge pump current and some internal bias currents. Use a 3.6 kΩ resistor with 5% tolerance.

Regulator Voltage for LNA/MIXER Block. Place a 100 nF capacitor between this pin and GND for regulator

stability and noise rejection.

12, 19, 22 GND4

13 to 18

MIX_I, MIX_I,

Ground for LNA/MIXER Block.

Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected.

MIX_Q, MIX_Q,

FILT_I, FILT_I

20, 21, 23 FILT_Q, FILT_Q, Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected.

TEST_A

24

25

26

27

28

CE

Chip Enable. Bringing CE low puts the ADF7021-N into complete power-down. Register values are lost when

CE is low, and the part must be reprogrammed after CE is brought high.

Load Enable, CMOS Input. When SLE goes high, the data stored in the shift registers is loaded into one of the

four latches. A latch is selected using the control bits.

Serial Data Input. The serial data is loaded MSB first with the four LSBs as the control bits. This pin is a high

impedance CMOS input.

Serial Data Output. This pin is used to feed readback data from the ADF7021-N to the microcontroller. The

SCLK input is used to clock each readback bit (for example, AFC or ADC) from the SREAD pin.

SLE

SDATA

SREAD

SCLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into

the 32-bit shift register on the CLK rising edge. This pin is a digital CMOS input.

Rev. 0 | Page 16 of 64

ADF7021-N

Pin No.

29

Mnemonic

GND2

Description

Ground for Digital Section.

30

ADCIN

Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin. Full scale is 0 V to

1.9 V. Readback is made using the SREAD pin.

31

CREG2

Regulator Voltage for Digital Block. Place a 100 nF capacitor between this pin and ground for regulator

stability and noise rejection.

32

33

VDD2

SWD

Voltage Supply for Digital Block. Place a decoupling capacitor of 10 nF as close as possible to this pin.

Sync Word Detect. The ADF7021-N asserts this pin when it has found a match for the sync word sequence

(see the Register 11—Sync Word Detect Register section). This provides an interrupt for an external

microcontroller indicating that valid data is being received.

34

35

TxRxDATA

TxRxCLK

Transmit Data Input/Received Data Output. This is a digital pin, and normal CMOS levels apply. In UART/SPI

mode, this pin provides an output for the received data in receive mode. In transmit UART/SPI mode, this pin

is high impedance (see the Interfacing to a Microcontroller/DSP section).

Outputs the data clock in both receive and transmit modes. This is a digital pin, and normal CMOS levels

apply. The positive clock edge is matched to the center of the received data. In transmit mode, this pin

outputs an accurate clock to latch the data from the microcontroller into the transmit section at the exact

required data rate. In UART/SPI mode, this pin is used to input the transmit data in transmit mode. In receive

UART/SPI mode, this pin is high impedance (see the Interfacing to a Microcontroller/DSP section).

36

37

CLKOUT

A divided-down version of the crystal reference with output driver. The digital clock output can be used to drive

several other CMOS inputs such as a microcontroller clock. The output has a 50:50 mark-space ratio and is inverted

with respect to the reference. Place a series 1 kΩ resistor as close as possible to the pin in applications where the

CLKOUT feature is being used.

Provides the DIGITAL_LOCK_DETECT signal. This signal is used to determine if the PLL is locked to the correct

frequency. It also provides other signals such as REGULATOR_READY, which is an indicator of the status of the

serial interface regulator (see the MUXOUT section for more information).

MUXOUT

38

39

OSC2

OSC1

Connect the reference crystal between this pin and OSC1. A TCXO reference can be used by driving this pin

with CMOS levels and disabling the internal crystal oscillator.

Connect the reference crystal between this pin and OSC2. A TCXO reference can be used by driving this pin

with ac-coupled 0.8 V p-p levels and by enabling the internal crystal oscillator.

40

41

VDD3

CREG3

Voltage Supply for the Charge Pump and PLL Dividers. Decouple this pin to ground with a 10 nF capacitor.

Regulator Voltage for Charge Pump and PLL Dividers. Place a 100 nF capacitor between this pin and ground

for regulator stability and noise rejection.

42

CPOUT

Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The

integrated current changes the control voltage on the input to the VCO.

43

VDD

Voltage Supply for VCO Tank Circuit. Decouple this pin to ground with a 10 nF capacitor.

44, 46

L2, L1

External VCO Inductor Pins. If using an external VCO inductor, connect a chip inductor across these pins to set

the VCO operating frequency. If using the internal VCO inductor, these pins can be left floating. See the

Voltage Controlled Oscillator (VCO) section for more information.

45, 47

48

GND, GND1

CVCO

Grounds for VCO Block.

Place a 22 nF capacitor between this pin and CREG1 to reduce VCO noise.

Rev. 0 | Page 17 of 64

ADF7021-N

TYPICAL PERFORMANCE CHARACTERISTICS

–70

DR = 9.6kbps

RF FREQ = 900MHz

DATA = PRBS9

f_DEV= 2.4kHz

RF FREQ = 869.5MHz

V

= 2.3V

DD

–80

–90

TEMPERATURE = 25°C

VCO_BIAS = 8

VCO_ADJUST = 3

I

= 0.8mA

CP

I

= 1.4mA

CP

2FSK

–100

–110

–120

–130

–140

–150

GFSK

I

= 2.2mA

CP

CENTER 869.5 25MHz

RES BW 300Hz

SPAN 50kHz

1

10

100

1000

10000

VBW 300Hz SWEEP 2.118s (601pts)

FREQUENCY OFFSET (kHz)

Figure 11. Phase Noise Response at 900 MHz, V_DD= 2.3 V

Figure 14. Output Spectrum in 2FSK and GFSK Modes

16

12

DR = 9.6kbps

PA_BIAS = 11µA

PA_BIAS = 9µA

DATA = PRBS9

f_DEV= 2.4kHz

RF FREQ = 869.5MHz

8

4

0

PA_BIAS = 5µA

–4

2FSK

PA_BIAS = 7µA

–8

–12

–16

–20

–24

–28

–32

–36

–40

RC2FSK

CENTER 869.5 25MHz

RES BW 300Hz

SPAN 50kHz

0

4

8

12 16 20 24 28 32 36 40 44 48 52 56 60

PA SETTING

VBW 300Hz SWEEP 2.118s (601pts)

Figure 12. RF Output Power vs. PA Setting

Figure 15. Output Spectrum in 2FSK and Raised Cosine 2FSK Modes

1R

RF FREQ = 440MHz

SR = 4.8ksym/s

DATA = PRBS9

f_DEV= 2.4kHz

OUTPUT POWER = 10dBm

FILTER = T-STAGE LC FILTER

MARKER Δ = 52.2dB

RF FREQ = 869.5MHz

4FSK

1

RC4FSK

START 300MHz

RES BW 100Hz

STOP 3.5GHz

VBW 100Hz SWEEP 385.8ms (601pts)

CENTER 869.493 8MHz

RES BW 300Hz

SPAN 100kHz

VBW 300Hz SWEEP 4.237s (601pts)

Figure 13. PA Output Harmonic Response with T-Stage LC Filter

Figure 16. Output Spectrum in 4FSK and Raised Cosine 4FSK Modes

Rev. 0 | Page 18 of 64

ADF7021-N

REF 15dBm

0

–1

–2

–3

–4

–5

–6

–7

–8

ATTEN 25dB

SAMP LOG 10dB/

DATA RATE = 1kbps

f_DEV= 1kHz

DR = 9.6kbps

DATA = PRS9

f_DEV= 2.4kHz

RF FREQ = 135MHz

IF BW = 12.5kHz

RF FREQ = 869.5MHz

3.0V, +25°C

2.3V, +85°C

VAVG 100

3FSK

V1 V2

S3 FC

3.6V, –40°C

RC3FSK

–130 –128 –126 –124 –122 –120 –118 –116 –114 –112 –110 –108

RF INPUT POWER (dBm)

CENTER 869.5MHz

RES BW 300Hz

VBW 300Hz

SPAN 50kHz

SWEEP2.226s (401pts)

Figure 17. Output Spectrum in 3FSK and Raised Cosine 3FSK Modes

Figure 20. 2FSK Sensitivity vs. V_DDand Temperature, f_RF= 135 MHz

0

RAMP RATE:

CW ONLY

256 CODES/BIT

128 CODES/BIT

64 CODES/BIT

32 CODES/BIT

TRACE = MAX HOLD

3FSK MODULATION

DATA RATE = 9.6kbps

10

0

PA ON/OFF RATE = 3Hz

PA ON/OFF CYCLES = 10,000

f_DEV= 2.4kHz

–1

–2

–3

–4

–5

–6

–7

–8

V

= 3.0V

DD

MOD INDEX = 0.5

RF FREQ = 440 MHz

–10

–20

–30

–40

–50

–60

2.3V +25°C

3.0V +25°C

3.6V +25°C

2.3V –40°C

3.0V –40°C

3.6V –40°C

2.3V +85°C

3.0V +85°C

3.6V +85°C

–120

–115

–110

–105

–100

–95

–100

–50

0

50

100

RF INPUT POWER (dBm)

FREQUENCY OFFSET (kHz)

Figure 18. Output Spectrum in Maximum Hold

for Various PA Ramp Rate Options

Figure 21. 3FSK Sensitivity vs. V_DDand Temperature, f_RF= 440 MHz

0

–1

–2

–3

–4

–5

–6

–7

–8

0

DATA RATE = 9.6kbps

f_DEV= 4kHz

DATA RATE = 19.6kbps

SYMBOL RATE = 9.8ksym/s

f_DEV(inner) = 2.4kHz

–1

RF FREQ = 868MHz

IF BW = 25kHz

MOD INDEX = 0.5

RF FREQ = 420MHz

–2

–3

–4

–5

–6

–7

–8

IF BW = 12.5kHz

3.0V, +25°C

2.3V, +85°C

3.6V, –40°C

2.3V +25°C

3.0V +25°C

3.6V +25°C

2.3V –40°C

3.0V –40°C

3.6V –40°C

2.3V +85°C

3.0V +85°C

3.6V +85°C

–122 –120 –118 –116 –114 –112 –110 –108 –106 –104

–120

–115

–110

–105

–100

–95

RF INPUT POWER (dBm)

Figure 19. 2FSK Sensitivity vs. V_DDand Temperature, f_RF= 868 MHz

Figure 22. 4FSK Sensitivity vs. V_DDand Temperature, f_RF= 420 MHz

Rev. 0 | Page 19 of 64

ADF7021-N

90

80

70

60

50

40

30

20

10

0

2.5

0

+90°C

–2.5

–5.0

–7.5

–10.0

–12.5

–15.0

–17.5

–20.0

–22.5

–25.0

–27.5

–30.0

–32.5

–35.0

–37.5

RF FREQ = 868MHz

WANTED SIGNAL

(10dB ABOVE SENSITIVITY

POINT) = 2FSK,

–40°C

f_DEV= 4kHz,

DATA RATE = 9.8kbps

BLOCKER = 2FSK,

f_DEV= 4kHz,

DATA RATE = 9.8kbps

V

= 3.0V

DD

TEMPERATURE = 25°C

–10

–22 –18 –14 –10 –6

–2 0

2

6

10 14 18

22

90

92

94

96

98

100 102 104 106 108 110

FREQUENCY OFFSET (MHz)

IF FREQUENCY (kHz)

Figure 23. Wideband Interference Rejection

Figure 26. Variation of IF Filter Response with Temperature

(IF_FILTER_BW = 9 kHz, Temperature Range is −40°C to +90°C in 10° Steps)

–20

–40

–100

RF FREQ = 860MHz

2FSK MODULATION

DATA RATE = 9.6kbps

RSSI

READBACK LEVEL

–102

IF BW = 25kHz

= 3.0V

–104

V

DD

TEMPERATURE = 25°C

–60

–106

–108

–110

–112

–114

–116

–118

–80

DISCRIMINATOR BANDWIDTH =

2× FSK FREQUENCY DEVIATION

–100

–120

–140

ACTUAL RF INPUT LEVEL

DISCRIMINATOR BANDWIDTH =

1× FSK FREQUENCY DEVIATION

–122.5 –112.5 –102.5 –92.5 –82.5 –72.5 –62.5 –52.5 –42.5

RF INPUT (dBm)

0

0.2 0.4 0.6

0.8

1.0

1.2

MODULATION INDEX

Figure 27. 2FSK Sensitivity vs. Modulation Index vs. Correlator

Discriminator Bandwidth

Figure 24. Digital RSSI Readback Linearity

70

0

RF FREQ = 430MHz

CALIBRATED

EXTERNAL VCO INDUCTOR

DATA RATE = 9.6kbps

60

50

40

30

20

10

0

–1

TEMPERATURE = 25°C, V = 3.0V

DD

THRESHOLD DETECTION

–2

VITERBI DETECTION

–3

UNCALIBRATED

–4

–5

3FSK MODULATION

DD

V

= 3.0V, TEMP = 25°C

DATA RATE = 9.6kbps

–6

f_DEV= 2.4kHz

RF FREQ = 868MHz

IF BW = 18.75kHz

–10

–7

429.80 429.85 429.90 429.95 430.00 430.05 430.10 430.15 430.20

–120 –118 –116 –114 –112 –110 –108 –106 –104 –102 –100

INPUT POWER (dBm)

RF FREQUENCY (MHz)

Figure 28. 3FSK Receiver Sensitivity Using Viterbi Detection and

Threshold Detection

Figure 25. Image Rejection, Uncalibrated vs. Calibrated

Rev. 0 | Page 20 of 64

ADF7021-N

–70

–80

MODULATION = 2FSK

DATA RATE = 9.6kbps

f_DEV= 4kHz

+3

+1

HIGH MIXER

LINEARITY

IF BW = 12.5kHz

DEMOD = CORRELATOR

SENSITIVITY @ 1E-3 BER

IP3= –5dBm

IP3 = –3dBm

–90

0

–100

–110

–120

–130

IP3 = –9dBm

–1

IP3 = –20dBm

IP3 = –24dBm

DEFAULT

MIXER

LINEARITY

IP3 = –13.5dBm

–3

RF I/P LEVEL = –70dBm

DATA RATE = 9.7kbps

f_DEV(inner) = 1.2kHz

IF BW = 25kHz

POST DEMOD BW = 12.4kHz

22452 ACQS

M 50µs

3, 72

(LOW GAIN MODE)

10, 72

30, 72

(HIGH GAIN MODE)

(MEDIUM GAIN MODE)

LNA GAIN, FILTER GAIN

Figure 31. Receive Sensitivity vs. LNA/IF Filter Gain and Mixer Linearity Settings

(The input IP3 at each setting is also shown)

Figure 29. 4FSK Receiver Eye Diagram Measured Using the Test DAC Output

+1

0

–1

RF I/P LEVEL = –70dBm

DATA RATE = 10kbps

f_DEV= 2.5kHz

IF BW = 12.5kHz

POST DEMOD BW = 12.4kHz

4

20834 ACQS

M 20µs

C13

1.7V

Figure 30. 3FSK Receiver Eye Diagram Measured Using the Test DAC Output

Rev. 0 | Page 21 of 64

ADF7021-N

FREQUENCY SYNTHESIZER

REFERENCE INPUT

CLKOUT Divider and Buffer

The CLKOUT circuit takes the reference clock signal from the

oscillator section, shown in Figure 32, and supplies a divided-

down, 50:50 mark-space signal to the CLKOUT pin. The CLKOUT

signal is inverted with respect to the reference clock. An even

divide from 2 to 30 is available. This divide number is set in

R1_DB[7:10]. On power-up, the CLKOUT defaults to divide-by-8.

The on-board crystal oscillator circuitry (see Figure 32) can use

a quartz crystal as the PLL reference. Using a quartz crystal with

a frequency tolerance of ≤10 ppm for narrow-band applications

is recommended. It is possible to use a quartz crystal with >10 ppm

tolerance, but to comply with the absolute frequency error

specifications of narrow-band regulations (for example, ARIB

STD-T67 and ETSI EN 300 220), compensation for the

frequency error of the crystal is necessary.

DV

DD

CLKOUT

ENABLE BIT

The oscillator circuit is enabled by setting R1_DB12 high. It is

enabled by default on power-up and is disabled by bringing CE

low. Errors in the crystal can be corrected by using the automatic

frequency control feature or by adjusting the fractional-N value

(see the N Counter section).

DIVIDER

1 TO 15

OSC1

÷2

CLKOUT

Figure 33. CLKOUT Stage

To disable CLKOUT, set the divide number to 0. The output

buffer can drive up to a 20 pF load with a 10% rise time at

4.8 MHz. Faster edges can result in some spurious feedthrough

to the output. A series resistor (1 kΩ) can be used to slow the

clock edges to reduce these spurs at the CLKOUT frequency.

OSC1

OSC2

CP1

CP2

R Counter

Figure 32. Oscillator Circuit on the ADF7021-N

The 3-bit R counter divides the reference input frequency by an

integer between 1 and 7. The divided-down signal is presented

as the reference clock to the phase frequency detector (PFD). The

divide ratio is set in R1_DB[4:6]. Maximizing the PFD frequency

reduces the N value. This reduces the noise multiplied at a rate of

20 log(N) to the output and reduces occurrences of spurious

components.

Two parallel resonant capacitors are required for oscillation at

the correct frequency. Their values are dependent on the crystal

specification. They should be chosen to make sure that the

series value of capacitance added to the PCB track capacitance

adds up to the specified load capacitance of the crystal, usually

12 pF to 20 pF. Track capacitance values vary from 2 pF to 5 pF,

depending on board layout. When possible, choose capacitors

that have a very low temperature coefficient to ensure stable

frequency operation over all conditions.

Register 1 defaults to R = 1 on power-up.

PFD [Hz] = XTAL/R

Using a TCXO Reference

Loop Filter

A single-ended reference (TCXO, VCXO, or OCXO) can also be

used with the ADF7021-N. This is recommended for applications

having absolute frequency accuracy requirements of <10 ppm, such

as applications requiring compliance with ARIB STD-T67 or

ETSI EN 300 220. The following are two options for interfacing

the ADF7021-N to an external reference oscillator.

The loop filter integrates the current pulses from the charge

pump to form a voltage that tunes the output of the VCO to the

desired frequency. It also attenuates spurious levels generated by

the PLL. A typical loop filter design is shown in Figure 34.

CHARGE

VCO

PUMP OUT

•

An oscillator with CMOS output levels can be applied to

OSC2. The internal oscillator circuit should be disabled by

setting R1_DB12 low.

Figure 34. Typical Loop Filter Configuration

•

An oscillator with 0.8 V p-p levels can be ac-coupled through

a 22 pF capacitor into OSC1. The internal oscillator circuit

should be enabled by setting R1_DB12 high.

The loop should be designed so that the loop bandwidth (LBW)

is approximately 100 kHz. This provides a good compromise

between in-band phase noise and out-of-band spurious rejection.

Widening the LBW excessively reduces the time spent jumping

between frequencies, but it can cause insufficient spurious attenua-

tion. Narrow-loop bandwidths can result in the loop taking long

periods to attain lock and can also result in a higher level of power

falling into the adjacent channel. The loop filter design on the

Programmable Crystal Bias Current

Bias current in the oscillator circuit can be configured between 20

μA and 35 μA by writing to the XTAL_BIAS bits (R1_DB [13:14]).

Increasing the bias current allows the crystal oscillator to power

up faster.

Rev. 0 | Page 22 of 64

ADF7021-N

EVAL-ADF7021-NDBxx should be used for optimum

performance.

voltage must be stabilized. Regulator status (CREG4) can be

monitored using the REGULATOR_READY signal from the

MUXOUT pin.

The free design tool ADI SRD Design Studio™ can also

be used to design loop filters for the ADF7021-N (see the ADI

SRD Design Studio web site for details).

MUXOUT

The MUXOUT pin allows access to various digital points in the

ADF7021-N. The state of MUXOUT is controlled in Register 0

(R0_DB[29:31]).

N Counter

The feedback divider in the ADF7021-N PLL consists of an

8-bit integer counter (R0_DB[19:26]) and a 15-bit, sigma-delta

(Σ-Δ) fractional_N divider (R0_DB[4:18]). The integer counter

is the standard pulse-swallow type that is common in PLLs. This

sets the minimum integer divide value to 23. The fractional divide

value provides very fine resolution at the output, where the output

frequency of the PLL is calculated as

REGULATOR_READY

REGULATOR_READY is the default setting on MUXOUT

after the transceiver is powered up. The power-up time of the

regulator is typically 50 μs. Because the serial interface is powered

from the regulator, the regulator must be at its nominal voltage

before the ADF7021-N can be programmed. The status of the

regulator can be monitored at MUXOUT. When the regulator

ready signal on MUXOUT is high, programming of the

ADF7021-N can begin.

Fractional_ N

⎛

⎞

XTAL

R

⎜

⎟

f_OUT

=

× Integer _ N +

2¹⁵

⎜

⎝

⎠

When RF_DIVIDE_BY_2 (see the Voltage Controlled

Oscillator (VCO) section) is selected, this formula becomes

DV

DD

REGULATOR_READY (DEFAULT)

FILTER_CAL_COMPLETE

DIGITAL_LOCK_DETECT

RSSI_READY

XTAL

R

Fractional _ N

⎛

⎝

⎞

⎟

⎠

f_OUT

=

×0.5× Integer_N +

⎜

2¹⁵

The combination of Integer_N (maximum = 255) and

Fractional_N (maximum = 32,768/32,768) gives a maximum

N divider of 255 + 1. Therefore, the minimum usable PFD is

MUX

CONTROL

MUXOUT

Tx_Rx

LOGIC_ZERO

TRISTATE

Maximum Required Output Frequency

LOGIC_ONE

PFD_MINHz =

[ ]

(

255 +1

)

For example, when operating in the European 868 MHz to

870 MHz band, PFD_MIN= 3.4 MHz.

REFERENCE IN

DGND

Figure 36. MUXOUT Circuit

FILTER_CAL_COMPLETE

PFD/

4\R

CHARGE

PUMP

VCO

MUXOUT can be set to FILTER_CAL_COMPLETE. This signal

goes low for the duration of both a coarse IF filter calibration

and a fine IF filter calibration. It can be used as an interrupt to

a microcontroller to signal the end of the IF filter calibration.

4\N

THIRD-ORDER

Σ-Δ MODULATOR

DIGITAL_LOCK_DETECT

DIGITAL_LOCK_DETECT indicates when the PLL has locked.

The lock detect circuit is located at the PFD. When the phase

error on five consecutive cycles is less than 15 ns, lock detect is

set high. Lock detect remains high until a 25 ns phase error is

detected at the PFD.

FRACTIONAL_N

INTEGER_N

Figure 35. Fractional_N PLL

Voltage Regulators

The ADF7021-N contains four regulators to supply stable

voltages to the part. The nominal regulator voltage is 2.3 V.

Regulator 1 requires a 3.9 Ω resistor and a 100 nF capacitor in

series between CREG1 and GND, whereas the other regulators

require a 100 nF capacitor connected between CREGx and GND.

When CE is high, the regulators and other associated circuitry

are powered on, drawing a total supply current of 2 mA. Bringing

the CE pin low disables the regulators, reduces the supply current

to less than 1 μA, and erases all values held in the registers.

RSSI_READY

MUXOUT can be set to RSSI_READY. This indicates that the

internal analog RSSI has settled and a digital RSSI readback can

be performed.

Tx_Rx

Tx_Rx signifies whether the ADF7021-N is in transmit or receive

mode. When in transmit mode, this signal is low. When in receive

mode, this signal is high. It can be used to control an external

Tx/Rx switch.

The serial interface operates from a regulator supply. Therefore,

to write to the part, the user must have CE high and the regulator

Rev. 0 | Page 23 of 64

ADF7021-N

A plot of the VCO operating frequency vs. total external

inductance (chip inductor + PCB track) is shown in Figure 38.

VOLTAGE CONTROLLED OSCILLATOR (VCO)

The ADF7021-N contains two VCO cores. The first VCO, the

internal inductor VCO, uses an internal LC tank and supports

842 MHz to 916 MHz and 421 MHz to 458 MHz operating

bands. The second VCO, the external inductor VCO, uses an

external inductor as part of its LC tank and supports the RF

operating band of 80 MHz to 650 MHz.

750

700

650

f_MAX(MHz)

600

550

500

450

400

350

To minimize spurious emissions, both VCOs operate at twice

the RF frequency. The VCO signal is then divided by 2 inside

the synthesizer loop, giving the required frequency for the

transmitter and the required local oscillator (LO) frequency for

the receiver. A further divide-by-2 (RF_DIVIDE_BY_2) is

performed outside the synthesizer loop to allow operation in

the 421 MHz to 458 MHz band (internal inductor VCO) and

the 80 MHz to 325 MHz band (external inductor VCO).

f_MIN(MHz)

300

250

200

0

5

10

15

20

25

30

TOTAL EXTERNAL INDUCTANCE (nH)

The VCO needs an external 22 nF capacitor between the CVCO

pin and the regulator (CREG1 pin) to reduce internal noise.

Figure 38. Direct RF Output vs. Total External Inductance

The inductance for a PCB track using FR4 material is approxi-

mately 0.57 nH/mm. This should be subtracted from the total

value to determine the correct chip inductor value.

VCO_BIAS

R1_DB(19:22)

Typically, a particular inductor value allows the ADF7021-N to

function over a range of 6% of the RF operating frequency.

When the RF_DIVIDE_BY_2 bit (R1_DB18) is selected, this

range becomes 3%. At 400 MHz, for example, an operating

range of 24 MHz (that is, 376 MHz to 424 MHz) with a single

inductor (VCO range centered at 400 MHz) can be expected.

LOOP FILTER

VCO

MUX

÷2

TO PA

÷2

220µF

CVCO PIN

TO

N DIVIDER

RF_DIVIDE_BY_2

R1_DB18

Figure 37. Voltage Controlled Oscillator (VCO)

The VCO tuning voltage can be checked for a particular RF

output frequency by measuring the voltage on the VCOIN pin

when the part is fully powered up in transmit or receive mode.

Internal Inductor VCO

To select the internal inductor VCO, set R1_DB25 to Logic 0,

which is the default setting.

The VCO tuning range is 0.2 V to 2 V. The external inductor

value should be chosen to ensure that the VCO is operating

as close as possible to the center of this tuning range. This is

particularly important for RF frequencies <200 MHz, where

the VCO gain is reduced and a tuning range of < 6 MHz exists.

VCO bias current can be adjusted using R1_DB[19:22]. To

ensure VCO oscillation, the minimum bias current setting under

all conditions when using the internal inductor VCO is 0x8.

The VCO should be recentered, depending on the required

frequency of operation, by programming the VCO_ADJUST

bits (R1_DB[23:24]). This is detailed in Table 9.

The VCO operating frequency range can be adjusted by

programming the VCO_ADJUST bits (R1_DB[23:24]). This

typically allows the VCO operating range to be shifted up or

down by a maximum of 1% of the RF frequency.

External Inductor VCO

When using the external inductor VCO, the center frequency of the

VCO is set by the internal varactor capacitance and the combined

inductance of the external chip inductor, bond wire, and PCB track.

The external inductor is connected between the L2 and L1 pins.

To select the external inductor VCO, set R1_DB25 to Logic 1.

The VCO_BIAS should be set depending on the frequency of

operation (as indicated in Table 9).

Rev. 0 | Page 24 of 64

ADF7021-N

Table 9. RF Output Frequency Ranges for Internal and External Inductor VCOs and Required Register Settings

Register Settings

RF Frequency

Output (MHz)

VCO to

Be Used

RF Divide

by 2

VCO_INDUCTOR

R1_DB25

RF_DIVIDE_BY_2

R1_DB18

VCO_ADJUST

R1_DB[23:24]

VCO_BIAS

R1_DB[19:22]

870 to 916

842 to 870

440 to 458

421 to 440

450 to 650

200 to 450

80 to 200

Internal L

External L

No

Yes

No

Yes

0

1

0

1

0

1

11

00

11

00

XX

8

4

3

2

These spurs are attenuated by the loop filter. They are more

noticeable on channels close to integer multiples of the reference

where the difference frequency may be inside the loop bandwidth;

thus, the name integer boundary spurs. The occurrence of these

spurs is rare because the integer frequencies are around multiples

of the reference, which is typically >10 MHz. To avoid having

very small or very large values in the fractional register, choose

a suitable reference frequency.

CHOOSING CHANNELS FOR BEST SYSTEM

PERFORMANCE

An interaction between the RF VCO frequency and the

reference frequency can lead to fractional spur creation. When

the synthesizer is in fractional mode (that is, the RF VCO and

reference frequencies are not integer related), spurs can appear

on the VCO output spectrum at an offset frequency that

corresponds to the difference frequency between an integer

multiple of the reference and the VCO frequency.

Rev. 0 | Page 25 of 64

ADF7021-N

TRANSMITTER

RF OUTPUT STAGE

1

2

3

4

...

8

... 16

DATA BITS

The power amplifier (PA) of the ADF7021-N is based on a

single-ended, controlled current, open-drain amplifier that has

been designed to deliver up to 13 dBm into a 50 Ω load at a

maximum frequency of 950 MHz.

PA RAMP 0

(NO RAMP)

PA RAMP 1

(256 CODES PER BIT)

PA RAMP 2

(128 CODES PER BIT)

The PA output current and consequently, the output power, are

programmable over a wide range. The PA configuration is shown

in Figure 39. The output power is set using R2_DB[13:18].

R2_DB(11:12)

PA RAMP 3

(64 CODES PER BIT)

PA RAMP 4

(32 CODES PER BIT)

PA RAMP 5

(16 CODES PER BIT)

2

PA RAMP 6

(8 CODES PER BIT)

6

IDAC

R2_DB(13:18)

PA RAMP 7

(4 CODES PER BIT)

RFOUT

RFGND

Figure 40. PA Ramping Settings

R2_DB7

+

R0_DB27

PA Bias Currents

The PA_BIAS bits (R2_DB[11:12]) facilitate an adjustment of

the PA bias current to further extend the output power control

range, if necessary. If this feature is not required, the default

value of 9 μA is recommended. If output power of greater than

10 dBm is required, a PA bias setting of 11 μA is recommended.

The output stage is powered down by resetting R2_DB7.

FROM VCO

Figure 39. PA Configuration

The PA is equipped with overvoltage protection, which makes it

robust in severe mismatch conditions. Depending on the appli-

cation, users can design a matching network for the PA to exhibit

optimum efficiency at the desired radiated output power level

for a wide range of antennas, such as loop or monopole antennas.

See the LNA/PA Matching section for more information.

MODULATION SCHEMES

The ADF7021-N supports 2FSK, 3FSK, and 4FSK modulation.

The implementation of these modulation schemes is shown in

Figure 41.

PA Ramping

TO

PA STAGE

LOOP FILTER

PFD/

CHARGE

PUMP

REF

When the PA is switched on or off quickly, its changing input

impedance momentarily disturbs the VCO output frequency.

This process is called VCO pulling, and it manifests as spectral

splatter or spurs in the output spectrum around the desired carrier

frequency. Some radio emissions regulations place limits on

these PA transient-induced spurs (for example, the ETSI EN 300 220

regulations). By gradually ramping the PA on and off, PA transient

spurs are minimized.

÷2

VCO

÷N

FRACTIONAL_N

THIRD-ORDER

Σ-Δ MODULATOR

INTEGER_N

Tx_FREQUENCY_

DEVIATION

The ADF7021-N has built-in PA ramping configurability. As

Figure 40 illustrates, there are eight ramp rate settings, defined

as a certain number of PA setting codes per one data bit period.

The PA steps through each of its 64 code levels but at different

speeds for each setting. The ramp rate is set by configuring

R2_DB[8:10].

2FSK

TxDATA

GAUSSIAN

2

3FSK

4FSK

PRE-

CODER

1 – D PR

SHAPING

OR

MUX

RAISED COSINE

FILTERING

4FSK

BIT SYMBOL

MAPPER

If the PA is enabled/disabled by the PA_ENABLE bit (R2_DB7),

it ramps up and down. If it is enabled/disabled by the Tx/Rx bit

(R0_DB27), it ramps up and turns hard off.

Figure 41. Transmit Modulation Implementation

Rev. 0 | Page 26 of 64

ADF7021-N

Setting the Transmit Data Rate

3-Level Frequency Shift Keying (3FSK)

In all modulation modes except oversampled 2FSK mode, an

accurate clock is provided on the TxRxCLK pin to latch the data

from the microcontroller into the transmit section at the required

data rate. The exact frequency of this clock is defined by

In 3-level FSK modulation (also known as modified duobinary

FSK), the binary data (Logic 0 and Logic 1) is mapped onto

three distinct frequencies: the carrier frequency (f_C), the carrier

frequency minus a deviation frequency (f_C− f_DEV), and the

carrier frequency plus the deviation frequency (f_C+ f_DEV).

XTAL

DATA CLK =

DEMOD _ CLK _ DIVIDE×CDR _ CLK _ DIVIDE×32

A Logic 0 is mapped to the carrier frequency while a Logic 1 is

either mapped onto the f_C− f_DEVfrequency or the f_C+ f_DEV

frequency.

where:

XTAL is the crystal or TCXO frequency.

DEMOD_CLK_DIVIDE is the divider that sets the demodulator

clock rate (R3_DB[6:9]).

0

+1

–1

CDR_CLK_DIVIDE is the divider that sets the CDR clock rate

(R3_DB[10:17]).

f_C

–

f_DEV

f_C

f_C+ f_DEV

Refer to the Register 3—Transmit/Receive Clock Register

section for more programming information.

RF FREQUENCY

Figure 42. 3FSK Symbol-to-Frequency Mapping

Setting the FSK Transmit Deviation Frequency

Compared to 2FSK, this bits-to-frequency mapping results in a

reduced transmission bandwidth because some energy is removed

from the RF sidebands and transferred to the carrier frequency.

At low modulation index, 3FSK improves the transmit spectral

efficiency by up to 25% when compared to 2FSK.

In all modulation modes, the deviation from the center

frequency is set using the Tx_FREQUENCY_DEVIATION bits

(R2_DB[19:27]).

The deviation from the center frequency in Hz is as follows:

For direct RF output,

Bit-to-symbol mapping for 3FSK is implemented using a linear

convolutional encoder that also permits Viterbi detection to be

used in the receiver. A block diagram of the transmit hardware

used to realize this system is shown in Figure 43. The convolu-

tional encoder polynomial used to implement the transmit

spectral shaping is

PFD×Tx_ FREQUENCY_ DEVIATION

f_DEV[Hz] =

2¹⁶

For RF_DIVIDE_BY_2 enabled,

PFD×Tx_ FREQUENCY_ DEVIATION

f_DEV[Hz] = 0.5×

2¹⁶

P(D) = 1 − D²

where Tx_FREQUENCY_DEVIATION is a number from 1 to

511 (R2_DB[19:27]).

where:

P is the convolutional encoder polynomial.

D is the unit delay operator.

In 4FSK modulation, the four symbols (00, 01, 11, 10) are

transmitted as 3 ꢁ f_DEVand 1 ꢁ f_DEV

.

A digital precoder with transfer function 1/P(D) implements an

inverse modulo-2 operation of the 1 − D²shaping filter in the

transmitter.

Binary Frequency Shift Keying (2FSK)

Two-level frequency shift keying is implemented by setting the

N value for the center frequency and then toggling it with the

TxDATA line. The deviation from the center frequency is set

using the Tx_FREQUENCY_DEVIATION bits, R2_DB[19:27].

Tx DATA

0, 1

CONVOLUTIONAL

ENCODER

P(D)

PRECODER

1/P(D)

2FSK is selected by setting the MODULATION_SCHEME bits

(R2_DB[4:6]) to 000.

0, +1, –1

Minimum shift keying (MSK) or Gaussian minimum shift

keying (GMSK) is supported by selecting 2FSK modulation and

using a modulation index of 0.5. A modulation index of 0.5 is

set up by configuring R2_DB[19:27] for an f_DEV= 0.25 ꢁ

transmit data rate.

f_C

FSK MOD

CONTROL

AND

+

–

f_DEV

TO

N DIVIDER

DATA FILTERING

Figure 43. 3FSK Encoding

Rev. 0 | Page 27 of 64

ADF7021-N

The signal mapping of the input binary transmit data to the

3-level convolutional output is shown in Table 10. The

convolutional encoder restricts the maximum number of

sequential +1s or −1s to two and delivers an equal number of

+1s and −1s to the FSK modulator, thus ensuring equal spectral

energy in both RF sidebands.

The transmit clock from Pin TxRxCLK is available after writing

to Register 3 in the power-up sequence for receive mode. The

MSB of the first symbol should be clocked into the ADF7021-N

on the first transmit clock pulse from the ADF7021-N after

writing to Register 3. Refer to Figure 6 for more timing

information.

Oversampled 2FSK

Table 10. 3-Level Signal Mapping of the Convolutional Encoder

In oversampled 2FSK, there is no data clock from the TxRxCLK

pin. Instead, the transmit data at the TxRxDATA pin is sampled

at 32 times the programmed rate.

1

0

1

0

1

0

1

0

1

0

1

0

1

TxDATA

1

0

1

0

Precoder Output

Encoder Output

+1

−1 +1

+1

−1

This is the only modulation mode that can be used with the UART

mode interface for data transmission (refer to the Interfacing to

a Microcontroller/DSP section for more information).

Another property of this encoding scheme is that the transmitted

symbol sequence is dc-free, which facilitates symbol detection

and frequency measurement in the receiver. In addition, there is

no code rate loss associated with this 3-level convolutional encoder;

that is, the transmitted symbol rate is equal to the data rate

presented at the transmit data input.

SPECTRAL SHAPING

Gaussian or raised cosine filtering can be used to improve

transmit spectral efficiency. The ADF7021-N supports Gaussian

filtering (bandwidth time [BT] = 0.5) on 2FSK modulation.

Raised cosine filtering can be used with 2FSK, 3FSK, or 4FSK

modulation. The roll-off factor (alpha) of the raised cosine filter

has programmable options of 0.5 and 0.7. Both the Gaussian

and raised cosine filters are implemented using linear phase

digital filter architectures that deliver precise control over the

BT and alpha filter parameters, and guarantee a transmit spectrum

that is very stable over temperature and supply variation.

3FSK is selected by setting the MODULATION_SCHEME bits

(R2_DB[4:6]) to 010. It can also be used with raised cosine

filtering to further increase the spectral efficiency of the transmit

signal.

4-Level Frequency Shift Keying (4FSK)

In 4FSK modulation, two bits per symbol spectral efficiency is

realized by mapping consecutive input bit-pairs in the Tx data

bit stream to one of four possible symbols (−3, −1, +1, +3). Thus,

the transmitted symbol rate is half of the input bit rate.

Gaussian Frequency Shift Keying (GFSK)

Gaussian frequency shift keying reduces the bandwidth occupied

by the transmitted spectrum by digitally prefiltering the transmit

data. The BT product of the Gaussian filter used is 0.5.

By minimizing the separation between symbol frequencies,

4FSK can have high spectral efficiency. The bit-to-symbol

mapping for 4FSK is gray coded and is shown in Figure 44.

Gaussian filtering can only be used with 2FSK modulation. This

is selected by setting R2_DB[4:6] to 001.

Tx DATA

0

1

0

1

Raised Cosine Filtering

f

Raised cosine filtering provides digital prefiltering of the transmit

data by using a raised cosine filter with a roll-off factor (alpha)

of either 0.5 or 0.7. The alpha is set to 0.5 by default, but the

raised cosine filter bandwidth can be increased to provide less

aggressive data filtering by using an alpha of 0.7 (set R2_DB30

to Logic 1). Raised cosine filtering can be used with 2FSK,

3FSK, and 4FSK.

+3f_DEV

+f_DEV

SYMBOL

FREQUENCIES

–f_DEV

–3f_DEV

Raised cosine filtering is enabled by setting R2_DB[4:6] as

outlined in Table 11.

t

Figure 44. 4FSK Bit-to-Symbol Mapping

The inner deviation frequencies (+f_DEVand −f_DEV) are set using

the Tx_FREQUENCY_DEVIATION bits, R2_DB[19:27]. The

outer deviation frequencies are automatically set to three times

the inner deviation frequency.

Rev. 0 | Page 28 of 64

ADF7021-N

Table 12. Bit/Symbol Latency in Transmit Mode for Various

Modulation Schemes

MODULATION AND FILTERING OPTIONS

The various modulation and data filtering options are described

in Table 11.

Modulation

Latency

2FSK

1 bit

Table 11. Modulation and Filtering Options

GFSK

4 bits

Modulation

BINARY FSK

2FSK

Data Filtering R2_DB[4:6]

RC2FSK, Alpha = 0.5

RC2FSK, Alpha = 0.7

3FSK

RC3FSK, Alpha = 0.5

RC3FSK, Alpha = 0.7

4FSK

5 bits

4 bits

None

000

1 bit

5 bits

4 bits

MSK¹

OQPSK with Half Sine

Baseband Shaping²

GFSK

GMSK³

1 symbol

5 symbols

4 symbols

Gaussian

Raised cosine

None

001

101

100

RC4FSK, Alpha = 0.5

RC4FSK, Alpha = 0.7

RC2FSK

Oversampled 2FSK

3-LEVEL FSK

3FSK

TEST PATTERN GENERATOR

The ADF7021-N has a number of built-in test pattern generators

that can be used to facilitate radio link setup or RF measurement.

None

Raised cosine

010

110

RC3FSK

A full list of the supported patterns is shown in Table 13. The

data rate for these test patterns is the programmed data rate set

in Register 3.

4-LEVEL FSK

4FSK

RC4FSK

None

Raised cosine

011

111

The PN9 sequence is suitable for test modulation when carrying

out adjacent channel power (ACP) or occupied bandwidth

measurements.

¹MSK is 2FSK modulation with a modulation index = 0.5.

²Offset quadrature phase shift keying (OQPSK) with half sine baseband shaping

is spectrally equivalent to MSK.

³GMSK is GFSK with a modulation index = 0.5.

Table 13. Transmit Test Pattern Generator Options

TRANSMIT LATENCY

Test Pattern

R15_DB[8:10]

Transmit latency is the delay time from the sampling of a

bit/symbol by the TxRxCLK signal to when that bit/symbol

appears at the RF output. The latency without any data filtering

is one bit. The addition of data filtering adds a further latency as

outlined in Table 12.

Normal

Transmit Carrier

000

001

010

011

100

101

110

Transmit + f_DEVTone

Transmit − f_DEVTone

Transmit 1010 Pattern

Transmit PN9 Sequence

Transmit SWD Pattern Repeatedly

It is important that the ADF7021-N be left in transmit mode

after the last data bit is sampled by the data clock to account for

this latency. The ADF7021-N should stay in transmit mode for

a time equal to the number of latency bit periods for the applied

modulation scheme. This ensures that all of the data sampled by

the TxRxCLK signal appears at RF.

The figures for latency in Table 12 assume that the positive

TxRxCLK edge is used to sample data (default). If the TxRxCLK

is inverted by setting R2_DB[28:29], an additional 0.5 bit

latency can be added to all values in Table 12.

Rev. 0 | Page 29 of 64

Error! Unknown document

property name.

ADF7021-N

RECEIVER SECTION

chosen as a compromise between interference rejection and

attenuation of the desired signal.

RF FRONT END

The ADF7021-N is based on a fully integrated, low IF receiver

architecture. The low IF architecture facilitates a very low

external component count and does not suffer from powerline-

induced interference problems.

If the AGC loop is disabled, the gain of the IF filter can be set to one

of three levels by using the FILTER_GAIN bits (R9_DB[22:23]).

The filter gain is adjusted automatically if the AGC loop is

enabled.

Figure 45 shows the structure of the receiver front end. The

many programming options allow users to trade off sensitivity,

linearity, and current consumption to best suit their application.

To achieve a high level of resilience against spurious reception,

the low noise amplifier (LNA) features a differential input.

Switch SW2 shorts the LNA input when transmit mode is

selected (R0_DB27 = 0). This feature facilitates the design of a

combined LNA/PA matching network, avoiding the need for an

external Rx/Tx switch. See the LNA/PA Matching section for

details on the design of the matching network.

IF Filter Bandwidth and Center Frequency Calibration

To compensate for manufacturing tolerances, the IF filter should be

calibrated after power-up to ensure that the bandwidth and

center frequency are correct. Coarse and fine calibration

schemes are provided to offer a choice between fast calibration

(coarse calibration) and high filter centering accuracy (fine

calibration). Coarse calibration is enabled by setting R5_DB4

high. Fine calibration is enabled by setting R6_DB4 high.

For details on when it is necessary to perform a filter

calibration, and in what applications to use either a coarse

calibration or fine calibration, refer to the IF Filter Bandwidth

Calibration section.

I (TO FILTER)

RFIN

Tx/Rx SELECT

SW2 LNA

LO

(R0_DB27)

RFINB

Q (TO FILTER)

RSSI/AGC

LNA_MODE

(R9_DB25)

The RSSI is implemented as a successive compression log amp

following the baseband (BB) channel filtering. The log amp

achieves 3 dB log linearity. It also doubles as a limiter to

convert the signal-to-digital levels for the FSK demodulator.

The offset correction circuit uses the BBOS_CLK_DIVIDE bits

(R3_DB[4:5]), which should be set between 1 MHz and 2 MHz.

The RSSI level is converted for user readback and for digitally

controlled AGC by an 80-level (7-bit) flash ADC. This level can

be converted to input power in dBm. By default, the AGC is on

when powered up in receive mode.

MIXER LINEARITY

(R9_DB28)

LNA_BIAS

(R9_DB[26:27])

LNA_GAIN

(R9_DB[20:21])

LNA/MIXER_ENABLE

(R8_DB6)

Figure 45. RF Front End

The LNA is followed by a quadrature downconversion mixer,

which converts the RF signal to the IF frequency of 100 kHz.

An important consideration is that the output frequency of the

synthesizer must be programmed to a value 100 kHz below the

center frequency of the received channel. The LNA has two

basic operating modes: high gain/low noise mode and low

gain/low power mode. To switch between these two modes, use

the LNA_MODE bit (R9_DB25). The mixer is also configurable

between a low current and an enhanced linearity mode using

the MIXER_LINEARITY bit (R9_DB28).

OFFSET

CORRECTION

FSK

DEMOD

1

A

LATCH

CLK

IFWR

RSSI

ADC

R

Based on the specific sensitivity and linearity requirements of

the application, it is recommended to adjust the LNA_MODE

bit and MIXER_LINEARITY bit as outlined in Table 15.

Figure 46. RSSI Block Diagram

RSSI Thresholds

The gain of the LNA is configured by the LNA_GAIN bits

(R9_DB[20:21]) and can be set by either the user or the

automatic gain control (AGC) logic.

When the RSSI is above AGC_HIGH_THRESHOLD

(R9_DB[11:17]), the gain is reduced. When the RSSI is

below AGC_LOW_THRESHOLD (R9_DB[4:10]), the gain

is increased. The thresholds default to 30 and 70 on power-up

in receive mode. A delay (set by AGC_CLK_DIVIDE,

R3_DB[26:31]) is programmed to allow for settling of the loop.

A value of 13 is recommended to give an AGC update rate of

7.7 kHz.

IF FILTER

IF Filter Settings

Out-of-band interference is rejected by means of a fifth-order

Butterworth polyphase IF filter centered on a frequency of

100 kHz. The bandwidth of the IF filter can be programmed to

9 kHz, 13.5 kHz, or 18.5 kHz by R4_DB[30:31] and should be

Rev. 0 | Page 30 of 64

ADF7021-N

The user has the option of changing the two threshold values

from the defaults of 30 and 70 (Register 9). The default AGC

setup values should be adequate for most applications. The

threshold values must be more than 30 apart for the AGC to

operate correctly.

By using the recommended setting for AGC_CLK_DIVIDE, the

total AGC settling time is

Number of AGC Gain Changes

AGC Settling Time [sec] =

AGC Update Rate [Hz]

The worst case for AGC settling occurs when the AGC control

loop has to cycle through all five gain settings, which gives a

maximum AGC settling time of 650 μs.

Offset Correction Clock

In Register 3, the user should set the BBOS_CLK_DIVIDE bits

(R3_DB[4:5]) to give a baseband offset clock (BBOS CLK)

frequency between 1 MHz and 2 MHz.

RSSI Formula (Converting to dBm)

The RSSI formula is

BBOS CLK [Hz] = XTAL/(BBOS_CLK_DIVIDE)

where BBOS_CLK_DIVIDE can be set to 4, 8, 16, or 32.

AGC Information and Timing

Input Power [dBm] = −130 dBm + (Readback Code + Gain

Mode Correction) ꢁ 0.5

where:

AGC is selected by default and operates by setting the appropriate

LNA and filter gain settings for the measured RSSI level. It is

possible to disable AGC by writing to Register 9 if the user wants to

enter one of the modes listed in Table 15. The time for the AGC

circuit to settle and, therefore, the time it takes to measure the RSSI

accurately, is typically 390 μs. However, this depends on how many

gain settings the AGC circuit has to cycle through. After each gain

change, the AGC loop waits for a programmed time to allow

transients to settle. This AGC update rate is set according to

Readback Code is given by Bit RV7 to Bit RV1 in the Register 7

readback register (see Figure 58 and the Readback Format

section).

Gain Mode Correction is given by the values in Table 14.

The LNA gain (LG2, LG1) and filter gain (FG2, FG1) values

are also obtained from the readback register, as part of an RSSI

readback.

Table 14. Gain Mode Correction

SEQ _ CLK _ DIVIDE [Hz]

AGC Update Rate [Hz] =

LNA Gain

(LG2, LG1)

Filter Gain

(FG2, FG1)

Gain Mode

Correction

AGC _ CLK _ DIVIDE

H (1, 0)

M (0, 1)

L (0, 0)

H (1, 0)

M (0, 1)

L (0, 0)

0

where:

24

38

58

86

AGC_CLK_DIVIDE is set by R3_DB[26:31]. A value of 13 is

recommended.

SEQ_CLK_DIVIDE = 100 kHz (R3_DB[18:25]).

An additional factor should be introduced to account for losses

in the front-end-matching network/antenna.

Table 15. LNA/Mixer Modes

LNA_MODE LNA_GAIN

MIXER_LINEARITY Sensitivity (2FSK, DR =

Rx Current

Consumption (mA)

Input IP3

(dBm)

Receiver Mode

(R9_DB25)

(R9_DB[20:21]) (R9_DB28)

4.8 kbps, f_DEV= 4 kHz)

High Sensitivity

Mode (Default)

0

30

0

1

−118

24.6

−24

Enhanced Linearity

High Gain

0

−114.5

−20

Medium Gain

1

10

0

1

−112

22.1

−13.5

−9

Enhanced Linearity

Medium Gain

−105.5

Low Gain

1

3

0

1

−100

−92.3

22.1

−5

−3

Enhanced Linearity

Low Gain

Rev. 0 | Page 31 of 64

ADF7021-N

Correlator Demodulator

DEMODULATION, DETECTION, AND CDR

The correlator demodulator can be used for 2FSK, 3FSK, and

4FSK demodulation. Figure 48 shows the operation of the

correlator demodulator for 2FSK.

System Overview

An overview of the demodulation, detection, and clock and

data recovery (CDR) of the received signal on the ADF7021-N

is shown in Figure 47.

FREQUENCY CORRELATOR

DISCRIM BW

The quadrature outputs of the IF filter are first limited and

then fed to either the correlator FSK demodulator or to the

linear FSK demodulator. The correlator demodulator is used

to demodulate 2FSK, 3FSK, and 4FSK. The linear demodulator

is used for frequency measurement and is enabled when the

AFC loop is active. The linear demodulator can also be used

to demodulate 2FSK.

I

OUTPUT LEVELS:

2FSK = +1, –1

3FSK = +1, 0, –1

LIMITERS

Q

4FSK = +3, +1, –1, –3

IF

IF – f_DEV

IF + f_DEV

R4_DB9

Rx_INVERT

R4_DB(10:19)

DISCRIMINATOR_BW

Following the demodulator, a digital post demodulator filter

removes excess noise from the demodulator signal output.

Threshold/slicer detection is used for data recovery of 2FSK and

4FSK. Data recovery of 3FSK can be implemented using either

threshold detection or Viterbi detection.

R4_DB7

DOT_PRODUCT

Figure 48. 2FSK Correlator Demodulator Operation

The quadrature outputs of the IF filter are first limited and then

fed to a digital frequency correlator that performs filtering and

frequency discrimination of the 2FSK/3FSK/4FSK spectrum.

An on-chip CDR PLL is used to resynchronize the received bit

stream to a local clock. It outputs the retimed data and clock on

the TxRxDATA and TxRxCLK pins, respectively.

For 2FSK modulation, data is recovered by comparing the

output levels from two correlators. The performance of this

frequency discriminator approximates that of a matched filter

detector, which is known to provide optimum detection in the

presence of additive white Gaussian noise (AWGN). This

method of FSK demodulation provides approximately 3 dB to

4 dB better sensitivity than a linear demodulator.

LIMITERS

I

FREQUENCY

CORRELATOR

Q

MUX

LINEAR

DEMODULATOR

THRESHOLD

DETECTION

2/3/4FSK

TxRxDATA

TxRxCLK

CLOCK

AND

DATA

MUX

RECOVERY

VITERBI

DETECTION

3FSK

Figure 47. Overview of Demodulation, Detection, and CDR Process

Rev. 0 | Page 32 of 64

ADF7021-N

Linear Demodulator

3FSK and 4FSK Threshold Detection

Figure 49 shows a block diagram of the linear demodulator.

4FSK demodulation is implemented using the correlator

demodulator followed by the post demodulator filter and

threshold detection. The output of the post demodulation

filter is a 4-level signal that represents the transmitted symbols

(−3, −1, +1, +3). Threshold detection of 4FSK requires three

threshold settings, one that is always fixed at 0 and two that

are programmable and are symmetrically placed above and

below zero using the 3FSK/4FSK_SLICER_THRESHOLD bits

(R13_DB[4:10]).

I

LEVEL

IF

+

2FSK RxDATA

LIMITER

Q

SLICER

2FSK

FREQUENCY

LINEAR

DISCRIMINATOR

RxCLK

R4_DB(20:29)

FREQUENCY

READBACK

AND AFC LOOP

Figure 49. Block Diagram of Linear FSK Demodulator

3FSK demodulation is implemented using the correlator demodu-

lator, followed by a post demodulator filter. The output of the

post demodulator filter is a 3-level signal that represents the

transmitted symbols (−1, 0, +1). Data recovery of 3FSK can be

implemented using threshold detection or Viterbi detection.

Threshold detection is implemented using two thresholds that

are programmable and are symmetrically placed above and

below zero using the 3FSK/4FSK_SLICER_THRESHOLD bits

(R13_DB[4:10]).

A digital frequency discriminator provides an output signal that

is linearly proportional to the frequency of the limiter outputs.

The discriminator output is filtered and averaged using a combined

averaging filter and envelope detector. The demodulated 2FSK

data from the post demodulator filter is recovered by slicing against

the output of the envelope detector, as shown in Figure 49. This

method of demodulation corrects for frequency errors between

transmitter and receiver when the received spectrum is close to

or within the IF bandwidth. This envelope detector output is

also used for AFC readback and provides the frequency estimate

for the AFC control loop.

3FSK Viterbi Detection

Viterbi detection of 3FSK operates on a four-state trellis and is

implemented using two interleaved Viterbi detectors operating

at half the symbol rate. The Viterbi detector is enabled by

R13_DB11.

Post Demodulator Filter

A second-order, digital low-pass filter removes excess noise from

the demodulated bit stream at the output of the discriminator.

The bandwidth of this post demodulator filter is programmable

and must be optimized for the user’s data rate and received

modulation type. If the bandwidth is set too narrow, performance

degrades due to intersymbol interference (ISI). If the bandwidth

is set too wide, excess noise degrades the performance of the

receiver. The POST_DEMOD_BW bits (R4_DB[20:29]) set the

bandwidth of this filter.

To facilitate different run length constraints in the transmitted

bit stream, the Viterbi path memory length is programmable

in steps of 4 bits, 6 bits, 8 bits, or 32 bits by setting the

VITERBI_PATH_MEMORY bits (R13_DB[13:14]). This

should be set equal to or longer than the maximum number

of consecutive 0s in the interleaved transmit bit stream.

When used with Viterbi detection, the receiver sensitivity

for 3FSK is typically 3 dB greater than that obtained using

threshold detection. When the Viterbi detector is enabled,

however, the receiver bit latency is increased by twice the

Viterbi path memory length.

2FSK Bit Slicer/Threshold Detection

2FSK demodulation can be implemented using the correlator

FSK demodulator or the linear FSK demodulator. In both cases,

threshold detection is used for data recovery at the output of the

post demodulation filter.

Clock Recovery

An oversampled digital clock and data recovery (CDR) PLL is

used to resynchronize the received bit stream to a local clock

in all modulation modes. The oversampled clock rate of the PLL

(CDR CLK) must be set at 32 times the symbol rate (see the

Register 3—Transmit/Receive Clock Register section). The

maximum data/symbol rate tolerance of the CDR PLL is

determined by the number of zero-crossing symbol transitions

in the transmitted packet. For example, if using 2FSK with a

101010 preamble, a maximum tolerance of 3.0% of the data

rate is achieved. However, this tolerance is reduced during

recovery of the remainder of the packet where symbol transi-

tions may not be guaranteed to occur at regular intervals.

To maximize the data rate tolerance of the CDR, some form

of encoding and/or data scrambling is recommended that

guarantees a number of transitions at regular intervals.

The output signal levels of the correlator demodulator are

always centered about zero. Therefore, the slicer threshold level

can be fixed at zero, and the demodulator performance is

independent of the run-length constraints of the transmit data

bit stream. This results in robust data recovery that does not

suffer from the classic baseline wander problems that exist in

the more traditional FSK demodulators.

When the linear demodulator is used for 2FSK demodulation,

the output of the envelope detector is used as the slicer threshold,

and this output tracks frequency errors that are within the IF

filter bandwidth.

Rev. 0 | Page 33 of 64

ADF7021-N

For example, using 2FSK with Manchester-encoded data

achieves a data rate tolerance of 2.0%.

For 3FSK,

K = Round

3

⎛

⎜

⎝

⎞

⎟

⎠

100×10

2× f_DEV

The CDR PLL is designed for fast acquisition of the recovered

symbols during preamble and typically achieves bit synchro-

nization within 5-symbol transitions of preamble.

For 4FSK,

K = Round_4FSK

where:

Round is rounded to the nearest integer.

Round_4FSKis rounded to the nearest of the following integers: 32,

31, 28, 27, 24, 23, 20, 19, 16, 15, 12, 11, 8, 7, 4, 3.

3

In 4FSK modulation, the tolerance using the +3, −3, +3, −3

preamble is 3% of the symbol rate (or 1.5% of the data rate).

However, this tolerance is reduced during recovery of the

remainder of the packet where symbol transitions may not be

guaranteed to occur at regular intervals. To maximize the

symbol/data rate tolerance, the remainder of the 4FSK packet

should be constructed so that the transmitted symbols retain close

to dc-free properties by using data scrambling and/or by inserting

specific dc balancing symbols that are inserted in the transmitted

bit stream at regular intervals such as after every 8 or 16 symbols.

⎛

⎜

⎝

⎞

⎟

⎠

100×10

4× f_DEV

f

_DEVis the transmit frequency deviation in Hz. For 4FSK, f_DEVis

the frequency deviation used for the 1 symbols (that is, the

inner frequency deviations).

To optimize the coefficients of the correlator, R4_DB7 and

R4_DB[8:9] must also be assigned. The value of these bits

depends on whether K is odd or even. These bits are assigned

according to Table 17 and Table 18.

In 3FSK modulation, the linear convolutional encoder scheme

guarantees that the transmitted symbol sequence is dc-free,

facilitating symbol detection. However, Tx data scrambling is

recommended to limit the run length of zero symbols in the

transmit bit stream. Using 3FSK, the CDR data rate tolerance is

typically 0.5%.

Table 17. Assignment of Correlator K Value for 2FSK and 3FSK

K

K/2

(K + 1)/2

R4_DB7

R4_DB[8:9]

RECEIVER SETUP

Correlator Demodulator Setup

Even

Odd

Even

Odd

N/A

Even

Odd

0

1

00

10

00

10

To enable the correlator for various modulation modes, refer to

Table 16.

Table 18. Assignment of Correlator K Value for 4FSK

Table 16. Enabling the Correlator Demodulator

K

R4_DB7

R4_DB[8:9]

Received Modulation

DEMOD_SCHEME (R4_DB[4:6])

Even

Odd

0

1

00

2FSK

3FSK

4FSK

001

010

011

Linear Demodulator Setup

To optimize receiver sensitivity, the correlator bandwidth must be

optimized for the specific deviation frequency and modulation

used by the transmitter. The discriminator bandwidth is

controlled by R4_DB[10:19] and is defined as

The linear demodulator can be used for 2FSK demodulation. To

enable the linear demodulator, set the DEMOD_SCHEME bits

(R4_DB[4:6]) to 000.

Post Demodulator Filter Setup

(

DEMOD CLK ×K

)

The 3 dB bandwidth of the post demodulator filter should be

set according to the received modulation type and data rate.

The bandwidth is controlled by R4_DB[20:29] and is given by

DISCRIMINATOR _ BW =

where:

400×10³

2

¹¹×π× f_CUTOFF

DEMOD CLK is as defined in the Register 3—Transmit/Receive

POST _ DEMOD _ BW =

Clock Register section.

DEMOD CLK

K is set for each modulation mode according to the following:

where f_CUTOFFis the target 3 dB bandwidth in Hz of the post

demodulator filter.

For 2FSK,

3

⎛

⎜

⎝

⎞

⎟

⎠

100×10

K = Round

Table 19. Post Demodulator Filter Bandwidth Settings for

2FSK/3FSK/4FSK Modulation Schemes

f_DEV

Received

Modulation

Post Demodulator Filter Bandwidth,

f_CUTOFF(Hz)

2FSK

3FSK

4FSK

0.75 × data rate

1 × data rate

1.6 × symbol rate (= 0.8 × data rate)

Rev. 0 | Page 34 of 64

ADF7021-N

3FSK Viterbi Detector Setup

3FSK Threshold Detector Setup

The Viterbi detector can be used for 3FSK data detection. This

is activated by setting R13_DB11 to Logic 1.

To activate threshold detection of 3FSK, R13_DB11 should be

set to Logic 0. The 3FSK/4FSK_SLICER_THRESHOLD bits

(R13_DB[4:10]) should be set as outlined in the 3FSK Viterbi

Detector Setup section.

The Viterbi path memory length is programmable in steps of 4,

6, 8, or 32 bits (VITERBI_PATH_MEMORY, R13_DB[13:14]).

3FSK CDR Setup

The path memory length should be set equal to or greater than

the maximum number of consecutive 0s in the interleaved

transmit bit stream.

In 3FSK, a transmit preamble of at least 40 bits of continuous

1s is recommended to ensure a maximum number of symbol

transitions for the CDR to acquire lock.

The Viterbi detector also uses threshold levels to implement the

maximum likelihood detection algorithm. These thresholds are

programmable via the 3FSK/4FSK_SLICER_THRESHOLD bits

(R13_DB[4:10]).

The clock and data recovery for 3FSK requires a number of

parameters in Register 13 to be set (see Table 20).

4FSK Threshold Detector Setup

These bits are assigned as follows:

The threshold for the 4FSK detector is set using the

3FSK/4FSK_SLICER_THRESHOLD bits (R13_DB[4:10]).

The threshold should be set according to

3FSK/4FSK_SLICER_THRESHOLD =

Transmit Frequency Deviation× K

100×10³

⎛

⎞

57×⎜

⎟

⎜

3FSK/4FSK_SLICER_THRESHOLD =

⎝

⎠

4FSK Outer Tx Deviation× K

100×10³

⎛

⎞

where K is the value calculated for correlator discriminator

bandwidth.

⎜

⎟

78×

⎝

⎠

where K is the value calculated for correlator discriminator

bandwidth.

Table 20. 3FSK CDR Settings

Parameter

Recommended Setting

Purpose

PHASE_CORRECTION (R13_DB12)

3FSK_CDR_THRESHOLD (R13_DB[15:21])

1

Phase correction is on

Sets CDR decision threshold levels

Transmit Frequency Deviation× K

⎛

⎜

⎞

⎟

62×

100×10³

⎝

⎠

where K is the value calculated for correlator

discriminator bandwidth.

3FSK_PREAMBLE_TIME_VALIDATE (R13_DB [22:25]) 15

Preamble detector time qualifier

Rev. 0 | Page 35 of 64

ADF7021-N

The linear demodulator (AFC disabled) tracks frequency errors

in the receive signal when the receive signal is within the IF

filter bandwidth. For example, for a receive signal with an

occupied bandwith = 9 kHz, using the 18.5 kHz IF filter

bandwidth allows the linear demodulator to track the signal at

an error of 4.75 kHz with no increase in bit errors or loss in

sensitivity.

DEMODULATOR CONSIDERATIONS

2FSK Preamble

The recommended preamble bit pattern for 2FSK is a dc-free

pattern (such as a 10101010… pattern). Preamble patterns with

longer run-length constraints (such as 11001100…) can also be

used but result in a longer synchronization time of the received

bit stream in the receiver. The preamble needs to allow enough

bits for AGC settling of the receiver and CDR acquisition. A

minimum of 16 preamble bits is recommended when using the

correlator demodulator and 48 bits when using the linear demod-

ulator. When the receiver uses the internal AFC, the minimum

recommended number of preamble bits is 64.

Correlator Demodulator and Low Modulation Indices

The modulation index in 2FSK is defined as

2× f_DEV

Modulation Index =

Data Rate

The receiver sensitivity performance and receiver frequency

tolerance can be maximized at low modulation index by

increasing the discriminator bandwidth of the correlator

demodulator. For modulation indices of less than 0.4, it is

recommended to double the correlator bandwidth by

calculating K as follows:

The remaining fields that follow the preamble header do not

have to use dc-free coding. For these fields, the ADF7021-N can

accommodate coding schemes with a run length of greater than

eight bits without any performance degradation. Refer to

Application Note AN-915 for more information.

4FSK Preamble and Data Coding

100³

⎛

⎞

The recommended preamble bit pattern for 4FSK is a repeating

00100010… bit sequence. This 2-level sequence of repeating

−3, +3, −3, +3 symbols is dc-free and maximizes the symbol

timing performance and data recovery of the 4FSK preamble in

the receiver. The minimum recommended length of the

preamble is 32 bits (16 symbols).

⎜

⎟

K = Round

2× f_DEV

⎝

⎠

The DISCRIMINATOR_BW in Register 4 should be recalculated

using the new K value. Figure 27 highlights the improved

sensitivity that can be achieved for 2FSK modulation, at low

modulation indices, by doubling the correlator bandwidth.

The remainder of the 4FSK packet should be constructed so

that the transmitted symbols retain close to a dc-free balance by

using data scrambling and/or by inserting specific dc balancing

symbols in the transmitted bit stream at regular intervals, such

as after every 8 or 16 symbols.

AFC OPERATION

The ADF7021-N also supports a real-time AFC loop that is

used to remove frequency errors due to mismatches between

the transmit and receive crystals/TCXOs. The AFC loop uses

the linear frequency discriminator block to estimate frequency

errors. The linear FSK discriminator output is filtered and

averaged to remove the FSK frequency modulation using a

combined averaging filter and envelope detector. In receive

mode, the output of the envelope detector provides an estimate

of the average IF frequency.

Demodulator Tolerance to Frequency Errors

Without AFC

The ADF7021-N has a number of options to combat frequency

errors that exist due to mismatches between the transmit and

receive crystals/TCXOs.

With AFC disabled, the correlator demodulator is tolerant to

frequency errors over a 0.3 ꢁ f_DEVrange, where f_DEVis the FSK

frequency deviation. For larger frequency errors, the frequency

tolerance can be increased by adjusting the value of K and thus

doubling the correlator bandwidth.

Two methods of AFC supported on the ADF7021-N are

external AFC and internal AFC.

External AFC

Here, the user reads back the frequency information through

the ADF7021-N serial port and applies a frequency correction

value to the fractional-N synthesizer-N divider.

K should then be calculated as

3

⎛

⎜

⎝

⎞

⎟

⎠

100×10

2× f_DEV

The frequency information is obtained by reading the 16-bit

signed AFC readback, as described in the Readback Format

section, and by applying the following formula:

K = Round

The DISCRIMINATOR_BW setting in Register 4 should also be

recalculated using the new K value. Doubling the correlator

bandwidth to improve frequency error tolerance in this manner

typically results in a 1 dB to 2 dB loss in receiver sensitivity.

Frequency Readback [Hz] = (AFC READBACK ꢁ DEMOD

CLK)/2¹⁸

Although the AFC READBACK value is a signed number, under

normal operating conditions, it is positive. In the absence of

frequency errors, the frequency readback value is equal to the

IF frequency of 100 kHz.

Rev. 0 | Page 36 of 64

ADF7021-N

Internal AFC

When AFC errors are removed using either the internal or

external AFC, further improvement in receiver sensitivity can

be obtained by reducing the IF filter bandwidth using the

IF_FILTER_BW bits (R4_DB[30:31]).

The ADF7021-N supports a real-time, internal, automatic

frequency control loop. In this mode, an internal control loop

automatically monitors the frequency error and adjusts the

synthesizer-N divider using an internal proportional integral

(PI) control loop.

AUTOMATIC SYNC WORD DETECTION (SWD)

The ADF7021-N also supports automatic detection of the sync

or ID fields. To activate this mode, the sync (or ID) word must

be preprogrammed into the ADF7021-N. In receive mode, this

preprogrammed word is compared to the received bit stream.

When a valid match is identified, the external SWD pin is

asserted by the ADF7021-N on the next Rx clock pulse.

The internal AFC control loop parameters are controlled in

Register 10. The internal AFC loop is activated by setting

R10_DB4 to 1. A scaling coefficient must also be entered, based

on the crystal frequency in use. This is set up in R10_DB[5:16]

and should be calculated using

24

This feature can be used to alert the microprocessor that a

valid channel has been detected. It relaxes the computational

requirements of the microprocessor and reduces the overall

power consumption.

⎛

⎜

⎝

⎞

⎟

⎠

2

×500

AFC _ SCALING _ FACTOR = Round

XTAL

Maximum AFC Range

The maximum frequency correction range of the AFC loop is

programmable on the ADF7021-N. This is set by R10_DB[24:31].

The maximum AFC correction range is the difference in

frequency between the upper and lower limits of the AFC

tuning range. For example, if the maximum AFC correction

range is set to 10 kHz, the AFC can adjust the receiver LO

within the f_LO5 kHz range.

The SWD signal can also be used to frame the received packet

by staying high for a preprogrammed number of bytes. The data

packet length can be set in R12_DB[8:15].

The SWD pin status can be configured by setting R12_DB[6:7].

R11_DB[4:5] are used to set the length of the sync/ID word, which

can be 12, 16, 20, or 24 bits long. A value of 24 bits is recommended

to minimize false sync word detection in the receiver that can

occur during recovery of the remainder of the packet or when a

noise/no signal is present at the receiver input. The transmitter

must transmit the sync byte MSB first and the LSB last to ensure

proper alignment in the receiver sync-byte-detection hardware.

However, when RF_DIVIDE_BY_2 (R1_DB18) is enabled, the

programmed range is halved. The user should account for this

halving by doubling the programmed maximum AFC range.

The recommended maximum AFC correction range should be

≤1.5 ꢁ IF filter bandwidth. If the maximum frequency correction

range is set to be >1.5 ꢁ IF filter bandwidth, the attenuation of

the IF filter can degrade the AFC loop sensitivity.

An error tolerance parameter can also be programmed that

accepts a valid match when up to three bits of the word are

incorrect. The error tolerance value is assigned in R11_DB[6:7].

The adjacent channel rejection (ACR) performance of the

receivers can be degraded when AFC is enabled and the AFC

correction range is close to the IF filter bandwidth. However,

because the AFC correction range is programmable, the user

can trade off correction range and ACR performance.

Rev. 0 | Page 37 of 64

ADF7021-N

APPLICATIONS INFORMATION

IF FILTER BANDWIDTH CALIBRATION

Lower Tone Frequency (kHz)

XTAL

The IF filter should be calibrated on every power-up in receive

mode to correct for errors in the bandwidth and filter center

frequency due to process variations. The automatic calibration

requires no external intervention once it is initiated by a write

to Register 5. Depending on numerous factors, such as IF filter

bandwidth, received signal bandwidth, and temperature variation,

the user must determine whether to carry out a coarse

calibration or a fine calibration.

IF_CAL_LOWER_TONE_DIVIDE × 2

Upper Tone Frequency (kHz)

XTAL

IF_CAL_UPPER_TONE_DIVIDE × 2

It is recommended to place the lower tone and upper tone as

outlined in Table 22.

The performance of both calibration methods is outlined in

Table 21.

Table 22. IF Filter Fine Calibration Tone Frequencies

IF Filter

Bandwidth

Lower Tone

Frequency

Upper Tone

Frequency

Table 21. IF Filter Calibration Specifications

Filter Calibration

Method

Center Frequency

Calibration

Time (Typ)

9 kHz

13.5 kHz

18.5 kHz

78.1 kHz

79.4 kHz

78.1 kHz

116.3 kHz

119 kHz

Accuracy¹

Coarse Calibration

Fine Calibration

100 kHz 2.5 kHz

100 kHz 0.6 kHz

200 μs

8.2 ms

Because the filter attenuation is slightly asymmetrical, it is

necessary to have a small offset in the filter center frequency to

give near equal rejection at the upper and lower adjacent

channels. The calibration tones given in Table 22 give this small

positive offset in the IF filter center frequency.

¹After calibration.

Calibration Setup

IF Filter calibration is initiated by writing to Register 5 and

setting the IF_CAL_COARSE bit (R5_DB4). This initiates a

coarse filter calibration. If the IF_FINE_CAL bit (R6_DB4) has

already been configured high, the coarse calibration is followed

by a fine calibration, otherwise the calibration ends.

In some applications, an offset may not be required, and the

user may wish to center the IF filter exactly at 100 kHz. In this

case, the user can alter the tone frequencies from those given in

Table 22 to adjust the fine calibration result.

Once initiated by writing to the part, the calibration is performed

automatically without any user intervention. Calibration time is

200 μs for coarse calibration and a few milliseconds for fine

calibration, during which time the ADF7021-N should not be

accessed. The IF filter calibration logic requires that the

IF_FILTER_DIVIDER bits (R5_DB[5:13]) be set such that

The calibration algorithm adjusts the filter center frequency

and measures the RSSI 10 times during the calibration. The

time for an adjustment plus RSSI measurement is given by

IF_CAL_DWELL_TIME

IF Tone Calibration Time =

SEQ CLK

XTAL[Hz]

= 50 kHz

It is recommended that the IF tone calibration time be at least

800 μs. The total time for the IF filter fine calibration is given by

IF _ FILTER _ DIVIDER

The fine calibration uses two internally generated tones at

certain offsets around the IF filter. The two tones are attenuated

by the IF filter, and the level of this attenuation is measured

using the RSSI. The filter center frequency is adjusted to allow

equal attenuation of both tones. The attenuation of the two test

tones is then remeasured. This continues for a maximum of

10 RSSI measurements, at which stage the calibration algorithm

sets the IF filter center frequency to within 0.6 kHz of 100 kHz.

IF Filter Fine Calibration Time = IF Tone Calibration Time × 10

When to Use Coarse Calibration

It is recommended to perform a coarse calibration on every

receive mode power-up. This calibration typically takes 200 μs.

The FILTER_CAL_COMPLETE signal from MUXOUT can be

used to monitor the filter calibration duration or to signal the

end of calibration. The ADF7021-N should not be accessed

during calibration.

The frequency of these tones is set by the IF_CAL_LOWER_

TONE_DIVIDE (R6_DB[5:12]) and IF_CAL_UPPER_TONE_

DIVIDE (R6_DB[13:20]) bits, outlined in the following equations:

Rev. 0 | Page 38 of 64

ADF7021-N

When to Use a Fine Calibration

LNA/PA MATCHING

In cases where the receive signal bandwidth is very close to the

bandwidth of the IF filter, it is recommended to perform a fine

filter calibration every time the unit powers up in receive mode.

The ADF7021-N exhibits optimum performance in terms of

sensitivity, transmit power, and current consumption, only if its

RF input and output ports are properly matched to the antenna

impedance. For cost-sensitive applications, the ADF7021-N is

equipped with an internal Rx/Tx switch that facilitates the use

of a simple, combined passive PA/LNA matching network.

Alternatively, an external Rx/Tx switch such as the ADG919 can

be used, which yields a slightly improved receiver sensitivity

and lower transmitter power consumption.

A fine calibration should be performed if

OBW + Coarse Calibration Variation > IF_FILTER_BW

where:

OBW is the 99% occupied bandwidth of the transmit signal.

Coarse Calibration Variation is 2.5 kHz.

IF_FILTER_BW is set by R4_DB[30:31].

Internal Rx/Tx Switch

The FILTER_CAL_COMPLETE signal from MUXOUT (set by

R0_DB[29:31]) can be used to monitor the filter calibration

duration or to signal the end of calibration. A coarse filter

calibration is automatically performed prior to a fine filter

calibration.

Figure 50 shows the ADF7021-N in a configuration where

the internal Rx/Tx switch is used with a combined LNA/PA

matching network. This is the configuration used on the EVAL-

ADF7021-NDBxx evaluation board. For most applications, the

slight performance degradation of 1 dB to 2 dB caused by the

internal Rx/Tx switch is acceptable, allowing the user to take

advantage of the cost saving potential of this solution. The

design of the combined matching network must compensate for

the reactance presented by the networks in the Tx and the Rx

paths, taking the state of the Rx/Tx switch into consideration.

When to Use Single Fine Calibration

In applications where the receiver powers up numerous times in

a short period, it is only necessary to perform a one-time fine

calibration on the initial receiver power-up.

After the initial coarse calibration and fine calibration, the result of

the fine calibration can be read back through the serial interface

using the FILTER_CAL_READBACK result (refer to the Filter

Bandwidth Calibration Readback section). On subsequent

power-ups in receive mode, the filter is manually adjusted using

the previous fine filter calibration result. This manual adjust is

performed using the IF_FILTER_ADJUST bits (R5_DB[14:19]).

V

BAT

L1

C1

PA_OUT

PA

ANTENNA

Z _PA

OPT

OPTIONAL

BPF OR LPF

Z

_RFIN

IN

C

A

RFIN

This method should only be used if the successive power-ups in

receive mode are over a short duration, during which time there

is little variation in temperature (<15ꢀC).

L

LNA

A

RFINB

Z

_RFIN

IN

IF Filter Variation with Temperature

C

B

ADF7021-N

When calibrated, the filter center frequency can vary with changes

in temperature. If the ADF7021-N is used in an application where

it remains in receive mode for a considerable length of time, the

user must consider this variation of filter center frequency with

temperature. This variation is typically 1 kHz per 20ꢀC, which

means that if a coarse filter calibration and fine filter calibration

are performed at 25ꢀC, the initial maximum error is 0.5 kHz,

and the maximum possible change in the filter center frequency

over temperature (−40ꢀC to +85ꢀC) is 3.25 kHz. This gives a

total error of 3.75 kHz.

Figure 50. ADF7021-N with Internal Rx/Tx Switch

The procedure typically requires several iterations until an

acceptable compromise has been reached. The successful imple-

mentation of a combined LNA/PA matching network for the

ADF7021-N is critically dependent on the availability of an

accurate electrical model for the PCB. In this context, the use of a

suitable CAD package is strongly recommended. To avoid this

effort, a small form-factor reference design for the ADF7021-N is

provided, including matching and harmonic filter components.

The design is on a 2-layer PCB to minimize cost. Gerber files

are available at www.analog.com.

If the receive signal occupied bandwidth is considerably less

than the IF filter bandwidth, the variation of filter center

frequency over the operating temperature range may not be

an issue. Alternatively, if the IF filter bandwidth is not wide

enough to tolerate the variation with temperature, a periodic

filter calibration can be performed or, alternatively, the on-chip

temperature sensor can be used to determine when a filter cali-

bration is necessary by monitoring for changes in temperature.

Rev. 0 | Page 39 of 64

ADF7021-N

External Rx/Tx Switch

Depending on the antenna configuration, the user may need a

harmonic filter at the PA output to satisfy the spurious emission

requirement of the applicable government regulations. The

harmonic filter can be implemented in various ways, for example, a

discrete LC pi or T-stage filter. The immunity of the ADF7021-N

to strong out-of-band interference can be improved by adding a

band-pass filter in the Rx path. Alternatively, the ADF7021-N

blocking performance can be improved by selecting one of the

enhanced linearity modes, as described in Table 15.

Figure 51 shows a configuration using an external Rx/Tx switch.

This configuration allows an independent optimization of the

matching and filter network in the transmit and receive path.

Therefore, it is more flexible and less difficult to design than the

configuration using the internal Rx/Tx switch. The PA is biased

through Inductor L1, while C1 blocks dc current. Together, L1

and C1 form the matching network that transforms the source

impedance into the optimum PA load impedance, Z_OPT_PA.

V

IMAGE REJECTION CALIBRATION

BAT

The image channel in the ADF7021-N is 200 kHz below the

desired signal. The polyphase filter rejects this image with an

asymmetric frequency response. The image rejection performance

of the receiver is dependent on how well matched the I and Q

signals are in amplitude and how well matched the quadrature

is between them (that is, how close to 90ꢀ apart they are). The

uncalibrated image rejection performance is approximately

29 dB (at 450 MHz). However, it is possible to improve on this

performance by as much as 20 dB by finding the optimum I/Q

gain and phase adjust settings.

L1

C1

PA_OUT

OPTIONAL

LPF

PA

ANTENNA

Z

_PA

OPT

Z

_RFIN

IN

C

A

OPTIONAL

BPF

(SAW)

RFIN

L

LNA

A

RFINB

ADG919

Rx/Tx – SELECT

Z

_RFIN

IN

C

B

ADF7021-N

Calibration Using Internal RF Source

Figure 51. ADF7021-N with External Rx/Tx Switch

With the LNA powered off, an on-chip generated, low level RF

tone is applied to the mixer inputs. The LO is adjusted to make

the tone fall at the image frequency where it is attenuated by the

image rejection of the IF filter. The power level of this tone is then

measured using the RSSI readback. The I/Q gain and phase adjust

DACs (R5_DB[20:31]) are adjusted and the RSSI is remeasured.

This process is repeated until the optimum values for the gain

and phase adjust are found that provide the lowest RSSI readback

level, thereby maximizing the image rejection performance of

the receiver.

Z_OPT_PA depends on various factors, such as the required

output power, the frequency range, the supply voltage range,

and the temperature range. Selecting an appropriate Z_OPT_PA

helps to minimize the Tx current consumption in the application.

Application Note AN-764 and Application Note AN-859 contain a

number of Z_OPT_PA values for representative conditions. Under

certain conditions, however, it is recommended to obtain a suitable

Z_OPT_PA value by means of a load-pull measurement.

Due to the differential LNA input, the LNA matching network

must be designed to provide both a single-ended-to-differential

conversion and a complex, conjugate impedance match. The

network with the lowest component count that can satisfy these

requirements is the configuration shown in Figure 51, consisting

of two capacitors and one inductor.

Rev. 0 | Page 40 of 64

ADF7021-N

RFIN

LNA

RFINB

POLYPHASE

IF FILTER

RSSI/

LOG AMP

MUX

INTERNAL

SIGNAL

SOURCE

7-BIT ADC

PHASE ADJUST

Q

I

FROM LO

SERIAL

INTERFACE

4

PHASE ADJUST

REGISTER 5

RSSI READBACK

4

GAIN ADJUST

REGISTER 5

MICROCONTROLLER

I/Q GAIN/PHASE ADJUST AND

RSSI MEASUREMENT

ALGORITHM

Figure 52. Image Rejection Calibration Using the Internal Calibration Source and a Microcontroller

IR_GAIN_ADJUST_I/Q bit (R5_DB30), whereas the

IR_GAIN_ADJUST_UP/DN bit (R5_DB31) sets whether

the gain adjustment defines a gain or an attenuation adjust.

Using the internal RF source, the RF frequencies that can be

used for image calibration are programmable and are odd

multiples of the reference frequency.

The calibration results are valid over changes in the ADF7021-N

supply voltage. However, there is some variation with temperature.

A typical plot of variation in image rejection over temperature

after initial calibrations at −40ꢀC, +25ꢀC, and +85ꢀC is shown in

Figure 53. The internal temperature sensor on the ADF7021-N

can be used to determine if a new IR calibration is required.

Calibration Using External RF Source

IR calibration can also be implemented using an external RF

source. The IR calibration procedure is the same as that used for

the internal RF source, except that an RF tone is applied to the

LNA input.

Calibration Procedure and Setup

60

CAL AT +25°C

The IR calibration algorithm available from Analog Devices, Inc., is

based on a low complexity, 2D optimization algorithm that can

be implemented in an external microprocessor or microcontroller.

50

40

30

20

10

0

CAL AT +85°C

CAL AT –40°C

To enable the internal RF source, the IR_CAL_SOURCE_

DRIVE_LEVEL bits (R6_DB[28:29]) should be set to the

maximum level. The LNA should be set to its minimum gain

setting, and the AGC should be disabled if the internal source is

being used. Alternatively, an external RF source can be used.

V

= 3.0V

IF BW = 25kHz

DD

INTERFERER SIGNAL:

WANTED SIGNAL:

RF FREQ = 430MHz

MODULATION = 2FSK

DATA RATE = 9.6kbps,

PRBS9

f_DEV= 4kHz

LEVEL= –100dBm

RF FREQ = 429.8MHz

MODULATION = 2FSK

DATA RATE = 9.6kbps,

PRBS11

The magnitude of the phase adjust is set by using the IR_PHASE_

ADJUST_MAG bits (R5_DB[20:23]). This correction can be

applied to either the I channel or Q channel, depending on the

value of the IR_PHASE_ADJUST_DIRECTION bit (R5_DB24).

f_DEV= 4kHz

–60

–40

–20

0

20

40

60

80

100

TEMPERATURE (°C)

The magnitude of the I/Q gain is adjusted by the IR_GAIN_

ADJUST_MAG bits (R5_DB[25:29]). This correction can be

applied to either the I or Q channel, depending on the value of

Figure 53. Image Rejection Variation with Temperature After Initial

Calibrations at −40°C, +25°C, and +85°C

Rev. 0 | Page 41 of 64

ADF7021-N

to a particular application, such as setting up sync byte

detection or enabling AFC. When going from Tx to Rx or vice

versa, the user needs to toggle the Tx/Rx bit and write only to

Register 0 to alter the LO by 100 kHz.

PACKET STRUCTURE AND CODING

The suggested packet structure to use with the ADF7021-N is

shown in Figure 54.

SYNC

WORD

ID

FIELD

Table 23. Minimum Register Writes Required for Tx/Rx Setup

PREAMBLE

DATA FIELD

CRC

Mode

Registers

Reg 1 Reg 3 Reg 0 Reg 2

Reg 1 Reg 3 Reg 0 Reg 5 Reg 4

Reg 0

Figure 54. Typical Format of a Transmit Protocol

Tx

Rx

Refer to the Receiver Setup section for information on the

required preamble structure and length for the various modulation

schemes.

Tx to Rx and Rx to Tx

The recommended programming sequences for transmit and

receive are shown in Figure 55 and Figure 56, respectively. The

difference in the power-up routine for a TCXO and XTAL

reference is shown in these figures.

PROGRAMMING AFTER INITIAL POWER-UP

Table 23 lists the minimum number of writes needed to set up

the ADF7021-N in either Tx or Rx mode after CE is brought

high. Additional registers can also be written to tailor the part

Rev. 0 | Page 42 of 64

ADF7021-N

TCXO

REFERENCE

XTAL

REFERENCE

POWER-DOWN

CE LOW

CE HIGH

WAIT 10µs + 1ms

(REGULATOR POWER-UP + TYPICAL XTAL SETTLING)

CE HIGH

WAIT 10µs (REGULATOR POWER-UP)

WRITE TO REGISTER 1 (TURNS ON VCO)

WAIT 0.7ms (TYPICAL VCO SETTLING)

WRITE TO REGISTER 3 (TURNS ON Tx/Rx CLOCKS)

WRITE TO REGISTER 0 (TURNS ON PLL)

WAIT 40µs (TYPICAL PLL SETTLING)

WRITE TO REGISTER 2 (TURNS ON PA)

WAIT FOR PA TO RAMP UP (ONLY IF PA RAMP ENABLED)

Tx MODE

WAIT FOR Tx LATENCY NUMBER OF BITS

(REFER TO TABLE 12)

WRITE TO REGISTER 2 (TURNS OFF PA)

WAIT FOR PA TO RAMP DOWN

CE LOW

POWER-DOWN

OPTIONAL. ONLY NECESSARY IF PA

RAMP DOWN IS REQUIRED.

Figure 55. Power-Up Sequence for Transmit Mode

Rev. 0 | Page 43 of 64

ADF7021-N

TCXO

REFERENCE

XTAL

REFERENCE

POWER-DOWN

CE LOW

CE HIGH

WAIT 10µs (REGULATOR POWER-UP)

WAIT 10µs + 1ms

(REGULATOR POWER-UP + TYPICAL XTAL SETTLING)

WRITE TO REGISTER 1 (TURNS ON VCO)

WAIT 0.7ms (TYPICAL VCO SETTLING)

WRITE TO REGISTER 3 (TURNS ON Tx/Rx CLOCKS)

OPTIONAL:

ONLY NECESSARY IF

IF FILTER FINE CAL IS REQUIRED.

WRITE TO REGISTER 6 (SETS UP IF FILTER CALIBRATION)

WRITE TO REGISTER 5 (STARTS IF FILTER CALIBRATION)

WAIT 0.2ms (COARSE CAL) OR WAIT 8.2ms

(COARSE CALIBRATION + FINE CALIBRATION)

WRITE TO REGISTER 11 (SET UP SWD)

WRITE TO REGISTER 12 (ENABLE SWD)

OPTIONAL:

ONLY NECESSARY IF

SWD IS REQUIRED.

WRITE TO REGISTER 0 (TURNS ON PLL)

WAIT 40µs (TYPICAL PLL SETTLING)

WRITE TO REGISTER 4 (TURNS ON DEMOD)

WRITE TO REGISTER 10 (TURNS ON AFC)

Rx MODE

OPTIONAL:

ONLY NECESSARY IF

AFC IS REQUIRED.

CE LOW

POWER-DOWN

OPTIONAL.

Figure 56. Power-Up Sequence for Receive Mode

Rev. 0 | Page 44 of 64

ADF7021-N

APPLICATIONS CIRCUIT

The ADF7021-N requires very few external components for

operation. Figure 57 shows the recommended application

circuit. Note that the power supply decoupling and regulator

capacitors are omitted for clarity.

For recommended component values, refer to the ADF7021-N

evaluation board data sheet and AN-859 application note

accessible from the ADF7021-N product page. Follow the

reference design schematic closely to ensure optimum

performance in narrow-band applications.

LOOP FILTER

VDD

TCXO

EXT VCO L*

CVCO

CAP

REFERENCE

VDD

1

36

35

CLKOUT

TxRxCLK

TxRxDATA

SWD

VCOIN

CREG1

VDD1

2

3

4

5

6

MATCHING

TO

MICROCONTROLLER

Tx/Rx SIGNAL

INTERFACE

34

33

32

VDD

T-STAGE LC

FILTER

RFOUT

RFGND

RFIN

ANTENNA

CONNECTION

VDD2

VDD

31

CREG2

ADCIN

GND2

ADF7021-N

30

29

7

8

RFINB

R

LNA

28

27

26

25

9

VDD4

RSET

CREG4

GND4

SCLK

TO

10

11

12

SREAD

SDATA

SLE

MICROCONTROLLER

CONFIGURATION

INTERFACE

RLNA

RESISTOR

CHIP ENABLE

TO MICROCONTROLLER

RSET

RESISTOR

*PIN 44 AND PIN 46 CAN BE LEFT FLOATING IF EXTERNAL INDUCTOR VCO IS NOT USED.

NOTES

1. PINS [13:18], PINS [20:21], AND PIN 23 ARE TEST PINS AND ARE NOT USED IN NORMAL OPERATION.

Figure 57. Typical Application Circuit (Regulator Capacitors and Power Supply Decoupling Not Shown)

Rev. 0 | Page 45 of 64

ADF7021-N

SERIAL INTERFACE

The serial interface allows the user to program the 16-/32-bit

registers using a 3-wire interface (SCLK, SDATA, and SLE).

It consists of a level shifter, 32-bit shift register, and 16 latches.

Signals should be CMOS compatible. The serial interface is

powered by the regulator, and, therefore, is inactive when CE is low.

AFC Readback

The AFC readback is valid only during the reception of FSK

signals with either the linear or correlator demodulator active.

The AFC readback value is formatted as a signed 16-bit integer

comprising Bit RV1 to Bit RV16 and is scaled according to the

following formula:

Data is clocked into the register, MSB first, on the rising edge of

each clock (SCLK). Data is transferred to one of 16 latches on the

rising edge of SLE. The destination latch is determined by the

value of the four control bits (C4 to C1); these are the bottom

4 LSBs, DB3 to DB0, as shown in Figure 2. Data can also be read

back on the SREAD pin.

FREQ RB [Hz] = (AFC_READBACK ꢁ DEMOD CLK)/2¹⁸

In the absence of frequency errors, FREQ RB is equal to the IF

frequency of 100 kHz. Note that, for the AFC readback to yield

a valid result, the downconverted input signal must not fall outside

the bandwidth of the analog IF filter. At low input signal levels,

the variation in the readback value can be improved by averaging.

READBACK FORMAT

The readback operation is initiated by writing a valid control

word to the readback register and enabling the READBACK bit

(R7_DB8 = 1). The readback can begin after the control word

has been latched with the SLE signal. SLE must be kept high

while the data is being read out. Each active edge at the SCLK

pin successively clocks the readback word out at the SREAD

pin, as shown in Figure 58, starting with the MSB first. The data

appearing at the first clock cycle following the latch operation

must be ignored. An extra clock cycle is needed after the 16^th

readback bit to return the SREAD pin to tristate. Therefore, 18

total clock cycles are needed for each read back. After the 18^th

clock cycle, SLE should be brought low.

RSSI Readback

The format of the readback word is shown in Figure 58. It

comprises the RSSI-level information (Bit RV1 to Bit RV7), the

current filter gain (FG1, FG2), and the current LNA gain (LG1,

LG2) setting. The filter and LNA gain are coded in accordance

with the definitions in the Register 9—AGC Register section. For

signal levels below −100 dBm, averaging the measured RSSI values

improves accuracy. The input power can be calculated from the

RSSI readback value as outlined in the RSSI/AGC section.

READBACK MODE

READBACK VALUE

DB8

DB7

RV8

FG1

DB6

RV7

DB5

RV6

DB4

RV5

DB3

RV4

DB2

RV3

DB1

RV2

DB0

RV1

DB15 DB14 DB13 DB12 DB11 DB10 DB9

AFC READBACK

RSSI READBACK

RV16 RV15 RV14 RV13 RV12 RV11 RV10 RV9

X

LG2

X

LG1

X

FG2

X

BATTERY VOLTAGE/ADCIN/

TEMP. SENSOR READBACK

X

RV7

RV6

RV5

RV4

RV3

RV2

RV1

SILICON REVISION

RV16 RV15 RV14 RV13 RV12 RV11 RV10 RV9

RV8

FILTER CAL READBACK

0

Figure 58. Readback Value Table

Rev. 0 | Page 46 of 64

ADF7021-N

Battery Voltage/ADCIN/Temperature Sensor Readback

Filter Bandwidth Calibration Readback

The battery voltage is measured at Pin VDD4. The readback

information is contained in Bit RV1 to Bit RV7. This also

applies to the readback of the voltage at the ADCIN pin and the

temperature sensor. From the readback information, the battery

or ADCIN voltage can be determined using

The filter calibration readback word is contained in Bit RV1 to

Bit RV8 (see Figure 58). This readback can be used for manual

filter adjust, thereby avoiding the need to do an IF filter

calibration in some instances. The manual adjust value is

programmed by R5_DB[14:19]. To calculate the manual adjust

based on a filter calibration readback, use the following formula:

V

_BATTERY= (BATTERY VOLTAGE READBACK)/21.1

_ADCIN= (ADCIN VOLTAGE READBACK)/42.1

IF_FILTER_ADJUST = FILTER_CAL_READBACK − 128

The result should be programmed into R5_DB[14:19] as outlined

in the Register 5—IF Filter Setup Register section.

The temperature can be calculated using

Temp [ꢀC] = −40 + (68.4 − TEMP READBACK) ꢁ 9.32

Silicon Revision Readback

The silicon revision readback word is valid without setting any

other registers. The silicon revision word is coded with four

quartets in BCD format. The product code (PC) is coded with

three quartets extending from Bit RV5 to Bit RV16. The revision

code (RC) is coded with one quartet extending from Bit RV1 to

Bit RV4. The product code for the ADF7021-N should read

back as PC = 0x211. The current revision code should read as

RC = 0x1.

Rev. 0 | Page 47 of 64

ADF7021-N

SPI Mode

INTERFACING TO A MICROCONTROLLER/DSP

In SPI mode, the TxRxCLK pin is configured to input transmit

data in transmit mode. In receive mode, the receive data is available

on the TxRxDATA pin. The data clock in both transmit and receive

modes is available on the CLKOUT pin. In transmit mode, data is

clocked into the ADF7021-N on the positive edge of CLKOUT. In

receive mode, the TxRxDATA data pin should be sampled by

the microcontroller on the positive edge of the CLKOUT.

Standard Transmit/Receive Data Interface

The standard transmit/receive signal and configuration interface

to a microcontroller is shown in Figure 59. In transmit mode,

the ADF7021-N provides the data clock on the TxRxCLK pin,

and the TxRxDATA pin is used as the data input. The transmit

data is clocked into the ADF7021-N on the rising edge of

TxRxCLK.

MICROCONTROLLER

ADuC84x

ADF7021-N

TxRxCLK

MISO

TxRxDATA

CLKOUT

MOSI

SCLK

SPI

MOSI

SCLOCK

SS

TxRxCLK

CE

P3.7

CE

SWD

SREAD

SLE

P3.2/INT0

P2.4

SWD

SREAD

SLE

GPIO

P2.5

SDATA

SCLK

GPIO

P2.6

P2.7

SDATA

SCLK

Figure 61. ADF7021-N (SPI Mode) to Microcontroller Interface

Figure 59. ADuC84x to ADF7021-N Connection Diagram

To enable SPI interface mode, set R0_DB28 high and set

R15_DB[17:19] to 0x7. Figure 8 and Figure 9 show the relevant

timing diagrams for SPI mode, while Figure 61 shows the

recommended interface to a microcontroller using the SPI

mode of the ADF7021-N.

In receive mode, the ADF7021-N provides the synchronized

data clock on the TxRxCLK pin. The receive data is available on

the TxRxDATA pin. The rising edge of TxRxCLK should be

used to clock the receive data into the microcontroller. Refer to

Figure 4 and Figure 5 for the relevant timing diagrams.

ADSP-BF533 interface

In 4FSK transmit mode, the MSB of the transmit symbol is

clocked into the ADF7021-N on the first rising edge of the data

clock from the TxRxCLK pin. In 4FSK receive mode, the MSB

of the first payload symbol is clocked out on the first negative

edge of the data clock after the SWD and should be clocked into

the microcontroller on the following rising edge. Refer to Figure 6

and Figure 7 for the relevant timing diagrams.

The suggested method of interfacing to the Blackfin® ADSP-

BF533 is given in Figure 62.

ADSP-BF533

ADF7021-N

SCLK

SCK

MOSI

MISO

SDATA

SREAD

SLE

PF5

RSCLK1

DT1PRI

DR1PRI

RFS1

TxRxCLK

TxRxDATA

UART Mode

In UART mode, the TxRxCLK pin is configured to input transmit

data in transmit mode. In receive mode, the receive data is available

on the TxRxDATA pin, thus providing an asynchronous data

interface. The UART mode can only be used with oversampled

2FSK. Figure 60 shows a possible interface to a microcontroller

using the UART mode of the ADF7021-N. To enable this UART

interface mode, set R0_DB28 high. Figure 8 and Figure 9 show

the relevant timing diagrams for UART mode.

SWD

CE

PF6

Figure 62. ADSP-BF533 to ADF7021-N Connection Diagram

MICROCONTROLLER

ADF7021-N

TxRxCLK

TxDATA

RxDATA

UART

TxRxDATA

CE

SWD

SREAD

SLE

GPIO

SDATA

SCLK

Figure 60. ADF7021-N (UART Mode) to

Asynchronous Microcontroller Interface

Rev. 0 | Page 48 of 64

ADF7021-N

REGISTER 0—N REGISTER

ADDRESS

MUXOUT

INTEGER_N

FRACTIONAL_N

BITS

FRACTIONAL_N

DIVIDE RATIO

TR1

Tx/Rx

M15 M14 M13 ...

M3

M2

M1

0

1

TRANSMIT

RECEIVE

0

.

1

0

.

1

0

.

1

...

0

.

1

0

1

.

0

1

0

1

0

.

0

1

0

1

0

1

2

.

U1

UART_MODE

0

1

DISABLED

ENABLED

32764

32765

32766

32767

M3

M2

M1

MUXOUT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

REGULATOR_READY (DEFAULT)

FILTER_CAL_COMPLETE

DIGITAL_LOCK_DETECT

RSSI_READY

Tx_Rx

LOGIC_ZERO

TRISTATE

LOGIC_ONE

INTEGER_N

N8

N7

N6

N5

N4

N3

N2

N1

DIVIDE RATIO

0

.

0

.

0

.

1

.

0

1

.

1

0

.

1

0

.

1

0

.

23

24

.

1

0

1

253

1

0

1

254

255

Figure 63. Register 0—N Register Map

•

The RF output frequency is calculated by the following:

For the direct output

•

FILTER_CAL_ COMPLETE in the MUXOUT map in

Figure 63 indicates when a coarse or coarse plus fine

IF filter calibration has finished. DIGITAL_

LOCK_DETECT indicates when the PLL has locked.

RSSI_READY indicates that the RSSI signal has settled

and an RSSI readback can be performed.

Fractional _ N

⎛

⎝

⎞

⎟

⎠

RF_OUT= PFD× Integer _ N +

⎜

2¹⁵

For the RF_DIVIDE_BY_2 (R1_DB18) selected

•

Tx_Rx gives the status of DB27 in this register, which

can be used to control an external Tx/Rx switch.

Fractional _ N

⎛

⎝

⎞

⎟

⎠

RF_OUT= PFD×0.5× Integer _ N +

⎜

2¹⁵

•

In UART/SPI mode, the TxRxCLK pin is used to input the

Tx data. The Rx Data is available on the TxRxDATA pin.

Rev. 0 | Page 49 of 64

ADF7021-N

REGISTER 1—VCO/OSCILLATOR REGISTER

XTAL_

BIAS

ADDRESS

BITS

CLKOUT_

DIVIDE

R_COUNTER

VCO_BIAS

RF R_COUNTER

R3 R2 R1 DIVIDE RATIO

VCO CENTER

FREQ ADJUST

RF_DIVIDE_BY_2

RFD1

0

.

0

1

.

1

0

.

1

2

.

VA2

VA1

0

1

OFF

ON

0

1

0

1

0

1

NOMINAL

VCO ADJUST UP 1

VCO ADJUST UP 2

VCO ADJUST UP 3

.

1

7

VCO_BIAS

CURRENT

0.25mA

VB4

VB3 VB2 VB1

CLKOUT_

DIVIDE RATIO

OFF

0

.

0

.

0

1

.

1

0

.

CL4

CL3

CL2

CL1

0.5mA

0

.

0

.

0

1

.

0

1

0

.

2

4

.

1

3.75mA

LOOP

CONDITION

.

VE1

.

0

1

VCO OFF

VCO ON

30

1

VCL1

VCO_INDUCTOR

XTAL_

DOUBLER

0

1

INTERNAL L VCO

EXTERNAL L VCO

D1

0

1

DISABLE

ENABLED

I

(mA)

CP

XOSC_ENABLE

X1

0

1

CP1

RSET

CP2

3.6kΩ

0.3

OFF

ON

0

1

0

1

0

1

0.9

XTAL_

BIAS

1.5

XB2 XB1

2.1

0

1

0

1

0

1

20µA

25µA

30µA

35µA

Figure 64. Register 1—VCO/Oscillator Register Map

•

The R_COUNTER and XTAL_DOUBLER relationship is

as follows:

•

The VCO_BIAS bits should be set according to Table 9.

The VCO_ADJUST bits adjust the center of the VCO

operating band. Each bit typically adjusts the VCO band

up by 1% of the RF operating frequency (0.5% if

RF_DIVIDE_BY_2 is enabled).

XTAL

If XTAL_DOUBLER = 0,

PFD =

R _COUNTER

XTAL × 2

R _COUNTER

If XTAL_DOUBLER =1,

PFD =

•

Setting VCO_INDUCTOR to external allows the use of the

external inductor VCO, which gives RF operating

frequencies of 80 MHz to 650 MHz. If the internal

inductor VCO is being used for operation, set this bit low.

•

CLOCKOUT_DIVIDE is a divided-down and inverted

version of the XTAL and is available on Pin 36 (CLKOUT).

Set XOSC_ENABLE high when using an external crystal.

If using an external oscillator (such as TCXO) with CMOS-

level outputs into Pin OSC2, set XOSC_ENABLE low. If

using an external oscillator with a 0.8 V p-p clipped sine

wave output into Pin OSC1, set XOSC_ENABLE high.

Rev. 0 | Page 50 of 64

ADF7021-N

REGISTER 2—TRANSMIT MODULATION REGISTER

TxDATA_

INVERT

MODULATION_

SCHEME

ADDRESS

BITS

Tx_FREQUENCY_DEVIATION

POWER_AMPLIFIER

PA_BIAS PA_RAMP

PE1 PA_ENABLED

OFF

ON

PA2 PA1 PA_BIAS

0

1

0

1

0

1

0

1

5µA

7µA

9µA

11µA

DI2 DI1 TxDATA_INVERT

PR3 PR2 PR1 PA_RAMP RATE

0

1

0

1

0

1

NORMAL

INVERT CLK

INVERT DATA

INV CLK AND DATA

0

1

0

1

0

1

0

1

0

1

0

1

0

1

NO RAMP

256 CODES/BIT

128 CODES/BIT

64 CODES/BIT

32 CODES/BIT

16 CODES/BIT

8 CODES/BIT

4 CODES/BIT

f_DEV

TFD9 ... TFD3 TFD2 TFD1

0

.

...

0

.

0

1

.

0

1

0

1

.

0

1

2

3

S3

S2

S1

MODULATION_SCHEME

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2FSK

GAUSSIAN 2FSK

3FSK

.

1

511

4FSK

OVERSAMPLED 2FSK

RAISED COSINE 2FSK

RAISED COSINE

3FSK

4FSK

POWER_

NRC1 R-COSINE_ALPHA

P6

.

AMPLIFIER

P2

P1

0.5 (Default)

0.7

0

1

0

.

0

1

.

0

1

0

1

.

0 (PA OFF)

1 (–16.0 dBm)

2

3

.

1

.

1

63 (13 dBm)

Figure 65. Register 2—Transmit Modulation Register Map

•

The 2FSK/3FSK/4FSK frequency deviation is expressed by

the following:

•

In the case of 4FSK, there are tones at 3 ꢁ the frequency

deviation and at 1 ꢁ the deviation.

Direct output

The power amplifier (PA) ramps at the programmed rate

(R2_DB[8:10]) until it reaches its programmed level

(R2_DB[13:18]). If the PA is enabled/disabled by the

PA_ENABLE bit (R2_DB7), it ramps up and down. If it is

enabled/disabled by the Tx/Rx bit (R0_DB27), it ramps up

and turns hard off.

Frequency Deviation [Hz] =

Tx_FREQUENCY_DEVIATION ×PFD

2¹⁶

With RF_DIVIDE_BY_2 (R1_DB18) enabled

Frequency Deviation [Hz] =

•

R-COSINE_ALPHA sets the roll-off factor (alpha) of the

raised cosine data filter to either 0.5 or 0.7. The alpha is set

to 0.5 by default, but the raised cosine filter bandwidth can

be increased to provide less aggressive data filtering by

using an alpha of 0.7.

Tx_FREQUENCY_DEVIATION ×PFD

0.5×

2¹⁶

where Tx_FREQUENCY_DEVIATION is set by

R2_DB[19:27] and PFD is the PFD frequency.

Rev. 0 | Page 51 of 64

ADF7021-N

REGISTER 3—TRANSMIT/RECEIVE CLOCK REGISTER

DEMOD_CLK_

DIVIDE

ADDRESS

BITS

AGC_CLK_DIVIDE

SEQ_CLK_DIVIDE

CDR_CLK_DIVIDE

SK8 SK7 ...

...

SK3 SK2 SK1 SEQ_CLK_DIVIDE

BK2 BK1 BBOS_CLK_DIVIDE

0

.

0

.

0

.

0

1

.

1

0

.

1

2

.

0

1

0

1

4

...

0

1

8

16

32

1

0

1

254

255

OK4 OK3 OK2 OK1 DEMOD_CLK_DIVIDE

GD6

GD5

GD4

GD3

GD2

GD1 AGC_CLK_DIVIDE

0

INVALID

0

...

1

0

...

1

0

...

1

...

1

...

15

0

...

1

0

...

1

0

...

1

0

...

1

0

...

1

0

1

...

1

INVALID

1

...

63

FS8

FS7

...

FS3

FS2

FS1 CDR_CLK_ DIVIDE

0

.

1

0

.

1

...

0

.

1

0

1

.

1

0

.

0

1

2

.

254

255

Figure 66. Register 3—Transmit/Receive Clock Register Map

•

Baseband offset clock frequency (BBOS CLK) must be

greater than 1 MHz and less than 2 MHz, where

•

The sequencer clock (SEQ CLK) supplies the clock to the

digital receive block. It should be as close to 100 kHz as

possible.

XTAL

BBOS _CLK _ DIVIDE

BBOS CLK =

XTAL

SEQ _ CLK _ DIVIDE

SEQ CLK =

Set the demodulator clock (DEMOD CLK) such that

2 MHz ≤ DEMOD CLK ≤ 15 MHz, where

•

The time allowed for each AGC step to settle is determined

by the AGC update rate. It should be set close to 8 kHz.

XTAL

DEMOD CLK =

SEQ CLK

AGC Update Rate [Hz] =

DEMOD _CLK _ DIVIDE

AGC _ CLK _ DIVIDE

For 2FSK/3FSK, the data/clock recovery frequency (CDR

CLK) needs to be within 2% of (32 ꢁ data rate). For 4FSK,

the CDR CLK needs to be within 2% of (32 ꢁ symbol rate).

DEMOD CLK

CDR CLK =

CDR _ CLK _ DIVIDE

Rev. 0 | Page 52 of 64

ADF7021-N

REGISTER 4—DEMODULATOR SETUP REGISTER

Rx_

INVERT

DEMOD_

SCHEME

ADDRESS

BITS

POST_DEMOD_BW

DISCRIMINATOR_BW

IF_FILTER _

BW

DP1

DOT_PRODUCT

IFB2 IFB1

0

1

CROSS_PRODUCT

DOT_PRODUCTD

0

1

0

1

0

1

9 kHz

13.5 kHz

18.5 kHz

INVALID

RI2 RI1

Rx_INVERT

0

1

0

1

0

1

NORMAL

INVERT CLK

INVERT DATA

INVERT CLK/DATA

DEMOD_SCHEME

DS3 DS2 DS1

POST_DEMOD_

BW

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2FSK LINEAR DEMODULATOR

2FSK CORRELATOR DEMODULATOR

3FSK DEMOD

4FSK DEMOD

RESERVED

DW10 .

DW6 DW5 DW4 DW3 DW2 DW1

0

.

0

.

0

.

0

.

0

.

0

1

.

1

0

.

1

2

.

1

.

1

.

1

.

1

.

1

.

1

.

1

1023

TD10 .

TD6 TD5 TD4 TD3 TD2 TD1

DISCRIMINATOR_BW

0

.

0

.

0

.

0

.

0

.

0

1

.

1

0

.

1

2

.

1

.

0

.

1

.

0

.

1

.

0

.

0

660

Figure 67. Register 4—Demodulator Setup Register Map

where:

•

To solve for DISCRIMINATOR_BW, use the following

equation:

Round is rounded to the nearest integer.

Round_4FSKis rounded to the nearest of the following integers:

32, 31, 28, 27, 24, 23, 20, 19, 16, 15, 12, 11, 8, 7, 4, 3.

DEMOD CLK × K

DISCRIMINATOR_BW =

400 ×10³

f

DEV is the transmit frequency deviation in Hz. For 4FSK,

DEV is the frequency deviation used for the 1 symbols

where the maximum value = 660.

(that is, the inner frequency deviations).

•

For 2FSK,

•

Rx_INVERT (R4_DB[8:9]) and DOT_PRODUCT

(R4_DB7) need to be set as outlined in Table 17 and

Table 18.

3

⎛

⎜

⎝

⎞

⎟

⎠

100 ×10

K = Round

For 3FSK,

K = Round

For 4FSK,

K = Round_4FSK

f_DEV

2¹¹×π × f_CUTOFF

POST_DEMOD_BW =

3

⎛

⎜

⎝

⎞

⎟

⎠

100×10

2× f_DEV

DEMOD CLK

where the cutoff frequency (fCUTOFF) of the post demod-

ulator filter should typically be 0.75 ꢁ the data rate in

2FSK. In 3FSK, it should be set equal to the data rate, while

in 4FSK, it should be set equal to 1.6 ꢁ symbol rate.

3

⎛

⎜

⎝

⎞

⎟

⎠

100×10

4× f_DEV

Rev. 0 | Page 53 of 64

ADF7021-N

REGISTER 5—IF FILTER SETUP REGISTER

IR_GAIN_

ADJUST_MAG

IR_PHASE_

ADJUST_MAG

ADDRESS

BITS

IF_FILTER_ADJUST

IF_FILTER_DIVIDER

CC1 IF_CAL_COARSE

0

1

NO CAL

DO CAL

IR PHASE

ADJUST

PM3 PM2 PM1 PM1

0

.

0

1

2

...

15

0

.

0

1

.

0

1

0

.

IF_FILTER_

IFD6 IFD5 IFD4 IFD3 IFD2 IFD1

DIVIDER

IFD9

.

0

.

0

.

0

.

0

.

0

.

0

1

.

1

0

.

1

2

.

1

.

1

.

PD1

IR_PHASE_ADJUST_DIRECTION

1

511

0

1

ADJUST I CH

ADJUST Q CH

IR_GAIN_

ADJUST_MAG

GM5 GM4 GM3 GM2 GM1

0

.

0

.

0

.

0

1

.

0

1

0

.

0

1

2

...

31

IFA6 IFA5

IFA2 IFA1 IF_FILTER_ADJUST

...

0

..

0

1

0

..

1

0

.

0

1

..

1

0

1

.

0

1

0

..

1

0

1

0

.

0

+1

+2

...

+31

0

–1

–2

...

1

GQ1 IR_GAIN_ADJUST_I/Q

0

1

ADJUST I CH

ADJUST Q CH

GA1 IR_GAIN_ADJUST_UP/DN

1

–31

1

0

1

GAIN

ATTENUATE

Figure 68. Register 5—IF Filter Setup Register Map

•

A coarse IF filter calibration is performed when the

IF_CAL_COARSE bit (R5_DB4) is set. If the IF_FINE_

CAL bit (R6_DB4) has been previously set, a fine IF filter

calibration is automatically performed after the coarse

calibration.

•

IF_FILTER_ADJUST allows the IF fine filter calibration

result to be programmed directly on subsequent receiver

power-ups, thereby saving on the need to redo a fine filter

calibration in some instances. Refer to the Filter Bandwidth

Calibration Readback section for information about using

the IF_FILTER_ ADJUST bits.

Set IF_FILTER_DIVIDER such that

•

R5_DB[20:31] are used for image rejection calibration. Refer

to the Image Rejection Calibration section for details on how

to program these parameters.

XTAL

= 50 kHz

IF _ FILTER _ DIVIDER

Rev. 0 | Page 54 of 64

ADF7021-N

REGISTER 6—IF FINE CAL SETUP REGISTER

ADDRESS

BITS

IF_CAL_DWELL_TIME

IF_CAL_UPPER_TONE_DIVIDE

IF_CAL_LOWER_TONE_DIVIDE

IRD1 IR_CAL_SOURCE ÷2

0

1

SOURCE ÷2 OFF

SOURCE ÷2 ON

IF_CAL_UPPER_

TONE_DIVIDE

FC1 IF_FINE_CAL

... UT3 UT2 UT1

UT8

UT7

0

1

DISABLED

ENABLED

0

1

.

1

0

1

.

0

.

0

.

...

0

.

1

2

3

.

IR_CAL_SOURCE_

IRC2 IRC1 DRIVE_LEVEL

0

1

0

1

0

1

OFF

.

LOW

MED

HIGH

0

1

...

1

127

IF_CAL_LOWER_

TONE_DIVIDE

LT7

...

LT3 LT2 LT1

LT8

0

.

0

1

.

1

0

1

.

0

.

0

.

...

1

2

3

.

IF_CAL_

DWELL_TIME

CD3 CD2 CD1

CD7

...

0

.

0

1

.

1

0

1

.

0

.

...

1

2

3

.

1

...

255

.

1

...

127

Figure 69. Register 6—IF Fine Cal Setup Register Map

•

A fine IF filter calibration is set by enabling the

IF_FINE_CAL Bit (R6_DB4). A fine calibration is then

carried out only when Register 5 is written to and R5_DB4

is set.

•

The IF tone calibration time is the amount of time that is

spent at an IF calibration tone. It is dependent on the

sequencer clock. For best practice, is recommended to have

the IF tone calibration time be at least 500 μs.

IF _ CAL _ DWELL _TIME

IF Tone Calibration Time =

Lower Tone Frequency (kHz) =

SEQ CLK

The total time for a fine IF filter calibration is

IF Tone Calibration Time ꢁ 10

XTAL

IF_CAL_LOWER_TONE_DIVIDE × 2

Upper Tone Frequency (kHz) =

•

R6_DB[28:30] control the internal source for the image

rejection (IR) calibration. The IR_CAL_SOURCE_

DRIVE_LEVEL bits (R6_DB[28:29]) set the drive strength

of the source, whereas the IR_CAL_SOURCE_÷2 bit

(R6_DB30) allows the frequency of the internal signal

source to be divided by 2.

XTAL

IF_CAL_UPPER_TONE_DIVIDE × 2

It is recommended to place the lower tone and upper tone

as outlined in Table 24.

Table 24. IF Filter Fine Calibration Tone Frequencies

IF Filter

Bandwidth

Lower Tone

Frequency

Upper Tone

Frequency

9 kHz

13.5 kHz

18.5 kHz

78.1 kHz

79.4 kHz

78.1 kHz

116.3 kHz

119 kHz

Rev. 0 | Page 55 of 64

ADF7021-N

REGISTER 7—READBACK SETUP REGISTER

READBACK_

SELECT

ADC_

MODE

CONTROL

BITS

DB1

DB0

DB7

RB2

DB8

RB3

DB6

RB1

DB5

AD2

DB4

AD1

DB3

DB2

C4 (0) C3 (1) C2 (1) C1 (1)

RB3 READBACK_SELECT

AD2 AD1 ADC_MODE

0

1

DISABLED

ENABLED

0

1

0

1

0

1

MEASURE RSSI

BATTERY VOLTAGE

TEMP SENSOR

TO EXTERNAL PIN

RB2 RB1 READBACK MODE

0

1

0

1

0

1

AFC WORD

ADC OUTPUT

FILTER CAL

SILICON REV

Figure 70. Register 7—Readback Setup Register Map

•

Readback of the measured RSSI value is valid only in Rx

mode. Readback of the battery voltage, temperature sensor, or

voltage at the external pin is not valid in Rx mode.

•

For AFC readback, use the following equations (see the

Readback Format section):

FREQ RB [Hz] = (AFC READBACK ꢁ DEMOD CLK)/2¹⁸

To read back the battery voltage, the temperature sensor, or

the voltage at the external pin in Tx mode, users should

first power up the ADC using R8_DB8 because it is turned

off by default in Tx mode to save power.

V

_BATTERY= BATTERY VOLTAGE READBACK/21.1

_ADCIN= ADCIN VOLTAGE READBACK/42.1

Temperature [ꢀC] = −40 + (68.4 − TEMP READBACK) ꢁ 9.32

Rev. 0 | Page 56 of 64

ADF7021-N

REGISTER 8—POWER-DOWN TEST REGISTER

CONTROL

BITS

Rx_RESET

DB10 DB9

LE1 PD6

DB1

DB2

DB0

DB7

PD4

DB15 DB14 DB13 DB12 DB11

DB8

PD5

DB6

PD3

DB5

DB4

PD1

DB3

PD7

SW1

C4 (1) C3 (0) C2 (0) C1 (0)

CR1

PD1 SYNTH_ENABLE

CR1 COUNTER_RESET

0

1

SYNTH OFF

SYNTH ON

0

1

NORMAL

RESET

CDR

RESET

DEMOD

RESET

PD3 LNA/MIXER_ENABLE

PD7 PA (Rx MODE)

0

1

LNA/MIXER OFF

LNA/MIXER ON

0

1

PA OFF

PA ON

PD4 FILTER_ENABLE

SW1 Tx/Rx SWITCH

0

1

FILTER OFF

FILTER ON

0

1

DEFAULT (ON)

OFF

PD5 ADC_ENABLE

LE1 LOG_AMP_ENABLE

0

1

ADC OFF

ADC ON

0

1

LOG AMP OFF

LOG AMP ON

PD6 DEMOD_ENABLE

0

1

DEMOD OFF

DEMOD ON

Figure 71. Register 8—Power-Down Test Register Map

•

It is not necessary to write to this register under normal

operating conditions.

•

For a combined LNA/PA matching network, R8_DB11

should always be set to 0, which enables the internal Tx/Rx

switch. This is the power-up default condition.

Rev. 0 | Page 57 of 64

ADF7021-N

REGISTER 9—AGC REGISTER

FILTER_

GAIN

LNA_

GAIN

AGC_

MODE

ADDRESS

BITS

AGC_HIGH_THRESHOLD

AGC_LOW_THRESHOLD

ML1 MIXER_LINEARITY

AGC_LOW_

THRESHOLD

AGC_MODE

GL7 GL6 GL5 GL4 GL3 GL2 GL1

0

1

DEFAULT

HIGH

0

1

2

3

AUTO AGC

0

.

0

.

0

.

0

.

0

1

.

0

1

0

.

1

0

1

0

.

1

2

3

4

.

MANUAL AGC

FREEZE AGC

RESERVED

LI2 LI1 LNA_BIAS

0

800µA (DEFAULT)

.

1

0

1

0

1

61

62

63

LG1 LNA_MODE

0

1

DEFAULT

REDUCED GAIN

AGC_HIGH_

THRESHOLD

GH7 GH6 GH5 GH4 GH3 GH2 GH1

FI1 FILTER_CURRENT

0

.

1

0

.

0

.

0

1

0

.

1

0

1

.

1

0

1

0

.

1

0

1

0

1

0

.

0

1

0

1

2

3

4

.

78

79

80

0

1

LOW

HIGH

FG2 FG1 FILTER_GAIN

0

1

0

1

0

1

8

24

72

INVALID

LG2 LG1 LNA_GAIN

0

1

0

1

0

1

3

10

30

INVALID

Figure 72. Register 9—AGC Register Map

•

It is necessary to program this register only if AGC

settings, other than the defaults, are required.

•

AGC high and low settings must be more than 30 apart to

ensure correct operation.

In receive mode, AGC is set to automatic AGC by default

on power-up. The default thresholds are AGC_ LOW_

THRESHOLD = 30 and AGC_HIGH_ THRESHOLD = 70.

See the RSSI/AGC section for details.

An LNA gain of 30 is available only if LNA_MODE

(R9_DB25) is set to 0.

Rev. 0 | Page 58 of 64

ADF7021-N

REGISTER 10—AFC REGISTER

ADDRESS

BITS

MAX_AFC_RANGE

KP

KI

AFC_SCALING_FACTOR

AE1 AFC_EN

KP3 KP2 KP1 KP

KI4 KI3 KI2 KI1 KI

0

.

0

.

0

.

0

.

0

1

.

2^0

2^1

...

0

.

0

1

.

2^0

2^1

...

0

1

OFF

AFC ON

1

2^7

1

2^15

MAX_AFC_

MA3 MA2 MA1

RANGE

AFC_SCALING_

FACTOR

...

MA8

...

M3

M2

M1

M12

0

.

1

...

0

1

0

.

0

1

0

1

.

1

0

1

0

.

1

0

1

2

3

4

.

253

254

255

0

.

1

...

0

1

.

1

0

1

0

.

0

1

0

1

0

.

1

0

1

2

3

4

.

4093

4094

4095

Figure 73. Register 10—AFC Register Map

•

The AFC_SCALING_FACTOR can be expressed as

•

When the RF_DIVIDE_BY_2 (R1_DB18) is enabled, the

programmed AFC correction range is halved. The user

accounts for this halving by doubling the programmed

MAX_AFC_RANGE value.

24

⎛

⎞

2

×500

⎜

⎟

AFC _ SCALING_ FACTOR = Round

XTAL

⎝

⎠

•

The settings for KI and KP affect the AFC settling time and

AFC accuracy. The allowable range of each parameter is

KI > 6 and KP < 7.

•

Signals that are within the AFC pull-in range but outside

the IF filter bandwidth are attenuated by the IF filter. As a

result, the signal can be below the sensitivity point of the

receiver and, therefore, not detectable by the AFC.

The recommended settings to give optimal AFC

performance are KI = 11 and KP = 4. To trade off between

AFC settling time and AFC accuracy, the KI and KP

parameters can be adjusted from the recommended settings

(staying within the allowable range) such that

AFC Correction Range = MAX_AFC_RANGE ꢁ 500 Hz

Rev. 0 | Page 59 of 64

ADF7021-N

REGISTER 11—SYNC WORD DETECT REGISTER

CONTROL

BITS

SYNC_BYTE_SEQUENCE

SYNC_BYTE_

PL2 PL1 LENGTH

0

1

0

1

0

1

12 BITS

16 BITS

20 BITS

24 BITS

MATCHING_

MT2 MT1 TOLERANCE

0

1

0

1

0

1

ACCEPT 0 ERRORS

ACCEPT 1 ERROR

ACCEPT 2 ERRORS

ACCEPT 3 ERRORS

Figure 74. Register 11—Sync Word Detect Register Map

REGISTER 12—SWD/THRESHOLD SETUP REGISTER

CONTROL

BITS

DATA_PACKET_LENGTH

0

1

...

INVALID

1 BYTE

...

255 255 BYTES

SWD_MODE

0

1

2

SWD PIN LOW

SWD PIN HIGH AFTER NEXT SYNCWORD

FOR DATA PACKET LENGTH NUMBER OF BYTES

INTERRUPT PIN HIGH

3

LOCK_THRESHOLD_MODE

0

1

2

THRESHOLD FREE RUNNING

LOCK THRESHOLD AFTER NEXT SYNCWORD

FOR DATA PACKET LENGTH NUMBER OF BYTES

LOCK THRESHOLD

3

Figure 75. Register 12—SWD/Threshold Setup Register Map

Lock threshold locks the threshold of the envelope detector. This has the effect of locking the slicer in linear demodulation and locking

the AFC and AGC loops when using linear or correlator demodulation.

Rev. 0 | Page 60 of 64

ADF7021-N

REGISTER 13—3FSK/4FSK DEMOD REGISTER

Refer to the Receiver Setup section for information about programming these settings.

3FSK_PREAMBLE_

TIME_VALIDATE

3FSK/4FSK_

SLICER_THRESHOLD

CONTROL

BITS

3FSK_CDR_THRESHOLD

3FSK_VITERBI_

DETECTOR

VD1

3FSK_CDR_

VT3 VT2 VT1

VT7

...

THRESHOLD

0

1

DISABLED

ENABLED

0

.

0

1

.

0

.

...

0

1

0

1

.

OFF

1

2

3

.

PHASE_

CORRECTION

DISABLED

ENABLED

PC1

0

1

.

1

...

127

SLICER

ST3 ST2 ST1

ST7

...

THRESHOLD

VITERBI_PATH _

MEMORY

0

.

0

1

.

0

.

...

0

1

0

1

.

OFF

VM2 VM1

1

2

3

.

0

1

0

1

0

1

4 BITS

6 BITS

8 BITS

32 BITS

.

1

...

127

3FSK_PREMABLE_

TIME_VALIDATE

PTV4 PTV3 PTV2 PTV1

0

.

0

.

0

1

.

0

1

0

1

.

0

1

2

3

.

1

15

Figure 76. Register 13—3FSK/4FSK Demod Register Map

Rev. 0 | Page 61 of 64

ADF7021-N

REGISTER 14—TEST DAC REGISTER

ADDRESS

BITS

TEST_DAC_GAIN

TEST_DAC_OFFSET

ED_LEAK_FACTOR

LEAKAGE =

PULSE_EXTENSION

TEST_DAC_GAIN

0

1

2

3

NO PULSE EXTENSION

0

NO GAIN

0

1

2

3

4

5

6

7

2^–8

2^–9

EXTENDED BY 1

EXTENDED BY 2

EXTENDED BY 3

1

...

15

× 2^1

...

× 2^15

2^–10

2^–11

2^–12

2^–13

2^–14

2^–15

ED_PEAK_RESPONSE

0

FULL RESPONSE TO PEAK

0.5 RESPONSE TO PEAK

0.25 RESPONSE TO PEAK

0.125 RESPONSE TO PEAK

1

2

3

Figure 77. Register 14—Test DAC Register Map

The demodulator tuning parameters, PULSE_EXTENSION,

ED_LEAK_FACTOR, and ED_PEAK_RESPONSE, can be

enabled only by setting R15_DB[4:7] to 0x9.

While the correlators and filters are clocked by DEMOD CLK,

CDR CLK clocks the test DAC. Note that although the test

DAC functions in regular user mode, the best performance is

achieved when the CDR CLK is increased to or above the

frequency of DEMOD CLK. The CDR block does not function

when this condition exists.

Using the Test DAC to Implement Analog FM DEMOD

and Measuring SNR

For detailed information about using the test DAC, see

Application Note AN-852.

Programming Register 14 enables the test DAC. Both the

linear and correlator/demodulator outputs can be multiplexed

into the DAC.

The test DAC allows the post demodulator filter out for both

linear and correlator demodulators to be viewed externally. The

test DAC also takes the 16-bit filter output and converts it to a

high frequency, single-bit output using a second-order, error

feedback Σ-Δ converter. The output can be viewed on the SWD

pin. This signal, when filtered appropriately, can then be used to

do the following:

Register 14 allows a fixed offset term to be removed from the

signal (to remove the IF component in the ddt case). It also has

a signal gain term to allow the usage of the maximum dynamic

range of the DAC.

•

Monitor the signals at the FSK post demodulator filter

output. This allows the demodulator output SNR to be

measured. Eye diagrams of the received bit stream can also

be constructed to measure the received signal quality.

•

Provide analog FM demodulation.

Rev. 0 | Page 62 of 64

ADF7021-N

REGISTER 15—TEST MODE REGISTER

ANALOG_TEST_

MODES

PLL_TEST_

MODES

Σ-Δ_TEST_

MODES

Tx_TEST_

MODES

Rx_TEST_

MODES

ADDRESS

BITS

CLK_MUX

CAL_OVERRIDE

0

1

2

3

AUTO CAL

OVERRIDE GAIN

OVERRIDE BW

PFD/CP_TEST_MODES

0

1

2

3

4

5

6

7

DEFAULT, NO BLEED

(+VE) CONSTANT BLEED

(–VE) CONSTANT BLEED

(–VE) PULSED BLEED

(–VE) PULSE BLD, DELAY UP?

CP PUMP UP

OVERRIDE BW AND GAIN

REG1_PD

0

1

NORMAL

PWR DWN

CP TRI-STATE

CP PUMP DN

FORCE_LD_HIGH

Σ-Δ_TEST_MODES

0

1

NORMAL

FORCE

0

1

2

3

4

5

6

7

DEFAULT, 3RD ORDER SD, NO DITHER

1ST ORDER SD

2ND ORDER SD

DITHER TO FIRST STAGE

DITHER TO SECOND STAGE

DITHER TO THIRD STAGE

DITHER × 8

ANALOG_TEST_MODES

0

1

2

3

4

5

6

7

8

9

BAND GAP VOLTGE

40µA CURRENT FROM REG4

FILTER I CHANNEL: STAGE 1

FILTER I CHANNEL: STAGE 2

FILTER I CHANNEL: STAGE 1

FILTER Q CHANNEL: STAGE 1

FILTER Q CHANNEL: STAGE 2

FILTER Q CHANNEL: STAGE 1

ADC REFERENCE VOLTAGE

BIAS CURRENT FROM RSSI 5µA

DITHER × 32

Tx_TEST_MODES

0

1

2

3

4

5

6

NORMAL OPERATION

Tx CARRIER ONLY

Tx +VE TONE ONLY

Tx –VE TONE ONLY

Tx "1010" PATTERN

Tx PN9 DATA, AT PROGRAMED RATE

Tx SYNC BYTE REPEATEDLY

10 FILTER COARSE CAL OSCILLATOR O/P

11 ANALOG RSSI I CHANNEL

12 OSET LOOP +VE FBACK V (I CH)

13 SUMMED O/P OF RSSI RECTIFIER+

14 SUMMED O/P OF RSSI RECTIFIER–

15 BIAS CURRENT FROM BB FILTER

Rx_TEST_MODES

0

1

2

3

4

5

6

7

8

9

NORMAL

SCLK, SDATA -> I, Q

REVERSE I,Q

I,Q TO TxRxCLK, TxRxDATA

3FSK SLICER ON TxRxDATA

CORRELATOR SLICER ON TxRxDATA

LINEAR SLICER ON RXDATA

SDATA TO CDR

ADDITIONAL FILTERING ON I, Q

ENABLE REG 14 DEMOD PARAMETERS

PLL_TEST_MODES

0

1

2

3

4

5

6

7

8

9

NORMAL OPERATION

R DIV

N DIV

RCNTR/2 ON MUXOUT

NCNTR/2 ON MUXOUT

ACNTR TO MUXOUT

PFD PUMP UP TO MUXOUT

PFD PUMP DN TO MUXOUT

SDATA TO MUXOUT (OR SREAD?)

10 POWER DOWN DDT AND ED IN T/4 MODE

11 ENVELOPE DETECTOR WATCHDOG DISABLED

12 RESERVED

13 PROHIBIT CALACTIVE

14 FORCE CALACTIVE

ANALOG LOCK DETECT ON MUXOUT

10 END OF COARSE CAL ON MUXOUT

11 END OF FINE CAL ON MUXOUT

12

FORCE NEW PRESCALER CONFIG.

FOR ALL N

15 ENABLE DEMOD DURING CAL

13 TEST MUX SELECTS DATA

14 LOCK DETECT PERCISION

15 RESERVED

CLK MUXES ON CLKOUT PIN

0

1

2

3

4

5

6

7

NORMAL, NO OUTPUT

DEMOD CLK

CDR CLK

SEQ CLK

BB OFFSET CLK

SIGMA DELTA CLK

ADC CLK

TxRxCLK

Figure 78. Register 15—Test Mode Register Map

•

Analog RSSI can be viewed on the Test_A pin by setting

ANALOG_TEST_MODES to 11.

Tx_TEST_MODES can be used to enable test modulation.

•

The CDR block can be bypassed by setting Rx_TEST_

MODES to 4, 5, or 6, depending on the demodulator used.

Rev. 0 | Page 63 of 64

ADF7021-N

OUTLINE DIMENSIONS

0.30

0.23

0.18

7.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

37

36

48

1

PIN 1

INDICATOR

EXPOSED

PAD

(BOTTOM VIEW)

4.25

4.10 SQ

3.95

TOP

VIEW

6.75

BSC SQ

0.50

0.40

0.30

25

24

12

13

0.25 MIN

5.50

REF

0.80 MAX

0.65 TYP

1.00

0.85

0.80

12° MAX

0.05 MAX

0.02 NOM

COPLANARITY

0.08

0.50 BSC

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2

Figure 79. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

7 mm × 7 mm Body, Very Thin Quad

(CP-48-3)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

−40°C to +85°C

Package Description

Package Option

CP-48-3

ADF7021-NBCPZ¹

48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Die on Film

ADF7021-NBCPZ-RL¹

ADF7021-NBCPZ-RL7¹

ADF7021-NDF

CP-48-3

EVAL-ADF70XXMBZ2¹

EVAL-ADF7021-NDBIZ¹

EVAL-ADF7021-NDBEZ¹

EVAL-ADF7021-NDBZ2¹

EVAL-ADF7021-NDBZ5¹

Evaluation Platform Mother Board

426 MHz to 429 MHz Daughter Board

860 MHz to 870 MHz Daughter Board

Matching Unpopulated Daughter Board

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D07246-0-2/08(0)

Rev. 0 | Page 64 of 64


型号：	EVAL-ADF7021-NDBZ51
厂家：	ADI
描述：	High Performance Narrow-Band Transceiver IC 高性能窄带收发器IC
文件：	总64页 (文件大小：2499K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EVAL-ADF7021-NDBZ51 [ADI]

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