OP17BIGZ [ADI]
IC OP-AMP, 3800 uV OFFSET-MAX, 26 MHz BAND WIDTH, CDIP8, CERDIP-8, Operational Amplifier;
| 型号： | OP17BIGZ |
| 厂家： | 
ADI |
| 描述： | IC OP-AMP, 3800 uV OFFSET-MAX, 26 MHz BAND WIDTH, CDIP8, CERDIP-8, Operational Amplifier 运算放大器 |
| 文件： | 总12页 (文件大小：431K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Precision JFET-Input
Operational Amplifiers
a
OP15/OP17
FEATURES
GENERAL DESCRIPTION
Significant Performance Advantages over LF155 and
LF157 Devices
The ADI-JFET input series of devices offer clear advantages over
industry-generic devices and are superior in both cost and perfor-
mance to many dielectrically-isolated and hybrid op amps. All devices
offer offset voltages as low as 0.5 mV with TCVOS guaranteed to
5 mV/∞C. A unique input bias cancellation circuit reduces the IB
by a factor 10 over conventional designs. In addition ADI specifies
IB and IOS with the devices warmed up and operating at 25∞C ambient.
Low Input Offset Voltages: 500 V Max
Low Input Offset Voltage Drift: 2.0 V/؇C
Minimum Slew Rate Guaranteed on All Models
Temperature-Compensated Input Bias Currents
Bias Current Specified Warmed-Up Over Temperature
Internal Compensation
Low Input Noise Current: 0.01 pA/÷Hz
High Common-Mode Rejection Ratio: 100 dB
Models with MIL-STD 883 Processing Available
These devices were designed to provide real precision performance
along with high speed. Although they can be nulled, the design
objective was to provide low offset-voltage without nulling. Systems
generally become more cost effective as the number of trim circuits
is decreased. ADI achieves this performance by use of an improved
bipolar compatible JFET process coupled with on chip, zener-zap
offset trimming.
OP15
156 Speed with 155 Dissipation: 80 mW Typ
Wide Bandwidth: 6 MHz
High Slew Rate: 13 V/s
Fast Settling to ±0.1%: 1,200 ns
T he OP15 provides an excellent combinations of high speed and
low input offset voltage. In addition, the OP15 offers the speed
of the 156A op amp with the power dissipation of a 155A. T he
combination of a low input offset voltage of 500 mV, slew rate of
13 V/ms, and settling time of 1,200 ns to 0.1% makes the OP15
an op amp of both precision and speed. T he additional features
of low supply current coupled with an input bias current makes
the OP15 ideal for a wide range of applications.
OP17
Highest Slew Rate: 60 V/s
Fastest Settling to ±0.1%: 600 ns
Highest Gain Bandwidth Product (AVCL = 5 Min): 30 MHz
Guaranteed Input Bias Current @ 125؇C
T he OP17 has a slew rate of 60 V/ms and is the best choice for
applications requiring high closed-loop gain with high speed. See
OP42 datasheet for unity gain applications and the OP215 datasheet
for a dual configuration of the OP15.
*R7, R8 ARE ELECTRONICALLY
ADJUSTED ON CHIP FOR
MINIMUM OFFSETVOLTAGE.
V+
J5
R8*
R7*
Q5
J8
NULL
NULL
Q16
Q6
Q7
R3
Q9
J6
Q19
Q24
Q8
R1
J11
NONINVERTING
INPUT
Q17
Q22
R13
J1
J2
R2
C2
Q2
–INV
INPUT
OUTPUT
Q1
Q10
J9
J10
Q3
Q4
Q12
Q23
R5
R6
3.6k⍀
Q13
Q11
Q14
Q20
Q25
3.6k⍀
R3
J4
J3
C1
7.4pF
Q21
Q16
Q15
R11
R4
V–
Figure 1. Simplified Schematic
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
OP15/OP17–SPECIFICATIONS
؇
(@ V = ؎15 V, T = 25 C, unless otherwise noted)
ELECTRICAL CHARACTERISTICS
S
A
OP15A, OP15E
OP17A, OP17E
OP15F
OP17F
Typ
OP15G
OP17G
Typ
Parameter
Symbol
Conditions
Min
Typ
Max
Min
Max
Min
Max Unit
Input Offset Voltage VOS
RS = 50 W
0.2
0.5
0.4
1.0
0.5
3.0
mV
Input Offset Current IOS
OP15
T J = 25∞C1
3
5
3
5
10
22
10
25
6
10
6
20
40
20
50
12
20
12
20
50
100
50
pA
pA
pA
pA
Device Operating
OP17
T J = 25∞C1
Device Operating
10
125
Input Bias Current
OP15
IB
T J = 25∞C1
±15
±18
±15
±20
±50
±30
±40
±30
±40
±100
±200
±100
±250
±60
±80
±60
±80
±200 pA
±400 pA
±200 pA
±500 pA
Device Operating
±110
±50
OP17
T J = 25∞C1
Device Operating
±130
Input Resistance
RIN
1012
1012
1012
W
Large-Signal
Voltage Gain
AVO
RL ≥ 2 kW
VO = ±10 V
100
240
75
220
50
200
V/mV
Output Voltage
Swing
VO
RL = 10 kW
RL = 2 kW
±12
±11
±13
±12.7
±12
±11
±13
±12.7
±12
±11
±13
±12.7
V
V
Supply Current
Slew Rate2
ISY
OP15
OP17
2.7
4.6
4.0
7.0
2.7
4.6
4.0
7.0
2.8
4.8
5.0
8.0
mA
mA
SR
AVCL = 1, OP15
AVCL = 5, OP17
10
45
13
60
7.5
35
11
50
5
25
9
40
V/ms
V/ms
Gain Bandwidth3
Product
GBW
CLBW
tS
OP15
OP17
4.0
20
6.0
30
3.5
15
5.7
28
3.0
11
5.4
26
MHz
MHz
Closed-Loop
Bandwidth
AVCL = 1, OP15
AVCL = 5, OP17
14
11
13
10
12
9
MHz
MHz
Settling T ime
OP15
T o 0.01%
T o 0.05%
T o 0.10%
T o 0.01%
T o 0.05%
T o 0.10%
4.5
1.5
1.2
1.5
0.7
0.6
4.5
1.5
1.2
1.5
0.7
0.6
4.7
1.6
1.3
1.6
0.8
0.7
ms
ms
ms
ms
ms
ms
OP17
Input Voltage Range IVR
±10.5
±10.5
±10.3
V
Common-Mode
Rejection Ratio
CMRR
VCM = ±10.5 V
VCM = ±10.3 V
86
100
10
86
100
10
dB
dB
82
96
10
Power Supply
Rejection Ratio
PSRR
en
VS = ±10 V to ±18 V
VS = ±10 V to ±18 V
51
51
mV/V
mV/V
80
Input Noise
Voltage Density
fO = 100 Hz
fO = 1 kHz
20
15
20
15
20
15
nV/÷Hz
nV/÷Hz
Input Noise
Current Density
in
fO = 100 Hz
fO = 1 kHz
0.01
0.01
0.01
0.01
0.01
0.01
pA/÷Hz
pA/÷Hz
Input Capacitance
NOT ES
CIN
3
3
3
pF
1Input bias current is specified for two different conditions. T he T J = 25∞C specification is with the junction at ambient temperature; the device operating specification
is with the device operating in a warmed-up condition at 25∞C ambient. T he warmed-up bias current value is correlated to the junction temperature value via the
curves of IB versus T J and IB versus T A. ADI has a bias current compensation circuit which gives improved bias current over the standard JFET input op amps. I B and
IOS are measured at VCM = 0.
2Settling time is defined here for a unity gain inverter connection using 2 kW resistors. It is the time required for the error voltage (the voltages at the inverting input pit
on the amplifier) to settle to within a specified percent of its final value from the time a 10 V step input is applied to the inverter. See settling time test circuit.
3Sample tested.
4Settling time is defined here for AV = –5 connection with RF = 2 kW. It is the time required for the error voltage (the voltage at the inverting input pin on the amplifier) to
settle to within 0.01% of its final value from the time a 2 V step input is applied to the inverter. See settling time test circuit.
–2–
REV. A
OP15/OP17
؇
؇
Electrical Characteristics (@ V = ±15 V, –55 C £ T £ 125 C, unless otherwise noted.)
S
A
Conditions
RS = 50 W
Parameter
Symbol
Min
Typ
Max
Units
Input Offset Voltage
VOS
0.4
0.9
mV
Average Input Offset Voltage Drift1
Without External T rim
With External T rim
T CVOS
T CVOS
2
2
5
mV/∞C
mV/∞C
RP = 100 W
Input Offset Current2
OP17
IOS
TJ = 125∞C
TA = 125∞C, device operating
0.6
1.0
4.0
8.5
nA
nA
Input Bias Current2
OP17
IB
TJ = 125∞C
TA = 125∞C, device operating
±1.2
±2.0
±5.0
±11
nA
nA
Input Voltage Range
IVR
±10.4
V
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage Swing
CMRR
PSRR
AVO
VCM = ±10.4 V
85
97
dB
VS = ±10 V to ±18 V
RL ≥ 2 kW, VO = ± 10 V
RL ≥ 10 kW
15
57
mV/V
V/mV
V
35
120
±13
VO
±12
NOT ES
1Sample tested.
2Input bias current is specified for two different conditions. T he T J = 25∞C specification is with the junction at ambient temperature; the device operating specification
is with the device operating in a warmed-up condition at 25∞C ambient. T he warmed-up bias current value is correlated to the junction temperature value via the
curves of IB versus T J and IB versus T A. ADI has a bias current compensation circuit which gives improved bias current over the standard JFET input op amps. I B and
IOS are measured at VCM = 0.
؇
؇
؇
؇
ELECTRICAL CHARACTERISTICS (@ V = ؎15 V, 0 C £ T £ 70 C for E and F grades, –40 C £ T £ 85 C for G grades
unless otherwise noted)
S
A
A
OP15E/OP17E
OP15F/OP17F
OP15G/OP17G
Parameter
Symbol
Conditions
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max Unit
Input Offset Voltage VOS
RS = 50 W
0.3
0.75
0.55
1.5
0.7
3.8
mV
Average Input Offset
Voltage Drift1
Without External Trim T CVOS
2
2
5
3
3
10
4
4
30
mV/∞C
mV/∞C
With External T rim
T CVOSn
RP = 100 W
T J = 70∞C
TA = 70∞C, Device Operating
T J = 70∞C
Input Offset Current2 IOS
OP15
0.04
0.06
0.04
0.07
0.30
0.55
0.30
0.70
0.06
0.08
0.06
0.10
0.45
0.80
0.45
1.1
0.08
0.10
0.08
0.15
0.85 nA
1.2 nA
0.85 nA
1.7 nA
OP17
TA = 70∞C, Device Operating
Input Bias Current2
OP15
IB
T J = 70∞C
TA = 70∞C, Device Operating
T J = 70∞C
±0.10 ±0.40
±0.13 ±0.75
±0.10 ±0.40
±0.15 ±0.90
±0.12 ±0.60
±0.16 ±1.1
±0.12 ±0.60
±0.20 ±1.4
±0.14 ±0.80 nA
±0.19 ±1.5 nA
±0.14 ±0.80 nA
±0.25 ±2.0 nA
OP17
TA = 70∞C, Device Operating
Input Voltage Range IVR
±10.4
±10.4
±10.25
V
Common-Mode
Rejection Ratio
CMRR
VCM = ±10.4 V
VCM = ±10.25 V
85
98
85
96
dB
dB
80
94
Power Supply
Rejection Ratio
PSRR
AVO
VO
VS = ±10 V to ±18 V
VS = ±10 V to ±15 V
13
57
13
57
mV/V
mV/V
20
100
Large Signal
Voltage Gain
RL ≥ 2 kW
VO = ±10 V
65
200
±13
50
180
±13
35
160
V/mV
Output Voltage
Swing
RL ≥ 10 kW
±12
±12
±12
±13
V
NOT ES
1Sample tested.
2Input bias current is specified for two different conditions. T he T J = 25∞C specification is with the junction at ambient temperature; the device operating specification
is with the device operating in a warmed-up condition at 25∞C ambient. T he warmed-up bias current value is correlated to the junction temperature value via the
curves of IB versus T J and IB versus T A. ADI has a bias current compensation circuit which gives improved bias current over the standard JFET input op amps. I B and
IOS are measured at VCM = 0.
–3–
REV. A
OP15/OP17–SPECIFICATIONS
ABSOLUTEMAXIMUMRATINGS1
Package Type
JA*
Unit
JC
Supply Voltage
All Devices Except C, G (Packaged)
and GR Grades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±22 V
C, G (Packaged) and GR Grades . . . . . . . . . . . . . . . . ±18 V
Operating T emperature
A Grade . . . . . . . . . . . . . . . . . . . . . . . . . . –55∞C to +125∞C
E, F Grades . . . . . . . . . . . . . . . . . . . . . . . . . . . 0∞C to 70∞C
G Grade . . . . . . . . . . . . . . . . . . . . . . . . . . . –40∞C to +85∞C
Maximum Junction T emperature . . . . . . . . . . . . . . . . . 150∞C
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .
All Devices Except C, G Grades . . . . . . . . . . . . . . . . ±40 V
C, G Grades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 V
Input Voltage2
8-Lead Hermetic DIP (Z)
8-Lead SO (S)
T O-99 (J)
148
158
150
16
43
18
∞C/W
∞C/W
∞C/W
*JA is specified for worst-case mounting conditions, i.e., JA is specified for device
in socket for CERDIP and PDIP packages; JA is specified for device soldered to
printed circuit board for SO packages.
+20V
10k⍀
All Devices Except C, G Grades . . . . . . . . . . . . . . . . ±20 V
C, G Grades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±16 V
Input Voltage
2
7
8
OP15E, OP15F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 V
OP15G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±16 V
OP17A, OP17E, OP17F . . . . . . . . . . . . . . . . . . . . . . ±20 V
OP17G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±16 V
3
+3V
4
10k⍀
300⍀
–20V
Output Short-Circuit Duration
Indefinite
Figure 2. Burn-In Circuit
Storage T emperature Range . . . . . . . . . . . . –65∞C to +150∞C
Lead T emperature Range (Soldering, 60 sec) . . . . . . . . 300∞C
NOT ES
*Absolute Maximum Ratings apply to packaged parts, unless otherwise noted.
8-LeadCERDIP
8-LeadSOIC
(S-Suffix)
8-Lead TO-99
(J-Suffix)
(Z-Suffix)
BAL
–IN
+IN
V–
NC
V+
BAL
–IN
+IN
V–
NC
V+
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
OUT
BAL
OUT
BAL
ORDERING GUIDE
Package Options
TA = 25∞C
VOS MAX
(mV)
Operating
Temperature
Range
TO-99
CERDIP
SOIC
0.5
1.0
3.0
OP17EJ
OP15EZ
OP17EZ
COM
COM
XIND
OP15FJ*
OP17FJ
OP15FZ*
OP17FZ
OP15GJ*
OP15GZ*
OP15GS*
OP17GZ
For military processed devices, please refer to the Standard Microcircuit Drawing
(SMD) available at www.dscc.dl.mil/programs/milspec/default.asp.
SMD Part Number
ADI Equivalent
5962-8954201GA*
5962-8954201PA*
5962-8954301GA*
5962-8954301PA*
OP15AJMDA
OP15AZMDA
OP16AJMDA
OP16AZMDA
*Not recommended for new designs. Obsolete April 2002.
–4–
REV. A
TypicalPerformanceCharacteristics –OP15/OP17
30
27
24
21
18
15
12
9
100
WARMED-UP IN FREE AIR
V
S
= 15V
V
S
=
15V
T
A
= 25؇C
80
60
–55؇C
+25؇C
a. UNDERCANCELLED I = +16pA @V
= 0
CM
B
b. PERFECTLY CANCELLED I = 0pA @V
= 0
B
CM
= 0
40 c. UNDERCANCELLED I = –16pA @V
B
CM
+125؇C
20
a
c
b
6
0
3
0
–20
–12 –10 –8 –6 –4 –2
100
1k
10k
100k
0
2
4
6
8
10 12
INPUT COMMON-MODEVOLTAGE –V
OUTPUT LOAD RESISTANCE –⍀
TPC 4. Input Bias Current vs. Common-Mode Voltage
TPC 1. Maximum Output Swing vs. Load Performance
1M
20
R
L
= 2k⍀
T
A
= 25؇C
500k
400k
–55؇C
15
10
5
300k
200k
25؇C
125؇C
100k
POSITIVE
FROM –55؇CTO –125؇C
CHANGE IN CMVR IS < 0.2V
NEGATIVE
10k
0
0
5
10
SUPPLYVOLTAGE –V
15
20
5
10
15
20
SUPPLYVOLTAGE –V
TPC 2. Common-Mode Input Voltage Range vs. Supply
Voltage
TPC 5. Open-Loop Voltage Gain vs. Supply Voltage
40
1k
T
V
= 25؇C
R
T
= 2k⍀
= 25؇C
A
L
=
15V
S
A
100Hz < f < 10kHz
10Hz < f < 10kHz FOR R > 4M⍀
a AMPLIFIER NOISE
b JOHNSON RESISTOR NOISE
c AMPLIFIER NOISE MEASURED
WITH SOURCE RESISTOR
100
10
S
30
20
10
0
c
b
1
0.1
0.01
a
0
5
10
15
20
100k
1M
10M
100M
1G
10G
SUPPLYVOLTAGE –V
SOURCE RESISTANCE –⍀
TPC 6. Output Voltage Swing vs. Supply Voltage
TPC 3. Voltage Noise vs. Source Resistance
–5–
REV. A
OP15/OP17
9
1n
100p
10p
V
S
= 15V
T
A
= 25؇C
7
I
= 4.0mA FOR MAX CURVES
2.5mA FOR TYP CURVES
SY
5
155A MAX
V
OS
3
OP15A MAX
1
155A TYP
TYPICAL DRIFT BAND
–1
–3
OP15 TYP
120 140
–5
10k
100k
R -TRIMMING POTENTIOMETERVALUE –⍀
1M
0
20
40
60
80
100
P
TIME AFTER POWER APPLIED – s
TPC 7. Nulled Offset Voltage Drift vs. Potentiometer Size
TPC 10. OP15 Bias Current vs. Time in Free Air
6
1n
V
S
= 15V
156A/157A MAX
4
2
156A/157A TYP
0
100p
OP17A MAX
V
S
=
15V
T
= 25؇C
A
–2
–4
–6
I
= 6.7mA FOR MAX CURVES
5.0mA FOR TYP CURVES
SY
OP17A TYP
10p
–50
–25
0
25
50
75
100
125
0
20
40
60
80
100
120
140
TEMPERATURE – ؇C
TIME AFTER POWER APPLIED – s
TPC 8. Offset Voltage Drift vs. Temperature of
Representative Units
TPC 11. OP17 Bias Current vs. Time in Free Air
100n
100n
V
S
= 15V
UNITS AREWARMED UP
155A MAX
10n
155A MAX
155ATYP
10n
1n
155ATYP
OP15A MAX
OP15A MAXP
OP15 TYP
1n
OP15A TYP
100p
100p
10p
10p
10
30
50
70
90
110
130
150
AMBIENTTEMPERATURE – ؇C
10
30
50
70
90
110
130
150
AMBIENTTEMPERATURE – ؇C
TPC 12. OP15 Input Bias Current vs. Ambient Temperature
(Units Warmed Up in Free Air)
TPC 9. Input Bias Current vs. Ambient Temperature
(Units Warmed Up in Free Air)
–6–
REV. A
OP15/OP17
100n
10n
1n
0
0
0
0
0
0
0
0
0
156A/157A MAX
156A/157A TYP
OP17A MAX
OP17A TYP
100p
10p
10
30
50
70
90
110
130
150
0
0
0
0
0
0
0
0
0
0
0
TIME – 500ns/DIV
AMBIENTTEMPERATURE – ؇C
TPC 13. OP17 Input Bias Current vs. Ambient Temperature
(Units Warmed Up in Free Air)
TPC 16. OP15 Large Signal Transient Response
0
0
0
0
0
0
0
0
0
3.5
3.0
–55؇C
2.5
25؇C
125؇C
2.0
1.5
0
5
10
15
20
0
0
0
0
0
0
0
0
0
0
0
TIME – 100ns/DIV
SUPPLYVOLTAGE –V
TPC 14. OP15 Supply Current vs. Supply Voltage
TPC 17. OP15 Small Signal Transient Response
5.5
10
V
T
= 15V
= 25؇C
S
10mV
5mV
1mV
A
A
V
= –1
5.0
4.5
5
0
–55؇C
25؇C
4.0
–5
125؇C
10mV
0.5
5mV
1mV
2.0
3.5
–10
0
5
10
15
20
0
1.0
1.5
2.5
SUPPLYVOLTAGE –V
SUPPLYVOLTAGE –V
TPC 15. OP17 Supply Current vs. Supply Voltage
TPC 18 OP15 Settling Time
–7–
REV. A
OP15/OP17
18
90
28
24
20
16
12
8
V
T
A
= 15V
= 25؇C
= 1
V
T
= 15V
= 25؇C
S
S
100
110
120
130
140
150
160
170
180
190
200
16
14
PHASE MARGIN = 86؇
A
A
V
12
10
8
6
A
V
> 10
4
2
0
–2
–4
–6
4
0
A
V
= 1
–8
–10
1M
100k
1M
10M
10M
100M
FREQUENCY – MHz
FREQUENCY – MHz
TPC 19. OP15 Closed-Loop Bandwidth and Phase vs.
Frequency
TPC 22. OP15 Maximum Output Swing vs. Frequency
70
28
V
= 15V
V
=
15V
S
S
A
= 1
60
50
40
30
20
10
0
24
20
16
12
8
V
BANDWIDTHVARIATION FROM
5V <V
<
20V IS < 5 %
S
NEGATIVE
CLOSED-LOOP
BANDWIDTH A = 1
V
GAIN BANDWIDTH
PRODUCT
POSITIVE
4
0
–50
–25
0
25
50
75
100
125
–50
–25
0
25
50
75
100
125
AMBIENTTEMPERATURE – ؇C
TEMPERATURE – ؇C
TPC 23. OP15 Slew Rate vs. Temperature
TPC 20. OP15 Bandwidth vs. Temperature
100
80
60
40
20
0
120
100
80
V
T
=
15V
V
T
=
15V
S
S
= 25؇C
= 25؇C
A
A
60
40
20
0
–20
1
10
100
1k
10k
100k
1M
10M 100M
1
10
100
1k
10k
100k
1M
10M 100M
FREQUENCY – Hz
FREQUENCY – Hz
TPC 24. OP15 Common-Mode Rejection Ratio vs. Frequency
TPC 21. OP15 Open-Loop Gain vs. Frequency
–8–
REV. A
OP15/OP17
120
100
80
60
40
20
0
0
0
0
0
0
0
0
0
0
T
= 25؇C
A
POSITIVE SUPPLY
NEGATIVE SUPPLY
10
100
1k
10k
100k
1M
10M
0
0
0
0
0
0
0
0
0
0
0
FREQUENCY – Hz
TIME – 200ns/DIV
TPC 25. OP15 Power Supply Rejection Ratio vs. Frequency
TPC 28. OP17 Large Signal Transient Response
100
0
0
0
0
0
0
0
0
0
V
T
=
15V
S
= 25؇C
A
A
= 100
V
10
A
= 10
V
A
V
= 1
1
0
1k
10k
100k
FREQUENCY – Hz
1M
10M
0
0
0
0
0
0
0
0
0
0
0
TIME – 100ns/DIV
TPC 26. OP15 Output Impedance vs. Frequency
TPC 29. OP17 Small Signal Transient Response
140
10
V
T
A
= 15V
= 25؇C
= –5
V
T
=
15V
S
S
= 25؇C
5mV
10mV
1mV
A
A
120
100
80
60
40
20
0
V
5
0
l/f CORNER FREQUENCY
–5
5mV
1mV
10mV
–10
1k
10k
100k
1M
10M
0
0.5
1.0
1.5
2.0
2.5
FREQUENCY – Hz
SUPPLYVOLTAGE –V
TPC 30. OP17 Settling Time
TPC 27. OP15 Voltage Noise Density vs. Frequency
–9–
REV. A
OP15/OP17
28
24
20
16
12
8
120
100
80
60
40
20
0
V
= 15V
= 25؇C
= 5
S
T
= 25؇C
A
T
A
A
V
POSITIVE
SUPPLY
NEGATIVE SUPPLY
4
0
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY – MHz
FREQUENCY – Hz
TPC 31. OP17 Maximum Output Swing vs. Frequency
TPC 34. OP17 Power Supply Rejection Ratio vs. Frequency
110
100
V
=
15V
V
T
= 15V
= 25؇C
NEGATIVE
POSITIVE
S
S
A
= 5
A
100
90
80
70
60
50
40
V
10
1.0
0
A
= 100
V
A
V
= 10
–50
–25
0
25
50
75
100
125
100k
FREQUENCY – Hz
1k
10k
1M
10M
AMBIENTTEMPERATURE – ؇C
TPC 32. OP17 Slew Rate vs. Temperature
TPC 35. OP17 Output Impedance vs. Frequency
100
80
60
40
20
0
140
V
=
15V
S
V
T
=
15V
S
T
A
= 25؇C
= 25؇C
A
120
100
80
60
40
20
0
l/f CORNER FREQUENCY
1
10
100
1k
10k
100k
1M
10M 100M
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
TPC 33. OP17 Common-Mode Rejection Ration vs.
Frequency
TPC 36. OP17 Voltage Noise vs. Frequency
–10–
REV. A
OP15/OP17
2k⍀
0.1%
TEST CIRCUITS
+15V
V+
400⍀
0.1%
10V
0V
100k⍀
2
3
7
6
7
OP17
2N4416
100pF
5
2
3
1k⍀
0.1%
1
4
6
4
3k⍀
–15V
V
OUT
SUMMING
NODE
A
V
= –1
5k⍀
0.1%
NOTE:V
CAN BETRIMMEDWITH POTENTIOMETERS
OS
RANGING FROM 10k⍀TO 1M⍀. FOR MOST UNITS
TCV WILL BE MINIMIZEDWHEN V IS ADJUSTED
WITH A 100k⍀ POTENTIOMETER
OS
OS
SCOPE
+15V
2N4416
Figure 3. Input Offset Voltage Nulling
2k⍀
2k⍀
0.1%
Figure 6. OP17 Settling Time Test Circuit
+15V
APPLICATION INFORMATION
DynamicOperatingConsiderations
2k⍀
0.1%
10V
0V
2
3
7
OP15
4
6
As with most amplifiers, care should be taken with lead dress,
component placement and supply decoupling in order to ensure
stability. For example, resistors from the output to an input should
be placed with the body close to the input to minimize “pick-up”
and maximize the frequency of the feedback pole by minimizing
the capacitance for the input to ground.
2N4416
5k⍀
0.1%
100pF
3k⍀
–15V
V
OUT
SUMMING
NODE
A
V
= –1
5k⍀
0.1%
SCOPE
A feedback pole is created when the feedback around any amplifier
is resistive. The parallel resistance and capacitance from the input
of the device (usually the inverting input) to ac ground set the
frequency of this pole. In many instances the frequency of this
pole is much greater than the expected, 3 dB frequency of the
close-loop gain, and consequently there is negligible effect on
stability margin. However, if the feedback pole is less than approxi-
mately six times the expected 3 dB frequency, a lead capacitor
should be placed from the output to the negative input of the op
amp. T he value of the added capacitor should be such that the
RC time-constant of this capacitor and the resistance it parallels
is greater than, or equal to, the original feedback pole time is constant.
+15V
2N4416
2k⍀
Figure 4. OP15 Settling Time Test Circuit
R1
R2
10k⍀
5k⍀
C2
30pF
DIGITAL INPUTS
+10V
LSB
MSB
5
+15V
7
R
6
7
8
9
10 11
12
REF
5k⍀
B1 B2 B3 B4 B5 B6 B7 B8
14
15
4
2
2
3
V
I
O
REF+
6
DAC08E
OP15F
V
I
O
REF–
V+
V
= 0VTO 10V
O
4
V–
13
C
C
V
LC
3
16
1
C1
0.1F
+15V
–15V
–15V
Figure 5. Current-to-Voltage Amplifier Output
REV. A
–11–
OP15/OP17
OUTLINEDIMENSIONS
D imensions shown in millimeters and (inches).
8-LeadCeramicDip–GlassHermeticSeal[CERDIP]
8-LeadStandardSmallOutlinePackage[SOIC]
(Q-8)
NarrowBody
(R-8)
0.13 (0.0051) 1.40 (0.0551)
MIN
MAX
5.00 (0.1968)
4.80 (0.1890)
8
5
7.87 (0.3089)
5.59 (0.2201)
8
1
5
4
PIN 1
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
1
4
2.54 (0.1000) BSC
10.29 (0.4051) MAX
PIN 1
8.13 (0.3201)
7.37 (0.2902)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
؋
45؇ 1.52 (0.0600)
0.38 (0.0150)
1.75 (0.0688)
1.35 (0.0532)
5.08 (0.2000)
MAX
0.25 (0.0098)
0.10 (0.0040)
3.81 (0.1500)
5.08 (0.2000)
3.18 (0.1252)
8؇
0.51 (0.0201)
0.33 (0.0130)
MIN
0؇ 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.19 (0.0075)
SEATING
PLANE
0.41 (0.0160)
0.38 (0.0150)
0.20 (0.0079)
0.58 (0.0228)
0.36 (0.0142)
SEATING
PLANE
15
0
1.78 (0.0701)
0.76 (0.0299)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AA
8-Lead MetalCan[TO-99]
(H-08)
REFERENCE PLANE
12.70 (0.5000)
MIN
4.70 (0.1850)
4.19 (0.1650)
6.35 (0.2500) MIN
2.54 (0.1000) BSC
5
4.06 (0.1600)
3.56 (0.1400)
1.27 (0.0500) MAX
4
6
1.14 (0.0450)
0.69 (0.0270)
5.08
(0.2000)
BSC
3
7
2
8
1
2.54
(0.1000)
BSC
0.48 (0.0190)
0.41 (0.0160)
0.86 (0.0340)
0.71 (0.0280)
1.02 (0.0400) MAX
0.53 (0.0210)
0.41 (0.0160)
1.02 (0.0400)
0.25 (0.0100)
45 BSC
BASE & SEATING PLANE
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-002AK
Revision History
Location
Page
9/02—DataSheetchangedfromREV. 0toREV. A.
Deleted OP16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Edits to FEAT URES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to GENERAL DESCRIPT ION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to SPECIFICAT IONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to ABSOLUT E MAXIMUM RAT INGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to DICE CHARACT ERIST ICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Edits to WAFER T EST LIMIT S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Deleted 12 T PCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
Updated OUT LINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
–12–
REV. A
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IC OP-AMP, 3000 uV OFFSET-MAX, 26 MHz BAND WIDTH, MBCY8, TO-99, 8 PIN, Operational Amplifier
ADI
OP17EJ
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