5962R9858301QXC中文资料_数据手册_规格书

Standard Products

UT80CRH196KD Microcontroller

Datasheet

September, 2002

FEATURES

INTRODUCTION

q

20MHz 16-bit Microcontroller compatible with industry

standard’s MCS-96 ISA

- Register to Register Architecture

- 1000 Byte Register RAM

The UT80CRH196KD is compatible with industry standard’s

MCS-96 instruction set. The UT80CRH196KD is supported

by commercial hardware and software development tools.

Built on UTMC’s Commercial RadHard^TMepitaxial CMOS

technology, the microcontroller is hardened against ionizing

dose and charged particles. The microcontroller’s on-board

1000 byte scratch-pad SRAM and flip-flops can withstand

q

Three 8-bit I/O Ports

On-board Interrupt Controller

Three Pulse-Width Modulated Outputs

High Speed I/O

charged particles with energies up to 25 MeV-cm²/mg.

The UT80CRH196KD accesses instruction code and data via

a 16-bit address and data bus. The 16-bit bus allows the

microcontroller to access 128K bytes of instruction/data

memory. Integrated software and hardware timers, high speed

I/O, pulse width modulation circuitry, and UART make the

UT80CRH196KD ideal for control type applications. The

CPU’s ALU supports byte and word adds and subtracts, 8 and

16 bit multiplies, 32/16 and 16/8 bit divides, as well as

increment, decrement, negate, compare, and logical

operations. The UT80CRH196KD’s interrupt controller

prioritizes and vectors 18 interrupt events. Interrupts include

normal interrupts and special interrupts. To reduce power

consumption, the microcontroller supports software invoked

idle and power down modes. The UT80CRH196KD is

packaged in a 68-lead quad flatpack.

UART Serial Port

Dedicated Baud Rate Generator

Software and Hardware Timers

- 16-Bit Watchdog Timer, Four 16-Bit Software Timers

- Three 16-Bit Counter/Timers

q

Radiation-hardened process and design; total dose

irradiation testing to MIL-STD-883 Method 1019

- Total-dose: 100K rads(Si)

- Effective LET threshold: 25 MeV-cm ²/mg

- Saturated cross section: 3.66e-7cm²/bit

- Latchup immune (LET > 128 MeV-cm²/mg)

q Error detection and correction for external memory accesses

q

QML Q and QML V compliant part

q Standard Microcircuit Drawing 5962-98583

CPU

1000 Bytes

ALU

RAM

Interrupt

PTS

Controller

Register File

MicroCode

Engine

Control

Signals

Memory

Controller

Queue

Address /Data Bus

Alternate

Functions

HOLD

HLDA

BREQ

PWM1

Alternate

Functions

Serial

Port

Watchdog

Timer

PWM

HSIO and

Timers

PORT0

PWM2

EXTINT

HSI HSO

PORT1

PORT2

ECB0-

ECB5

Figure 1. UT80CRH196KD Microcontroller

1.0 SIGNAL DESCRIPTION

Port 0 (P0.0 - P0.7):Port 0 is an 8-bit input only port when used

in its default mode. When configured for their alternate function,

five of the bits are bi-directional EDAC check bits as shown in

Table 1.

Table 2. Port 1 Alternate Functions

Port

Alternate

Name

Alternate Function

P1.0

P1.1

P1.2

P1.3

P1.0

P1.1

I/O Pin

Port 1 (P1.0 - P1.7): Port 1 is an 8-bit, quasi-bidirectional, I/O

port. All pins are quasi-bidirectional unless the alternate

function is selected per Table 2. When the pins are configured

for their alternate functions, they act as standard I/O, not quasi-

bidirectional.

I/O Pin

P1.2

PWM1

Setting IOC3.2=1 enables P1.3 as

the Pulse Width Modulator

(PWM1) output pin.

Port 2 (P2.0 - P2.7):Port 2 is an 8-bit, multifunctional, I/O port.

These pins are shared with timer 2 functions, serial data I/O and

PWM0 output, per Table 3.

P1.4

P1.5

PWM2

BREQ

Setting IOC3.3=1 enables P1.4 as

the Pulse Width Modulator

(PWM2) output pin.

AD0-AD7: The lower 8-bits of the multiplexed address/data

bus. The pins on this port are bidirectional during the data phase

of the bus cycle.

Bus Request, output activated

when the bus controller has a

pending external memory cycle.

AD8-AD15: The upper 8-bits of the multiplexed address/data

bus. The pins on this port are bidirectional during the data phase

of the 16-bit bus cycle. When running in 8-bit bus width, these

pins are non-multiplexed, dedicated upper address bit outputs.

P1.6

P1.7

HLDA

HOLD

Bus Hold Acknowledge, output

indicating the release of the bus.

HSI: Inputs to the High Speed Input Unit. Four HSI pins are

available: HSI.0, HSI.1, HSI.2, and HSI.3. Two of these pins

(HSI.2 and HSI.3) are shared with the HSO Unit. Two of these

pins (HSI.0 and HSI.1) have alternate functions for Timer 2.

Bus Hold, input requesting control

of the bus.

Table 3. Port 2 Alternate Functions

Port

Alternate

Name

Alternate Function

HSO: Outputs from the High Speed Output Unit. Six HSO pins

are available: HSO.0, HSO.1, HSO.2, HSO.3, HSO.4, and

HSO.5. Pins HSO.4 and HSO.5 are shared with pins HSI.2 and

HSI.3 of the HSI Unit respectively.

P2.0

P2.1

P2.2

TXD

RXD

Transmit Serial Data.

Receive Serial Data.

EXTINT

External interrupt. Clearing

IOC1.1 will allow P2.2 to be

used for EXTINT (INT07)

Table 1. Port 0 Alternate Functions

P2.3

T2CLK

Timer 2 clock input and Serial

port baud rate generator input.

Port Pin

Alternate

Name

Alternate Function

P2.4

P2.5

T2RST

PWM0

Timer 2 Reset

P0.0-P0.3,

P0.6

ECB0-ECB4 Error Detection & Correction

Check Bits

Pulse Width Modulator

output 0

P0.4

P0.5

Input Port Pins

P2.6

P2.7

T2UP-DN

Controls the direction of the

Timer 2 counter. Logic High

equals count down. Logic low

equals count up.

P0.7

EXTINT

Setting IOC1.1=1 will allow P0.7

to be used for EXTINT (INT07)

T2CAPTURE A rising edge on P2.7 causes

the value of Timer 2 to be

captured into this register, and

generates a Timer 2 Capture

interrupt (INT11).

2

1.1 Hardware Interface

There are 8 configuration bits available in the CCR. However,

bits 7 and 6 are not used by the UT80CRH196KD. Bits 5 and 4

comprise the READY mode control which define internal limits

for waitstates generated by the READY pin. Bit 3 controls the

definition of the ALE/ADV pin for system memory controls

while bit 2 selects between the different write modes. Bit 1

selects whether the UT80CRH196KD will use a dynamic 16-

bit bus or whether it will be locked in as an 8-bit bus. Finally,

Bit 0 enables the Power Down mode and allows the user to

disable this mode for protection against inadvertent power

downs.

1.1.1 Interfacing with External Memory

The UT80CRH196KD can interface with a variety of external

memory devices. It supports either a fixed 8-bit bus width or a

dynamic 8-bit/16-bit bus width, internal READY control for

slow external memory devices, a bus-hold protocol that enables

external devices to take over the bus, and several bus-control

modes. These features provide a great deal of flexibility when

interfacing with external memory devices.

1.1.1.1 Chip Configuration Register

1.1.1.2 Bus Width and Memory Configurations

The Chip Configuration Register (CCR) is used to initialize the

UT80CRH196KD immediately after reset. The CCR is fetched

from external address 2018H (Chip Configuration Byte) after

removal of the reset signal. The Chip Configuration Byte (CCB)

is read as either an 8-bit or 16-bit word depending on the value

of the BUSWIDTH pin. The composition of the bits in the CCR

are shown in Table 4.

The UT80CRH196KD external bus can operate as either an 8-

bit or 16-bit multiplexed address/data bus (see figure 2). The

value of bit 1 in the CCR determines the bus operation. A logic

low value on CCR.1 locks the bus controller in 8-bit bus mode.

If, however, CCR.1 is a logic high, then the BUSWIDTH signal

is used to decide the width of the bus. The bus is 16 bits wide

when the BUSWIDTH signal is high, and is 8 bits when the

BUSWIDTH signal is low.

1.1.2 Reset

Table 4. Chip Configuration Register

To reset the UT80CRH196KD, hold the RESET pin low for at

least 16 state times after the power supply is within tolerance

and the oscillator has stabilized. Resets following the power-up

reset may be asserted for at least one state time, and the device

will turn on a pull-down transistor for 16 state times. This

enables the RESET signal to function as the system reset. The

reset state of the external I/O is shown in Table9,and the register

reset values are shown in Table 8.

Bit

7

Function

N/A

6

5

IRC1 - Internal READY Mode Control

IRC0 - Internal READY Mode Control

Address Valid Strobe Select (ALE/ADV)

Write Strobe Mode Select (WR and BHE/WRL and WRH)

Dynamic Bus Width Enable

4

3

2

1.1.3 Instruction Set

1

The instruction set for the UT80CRH196KD is compatible with

the industry standardMCS-96 instruction set used on the

8XC196KD.

0

Enable Power Down Mode

Table 5. Memory Map

Memory Description

External Memory¹

Reserved

Begin

02080H

0205EH

02040H

02030H

02020H

02019H

02018H

02014H

02000H

00400H

0001AH

00000H

End

0FFFFH

0207FH

0205DH

0203FH

0202FH

0201FH

02018H

02017H

02013H

1FFFH

PTS Vectors

Upper Interrupt Vectors

Reserved

Chip Configuration Byte

Reserved

Lower Interrupt Vectors

External Memory

Internal Memory (RAM)

Special Function Registers

003FFH

00019H

Notes:

1.The first instruction read following reset will be from location 2080h. All other external memory can be used as instruction and/or data memory.

3

Table 6. Interrupt Vector Sources, Locations, and Priorities

Interrupt

Priority¹

(0 is the

Lowest

PTS

Vector

Location

Number

Interrupt Vector

Source(s)

Vector

Location

Priority)

Special

Unimplemented

Opcode

Unimplemented Opcode

2012h

N/A

Special

INT 15

Software Trap

NMI

2010h

203Eh

N/A

15

NMI²

INT 14

INT 13

HSI FIFO Full

Port 2.2

203Ch

203Ah

205Ch

205Ah

14

13

EXTINT 1²

INT 12

INT 11

Timer 2 Overflow

Timer 2 Capture

2038h

2036h

2058h

2056h

12

11

Timer 2 Capture²

HSI FIFO 4

INT 10

HSI FIFO

2034h

2054h

10

Fourth Entry

RI Flag³

INT 9

INT 8

INT 7

INT 6

Receive

2032h

2030h

200Eh

200Ch

2052h

2050h

204Eh

204Ch

9

8

7

6

TI Flag³

Transmit

EXTINT²

Serial Port

Port 2.2 or Port 0.7

RI Flag and

TI Flag⁴

INT 5

Software Timer

HSI.0²

Software Timer 0-3

Timer 2 Reset

200Ah

204Ah

5

INT 4

INT 3

HSI.0 Pin

2008h

2006h

2048h

2046h

4

3

High Speed

Outputs

Events on HSO.0 thru

HSO.5 Lines

INT 2

INT 1

INT 0

HSI Data Available

EDAC Bit Error

Timer Overflow

HSI FIFO Full or

HSI Holding Reg.

Loaded

2004h

2002h

2000h

2044h

2042h

2040h

2

1

0

Single Bit Error

Single Bit Error OVF

Double Bit Error

Timer 1 or Timer 2

All of the previous maskable interrupts can be assigned to the PTS.

Any PTS interrupt has priority over all other maskable interrupts.

4

Notes:

1.

The Unimplemented Opcode and Software Trap interrupts are not prioritized. The Interrupt Controller immediately services these interrupts when they are

asserted. NMI has the highest priority of all prioritized interrupts. Any PTS interrupt has priority over lower priority interrupts, and over all other maskable

interrupts. The standard maskable interrupts are serviced according to their priority number with INT0 has the lowest priority of all interrupts.

These interrupts can be configured to function as independent, external interrupts.

If the Serial interrupt is masked and the Receive and Transmit interrupts are enabled, the RI flag and TI flag generate separate Receive and Transmit inter-

rupts.

2.

3.

4.

If the Receive and Transmit interrupts are masked and the Serial interrupt is enabled, both RI flag and TI flag generate a Serial Port interrupt.

5

Table 7. SFR Memory Mapping

HWin 0 Read HWin 0 Write HWin 1

HWin 15¹

Address

019H

018H

017H

016H

015H

Stack Pntr (hi) Stack Pntr (hi)

Stack Pntr (lo) Stack Pntr (lo)

Stack Pntr (hi) Stack Pntr (hi)

Stack Pntr (lo) Stack Pntr (lo)

PWM2_CTRL ***

IOS2

IOS1

IOS0

PWM0_CTRL

IOC1

PWM1_CTRL ***

EDAC-CS²

***

IOC0

014H

013H

012H

011H

010H

WSR

INT_MASK1

INT_PEND1

SP_STAT

PORT 2

INT_MASK1

INT_PEND1

SP_CON

PORT 2

INT_MASK1

INT_PEND1

RESERVED

INT_MASK1

INT_PEND1

***

PSW²

Timer 3(hi)²

Timer 3(lo)²

00FH

00EH

00DH

PORT 1

RESERVED

PORT 0

BAUD RATE

Timer 2 (hi)

RESERVED

WDT-SCALE²

IOC3

Timer 2 (hi)

T2CAPTURE (hi)

00CH

00BH

Timer 2 (lo)

Timer 1 (hi)

Timer 2 (lo)

IOC2

T2CAPTURE (lo)

***

INT_PRI(hi)²

INT_PRI(lo)²

INT_PEND

INT_MASK

PTSSRV (hi)

PTSSRV (lo)

PTSSEL (hi)

PTSSEL (lo)

RESERVED

Zero-reg (hi)

Zero_reg (lo)

00AH

Timer 1 (lo)

Watchdog

***

009H

008H

007H

006H

005H

004H

003H

002H

001H

000H

INT_PEND

INT_MASK

SBUF (RX)

HSI_status

INT_PEND

INT_MASK

***

INT_MASK

SBUF (TX)

HSO_command

HSO_time (hi)

HSO_time (lo)

HSI_mode

***

HSI_time(hi)

HSI_time (lo)

RESERVED

Zero_reg (hi)

Zero_reg (lo)

***

RESERVED

Zero_reg (hi)

Zero_reg (lo)

RESERVED

Zero_reg (hi)

Zero_reg (lo)

Notes:

1. For some functions that share a register address in HWindow0, the opposite access type (read/write) is available in HWindow 15 if

indicated by the three asterisks (***).

2. These registers are not available in the industry standard 8XC196KD. Therefore, industry standard development software will not recognize these

mnemonics, and you will only be able to access them via their physical addresses.

6

Table 8: Special Function Register Reset Values

Binary Reset State

Hexadecimal Reset

Value

Internal Register

Stack Pointer (SP)

XXXX XXXX XXXX XXXX

0000 0000

XXXX

I/O Status Register 2 (IOS2)

I/O Status Register 1 (IOS1)

I/O Status Register 0 (IOS0)

Window Select Register (WSR)

00

0000 0000

Interrupt Mask Register 1 (INT_MASK1)

0000 0000

Interrupt Pending Register 1

(INT_PEND1)

Serial Port Status Register (SP_STAT)

Port 2 Register (PORT2)

0000 1011

110X XXX1

0B

XX

FF

Port 1 Register (PORT1)

1111 1111

Port 0 Register (PORT0)

XXXX XXXX

0000 0000 0000 0000

0000 0000

XX

0000

00

Timer 2 Value Register (TIMER2)

Timer 1 Value Register (TIMER1)

Interrupt Pending Register (INT_PEND)

Interrupt Mask Register (INT_MASK)

0000 0000

00

Receive Serial Port Register (SBUF

(RX))

0000 0000

00

HSI Status Register (HSI_status)

HSI Time Register (HSI_time)

Zero Register (ZERO_REG)

X0X0 X0X0

XXXX XXXX XXXX XXXX

0000 0000 0000 0000

0000 0000

XX

XXXX

0000

00

PWM0 Control Register (PWM0_CTRL)

I/O Control Register 1 (IOC1)

I/O Control Register 0 (IOC0)

Serial Port Control Register (SP_CON)

Baud Rate Register (BAUD_RATE)

I/O Control Register 2 (IOC2)

0010 0001

21

0000 00X0

0X

0000 1011

0B

0000 0000 0000 0001

X00X X000

0001

XX

Watch Dog Timer Register (WATCH-

DOG)

0000 0000

00

7

Table 8: Special Function Register Reset Values

Binary Reset State

Hexadecimal Reset

Value

Internal Register

Transmit Serial Port Buffer (SBUF (TX))

0000 0000

00

HSO Command Register

(HSO_command)

00

HSO Time Register (HSO_time)

0000 0000 0000 0000

1111 1111

0000

FF

HSI Mode Register (HSI_mode)

PWM2 Control Register (PWM2_CTRL)

PWM1 Control Register (PWM1_CTRL)

0000 0000

00

0000 0000

00

EDAC Control and Status Register

(EDAC_CS)

0000 0000

00

Timer 3 Value Register (TIMER3)

0000 0000 0000 0000

0000 0000

0000

00

Watchdog Timer Prescaler

(WDT_SCALE)

I/O Control Register 3 (IOC3)

Interrupt Priority Register (INT_PRI)

PTS Service Register (PTSSRV)

PTS Select Register (PTSSEL)

1111 0000

0000 0000

F0

00

0000 0000 0000 0000

0000

Timer 2 Capture Register

(T2CAPTURE)

Program Counter (PC)

0010 0000 1000 0000

XX10 1111

2080

XF

Chip Configuration Register (CCR)

8

Table 9: External I/O Reset State

I/O State During

Reset

External I/O

I/O Function After Reset

I/O State After Reset

Address/Data Bus (AD15:0)

Address/Data Bus

ALE

Pulled High

Driven Output

ALE

ADV

Pulled High

RD

Pulled High

Driven Output

WR

WRL

Undefined Inputs ¹

Undefined I/O^1,2

Port 0 (P0.0-P0.3; P0.6)

ECB(4:0)

[P0.0-P0.3; P0.6] and

ECB(4:0)

Undefined Inputs ¹

Undefined Input¹

Undefined Inputs ¹

Undefined Input¹

Port 0 (P0.4 and P0.5)

P0.4 and P0.5

P0.7

Port 0 (P0.7)

EXTINT

NMI

Pulled Down

Disabled Input¹

HSI.0

T2RST

HSI.0

Disabled Input¹

HSI.1

T2CLK

HSI.1

Disabled I/O¹

HSI.2/HSO.4

Undefined

Disabled I/O¹

Pulled Down

HSI.3/HSO.5

Undefined

HSO.0 through HSO.3

HSO.0-HSO.3

Driven Low

Outputs

Port 1 (P1.0-P1.7)

PWM1; PWM2;

BREQ; HLDA; HOLD

P1.0-P1.7

Pulled Up

Port 2 (P2.0)

TXD

Driven High

Output

Undefined Input¹

Port 2 (P2.1)

RXD

Port 2 (P2.2)

EXTINT

P2.2 and EXTINT

P2.3 and T2CLK

P2.4

Port 2 (P2.3)

T2CLK

Port 2 (P2.4)

T2RST

9

Table 9: External I/O Reset State

I/O State During

Reset

External I/O

Port 2 (P2.5)

I/O Function After Reset

I/O State After Reset

PWM0

Pulled Down

Driven Low Output

PWM0

Port 2 (P2.6)

T2UP-DN

P2.6

Pulled Up

Port 2 (P2.7)

T2CAPTURE

P2.7 and T2CAPTURE

Undefined Input¹

Undefined I/O¹

Undefined Input¹

Undefined I/O^1,2

Undefined Input¹

EDACEN

ECB5

EDACEN

ECB5

READY

BUSWIDTH

READY

BUSWIDTH

BHE

Undefined Input¹

Pulled Up

Undefined Input¹

Driven Output

BHE

WRH

CLKOUT

INST

CLKOUT

INST

Driven Output

Pulled Down

Driven Output

Pulled Up

RESET

Pulled Low by

System

Notes:

1. These pins must not be left floating. Input voltages must not exceed V

during power-up.

DD

2. Do not directly tie these pins to V

or GND; if EDACEN goes low, they may be driven by the UT80CRH196KD and bus contention may occur.

DD

10

Bus Control

UT80CRH196KD

AD8-AD15

8-Bit

Latched

Address High

AD0-AD15

AD0-AD7

16-Bit

8-Bit

Multiplexed

Address/Data

Multiplexed

Address/Data

16-Bit Bus

8-Bit Bus

Figure 2. Bus Width Options

11

P0.5

P0.4

V_SS

10

11

12

13

14

15

16

17

18

AD0

AD1

AD2

60

59

58

57

56

55

54

53

52

V_DD

V_SS

AD3

AD4

AD5

EXTINT/P2.2

RESET

AD6

AD7

AD8

AD9

AD10

AD11

UT80CRH196KD

TOP VIEW

RXD/P2.1

TXD/P2.0

P1.0

19

20

51

50

49

48

47

P1.1

P1.2

PWM1/P1.3

PWM2/P1.4

T2RST/HSI.0

21

22

23

24

25

26

AD12

AD13

46

45

44

AD14

T2CLK/HSI.1

HSI.2/HS0.4

AD15

P2.3/T2CLK

Figure 3. 68-pin Quad Flatpack Package

12

Legend for I/O fields:

TDI

= TTL compatible input

(internally pulled low)

TO

TI

CI

= TTL compatible output

= TTL compatible input

= CMOS only input

TB

TUQ

= TTL compatible bidirectional

= TTL compatible quasi-bidirectional

(internally pulled high)

TUO

= TTL compatible output

(internally pulled high)

= TTL compatible output

(internally pulled low)

= TTL compatible input

(internally pulled high)

TUB

= TTL compatible bidirectional

(internally pulled high)

TDO

TUI

TUBS = TTL compatible bidirectional Schmitt

Trigger (internally pulled high)

PWR

= +5V (V_DD

)

GND

= OV (V_SS

)

Table 10: 68-lead Flat Pack Pin Descriptions

QFP Pin#

I/O

Name

Active

Description

1

PWR

V_DD

---

Digital supply voltage (+5V). There are 2 V_DDpins, both of

which must be connected.

ECB5¹

NMI

2

TB

---

EDAC Check Bit 5. Asserting the EDACEN pin will cause the

error detection and correction engine to pass the EDAC Check

Bit 5 through pin 2 of the UT80CRH196KD.

3

4

TDI

High

Non-Maskable Interrupt. A positive transition causes a vector

through the NMI interrupt at location 203Eh. Assert NMI for at

least 1 state time to guarantee acknowledgment by the interrupt

controller.

TI

P0.3

---

Port 0 Pin 3. An input only port pin that is read at location 0Eh

in HWindow 0.

ECB4¹

TB

EDAC Check Bit 4. Asserting the EDACEN pin will cause the

error detection and correction engine to pass the EDAC Check

Bit 4 through pin 4 of the UT80CRH196KD.

5

6

TI

P0.1

---

Port 0 Pin 1. An input only port pin that is read at location 0Eh

in HWindow 0.

ECB3¹

TB

EDAC Check Bit 3. Asserting the EDACEN pin will cause the

error detection and correction engine to pass the EDAC Check

Bit 3 through pin 5 of the UT80CRH196KD.

TI

P0.0

---

Port 0 Pin 0. An input only port pin that is read at location 0Eh

in HWindow 0.

ECB2¹

TB

EDAC Check Bit 2. Asserting the EDACEN pin will cause the

error detection and correction engine to pass the EDAC Check

Bit 2 through pin 6 of the UT80CRH196KD.

13

Table 10: 68-lead Flat Pack Pin Descriptions

QFP Pin#

I/O

Name

Active

Description

7

TI

P0.2

---

Port 0 Pin 2. An input only port pin that is read at location 0Eh

in HWindow 0.

ECB1¹

TB

---

EDAC Check Bit 1. Asserting the EDACEN pin will cause the

error detection and correction engine to pass the EDAC Check

Bit 1 through pin 7 of the UT80CRH196KD.

8

9

TI

P0.6

---

Port 0 Pin 6. An input only port pin that is read at location 0Eh

in HWindow 0.

ECB0¹

TB

EDAC Check Bit 0. Asserting the EDACEN pin will cause the

error detection and correction engine to pass the EDAC Check

Bit 0 through pin 8 of the UT80CRH196KD.

TI

P0.7

---

Port 0 Pin 7. An input only port pin that is read at location 0Eh

in HWindow 0.

EXTINT

High

External Interrupt. Setting IOC1.1 = 1 enables pin 9 as the

source for the external interrupt EXTINT. A rising edge on this

pin will generate EXTINT (INT07, 200Eh). Assert EXTINT for

at least 2 state times to ensure acknowledgment by the interrupt

controller.

During Power Down mode, asserting EXTINT places the chip

back into normal operation, even if EXTINT is masked.

10

11

12

TI

P0.5

P0.4

V_SS

---

Port 0 Pin 5. An input only port pin that is read at location 0Eh

in HWindow 0.

Port 0 Pin 4. An input only port pin that is read at location 0Eh

in HWindow 0.

GND

Digital circuit ground (0V). There are 4 V_SSpins, all of which

must be connected and one additional recommended V_SScon-

nection.

13

14

PWR

GND

V_DD

---

Digital supply voltage (+5V). There are 2 V_DDpins, both of

which must be connected.

V_SS

Digital circuit ground (0V). There are 4 V_SSpins, all of which

must be connected and one additional recommended V_SScon-

nection.

14

Table 10: 68-lead Flat Pack Pin Descriptions

QFP Pin#

I/O

Name

Active

Description

15

TI

P2.2

---

Port 2 Pin 2. An input only port pin that is written at location

10h of HWindow 0. P2.2 will always generate EXTINT1

(INT13, 203Ah) unless masked by the INT_MASK1 register.

Assert EXTINT1 for at least 2 state times to guarantee acknowl-

edgment by the interrupt controller.

TI

EXTINT

High

External Interrupt. Setting IOC1.1 = 0 enables pin 15 as the

source for the external interrupt EXTINT. A rising edge on this

pin will generate EXTINT (INT07, 200Eh). Assert EXTINT for

at least 2 state times to ensure acknowledgment by the interrupt

controller.

During Power Down mode, asserting EXTINT places the chip

back into normal operation, even if EXTINT is masked.

16

TUBS

RESET

Low

Master Reset. The first external reset signal supplied to the

UT80CRH196KD must be active for at least 16 state times. All

subsequent RESET assertions need only be active for 1 state

time because the UT80CRH196KD will continue driving the

RESET signal for an additional 16 state times. See section 1.1.2

for more information on the RESET function of the

UT80CRH196KD.

17

TI

P2.1

---

Port 2 Pin 1. An input only port pin that is read at location 10h

of HWindow 0.

Setting SPCON.3 = 0 enables the P2.1 function of pin 17.

TB

RXD

RXD is a bidirectional serial data port. When operating in Serial

Modes 1, 2, and 3, RXD receives serial data. When using Serial

Mode 0, RXD operates as an input and an open-drain output for

data.

Setting SPCON.3 = 1 enables the RXD function of pin 17.

18²

TUO

P2.0

---

Port 2 Pin 0. An output only port pin that is written at location

10h of HWindow 0.

Setting IOC1.5 = 0 enables the P2.0 function of pin 18.

TXD

Transmit Serial Data (TXD). When set to Serial Mode 1, 2, or 3,

TXD transmits serial port data. When using Serial Mode 0,

TXD is used as the Serial Clock output.

Setting IOC1.5 = 1 enables the TXD function of pin 18.

TUI

ICT

Low

In-Circuit Test. The UT80CRH196KD will enter the In-Circuit

Test mode if this pin is held low during the rising edge of

RESET.

15

Table 10: 68-lead Flat Pack Pin Descriptions

QFP Pin#

I/O

Name

Active

Description

19

TUQ

P1.0

---

Port 1 Pin 0. A quasi-bidirectional port pin that is read and writ-

ten at location 0Fh of HWindow 0.

20

21

22

TUQ

P1.1

P1.2

P1.3

---

Port 1 Pin 1. A quasi-bidirectional port pin that is read and writ-

ten at location 0Fh of HWindow 0.

Port 1 Pin 2. A quasi-bidirectional port pin that is read and writ-

ten at location 0Fh of HWindow 0.

Port 1 Pin 3. A quasi-bidirectional port pin that is read and writ-

ten at location 0Fh of HWindow 0.

Setting IOC3.2 = 0 enables the P1.3 function of pin 22.

TUO

PWM1

---

Pulse Width Modulator (PWM) Output 1. The output signal

will be a waveform whose duty cycle is programmed by the

PWM1_CONTROL register, and the frequency is selected by

IOC2.2.

Setting IOC3.2 = 1 enables the PWM1 function of pin 22.

23

TUQ

TUO

P1.4

---

Port 1 Pin 4. A quasi-bidirectional port pin that is read and writ-

ten at location 0Fh of HWindow 0.

Setting IOC3.3 = 0 enables the P1.4 function of pin 23.

PWM2

Pulse Width Modulator (PWM) Output 2. The output signal

will be a waveform whose duty cycle is programmed by the

PWM2_CONTROL register, and the frequency is selected by

IOC2.2.

Setting IOC3.3 = 1 enables the PWM2 function of pin 23.

24

TI

HSI.0

---

High Speed Input Module, input pin 0. Unless masked, a rising

edge on this input will generate the HSI.0 Pin interrupt (INT04,

2008h). Assert the HSI.0 pin for at least 2 state times to ensure

acknowledgment by the interrupt controller.

Setting IOC0.0 = 1 enables pin 24 as an HSI input, and allows

events on this pin to be loaded into the HSI FIFO.

T2RST

High

Timer 2 Reset. A rising edge on the T2RST pin resets Timer 2.

To enable the T2RST function of pin 24, set IOC0.3 = 1 and

IOC0.5 = 1.

16

Table 10: 68-lead Flat Pack Pin Descriptions

QFP Pin#

I/O

Name

Active

Description

25

TI

HSI.1

---

High Speed Input Module, input pin 1.

Setting IOC0.2 = 1 enables pin 25 as an HSI input, and allows

events on this pin to be loaded into the HSI FIFO.

TI

T2CLK

HSO.4

---

Timer 2 Clock.

Setting IOC0.7 = 1 and IOC3.0 = 0 enables pin 25 to function as

the Timer 2 clock source.

26

TO

High Speed Output Module, output pin 4. This pin can simulta-

neously operate in the HSI and HSO modes of operation. As a

result, this pin acts as an output that the HSI monitors.

Setting IOC1.4 = 1 enables the HSO.4 function of pin 26.

TI

HSI.2

---

High Speed Input Module, input pin 2. This pin can simulta-

neously operate in the HSI and HSO modes of operation. As a

result, this pin can monitor events on the HSO.

Setting IOC0.4 = 1 enables pin 26 as an HSI input pin, and

allows events on this pin to be loaded into the HSI FIFO.

27

TO

TI

HSO.5

HSI.3

---

High Speed Output Module, output pin 5. This pin can simulta-

neously operate in the HSI and HSO modes of operation. As a

result, this pin acts as an output that the HSI monitors.

Setting IOC1.6 = 1 enables the HSO.5 function of pin 27.

High Speed Input Module, input pin 3. This pin can simulta-

neously operate in the HSI and HSO modes of operation. As a

result, this pin can monitor events on the HSO.

Setting IOC0.6 = 1 enables pin 27 as an HSI input pin, and

allows events on this pin to be loaded into the HSI FIFO.

28

29

TDO

HSO.0

HSO.1

---

High Speed Output Module, output pin 0. The HSO.0 pin is a

dedicated output for the HSO module.

High Speed Output Module, output pin 1. The HSO.1 pin is a

dedicated output for the HSO module.

17

Table 10: 68-lead Flat Pack Pin Descriptions

QFP Pin#

I/O

Name

Active

Description

30

TUQ

P1.5

---

Port 1 Pin 5. A quasi-bidirectional port pin that is read and writ-

ten at location 0Fh of HWindow 0.

Setting WSR.7 = 0 enables the P1.5 function of pin 30.

TUO

BREQ

Low

Bus Request. The BREQ output signal asserts during a HOLD

cycle when the internal bus controller has a pending external

memory cycle.

During a HOLD cycle, BREQ will not be asserted until the

HLDA signal is asserted. Once asserted, BREQ does not deas-

sert until the HOLD signal is released.

Setting WSR.7 = 1 enables the BREQ function of pin 30.

31²

TUQ

TUO

P1.6

---

Port 1 Pin 6. A quasi-bidirectional port pin that is read and writ-

ten at location 0Fh of HWindow 0.

Setting WSR.7 = 0 enables the P1.6 function of pin 31.

HLDA

Low

Bus Hold Acknowledge. The UT80CRH198KD asserts the

HLDA signal as a result of another device activating the HOLD

signal. By asserting this signal, the UT80CRH196KD is indicat-

ing that it has released the bus.

Setting WSR.7 = 1 enables the HLDA function of pin 31.

32

TUQ

TUI

P1.7

HOLD

P2.6

---

Low

---

Port 1 Pin 7. A quasi-bidirectional port pin that is read and writ-

ten at location 0Fh of HWindow 0.

Setting WSR.7 = 0 enables the P1.7 function of pin 32.

Bus Hold. The HOLD signal is used to request control of the

bus by another DMA device.

Setting WSR.7 = 1 enables the HOLD function of pin 32.

33

TUQ

TUI

Port 2 Pin 6. A quasi-bidirectional port pin that is read and writ-

ten at location 10h of HWindow 0.

Setting IOC2.1 = 0 enables the P2.6 function of pin 33.

T2UP-DN

---

Timer 2 Up or Down. The T2UP-DN pin will dynamically

change the direction that Timer 2 counts.

T2UP-DN = 1 then Timer 2 counts down.

T2UP-DN = 0 then Timer 2 counts up.

Setting IOC2.1 = 1 enables the T2UP-DN function of pin 33.

When IOC2.1 = 0, Timer 2 will only count up.

18

Table 10: 68-lead Flat Pack Pin Descriptions

QFP Pin#

I/O

Name

Active

Description

34

TDO

HSO.2

---

High Speed Output Module, output pin 2. The HSO.2 pin is a

dedicated output for the HSO module.

35

36

TDO

GND

HSO.3

V_SS

---

High Speed Output Module, output pin 3. The HSO.3 pin is a

dedicated output for the HSO module.

Digital circuit ground (0V). There are 4 V_SSpins, all of which

must be connected and one additional recommended V_SScon-

nection.

37

38

TI

EDACEN

Low

EDAC Enable. Asserting the EDACEN signal activates the

error detection and correction engine. This causes the

UT80CRH196KD to include ECB(5:0) as the EDAC check bit

pins in all external memory cycles.

TUQ

P2.7

---

Port 2 Pin 7. A quasi-bidirectional port pin that is read and writ-

ten at location 10h of HWindow 0.

T2CAPTURE

High

Timer 2 Capture. A rising edge on this pin loads the value of

Timer 2 into the T2CAPTURE register, and generates a Timer 2

Capture interrupt (INT11, 2036h). Assert the T2CAPTURE sig-

nal for at least 2 state times to guarantee acknowledgment by the

interrupt controller. Using INT_Mask1.3 controls whether or not

a rising edge causes an interrupt.

39

TDO

P2.5

---

Port 2 Pin 5. An output only port pin that is written at location

10h of HWindow 0.

Setting IOC1.0 = 0 enables the P2.5 function of pin 39.

PWM0

Pulse Width Modulator (PWM) Output 0. The output signal

will be a waveform whose duty cycle is programmed by the

PWM0_CONTROL register, and the frequency is selected by

IOC2.2.

Setting IOC1.0 = 1 enables the PWM0 function of pin 39.

40²

TUO

WR

Low

Write. The WR signal indicates that an external write is occur-

ring. Activation of this signal only occurs during external mem-

ory writes.

Setting CCR.2 = 1 enables the WR function of pin 40.

WRL

Write Low. The WRL signal is activated when writing the low

byte of a 16-bit wide word, and is always asserted for 8-bit wide

memory writes.

Setting CCR.2 = 0 enables the WRL function of pin 40.

19

Table 10: 68-lead Flat Pack Pin Descriptions

QFP Pin#

I/O

Name

Active

Description

41

TUO

BHE

Low

Byte High Enable. The assertion of the BHE signal will occur

for all 16-bit word writes, and high byte writes in both 8- and 16-

bit wide bus cycles.

Setting CCR.2 = 1 enables the BHEfunction of pin 41.

TUO

WRH

Low

Write High. The WRH signal is asserted for high byte writes,

and word writes for 16-bit wide bus cycles. Additionally, WRH

is asserted for all write operations when using an 8-bit wide bus

cycle.

Setting CCR.2 = 0 enables the WRH function of pin 41.

42

43

TI

P2.4

---

Port 2 Pin 4. An input only port pin that is read at location 10h

of HWindow 0.

T2RST

High

Timer 2 Reset. Asserting the T2RST signal will reset Timer 2.

To enable the T2RST function of pin 42, set IOC0.3 = 1 and

IOC0.5 = 0.

TI

READY

High

READY input. The READY signal is used to lengthen memory

cycles by inserting “wait states” for interfacing to slow peripher-

als. When the READY signal is high, no “wait states” are gener-

ated, and the CPU operation continues in a normal fashion. If

READY is low during the falling edge of CLKOUT, the mem-

ory controller inserts “wait states” into the memory cycle. “Wait

state” generation will continue until a falling edge of CLKOUT

detects READY as logically high, or until the number of “wait

states” is equal to the number programmed into CCR.4 and

CCR.5.

Note: The READY signal is only used for external memory

accesses, and is functional during the CCR fetch.

44

TI

P2.3

---

Port 2 Pin 3. An input only port pin that is read at location 10h

of HWindow 0.

T2CLK

Timer 2 Clock input. Setting IOC0.7 = 0 and IOC3.0 = 0

enables this pin as the external clock source for Timer 2.

IOC0.7:

X

0

IOC3.0:

Timer 2 Clock Source:

Internal Clock Source

P2.3 External Clock Source

HSI.1 External Clock Source

1

0

1

45

TUB

AD15

---

Bit 15 of the Address/Data bus. This pin is a dedicated address

pin when operating with 8-bit wide bus cycles. For 16-bit wide

bus cycles, this pin is used as multiplexed address and data.

20

Table 10: 68-lead Flat Pack Pin Descriptions

QFP Pin#

I/O

Name

Active

Description

46

TUB

AD14

---

Bit 14 of the Address/Data bus. This pin is a dedicated address

pin when operating with 8-bit wide bus cycles. For 16-bit wide

bus cycles, this pin is used as multiplexed address and data.

47

48

49

50

51

52

TUB

AD13

AD12

AD11

AD10

AD9

---

Bit 13 of the Address/Data bus. This pin is a dedicated address

pin when operating with 8-bit wide bus cycles. For 16-bit wide

bus cycles, this pin is used as multiplexed address and data.

Bit 12 of the Address/Data bus. This pin is a dedicated address

pin when operating with 8-bit wide bus cycles. For 16-bit wide

bus cycles, this pin is used as multiplexed address and data.

Bit 11 of the Address/Data bus. This pin is a dedicated address

pin when operating with 8-bit wide bus cycles. For 16-bit wide

bus cycles, this pin is used as multiplexed address and data.

Bit 10 of the Address/Data bus. This pin is a dedicated address

pin when operating with 8-bit wide bus cycles. For 16-bit wide

bus cycles, this pin is used as multiplexed address and data.

Bit 9 of the Address/Data bus. This pin is a dedicated address

pin when operating with 8-bit wide bus cycles. For 16-bit wide

bus cycles, this pin is used as multiplexed address and data.

AD8

Bit 8 of the Address/Data bus. This pin is a dedicated address

pin when operating with 8-bit wide bus cycles. For 16-bit wide

bus cycles, this pin is used as multiplexed address and data.

53

54

55

56

57

58

59

60

TUB

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

---

Bit 7 of the Address/Data bus. This pin is used as multiplexed

address and data for both 8- and 16-bit wide bus cycles.

Bit 6 of the Address/Data bus. This pin is used as multiplexed

address and data for both 8- and 16-bit wide bus cycles.

Bit 5 of the Address/Data bus. This pin is used as multiplexed

address and data for both 8- and 16-bit wide bus cycles.

Bit 4 of the Address/Data bus. This pin is used as multiplexed

address and data for both 8- and 16-bit wide bus cycles.

Bit 3 of the Address/Data bus. This pin is used as multiplexed

address and data for both 8- and 16-bit wide bus cycles.

Bit 2 of the Address/Data bus. This pin is used as multiplexed

address and data for both 8- and 16-bit wide bus cycles.

Bit 1 of the Address/Data bus. This pin is used as multiplexed

address and data for both 8- and 16-bit wide bus cycles.

Bit 0 of the Address/Data bus. This pin is used as multiplexed

address and data for both 8- and 16-bit wide bus cycles.

21

Table 10: 68-lead Flat Pack Pin Descriptions

QFP Pin#

I/O

Name

Active

Description

61²

TUO

RD

Low

Read. The RD signal is an output to external memory that is

only asserted during external memory reads.

62²

TUO

ALE

High

Address Latch Enable. The ALE signal is an output to external

memory that is only asserted during external memory accesses.

ALE is used to specify that valid address information is avail-

able on the address/data bus, and signals the start of a bus cycle.

ALE is used by an external latch to demultiplex the address from

the address/data bus. Setting CCR.3 = 1 enables the ALE func-

tion of pin 62.

TUO

ADV

Low

Address Valid. The ADV signal is an output to external mem-

ory that is only asserted during external memory accesses. ADV

is driven high to specify that valid address information is avail-

able on the address/data bus. The ADV signal is held low during

the data transfer portion of the bus cycle, and is driven high

when the bus cycle completes. ADV is used by an external latch

to demultiplex the address from the address/data bus. Setting

CCR.3 = 0 enables the ADV function of pin 62.

63

64

TDO

INST

High

Instruction Fetch. The INST signal indicates the type of external

memory cycle being performed. The INST signal will be high

during instruction fetches, and will be low for data fetches.

Note: CCB bytes and Interrupt vectors are considered data.

TI

BUSWIDTH

---

Bus Width. The BUSWIDTH pin dynamically modifies the

width of bus cycles. When a high logic value is supplied, the

bus width will be set to 16-bits wide. When a low logic level is

supplied, the bus width will be set to 8-bits wide.

Setting CCR.1 = 1 enables the BUSWIDTH pin. Setting

CCR.1 = 0 disables the BUSWIDTH pin. As a result, the

UT80CRH196KD will only perform 8-bit wide bus cycles.

65

66

TUO

GND

CLKOUT

---

Clock Output. The CLKOUT signal is the output of the internal

clock. This signal has a 50% duty cycle, and runs at 1/2 the fre-

quency of the system clock input to XTAL1. Setting IOC3.1 = 0

will enable the CLKOUT output signal.

3

Digital circuit ground (0V). Recommended connection for sig-

nal integrity improvement. There are 4 other V_SSpins, all of

V_SS

which must be connected.

67

68

CI

XTAL1

V_SS

---

External oscillator or clock input to the UT80CRH196KD. The

XTAL1 input is fed to the on-chip clock generator.

GND

Digital circuit ground (0V). There are 4 V_SSpins, all of which

must be connected and one additional recomended V_SSconnec-

tion.

Notes:

1. These pins should be pulled high or low when using EDAC (i.e. EDACEN = 0) to prevent the voltages on these pins from floating to the switching threshold of

the input buffers during long read cycles.

2. These pins must be high on the rising edge of RESET in order to avoid entering any test modes.

3. This pin is a recommended V connection. The remaining 4 V pins are required to be tied to the circuit card ground plane.

SS

22

2.0 RADIATION HARDNESS

enhances the total dose radiation hardness of the field and gate

oxides while maintaining current density and reliability. In

addition, for both greater transient radiation-hardness and latch-

up immunity, the UT80CRH196KD is built on epitaxial

substrate wafers.

The UT80CRH196KD incorporates special design and layout

features and is built on UTMC’s Commercial RadHard^TM

silicon. The Commercial RadHard^TMsilicon is fabricated using

a minimally invasive process module, developed by UTMC, that

RADIATION HARDNESS DESIGN SPECIFICATIONS

Total Dose

1.0E5

25

rads(Si)

MeV-cm²/mg

n/cm²

LET Threshold

Neutron Fluence

1.0E14

3.66E-7

4.9E-4

cm²/bit

Saturated Cross-Section (1Kx8)

Single Event Upset¹

Single Event Latchup¹

Notes:

errors/device day²

MeV-cm²/mg

LET > 128

o

1. Worst case temperature T = 25 C for Single Event Upset and 100 C for Single Event Latchup.

A

2. Adams 90% worst case environment (geosynchronous).

WEIBULL AND DEVICE PARAMETERS FOR ERROR-RATE CALCULATION

SHAPE

PARAMETER

WIDTH

PARAMETER

STRUCTURAL

CROSS-SECTION

ONSET

LET

DEPLETION

FUNNEL

DEPTH

1

14

3.66E-7cm2/bit

14.4MeV-cm2/mg

0.8mm

1.45mm

3.0 ABSOLUTE MAXIMUM RATINGS ¹

(Referenced to V_SS

)

SYMBOL

PARAMETER

LIMITS

-0.3 to 6.0

UNITS

V_DD

DC Supply Voltage

V

2

Voltage on Any Pin

-0.3 to V_DD+0.3V

V_I/O

T_STG

T_J

Storage Temperature

-65 to +150

°C

Maximum Junction Temperature

175

16

Thermal Resistance, Junction-to-Case ³

DC Input Current

Q_JC

°C/W

I_I²

mA

±10

Notes:

1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the

device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

2. These ratings are provided as design guidelines. They are not guaranteed by test or characterization.

3. Test per MIL-STD-883, Method 1012.

23

4.0 DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*

(V_DD= 5.0V ±10% ) (T_C= -55°C to +125°C for "C" screening and -40°C to +125°C for "W" screening)

SYMBOL

PARAMETER

CONDITION

MINIMUM

MAXIMUM UNIT

V_IL

Low-level Input Voltage

(except XTAL1, RESET)

0.8

V

V_IH

High-level Input Voltage

(except XTAL1, RESET)

2.2

V

V_IH1

High-level Input Voltage

(XTAL1)

.7V_DD

V_IL1

V_T+

V_T-

Low-level Input Voltage

(XTAL1)

.3V_DD

.7V_DD

.4V_DD

V

Positive Going Threshold

RESET

.5V_DD

.2V_DD

.9

Negative Going Threshold

RESET

Typical Range of Hysteresis⁶

RESET

V_H

V_OL

V_OH

I_OHI

Low-level Output Voltage

(CMOS load)

I_OL= 200mA⁶

0.3

0.4

V

(TTL load)

I_OL= 4.0mA

High-level Output Voltage⁸

(CMOS load)

I_OH= -200mA⁶

V_DD-.3

3.8

V

(Standard outputs) (TTL load)

I_OH= -4.0mA

High-level Output Current¹

(Open drain outputs with pullups)

V_OH= V_DD- .3

V_OH= V_DD- .9

(see Note 6)

-20

-60

mA

Logical 0 Input Current²

(Test mode entry)

I_IL

I_LI

V_IN= V_IH

-550

-5

-120

+5

mA

I/O Leakage Current, standard

inputs/outputs in Z state

V_IN= V_SSor V_DD

I/O Leakage Current, with pullups³

I/O Leakage Current, with

pulldowns⁴

I_LI1

I_LI2

V_IN= V_SS

V_IN= V_DD

-800

200

-150

1500

mA

Pin Capacitance⁶

C_IO

@ 1MHZ, 25°C

15

pF

AI_DD

Active Power Supply Current

Clk@20MHz, typical program

flow

110

mA

QI_DD

Quiescent Power Supply Current Unloaded -55° to +25°C

Outputs, +125°C

20

1000

6

mA

No Clock +25°C post-rad

I_DDPD

Power Supply Current in Power

Down

No Active I/O, Clk@20MHz

mA

I_DDIDLEPower Supply Current in Idle Mode No Active I/O, Clk@20MHZ

55

65

mA

I_DDRESETPower Supply Current in Reset

CLK @20 MHz, RESET < V_IL

I_OS

Short Circuit output current (except V_DD= 5.5V

for pins listed in Note 5)^6,7

-100

-200

130

Short Circuit output current^5,6,7

I_OS1

V_DD= 5.5V

250

mA

24

Notes:

* Post-radiation performance guaranteed at 25°C per MIL-STD-883.

1. Open-drain outputs with pullups include Port 1, P2.6 and P2.7.

2. Test modes are entered at the RESET rising edge by applying V to one or more of the following pins: TXD, RD, WR, HLDA. To avoid entering a test mode,

IL

ensure that these pins remain above V at the rising edge of RESET.

IH

3. Inputs/outputs with pullup resistors include: RESET, Port 1, P2.0, P2.6, P2.7, WR, BHE, AD0-15, RD, ALE, CLKOUT.

4. Inputs/outputs will pulldown resistors include: NMI, HS0.0-HS0.3, P2.5, INST.

5. The I

spec applies to pins RESET, BHE, R D, CLKOUT.

OS1

6. Tested only at initial qualification and after any design or process changes which may affect this characteristic.

7. Not more than one output may be shorted at a time for maximum duration of one second.

8. For standard outputs not covered by IOH1 spec.

25

5.0 AC CHARACTERISTICS READ CYCLE (Post-Radiation)*

(V_DD= 5.0V ±10%) (T_C= -55°C to +125°C for "C" screening and -40°C to +125°C for "W" screening)

SYMBOL

PARAMETER

MINIMUM

MAXIMUM

UNIT

5

Address VALID to READY setup

2T _OSC- 30

ns

t_AVYV

5

Non-READY time

No upper limit

ns

t_YLYH

1,5

READY hold after CLKOUT low

READY hold after ALE low

Address valid to BUSWIDTH setup

BUSWIDTH hold after CLKOUT low

Address valid to input data valid

RD Active to input data valid

CLKOUT low to input data valid

End of RD to input data float

Data hold after RD inactive

Frequency on XTAL1

0

2T _OSC- 20

3T _OSC- 20

2T _OSC- 30

t_CLYX

1,5

T_OSC

ns

t_LLYX

5

ns

t_AVGV

5

0

ns

t_CLGX

2,5

3T _OSC- 29

T_OSC- 26

ns

t_AVDV

2

5 (see Note 5)

ns

t_RLDV

5

T_OSC- 26

ns

t_CLDV

5

0

T_OSC-10

ns

t_RHDZ

5

0

T_OSC-10

ns

t_RXDX

5

1 (see Note 7)

20 (see Note 6)

Mhz

ns

f_OSC

5

XTAL1 period (1/f_OSC

)

50 (see Note 6) 1000 (see Note 7)

T_OSC

t_XHCH

XTAL1 high to CLKOUT high or low

CLKOUT cycle time

0

+25

ns

6

2T_OSCTypical

t_CLCL

5

CLKOUT high period

T_OSC- 10

T_OSC+10

ns

t_CHCL

t_CLLH

CLKOUT falling edge to ALE rising

ALE falling edge to CLKOUT rising

-5

+15

+10

ns

5

-10

t_LLCH

2, 6

ALE cycle time

4T_OSCTypical

ns

t_LHLH

5

ALE high period

T_OSC- 10

T_OSC- 15

T_OSC+15

t_LHLL

5

Address setup to ALE falling edge

t_AVLL

t_LLAX

t_LLRL

t_RLCL

Address hold after ALE falling edge

ALE falling edge toRD falling edge

RD low to CLKOUT falling edge

RD low period

T_OSC- 20

T_OSC- 5

-5

T_OSC+5

T_OSC+10

+10

ns

2

T_OSC- 5

t_RLRH

3,5

RD rising edge to ALE rising edge

RD low to address float

T_OSC-10

-5

T_OSC+10

+5

ns

t_RHLH

5

t_RLAZ

26

5

ALE falling edge toWR falling edge

T_OSC- 10

T_OSC+10

ns

t_LLWL

t_CLWL

CLKOUT low to WR falling edge

Data stable toWR rising edge

-5

+10

ns

2

T_OSC- 10

T_OSC+10

t_QVWH

5

CLKOUT high to WR rising edge

WR low period

-10

+15

ns

t_CHWH

2,5

T_OSC- 10

T_OSC- 25

T_OSC- 10

T_OSC- 25

t_WLWH

5

Data hold after WR rising edge

WR rising edge to ALE rising edge

BHE, INST after WR rising edge

AD8-15 HOLD after WR rising

BHE, INST after RD rising edge

AD8-15 HOLD afterRD rising

Address valid toEDACEN valid

EDACEN hold after ALE high

Address valid to EDAC input valid

EDAC hold after RD inactive

EDAC output stable to WR rising

EDAC output hold afterWR rising

T_OSC+10

t_WHQX

3,5

t_WHLH

5

t_WHBX

4,5

t_WHAX

5

T_OSC+10

2T_OSC-30

t_RHBX

4,5

t_RHAX

5

t_AVENV

5

0

t_LHENX

2,5

3T_OSC-29

T_OSC-10

T_OSC+10

t_AVEV

5

0

t_RXEX

2,5

T_OSC-10

t_EVWH

5

t_WHEX

Note:

* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1.0E5 rads(Si).

1. If max exceeded, additional wait state occurs.

2. If wait states are used, add 2 T

*N, where N = number of wait states.

OSC

3. Assuming back-to-back bus cycles.

4. 8-bit only

5. Tested only at initial qualification, and after any design or process changes which may affect this characteristic.

6. These specs are verified using functional vectors (strobed) only.

7. Low speed tests performed at 5MHz. 1MHz operation is guaranteed by design.

27

T

OSC

XTAL1

t

CHCL

XHCH

t

CLCL

CLKOUT

t_CLLH

t

LLCH

t

RLCL

t

LHLH

ALE

t

LHLL

RHLH

LLRL

RLRH

READ

t

RHDZ

t

CLDV

t

RLDV

AVLL

LLAX

t

RXDX

t_RLAZ

ADDRESS OUT

DATA

BUS

t

AVDV

t

CHWH

t

WHLH

t

LLWL

WLWH

WRITE

BUS

t

CLWL

t

WHQX

t

QVWH

ADDRESS OUT

DATA OUT

ADDRESS

t

WHBX, RHBX

VALID

BHE, INST

AD8-15

t

WHAX, RHAX

ADDRESS OUT

t

RXEX

AVEV

ECB(5:0) READ

CYCLE

VALID

t

WHEX

ECB(5:0)

VALID

WRITE CYCLE

t

EVWH

Figure 4. System Bus Timings

28

T_OSC

XTAL1

t_XHCH

t_CHCL

t_CLCL

CLKOUT

t_CLYX

t_CLLH

max

t_LLYX

max

t_YLYH

ALE

t_LHLH+ 2T_OSC

t_LLYX

min

READY

READ

t_AVYV

t_CLYX

t_RLRH+ 2T_OSC

min

t_RLDV+ 2T_OSC

t_AVDV+ 2T_OSC

ADDRESS OUT

DATA

BUS

t_WLWH+2T _OSC

WRITE

BUS

ADDRESS

DATA OUT

ADDRESS

t_QVWH+ 2T _OSC

Figure 5. READY Timing (One Wait State)

29

XTAL1

CLKOUT

ALE

t_CLGX

BUSWIDTH

VALID

t_AVGV

ADDRESS OUT

DATA

BUS

t_LHENX

t_AVENV

EDACEN

VALID

Figure 6. BUSWIDTH and EDACEN Timings

30

6.0 XTAL1 CLOCK DRIVE TIMING CHARACTERISTICS

SYMBOL

PARAMETER

Oscillator Frequency

MINIMUM

MAXIMUM

UNIT

1^{(note 1)}

f_OSC

20

MHz

)

1000^{(note 1}

T_OSC

t_OSCH

t_OSCL

t_OSCR

t_OSCF

Oscillator Period

High Time

Low Time

50

ns

17^{(note 1)}

10^{(note 2)}

Rise Time

)

10^{(note 2}

Fall Time

Note:

1. Tested only at initial qualification, and after any design or process changes which may affect this characteristic.

2. Supplied as a design limit, but not guaranteed or tested.

t

OSCH

t

OSCR

OSCF

t

OSCL

0.7 V

DD

0.7 V

DD

0.3V

DD

T

OSC

Figure 7. External Clock Drive Timing Waveforms

31

Table 11. DC Specifications in Hold¹

DESCRIPTION

MIN

MAX

CONDITIONS

Pullups on ADV, RD, WR, WRL, BHE, ALE

Pulldown on INST

6.9K

3.7K

36.7K

V_DD=5.5V, V_IN= V_SS

27.5K

V_DD=5.5V, V_IN= V_DD

Note:

1.Tested only at initial qualification, and after any design or process changes which may affect this characteristic.

7.0 HOLD/HLDA Timings

SYMBOL

PARAMETER

MINIMUM

MAXIMUM

UNIT

1

HOLD Setup

25

ns

t_HVCH

1

CLKOUT low to HLDA low

CLKOUT low to BREQ low

HLDA low to address float

-15

15

10

15

ns

t_CLHAL

1

t_CLBRL

1

t_HALAZ

1

HLDA low to BHE, INST, RD, WR

driven weakly

t_HALBZ

1

CLKOUT low to HLDA high

-15

-10

-5

15

ns

t_CLHAH

1

CLKOUT low to BREQ high

t_CLBRH

1

HLDA high to address no longer float

HLDA high to BHE, INST, RD, WR valid

CLKOUT low to ALE high

t_HAHAX

1

t_HAHBV

1

15

t_CLLH

Note:

1.Tested only at initial qualification, and after any design or process changes which may affect this characteristic.

32

CLKOUT

HOLD

t_HVCH

t_CLHAH

t_CLBRH

t_HAHAX

t_CLHAL

HLDA

t_CLBRL

BREQ

BUS

t_HALAZ

t_HALBZ

t_HAHBV

Weakly Driven Inactive

BHE, INST

RD, WR

t_CLLH

ALE/ADV

Weakly Driven High

Figure 8. DC Specifications In Hold

33

External Clock

Input

XTAL1

UT80CRH196KD

Figure 9. External Clock Connections

V_DD

0.0V

TEST POINTS

1.4V

AC Testing inputs are driven at V_DDfor a Logic “1” and 0.0V for a Logic “0”. Timing measure-

ments are made at 1.4V.

Figure 10. AC Testing Input, Output Waveforms

V_OH- 0.5V

V_LOAD

V_OH- 0.5V

TIMING REFERENCE

POINTS

V_OL+ 0.5V

For timing purposes a port pin is no longer floating when it changes to a voltage outside the ref-

erence points shown and begins to float when it changes to a voltage inside the reference points

shown. I_OL= 4mA, I_OH= -4mA.

Figure 11. Float Waveforms

34

Table 12. Serial Port Timing

PARAMETER MINIMUM

SYMBOL

MAXIMUM

UNIT

2

Serial port clock period (BRR > 8002H)

6 T_OSCtypical

ns

t_XLXL

1

Serial port clock falling edge to rising edge

(BRR > 8002H)

4 T_OSC-50

4 T_OSC+50

ns

t_XLXH

2

Serial port clock period (BRR = 8001H)

4 T_OSCtypical

ns

t_XLXL

1

Serial port clock falling edge to rising edge

(BRR = 8001H)

2 T_OSC-50

2 T_OSC+50

t_XLXH

1

Output data valid to clock rising edge

Output data hold after clock rising edge

Next output data valid after clock rising edge

Input data setup to clock rising edge

Input data hold after clock rising edge

Last clock rising to output float

2 T_OSC-50

ns

t_QVXH

1

t_XHQX

1

2 T_OSC+50

t_XHQV

1

T_OSC+50

0

t_DVXH

1

t_XHDX

1

2 T_OSC-10

2 T_OSC+10

t_XHQZ

Note:

1.Tested only at initial qualification, and after any design or process changes which may affect this characteristic.

2. These specs are verified using functional vectors (strobed) only.

T_XLXL

TXD

t_QVXH

t_XLXH

t_XHQX

t_XHQV

t_XHQZ

RXD (OUT)

RXD (IN)

0

1

2

3

4

5

6

7

t_DVXH

1

0

2

3

4

5

6

7

t_XHDX

Figure 12. Serial Port Waveform - Shift Register Mode

35

APPENDIX A

Difference Between Industry Standard and UT80CRH196KD

1.0 UT80CRH196KD DIFFERENCES TO INDUSTRY

reading bits 3 through 0 of the EDAC_CS Register tells you

how many single bit errors have been corrected. The EDAC_CS

Register is located at location 15h of HWindow 1.

STANDARD 80C196KD

1.1 Analog to Digital Converter

1.8 Instruction Queue

The Analog to Digital Converter will not be implemented in the

UT80CRH196KD.

The instruction queue is eight bytes deep instead of four. The

instruction queue also interfaces to the CPU through a 16-bit

bus. This configuration will speed up the operation of the

UT80CRH196KD.

1.3 Clocking

The XTAL2 output is not used and the UT80CRH196KD

expects the input on the XTAL 1 to be a valid digital clock signal.

The clock should be stable before reset is removed or Power

Down mode is exited. In Power Down mode, a small number

of gates will be clocked by the XTAL1 input. The

1.9 WDT and Prescalar

TheWDTcannowbedisabledthroughthesoftware. Thedisable

feature should allow the user flexibility in using the Watch Dog

Timer. The WDT also now has a prescalar which can slow down

UT80CRH196KD XTAL2 has been replaced with a V_SSpin.

the counter by a factor of 2⁰to 2⁷. The prescalar will give the

user extra time between clears of the WDT. The WDT prescaler

(WDT_SCALE) is located at location 0Dh of HWindow 1.

1.4 CCB Read after Reset

The CCB fetch after Reset will be a normal fetch as if the chosen

bus width is selectable based on the BUSWIDTH input. Systems

with an 8-bit wide interface should tie BUSWIDTH to ground.

Systems that use BUSWIDTH should perform a normal decode

based on the memory configuration of the system. The Industry

Standard 80C196KD treats the CCB fetch as an 8-bit fetch

(driving the upper 8-bits with address 20H) regardless of the

state of BUSWIDTH.

1.10 Interrupt Priority Levels

An additional level of priority encoding is available to the user.

Every standard interrupt can be programed to a higher level of

priority. All interrupts in the higher priority will maintain their

relative priority, but low priority interrupts can then be

programmed for a higher interrupt priority if necessary. The

interrupt priority register is 16-bits wide, and maps to the

standard interrupts in the same fashion as the INT_MASK and

INT_MASK1 registers. The high byte of the Interrupt Priority

Register (IN_PRI(hi)) is located at 0Bh of HWindow 1, and the

low byte (INT_PRI(lo)) is located at 0Ah of HWindow 1.

1.5 Internal Program Memory

The UT80CRH196KD does not have internal program memory,

and pin 2 (EA) will be ignored for choosing between internal

and external program reads. The user may tie this pin to ground

for compatibility reasons, unless EDAC is enabled.

1.11 Faster Multiply and Divide

1.6 Ports 3 and 4

The multiplier and divider have been optimized to perform their

operations in fewer state times than in the current version.

Since the UT80CRH196KD will not have internal program

memory, Ports 3 and 4 will always be used as the multiplexed

Address and Data bus. Therefore, these ports will not be

configured as I/O ports, and the bidirectional port function of

these pins will not be implemented. The pins will only be

configured as Address and bidirectional data pins.

1.12 Instructions State Time Reduction

The CPU has been streamlined for faster execution where

possible. Examples include 1 state reduction for WORD

immediate instructions, 1 state reductions for long indexed

instructions, and state reductions for the BMOV instructions.

1.7 Built in EDAC

1.13 STACK_PNTR implemented as Special Function

Register

The UT80CRH196KD incorporates a built in Error Detection

and Correction circuit for external memory reads and writes.

The EDAC can be controlled from an external pin. The external

pin (Pin 37) can be used to enable or disable this feature

interactively. Therefore, different regions of external memory

can be assigned to have EDAC as necessary. Additionally, the

EDAC check bits will be passed through Port 0, which varies

from the industry standard version where Port 0 is an input only

port. You can control the interrupt behavior of the EDAC engine

by setting bits 6 and 5 of the EDAC Control and Status Register

(EDAC_CS). Additionally, reading bit 4 of the EDAC_CS

allows you to determine if a double bit error occurred, and

The STACK_PNTR has been implemented as a true Special

Function Register instead of in the RAM to allow for quicker

pushes and pops. If the stack is not used, the SFR can be used

for general purpose data storage.

1.14 Timer3

An additional 16-bit timer/counter has been implemented as a

general purpose timer that can be used if Timer1 and Timer 2

are being dedicated to other functional uses. The current value

36

of Timer3 can be found in locations 0Fh (high byte), and 0Eh

(low byte) of HWindow 1.

PROCESSING FLOW FOR THE ST R0, [R0]+

INSTRUCTION

1.15 Input/Output Pullup/Pulldown Currents

UT80CRH196KD

Address = [R0]; 1000h

R0 ---> Address

Industry Standard

Address = [R0]; 1000h

R0 = R0+1; 1001h

R0 ---> Address

Leakage currents may not meet the industry standard specs due

to differently sized weak pullups/pulldowns, during Quasi-

Bidirectional and reset/powerdown modes. Refer to specs for

I_LI1and I_LI2

.

R0 = R0+1; 1001h

* The contents in address

1000h are 1000h

* The contents in address

1000h are 1001h

1.16 Power-down exit

Pin 37 will not be used to exit power-down mode. Since a digital

clock is supplied, no connection between this V_pppin and the

power-down circuitry exists.

1.23 AC Timing Differences

There are some AC timing differences between the

1.17 Test Mode Entry

UT80CRH196KD and the industry standard 80C196KD. Most

changes resulted in loosened timing specifications. However,

the t_RHDZand t_RXDXtiming specifications were tightened by

Test mode entry will be via four pins: WR, RD, ALE andHLDA

instead of PWM0.

1.18 Power-on Reset

5ns. If you have been designing to the industry standard timing

specifications, it is important to recognize these two shortened

timing specifications.

The UT80CRH196KD will not guarantee the 16-state "pulse

stretching" function of a Reset_n pulse applied at power-up. The

user must hold Reset_n low until the power and clocks stabilize

plus 16-state times, or provide a high to low transition after the

power and clocks have stabilized.

NOTE: Please visit the UTMC website at www.utmc.com to

obtain the latest data sheet updates, application notes, software

examples, advisories and erratas for the UT80CRH196KD.

1.19 Pullup/Pulldown states

1.24 T2UP-DN Input Signal

The INST pin will be driven to a weak low during Reset. The

ALE signal will be driven to a weak high during Bus Hold.

Port 2.6 has an alternate function of T2UP-DN enabled by

IOC2.1. The industry standard device appears to allow writes

into Port 2.6 to directly affect the pin state when in the T2UP-

DN mode. (This would allow software control of the T2 direc-

tion, but requires ensuring a one (QBD pullup) is written to

Port 2.6 if the pin is driven externally). The UT80CRH196KD

device is designed to disable the Port 2.6 output when T2UP-

DN is enabled. This protects the P2.6/T2UP-DN pin from con-

tention with an externally driven signal, independent of the

value written into Port 2.

1.20 Modifying the INT_PEND registers

Two operand rd-modify-wr instructions should be used to

modify the INT_PEND registers. Three operand rd-modify-wr

instructions may lose an incoming interrupt.

1.21 Serial Port Synchronous Mode

The last clock rising edge to output float time (T_XHQZ) is made

consistent with the output data hold (T_XHQX) time of 2 T_OSC

+/-50nsec. This is longer than the industry standard of 1 T_OSC

max.

1.25 NEG 8000h Instruction Operation

1.22 Industry Standard Register Indirect with Auto Incre-

ment

The UT80CRH196KD and the industry standard 80C196KD

set the N-Flag differently when executing the NEG 8000h

instruction. NEG represents the MCS-96 opcode to negate a

defined operand (8000h). When the UT80CRH196KD exe-

cutes the NEG 8000h instruction, the result becomes 8000h

with both the N-Flag and the V-Flag set. The industry stan-

dard 80C196KD, however, executes the NEG 8000h instruc-

tion with a result of 8000h and only the V-Flag set.

The industry standard increments the auto-incremented regis-

ter after determining the external address instead of at the end

of the instruction completion. The UT80CRH196KD performs

the auto-increment function at the end of the instruction pro-

cessing. Please reference the example below that shows the

processing difference between the UT80CRH196KD and the

industry standard:

ST R0, [R0]+

assume R0 holds the value 1000h before the instruction is exe-

cuted.

1.26 Reserved Opcode EEH

The industry standard 80C196KD using the MCS-96 ISA

declares the opcode EEH as a reserved opcode and does not

37

guarantee the generation of the Unimplemented Opcode Inter-

rupt. The UT80CRH196KD, on the other hand, generates the

Unimplemented Opcode Interrupt when the EEH opcode is

executed.

1.29 BREQ Activation Prior to HLDA

The BREQ signal is used by the UT80CRH196KD to signal a

DMA arbiter that it would like to recover access to the mem-

ory bus. The UT80CRH196KD, on the other hand, uses the

HLDA signal to provide confirmation to the DMA arbiter that

the UT80CRH196KD has relinquished control of the memory

bus. If the wait state control signal (READY) is high when the

UT80CRH196KD decides it will release the bus based on the

assertion of the HOLD signal, it will drive the BREQ low one

CLKOUT cycle ahead of its assertion of the HLDA. Con-

versely, if the READY signal is low when the

UT80CRH196KD decides to relinquish the bus, it will assert

BREQ coincidently withHLDA or some CLKOUT cycle

later. The latter behavior is compatible with the industry stan-

dard 80C196KD functionality, but the former is unique to the

UT80CRH196KD.

1.27 Byte-Wide Reads of the HSI_Time SFR

In order to ensure that the next HSI event is loaded from the

FIFO into the HSI holding register, the HSI_TIME special

function register must be read as a 16-bit word. Byte-wide

reads of the HSI_TIME register will not result in successful

loading of the HSI holding register.

1.28 BMOV and BMOVI Maximum Count Limitation

The BMOV and BMOVI instructions provide a powerful

method to transferring a large block of data from one location

in memory to another. The syntax for the BMOV and BMOVI

instructions are as follows:

1.30 HOLD Must Be Synchronized with CLKOUT

The DMA arbiter must synchronize the HOLD signal with the

CLKOUT on the UT80CRH196KD. The timing diagram in

Figure 8 eludes to the synchronicity of the HOLD signal, but

does not clearly identify the outcome if the HOLD signal does

not satisfy the timing parameter t_HVCH. If the HOLD setup

BMOV

SRC_DEST_REG, CNTREG

BMOVI

SRC_DEST_REG, CNTREG

time is violated on the industry standard 80C196KD, it will

require one additional CLKOUT cycle before it recognizes the

state change of HOLD. Violating the HOLD setup time on the

UT80CRH196KD will result in a metastable condition and the

UT80CRH196KD’s reaction is undefined.

The SRC_DEST_REG is a long register that contains both

addresses for the source and destination blocks. The CNTREG

is a 16-bit register specifying the number of transfers being

performed. Unlike the industry standard 80C196KD which

will accept any 16-bit counter value, the UT80CRH196KD

will only accept a value in the range of 0000H to 3FFFH.

38

8.0 PACKAGE

Notes:

1. All package finishes are per MIL-PRF-38535.

2. Letter designations are for cross-reference to MIL-STD-1835.

3. All leads increase max. limit by 0.003 measured at the

center of the flat, when lead finish A (solder) is applied.

4. ID mark: Configuration is optional.

5. Lettering is not subject to marking criteria.

6. Total weight is approx. 8.0 grams.

7. All dimensions are in inches.

Figure 14. 68-lead Quad Flatpack

39

ORDERING INFORMATION

UT80CRH196KD 16-Bit Microcontroller: SMD

5962 R 98583 **

*

Lead Finish: (Note 1,2)

(A)

(C)

=

Solder

Gold

(X)

=

Optional

Case Outline:

(X) 68-lead top brazed flatpack

=

Class Designator: (Note 3)

(Q)

(V)

=

Class Q

Class V

Device Type

(01) = 20 Mhz, 16-bit microcontroller, Mil-Temp

o

(02) = 20 Mhz, 16-bit microcontroller, Extended Industrial Temp (-40 C to +125 C)

Drawing Number: 98583

Total Dose:

(R)

=

1E5 rads(Si)

Federal Stock Class Designator: No options

Notes:

1. Lead finish (A, C, or X) must be specified.

2. If an “X” is specified when ordering, part number will match the lead finish and will be either “A” (solder) or “C” (gold).

3. Total dose radiation must be specified when ordering. QML V is not available without radiation testing.

40

UT80CRH196KD Microcontroller

UT80CRH196KD - *

*

Lead Finish: (Note 1,2)

(A)

(C)

(X)

=

Solder

Gold

Optional

Screening: (Note 3,4,5)

(C)

(P)

=

Mil Temp

Prototype

o

(W)

=

Extended Industrial Temp (-40 C to +125 C)

Package Type:

(W) 68-lead top brazed Flatpack

=

UTMC Core Part Number

Notes:

1. Lead finish (A,C, or X) must be specified.

2. If an “X” is specified when ordering, then the part number will match the lead finish and will be either “A” (solder) or “C” (gold).

o

3. Military Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested -55 C, room temp, and 125 C. Radiation neither

tested nor guaranteed.

o

4. Prototype flow per UTMC Manufacturing Flows Document Tested at 25 C only. Lead finish is gold only. Radiation is neither tested nor guaranteed.

o

5. Extended Industrial Temperature Range Flow per UTMC Manufacturing Flows Document. Devices are tested at -40 C, room temp, and +125 C.

Radiation is neither tested nor guaranteed.

41

Notes

42

Notes

43

型号	制造商	描述	价格	文档
5962R9858301QXX	AEROFLEX	20MHz 16-bit Microcontroller	获取价格
5962R9858301QXXA	AEROFLEX	20MHz 16-bit Microcontroller	获取价格
5962R9858301QXXC	AEROFLEX	20MHz 16-bit Microcontroller	获取价格
5962R9858301V9A	ETC	Microcontroller	获取价格
5962R9858301VXA	AEROFLEX	20MHz 16-bit Microcontroller	获取价格
5962R9858301VXC	AEROFLEX	20MHz 16-bit Microcontroller	获取价格
5962R9858301VXX	AEROFLEX	20MHz 16-bit Microcontroller	获取价格
5962R9858301VXXA	AEROFLEX	20MHz 16-bit Microcontroller	获取价格
5962R9858301VXXC	AEROFLEX	20MHz 16-bit Microcontroller	获取价格
5962R9858302Q9A	ETC	Microcontroller	获取价格

5962R9858301QXC

5962R9858301QXC 概述

5962R9858301QXC 数据手册

5962R9858301QXC 相关器件

5962R9858301QXC 相关文章

热门型号