ACT-F512K32N-090F5T [AEROFLEX]
ACT-F512K32 High Speed 16 Megabit FLASH Multichip Module; ACT- F512K32高速16兆位闪存多芯片模块
| 型号： | ACT-F512K32N-090F5T |
| 厂家： | 
AEROFLEX CIRCUIT TECHNOLOGY |
| 描述： | ACT-F512K32 High Speed 16 Megabit FLASH Multichip Module |
| 文件： | 总20页 (文件大小：239K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACT–F512K32 High Speed
16 Megabit FLASH Multichip Module
CIRCUIT TECHNOLOGY
www.aeroflex.com
Features
■ 4 Low Power 512K x 8 FLASH Die in One MCM
Package
■ Industry Standard Pinouts
■ Packaging – Hermetic Ceramic
■ TTL Compatible Inputs and CMOS Outputs
■ Access Times of 60, 70, 90, 120 and 150ns
■ +5V Programing, 5V 10ꢀ Supply
■ 100,000 Erase/Program Cycles
■ Low Standby Current
■ Page Program Operation and Internal Program
Control Time
■ Sector Architecture (Each Die)
● 68 Lead, .88" x .88" x .160" Single-Cavity Small
Outline gull wing, Aeroflex code# "F5" (Drops into
the 68 Lead JEDEC .99"SQ CQFJ footprint)
● 66 Pin, 1.08" x 1.08" x .160" PGA Type, No
Shoulder, Aeroflex code# "P3"
● 66 Pin, 1.08" x 1.08" x .185" PGA Type, With
Shoulder, Aeroflex code# "P7"
■ Internal Decoupling Capacitors for Low Noise
Operation
● 8 Equal size sectors of 64K bytes each
● Any Combination of Sectors can be erased with
one command sequence
■ Commercial, Industrial and Military Temperature
Ranges
■ DESC SMD# 5962–94612
Released (P3,P7,F5)
● Supports full chip erase
■ Embedded Erase and Program Algorithms
■ MIL-PRF-38534 Compliant MCMs Available
Block Diagram – PGA Type Package(P3,P7) & CQFP(F5)
General Description
The ACT–F512K32 is a high
speed, 16 megabit CMOS flash
WE1 CE1 WE2 CE2 WE3 CE3 WE4 CE4
multichip
module
(MCM)
designed for full temperature
range military, space, or high
reliability applications.
OE
A0 – A18
512Kx8
512Kx8
512Kx8
512Kx8
The MCM can be organized
as a 512K x 32bits, 1M x 16bits
or 2M x 8bits device and is input
8
8
8
8
TTL
and
output
The
CMOS
compatible.
command
I/O0-7
I/O8-15
I/O16-23
I/O24-31
register is written by bringing
WE to a logic low level (VIL),
while CE is low and OE is at
logic high level (VIH). Reading is
accomplished by chip Enable
(CE) and Output Enable (OE)
being logically active, see
Figure 9. Access time grades of
60ns, 70ns, 90ns, 120ns and
150ns maximum are standard.
Pin Description
I/O0-31 Data I/O
A0–18 Address Inputs
WE1-4 Write Enables
CE1-4 Chip Enables
OE
VCC
GND
Output Enable
Power Supply
Ground
The
ACT–F512K32
is
packaged in a hermetically
NC Not Connected
eroflex Circuit Technology - Advanced Multichip Modules © SCD1665 REV B 6/29/01
General Description, Cont’d,
sealed co-fired ceramic 66 pin, 1.08"SQ PGA executing the erase command sequence. This
or a 68 lead, .88"SQ Ceramic Gull Wing CQFP will invoke the Embedded Erase Algorithm
package for operation over the temperature which is an internal algorithm that
range of -55°C to +125°C and military automatically preprograms the array, (if it is not
environment.
already programmed) before executing the
erase operation. During erase, the device
automatically times the erase pulse widths and
verifies proper cell margin.
Each flash memory die is organized as
512KX8 bits and is designed to be
programmed in-system with the standard
system 5.0V Vcc supply. A 12.0V VPP is not
Each die in the module or any individual
required for write or erase operations. The sector of the die is typically erased and verified
MCM can also be reprogrammed with standard in 1.5 seconds (if already completely
EPROM programmers (with the proper socket).
preprogrammed).
The standard ACT–F512K32 offers access
Each die also features a sector erase
A
times between 60ns and 150ns, allowing architecture. The sector mode allows for 64K
operation of high-speed microprocessors byte blocks of memory to be erased and
without wait states. To eliminate bus reprogrammed without affecting other blocks.
contention, the device has separate chip The ACT-F512K32 is erased when shipped
enable (CE) and write enable (WE). The from the factory.
ACT-F512K32 is command set compatible with
The device features single 5.0V power
JEDEC standard
4
Mbit
EEPROMs.
supply operation for both read and write
functions. lnternally generated and regulated
voltages are provided for the program and
erase operations. A low VCC detector
automatically inhibits write operations on the
loss of power. The end of program or erase is
detected by Data Polling of D7 or by the Toggle
Bit feature on D6. Once the end of a program
or erase cycle has been completed, the device
Commands are written to the command
register using standard microprocessor write
timings. Register contents serve as input to an
internal state-machine which controls the
erase and programming circuitry. Write cycles
also internally latch addresses and data
needed for the programming and erase
operations.
Reading data out of the device is similar to internally resets to the read mode.
reading from 12.0V Flash or EPROM devices.
All bits of each die, or all bits within a
The ACT-F512K32 is programmed by
executing the program command sequence.
This will invoke the Embedded Program
Algorithm which is an internal algorithm that
automatically times the program pulse widths
and verifies proper cell margin. Typically, each
sector can be programmed and verified in less
than one second. Erase is accomplished by
sector
of
a
die,
are
erased
Bytes
via
Fowler-Nordhiem
tunneling.
are
programmed one byte at a time by hot electron
injection.
DESC Standard Military Drawing (SMD)
numbers are released.
2
Aeroflex Circuit Technology
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
z
Absolute Maximum Ratings
Parameter
Symbol
TC
Range
Units
°C
-55 to +125
-65 to +150
-2.0 to +7.0
Case Operating Temperature
Storage Temperature Range
Supply Voltage Range
TSTG
VCC
°C
V
VG
-2.0 to +7.0
300
V
°C
Signal Voltage Range (Any Pin Except A9) Note 1
Maximum Lead Temperature (10 seconds)
Data Retention
-
-
10
Years
-
100,000 Minimum
-2.0 to +14.0
Endurance (Write/Erase cycles)
A9 Voltage for sector protect, Note 2
VID
V
Note 1. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may undershoot VSS to -2.0v for periods of up to
20ns. Maximum DC voltage on input and I/O pins is VCC + 0.5V. During voltage transitions, inputs and I/O pins may overshoot to
VCC + 2.0V for periods up to 20 ns.
Note 2. Minimum DC input voltage on A9 is -0.5V. During voltage transitions, A9 may undershoot VSS to -2.0V for periods of up to 20ns.
Maximum DC input voltage on A9 is +12.5V which may overshoot to 14.0V for periods up to 20ns.
Normal Operating Conditions
A
Symbol Parameter
Minimum
Maximum
Units
VCC
VIH
VIL
TA
+4.5
+5.5
V
Power Supply Voltage
Input High Voltage
+2.0
-0.5
-55
V
+ 0.5
V
V
CC
+0.8
Input Low Voltage
+125
12.5
°C
V
Operating Temperature (Military)
A9 Voltage for sector protect
VID
11.5
Capacitance
(VIN= 0V, f = 1MHz, Tc = 25°C)
Symbol Parameter
Maximum
Units
CAD
COE
CWE
50
50
pF
pF
A0 – A16 Capacitance
OE Capacitance
Write Enable Capacitance
CQFP(F5) Package
20
20
20
20
pF
pF
pF
pF
PGA(P3,P7) Package
Chip Enable Capacitance
I/O0 – I/O31 Capacitance
CCE
CI/O
Parameters Guaranteed but not tested
DC Characteristics – CMOS Compatible
(Vcc = 5.0V, Vss = 0V, TC = -55°C to +125°C, unless otherwise indicated)
Speeds 60, 70, 90, 120 & 150ns
Parameter
Sym
Conditions
Minimum
Maximum
Units
ILI
ILOX32
ICC1
ICC2
ICC4
ICC3
VOL
10
µA
Input Leakage Current
VCC = 5.5V, ViN = GND to VCC
VCC = 5.5V, ViN = GND to VCC
CE = VIL, OE = VIH, f = 5MHz
CE = VIL, OE = VIH
10
190
240
6.5
µA
mA
mA
mA
mA
V
Output Leakage Current
Active Operating Supply Current for Read (1)
Active Operating Supply Current for Program or Erase (2)
Standby Supply Current
VCC = 5.5V, CE = VIH, f = 5MHz
VCC = 5.5V, CE = VIH
0.6
Static Supply Current (4)
0.45
Output Low Voltage
IOL = +8.0 mA, VCC = 4.5V
IOH = –2.5 mA, VCC = 4.5V
VOH
0.85 x VCC
3.2
V
Output High Voltage
VLKO
4.2
V
Low Power Supply Lock-Out Voltage (4)
Note 1. The Icc current listed includes both the DC operating current and the frequency dependent component (At 5 MHz). The frequency
component typically is less than 2 mA/MHz, with OE at VIN.
Note 2. Icc active while Embedded Algorithm (Program or Erase) is in progress.
Note 3. DC Test conditions: VIL = 0.3V, VIH = VCC - 0.3V, unless otherwise indicated
Note 4. Parameter Guaranteed but not tested.
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Aeroflex Circuit Technology
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
AC Characteristics – Read Only Operations
(Vcc = 5.0V, Vss = 0V, TC = -55°C to +125°C)
Symbol –60
JEDEC Stand’d Min Max Min Max Min Max Min Max Min Max
–70
–90
–120
–150
Parameter
Units
tAVAV
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tAXQX
tRC
tACC
tCE
60
70
90
120
150
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
60
60
30
20
20
70
70
35
20
20
90
90
35
20
20
120
120
50
150
150
55
Address Access Time
Chip Enable Access Time
tOE
tDF
Output Enable to Output Valid
30
35
Chip Enable to Output High Z (1)
Output Enable High to Output High Z (1)
Output Hold from Address, CE or OE Change, Whichever is First
Note 1. Guaranteed by design, but not tested.
tDF
30
35
tOH
0
0
0
0
0
AC Characteristics – Write/Erase/Program Operations, WE Controlled
(Vcc = 5.0V, Vss = 0V, TC = -55°C to +125°C)
Symbol –60 –70
–90
–120
–150
Parameter
Units
JEDEC Stand’d Min Max Min Max Min Max Min Max Min Max
tAVAC
tELWL
tWLWH
tAVWL
tWC
tCE
tWP
tAS
60
0
70
0
90
0
120
0
150
0
ns
ns
Write Cycle Time
A
Chip Enable Setup Time
Write Enable Pulse Width
Address Setup Time
40
0
45
0
45
0
50
0
50
0
ns
ns
tDVWH
tWHDX
tWLAX
tDS
40
0
45
0
45
0
50
0
50
0
ns
Data Setup Time
tDH
tAH
tWPH
ns
Data Hold Time
45
20
45
20
45
20
50
20
50
20
ns
Address Hold Time
tWHWL
tWHWH1
tWHWH2
tWHWH3
ns
Write Enable Pulse Width High
Duration of Byte Programming
Sector Erase Time
14 TYP 14 TYP 14 TYP 14 TYP 14 TYP
µs
30
30
30
30
30
Sec
Sec
µs
120
120
120
120
120
Chip Erase Time
tGHWL
0
0
0
0
0
Read Recovery Time before Write (2)
Vcc Setup Time (2)
tVCE
50
50
50
50
50
µs
50
50
50
50
50
Sec
ns
Chip Programming Time
Output Enable Setup Time (2)
Output Enable Hold Time (1) (2)
tOES
tOEH
0
0
0
0
0
10
10
10
10
10
ns
Notes: 1. For Toggle and Data Polling. 2. Guaranteed by design, but not tested.
AC Characteristics – Write/Erase/Program Operations, CE Controlled
(Vcc = 5.0V, Vss = 0V, TC = -55°C to +125°C)
Symbol –60 –70
JEDEC Stand’d Min Max Min Max Min Max Min Max Min Max
–90
–120
–150
Parameter
Units
tAVAC
tWLEL
tELEH
tWC
tWS
tCP
60
0
70
0
90
0
120
0
150
0
ns
ns
Write Cycle Time
Write Enable Setup Time
Chip Enable Pulse Width
Address Setup Time
40
0
45
0
45
0
50
0
50
0
ns
tAVEL
tAS
ns
tDVEH
tDS
40
0
45
0
45
0
50
0
50
0
ns
Data Setup Time
tEHDX
tDH
tAH
tCPH
ns
Data Hold Time
tELAX
45
20
45
20
45
20
50
20
50
20
ns
Address Hold Time
tEHEL
ns
Chip Enable Pulse Width High
Duration of Byte Programming Operation
Sector Erase Time
tWHWH1
tWHWH2
tWHWH3
14 TYP 14 TYP 14 TYP 14 TYP 14 TYP
µs
30
30
30
30
30
Sec
Sec
µs
120
120
120
120
120
Chip Erase Time
t
GHEL
0
0
0
0
0
Read Recovery Time Before Write (1)
Chip Programming Time
1. Guaranteed by design, but not tested.
50
50
50
50
50
Sec
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SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
If the device is deselected during erasure or
programming, the device will draw active current until the
operation is completed.
Device Operation
The ACT-F512K32 MCM is composed of four, four
megabit Flash chips. The following description is for the
individual flash device, is applicable to each of the four
memory chips inside the MCM. Chip 1 is distinguished by
CE1 and I/O1-7, Chip 2 by CE2 and I/08-15, Chip 3 by CE3
and I/016-23, and Chip 4 by CE4 and I/024-31.
WRITE
Device erasure and programming are accomplished via
the command register. The contents of the register serve
as input to the internal state machine. The state machine
outputs dictate the function of the device.
Programming of the ACT-F512K32 is accomplished by
executing the program command sequence.
The
program algorithm, which is an internal algorithm,
automatically times the program pulse widths and verifies
proper cell status. Sectors can be programed and
verified in less than one second. Erase is accomplished
by executing the erase command sequence. The erase
algorithm, which is internal, automatically preprograms
the array if it is not already programed before executing
The command register itself does not occupy an
addressable memory location. The register is a latch
used to store the command, along with address and data
information needed to execute the command. The
command register is written by bringing WE to a logic low
level (VIL), while CE is low and OE is at VIH. Addresses
are latched on the falling edge of WE or CE, whichever
happens later. Data is latched on the rising edge of the
the erase operation.
During erase, the device
automatically times the erase pulse widths and verifies
proper cell status. The entire memory is typically erased
and verified in 1.5 seconds (if pre-programmed). The
sector mode allows for 64K byte blocks of memory to be
erased and reprogrammed without affecting other blocks.
WE or CE whichever occurs first.
Standard
A
microprocessor write timings are used. Refer to AC
Program Characteristics and Waveforms, Figures 3,
8 and 13.
Command Definitions
Bus Operation
Device operations are selected by writing specific
address and data sequences into the command register.
Table 3 defines these register command sequences.
READ
The ACT-F512K32 has two control functions, both of
which must be logically active, to obtain data at the
outputs. Chip Enable (CE) is the power control and
should be used for device selection. Output-Enable (OE)
is the output control and should be used to gate data to
the output pins of the chip selected. Figure 7 illustrates
AC read timing waveforms.
READ/RESET COMMAND
The read or reset operation is initiated by writing the
read/reset command sequence into the command
register. Microprocessor read cycles retrieve array data
from the memory. The device remains enabled for reads
until the command register contents are altered.
The device will automatically power-up in the read/reset
state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will
OUTPUT DISABLE
With Output-Enable at a logic high level (VIH), output from
the device is disabled. Output pins are placed in a high
impedance state.
retrieve array data.
The device will automatically
power-up in the read/reset state. In this case, a
command sequence is not required to read data.
Standard Microprocessor read cycles will retrieve array
data. This default value ensures that no spurious
alteration of the memory content occurs during the power
transition. Refer to the AC Read Characteristics and
Figure 7 for the specific timing parameters.
STANDBY MODE
The ACT-F512K32 standby mode consumes less than
6.5 mA. In the standby mode the outputs are in a high
impedance state, independent of the OE input.
Table 2 – Sector Addresses Table
Table 1 – Bus Operations
A18 A17 A16
Address Range
00000h – 0FFFFh
10000h – 1FFFFh
20000h – 2FFFFh
30000h – 3FFFFh
40000h – 4FFFFh
50000h – 5FFFFh
60000h – 6FFFFh
70000h – 7FFFFh
Operation
READ
CE OE WE A0 A1 A6 A9
I/O
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
L
H
L
L
X
H
H
H
X
H
L
A0 A1 A6 A9 DOUT
X
X
X
X
X
X
X
X
HIGH Z
HIGH Z
DIN
STANDBY
OUTPUT DISABLE
WRITE
L
A0 A1 A6 A9
ENABLE SECTOR
PROTECT
L
L
VID
L
L
X
L
X
H
X
L
VID
X
VERIFY SECTOR
PROTECT
H
VID Code
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SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
Table 3 — Commands Definitions
Bus
Write
Command
Sequence
First Bus Write Second Bus Write Third Bus Write
Cycle Cycle Cycle
Fourth Bus
Read/Write Cycle
Fifth Bus Write SixthBus Write
Cycle Cycle
Cycles
Required
Addr
Data
F0H
Addr
Data
Addr
Data
Addr
RA
Data
RD
Addr
Data
Addr
Data
Read/Reset
Read/Reset
Autoselect
Byte Program
Chip Erase
Sector Erase
1
4
4
6
6
6
XXXH
5555H
5555H
5555H
5555H
5555H
AAH
AAH
AAH
AAH
AAH
2AAAH
2AAAH
2AAAH
2AAAH
2AAAH
55H
55H
55H
55H
55H
5555H
5555H
5555H
5555H
5555H
F0H
90H
A0H
80H
80H
PA
PD
5555H
5555H
AAH
AAH
2AAAH
2AAAH
55H
55H
5555H 10H
SA 30H
Sector Erase Suspend Erase can be suspended during sector erase with Address (Don’t care), Data (B0H)
Sector Erase Resume Erase can be resumed after suspend with Address (Don’t care), Data (30H)
NOTES:
1. Address bit A15, A16, A17 and A18 = X = Don't Care. Write Sequences may be initiated with A15 in either state.
2. Address bit A15, A16, A17 and A18 = X = Don't Care for all address commands except for Program Address (PA) and Sector Address (SA).
3. RA = Address of the memory location to be read
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse.
SA = Address of the sector to be erased. The combination of A18, A17, A16 will uniquely select any sector.
4. RD = Data read from location RA during read Operation.
A
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.
Chip erase does not require the user to program the
Embedded Erase Algorithm (Figure 4) sequence the
device automatically will program and verify the entire
memory for an all zero data pattern prior to electrical
erase. The chip erase is performed sequentially one
sector at a time. Note: Post Erase data state is all "1"s.
The system is not required to provide any controls or
timings during these operations.
BYTE PROGRAMING
The device is programmed on a byte-byte basis.
Programming is a four bus cycle operation. There are
two "unlock" write cycles. These are followed by the
program set-up command and data write cycles.
Addresses are latched on the falling edge of CE or WE,
whichever occurs later, while the data is latched on the
rising edge of CE or WE whichever occurs first. The
rising edge of CE or WE (whichever occurs first) begins
programming. Upon executing the Embedded Program
Algorithm command sequence the system is not
required to provide further controls or timings. The
device will automatically provide adequate internally
generated program pulses and verify the programmed
cell margin. The automatic programming operation is
completed when the data on D7 is equivalent to data
written to this bit at which time the device returns to the
read mode and addresses are no longer latched.
Therefore, the device requires that a valid address to the
device be supplied by the System at this time. Data
Polling must be performed at the memory location which
is being programmed.
The automatic erase begins on the rising edge of the
last WE pulse in the command sequence and terminates
when the data in D7 is "1" (see Write Operation Status
section - Table 4) at which time the device returns to
read the mode. See Figures 4 and 9.
SECTOR ERASE
Sector erase is a six bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"setup" command. Two more "unlock" write cycles are
then followed by the sector erase command. The sector
address (any address location within the desired sector)
is latched on the falling edge of WE, while the command
(data) is latched on the rising edge of WE. A time-out of
80µs from the rising edge of the last sector erase
command will initiate the sector erase command(s).
Please note: Do not attempt to write an invalid
command sequence during the sector erase operation.
otherwise, it wili terminate the sector erase operation
and the device will reset back into the read mode.
Programming is allowed in any sequence and across
sector boundaries. Beware that a data "0" cannot be
programmed back to a “1". Attempting to do so may
cause the device to exceed programming time limits (D5
= 1) or result in an apparent success, according to the
data polling algorithm, but a read from reset/read mode
will show that the data is still “0". Only erase operations
can convert “0"s to “1"s.
Multiple sectors may be erased concurrently by writing
the six bus cycle operations as described above. This
sequence is followed with writes of the sector erase
command (30H) to addresses in other sectors desired to
be concurrently erased. The time between writes must
be less than 80µs, otherwise that command will not be
accepted. A time-out of 80µs from the rising edge of
the WE pulse for the last sector erase command will
Figure 3, 8 and 13 illustrates the programming algorithm
using typical command strings and bus operations.
CHIP ERASE
Chip erase is a six bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command. Two more"unlock" write cycles are
then followed by the chip erase command.
initiate the sector erase.
If another sector erase
command is written within the 80µs time-out window the
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Aeroflex Circuit Technology
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
timer is reset. Any command other than sector erase
within the time-out window will reset the device to the
read mode, ignoring the previous command string.
Loading the sector erase buffer may be done in any
sequence and with any number of sectors (1 to 8).
VIH or WE = VIH. To initiate a write cycle CE and WE
must be logical zero while OE is a logical one.
POWER-UP WRITE INHIBIT
Power-up of the device with WE = CE = VIL and OE =
VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the
read mode on power-up.
Sector erase does not require the user to program the
device prior to erase.
The device automatically
programs all memory locations in the sector(s) to be
erased prior to electrical erase. When erasing a sector
or sectors the remaining unselected sectors are not
affected. The system is not required to provide any
controls or timings during these operations. Post Erase
data state is all "1"s.
Write Operation Status
D7
DATA POLLING
The automatic sector erase begins after the 80µs time
out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the
data on D7 is “1" at which time the device returns to
read mode. During the execution of the Sector Erase
command, only the Erase Suspend and Erase Resume
commands are allowed. All other commands will reset
the device to read mode. Data Polling must be
performed at an address within any of the sectors being
erased.
The ACT-F512K32 features Data Polling as a method to
indicate to the host that the internal algorithms are in
progress or completed. During the program algorithm,
an attempt to read the device will produce compliment
data of the data last written to D7. During the erase
algorithm, an attempt to read the device will produce a
"0" at the D7 Output. Upon completion of the erase
algorithm an attempt to read the device will produce a
"1" at the D7 Output.
A
For chip Erase, the Data Polling is valid after the rising
edge of the sixth WE pulse in the six write pulse
sequence. For sector erase, the Data Polling is valid
after the last rising edge of the sector erase WE pulse.
Data polling must be performed at a sector address
within any of the sectors being erased and not a
protected sector. Otherwise, the status may not be valid.
Once the algorithm operation is close to being
completed, data pins (D7) change asynchronously while
the output enable (OE) is asserted low. This means that
the device is driving status information on D7 at one
instance of time and then that byte's valid data at the
next instant of time. Depending on when the system
samples the D7 Output, it may read the status or valid
data. Even if the device has completed internal
algorithm operation and D7 has a valid data, the data
outputs on D0 - D6 may be still invalid. The valid data on
D0 - D7 will be read on the successive read attempts.
The Data Polling feature is only active during the
programming algorithm, erase algorithm, or sector erase
time-out.
Data Protection
The ACT-F512K32 is designed to offer protection
against accidental erasure or programming caused by
spurious system level singles that may exist during
power transitions.
During power up the device
automatically resets the internal state machine in the
read mode. Also, with its control register architecture,
alteration of the memory content only occurs after
successful completion of specific multi-bus cycle
command sequences.
The device also incorporates several features to prevent
inadvertent write cycles resulting from Vcc power-up
and power-down transitions or system noise.
LOW Vcc WRITE INHIBIT
To avoid initiation of a write cycle during Vcc power-up
and power-down, a write cycle is locked out for VCC less
than 3.2V (typically 3.7V). If VCC < VLKO, the command
register is disabled and all internal program/erase
circuits are disabled. Under this condition the device will
reset to read mode. Subsequent writes will be ignored
until the Vcc level is greater than VLKO. It is the users
responsibility to ensure that the control pins are logically
correct to prevent unintentional writes when Vcc is
above 3.2V.
See Figures 6 and 10
D6
TOGGLE BIT
The ACT-F512K32 also features the "Toggle Bit" as a
method to indicate to the host system that algorithms
are in progress or completed.
During a program or erase algorithm cycle, successive
attempts to read data from the device will result in D6
toggling between one and zero. Once the program or
erase algorithm cycle is completed, D6 Will stop toggling
and valid data will be read on successive attempts.
During programming the Toggle Bit is valid after the
rising edge of the fourth WE pulse in the four write pulse
sequence. For chip erase the Toggle Bit is valid after the
rising edge of the sixth WE pulse in the six write pulse
WRITE PULSE GLITCH PROTECTION
Noise pulses of less than 5ns (typical) on OE, CE or
WE will not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding anyone of OE = VIL, CE =
7
Aeroflex Circuit Technology
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
sequence. For Sector erase, the Toggle Bit is valid after
the last rising edge of the sector erase WE pulse. The
Toggle Bit is active during the sector time out.
To verify programming of the protection circuitry, the
programming equipment must force VID on address pin
A9 with CE and OE at VIL and WE at VIH. Scanning the
sector addresses (A16, A17, and A18) while (A6, A1, A0)
= (0, 1, 0,) will produce a logical "1" code at device
output D0 for a protected sector. Otherwise the device
will read 00H for unprotected sector. In this mode, the
lower order addresses, except for 0, A1, and A6 are don't
care.
See Figure 1 and 5.
D5
EXCEEDED TIMING LIMITS
D5 will indicate if the program or erase time has
exceeded the specified limits. Under these conditions
D5 will produce a "1". The Program or erase cycle was
not successfully completed. Data Polling is the only
operation function of the device under this condition.
The CE circuit will partially power down the device under
these conditions by approximately 8 mA per chip. The
OE and WE pins will control the output disable functions
as shown in Table 1. To reset the device, write the reset
command sequence to the device. This allows the
system to continue to use the other active sectors in the
device.
It is also possible to verify if a sector is protected during
the sector protection operation. This is done by setting
A6 = CE = OE = VIL and WE = VIH (A9 remains high at
VID). Reading the device at address location XXX2H,
where the higher order addresses (AL8, A17, and A16)
define a particular sector, will produce 01H at data
outputs (D0 - D7) for a protected sector.
SECTOR UNPROTECT
A
The ACT-F512K32 also features a sector unprotect
mode, so that a protected sector may be unprotected to
incorporate any changes in the code. All sectors should
be protected prior to unprotecting any sector.
D3
To activate this mode, the programming equipment must
force Vid on control pins OE, CE, and address pin A9.
The address pins A6, A16, and A12 should be set to VIH.
The unprotection mechanism begins on the falling edge
of the WE pulse and is terminated with the rising edge of
the same.
SECTOR ERASE TIMER
After the completion of the initial sector erase command
sequence the sector erase time-out will begin. D3 will
remain low until the time-out is complete. Data Polling
and Toggle Bit are valid after the initial sector erase
command sequence.
It is also possible to determine if a sector is unprotected
in the system by writing the autoselect command and A6
is set at VIH. Performing a read operation at address
location XXX2H, where the higher order addresses (A18,
A17, and A16) define a particular sector address, will
produce 00H at data outputs (D0-D7) for an unprotected
sector.
If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, D3 may be
used to determine if the sector erase timer window is still
open. If D3 is high ("1") the internally controlled erase
cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or
Toggle Bit. If D3 is low ("0"), the device will accept
additional sector erase commands. To ensure the
command has been accepted, the software should
check the status of D3 prior to and following each
subsequent sector erase command. If D3 were high on
the second status check, the command may not have
been accepted. See Table 4
Sector Protection
Algorithims
SECTOR PROTECTION
The ACT-F512K32 features hardware sector protection
which will disable both program and erase operations to
an individual sector or any group of sectors. To activate
this mode, the programming equipment must force VID
on control pin OE and address pin A9. The sector
addresses should be set using higher address lines A18,
A17, and A16. The protection mechanism begins on the
falling edge of the WE pulse and is terminated with the
rising edge of the same.
8
Aeroflex Circuit Technology
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
Table 4 — Hardware Sequence Flags
Status
D7
D7 Toggle
Toggle
D7 Toggle
Toggle
D6
D5 D3
D2 – D0
0
0
1
1
0
1
1
1
In Progress
Auto-Programming
Programming in Auto Erase
Auto-Programming
Programming in Auto Erase
D
0
Exceeding Time Limits
D
0
Figure 1
AC Waveforms for Toggle Bit During Embedded Algorithm Operations
A
CE
tOEH
WE
tOES
OE
Data
D0-D7
D6
D0-D7
Valid
D6=Toggle
D6=Toggle
Stop Toggle
tOE
Figure 2
AC Test Circuit
Current Source
IOL
Parameter
Typical
0 – 3.0
5
Units
V
VZ ~ 1.5 V (Bipolar Supply)
To Device Under Test
Input Pulse Level
Input Rise and Fall
CL =
ns
50 pF
Input and Output Timing Reference Level
Output Lead Capacitance
1.5
V
IOH
Current Source
50
pF
Notes:
1) VZ is programmable from -2V to +7V. 2) IOL and IOH programmable from 0 to 16 mA. 3) Tester Impedance
ZO = 75Ω. 4) VZ is typically the midpoint of VOH and VOL. 5) IOL and IOH are adjusted to simulate a typical
resistance load circuit. 6) ATE Tester includes jig capacitance.
9
Aeroflex Circuit Technology
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
Figure 3
Programming Algorithm
Bus
Operations
Command
Sequence
Comments
Standby
Write
Program
Valid Address/Data Sequence
Read
Data Polling to Verify Programming
Compare Data Output to Data Expected
Standby
Start
Write Program Command Sequence
(See Below)
A
Data Poll Device
No
Increment
Address
Last Address
?
Yes
Programming Complete
Program Command Sequence (Address/Command):
5555H/AAH
2AAAH/55H
5555H/A0H
Programming Address/Program Data
10
Aeroflex Circuit Technology
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
Bus
Operations
Command
Sequence
Comments
Figure 4
Erase Algorithm
Standby
Write
Erase
Read
Data Polling to Verify Erasure
Compare Output to FFH
Standby
Start
Write Erase Command Sequence
(See Below)
A
Data Poll or Toggle Bit
Successfully Completed
Erasure Completed
Chip Erase Command Sequence
Individual Sector/Multiple Sector
Erase Command Sequence
(Address/Command)
(Address/Command)
5555H/AAH
5555H/AAH
2AAAH/55H
5555H/80H
5555H/AAH
2AAAH/55H
5555H/10H
2AAAH/55H
5555H/80H
5555H/AAH
2AAAH/55H
Sector Address/30H
Sector Address/30H
Sector Address/30H
Additional Sector
Erase Commands
are Optional
11
Aeroflex Circuit Technology
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
Figure 5
Toggle Bit Algorithm
Figure 6
Data Polling Algorithm
Start
Start
VA = Byte Address for Programming
VA = Byte Address for Programming
= Any of the Sector Addresses
within the sector being erased
during sector erase operation
= Any of the Sector Addresses
within the sector being erased
during sector erase operation
Read Byte
D0-D7
Address = VA
Read Byte
D0-D7
Address = VA
= XXXXH during Chip Erase
= XXXXH during Chip Erase
Yes
No
D7 = Data
?
D6 = Toggle
?
No
Yes
No
No
D5 = 1
?
D5 = 1
?
A
Yes
Yes
Read Byte
D0-D7
Address = VA
Read Byte
D0-D7
Address = VA
D6 =
Toggle?
(Note 1)
D7 =
Toggle?
(Note 1)
Yes
No
Pass
Pass
No
Yes
Fail
Fail
Note 1. D6 is rechecked even if D5 = "1" because D6 may stop toggling at
the same time as D5 changes to "1".
Note 1. D7 is rechecked even if D5 = "1" because D7 may change
simultaneously with D5.
12
Aeroflex Circuit Technology
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
Figure 7
AC Waveforms for Read Operations
tRC
Addresses
CE
Addresses Stable
tACC
tDF
OE
WE
tOE
tCE
tOH
High Z
High Z
A
Outputs
Output Valid
Figure 8
Write/Erase/Program
Operation, WE Controlled
Data Polling
Addresses
5555H
PA
PA
tRC
tWC
tAH
tAS
CE
OE
tGHWL
tWP
tWHWH1
tWPH
WE
tCE
tDF
tOE
tDH
AOH
PD
D7
DOUT
Data
5.0V
tDS
tOH
tCE
Notes:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. D7 is the 0utput of the complement of the data written to the deviced.
4. Dout is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
13
Aeroflex Circuit Technology
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
Figure 9
AC Waveforms Chip/Sector
Erase Operations
Data Polling
5555H
tAH
5555H
2AAAH
5555H
2AAAH
SA
Addresses
tAS
CE
OE
WE
tGHWL
tWP
tWPH
A
tCE
tDH
AAH
55H
80H
AAH
55H
10H/30H
Data
VCC
tDS
tVCE
Notes:
1. SA is the sector address for sector erase.
Figure 10
AC Waveforms for Data Polling
During Embedded Algorithm Operations
tCH
CE
tDF
tOE
OE
tOEH
WE
tCE
tOH
*
High Z
DQ7=
Valid Data
DQ7
DQ7
tWHWH1 or 2
DQ0–DQ6
Valid Data
DQ0-DQ6
DQ0–DQ6=Invalid
tOE
* DQ7=Valid Data (The device has completed the Embedded operation).
14
Aeroflex Circuit Technology
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
Figure 11
Sector Protection Algorithm
Start
Set Up Sector Address
(A18, A17, A16)
PLSCNT = 1
OE = VID
A9 = VID, CE = VIL
A
Activate WE Pulse
Time Out 100µs
Increment
PLSCNT
Power Down OE
WE = VIH
CE = OE = VIL
A9 Should Remain VID
Read From Sector
Address = SA, A0 = 0, A1 = 1, A6 = 0
No
PLSCNT = 25?
Yes
No
Data = 01H
?
Yes
Device Failure
Protect
Another
Yes
Sector?
No
Remove VID from A9
Write Reset Command
Sector Protection
Complete
15
Aeroflex Circuit Technology
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
Figure 12
Sector Unprotect Algorithm
Start
Protect All Sectors
Verify 98403/98406
Device Code
PLSCNT = 1
Set Up Sector Address
Unprotected Mode
(A5 = VIH, A9 = VIL)
A
Set OE = VID OR VSP
WE = VSP
Activate CE Pulse
Time Out 5 mS
Increment
PLSCNT
Set OE = VIL, WE = VIH
A6 = VIH, A9 = VID OR VSP
Setup Sector Address SA0
Set A1, A0 = 1, 0
CE = VIL
Read Data
From Device
No
Increment
Sector Address
No
Data = 00H
?
PLSCNT = 1000
?
Yes
Yes
Sector
Address = SA7
No
Device Failure
?
Yes
Notes:
Remove VID OR VSP from A9
SA0 = Sector Address for initial sector
SA7 = Sector Address for last sector
Please refer to Table 2 for details
Sector Unprotect
Completed
16
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SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
Figure 13
Alternate CE Controlled Programming Operation Timings
Data Polling
5555H
PA
PA
Addresses
tWC
tAS
tAH
WE
OE
tGHEL
tCP
tWHWH1
CE
tCPH
tWS
tDH
A
AOH
PD
D7
DOUT
Data
5.0V
tDS
Notes:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. D7 is the 0utput of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
17
Aeroflex Circuit Technology
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
Pin Numbers & Functions
66 Pins — PGA
Pin#
1
Function
I/O8
I/O9
I/O10
A14
Pin#
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Function
Pin#
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Function
I/O25
I/O26
A7
Pin#
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
Function
WE3
CE3
A15
2
Vcc
3
CE1
NC
GND
I/O19
I/O31
I/O30
I/O29
I/O28
A1
4
A12
5
A16
I/O3
NC
6
A11
I/O15
I/O14
I/O13
I/O12
OE
A13
7
A0
A8
8
A18
I/O16
I/O17
I/O18
VCC
9
I/O0
I/O1
I/O2
WE2
CE2
GND
I/O11
A10
A
10
11
12
13
14
15
16
17
A2
A17
A3
WE1
I/O7
CE4
WE4
I/O27
A4
I/O23
I/O22
I/O21
I/O20
I/O6
I/O5
I/O4
A5
A9
I/O24
A6
"P3" — 1.08" SQ PGA Type (without shoulder) Package
"P7" — 1.08" SQ PGA Type (with shoulder) Package
Bottom View (P7 & P3)
Side View
(P7)
Side View
(P3)
1.085 SQ
MAX
.185
1.000
MAX
Pin 1
.600
.025
.035
Pin 56
.050
.100
1.030
1.040
1.030
1.040
.100
1.000
.020
.016
.020
.016
Pin 66
Pin 11
.180
TYP
.100
.180
TYP
.160
MAX
All dimensions in inches
18
Aeroflex Circuit Technology
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
Pin Numbers & Functions
68 Pins — CQFP Package
Pin#
1
Function
GND
CE3
A5
Pin#
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Function
GND
I/O8
Pin#
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Function
OE
Pin#
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Function
GND
I/O23
I/O22
I/O21
I/O20
I/O19
I/O18
I/O17
I/O16
VCC
2
CE2
3
I/O9
A17
4
A4
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
VCC
WE2
WE3
WE4
A18
5
A3
6
A2
7
A1
8
A0
NC
9
NC
NC
A
10
11
12
13
14
15
16
17
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O31
I/O30
I/O29
I/O28
I/O27
I/O26
I/O25
I/O24
A11
A10
A12
A9
A13
A8
A14
A7
A15
A6
A16
WE1
CE4
CE1
"F5" — Single-Cavity CQFP
Top View
Side View
0.990 SQ
.010
0.880 SQ
0.160
MAX
.010
Pin 9
Pin 61
Pin 10
Pin 60
0.010
REF
0.015
.002
0.946
.010
.010 R
1°-7°
0.040
0.010
.005
Detail “A”
0.050
TYP
Pin 26
Pin 27
Pin 44
Pin 43
See Detail “A”
0.800 REF
All dimensions in inches
19
Aeroflex Circuit Technology
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
C I R C U I T T E C H N O L O G Y
Ordering Information
Model Number
DESC Drawing Number
5962–9461205HXX*
5962–9461204HXX
5962–9461203HXX
5962–9461202HXX
5962–9461201HXX
5962–9461205HUX*
5962–9461204HUX
5962–9461203HUX
5962–9461202HUX
5962–9461201HUX
5962–9461205HMX*
5962–9461204HMX
5962–9461203HMX
5962–9461202HMX
5962–9461201HMX
Speed
Package
PGA
ACT–F512K32N–060P3Q
ACT–F512K32N–070P3Q
ACT–F512K32N–090P3Q
ACT–F512K32N–120P3Q
ACT–F512K32N–150P3Q
ACT–F512K32N–060P7Q
ACT–F512K32N–070P7Q
ACT–F512K32N–090P7Q
ACT–F512K32N–120P7Q
ACT–F512K32N–150P7Q
ACT–F512K32N–060F5Q
ACT–F512K32N–070F5Q
ACT–F512K32N–090F5Q
ACT–F512K32N–120F5Q
ACT–F512K32N–150F5Q
* Pending
60 ns
70 ns
90 ns
120 ns
150 ns
60 ns
70 ns
90 ns
120 ns
150 ns
60 ns
70 ns
90 ns
120 ns
150 ns
PGA
PGA
PGA
A
PGA
PGA
PGA
PGA
PGA
PGA
CQFP
CQFP
CQFP
CQFP
CQFP
Part Number Breakdown
ACT– F 512K 32 N– 090 F5 Q
Aeroflex Circuit
Technology
Screening
Memory Type
C = Commercial Temp, 0°C to +70°C
I = Industrial Temp, -40°C to +85°C
T = Military Temp, -55°C to +125°C
F = FLASH EEPROM
Memory Depth
M = Military Temp, -55°C to +125°C, Screened *
Q = MIL-PRF-38534 Compliant/SMD if applicable
Memory Width, Bits
Package Type & Size
Surface Mount Packages
F5 = .88"SQ 68 Lead
Single-Cavity CQFP
Thru-Hole Packages
P3 = 1.075"SQ PGA 66 Pins W/O Shoulder
P7 = 1.075"SQ PGA 66 Pins With Shoulder
Options
N = None
Memory Speed, ns
*
Screened to the individual test methods of MIL-STD-883
Specification subject to change without notice
Telephone: (516) 694-6700
Aeroflex Circuit Technology
35 South Service Road
Plainview New York 11830
Aeroflex Circuit Technology
FAX:
(516) 694-6715
Toll Free Inquiries: 1-(800) 843-1553
20
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
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