ACT-SF128K16N-39F18Q [AEROFLEX]
ACT-SF128K16 High Speed 128Kx16 SRAM/FLASH Multichip Module; ACT- SF128K16高速128Kx16 SRAM /闪存多芯片模块
| 型号： | ACT-SF128K16N-39F18Q |
| 厂家： | 
AEROFLEX CIRCUIT TECHNOLOGY |
| 描述： | ACT-SF128K16 High Speed 128Kx16 SRAM/FLASH Multichip Module |
| 文件： | 总11页 (文件大小：171K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACT–SF128K16 High Speed
128Kx16 SRAM/FLASH Multichip Module
CIRCUIT TECHNOLOGY
www.aeroflex.com
FEATURES
■ 2 – 128K x 8 SRAMs & 2 – 128K x 8 Flash Die in
One MCM
■ Access Times of 25ns (SRAM) and 60ns (Flash) or
35ns (SRAM) and 70 or 90ns (Flash)
■ 128K x 16 SRAM
■ 128K x 16 5V Flash
■ Organized as 128K x 16 of SRAM and 128K x 16 of
■ Packaging – Hermetic Ceramic
● 66 Pin, 1.08" x 1.08" x .160" PGA Type, No Shoulder,
Aeroflex code# "P3"
● 66 Pin, 1.08" x 1.08" x .185" PGA Type, With
Shoulder, Aeroflex code# "P7"
● 68 Lead, .94" x .94" x .140" Single-Cavity Small
Outline Gull Wing, Aeroflex code# "F18" (Drops into
the 68 Lead JEDEC .99"SQ CQFJ footprint)
Flash Memory with Separate Data Buses
■ DESC SMD Pending – 5962-96900
■ Both Blocks of Memory are User Configurable as
256K x 8
■ Low Power CMOS
■ Input and Output TTL Compatible Design
■ MIL-PRF-38534 Compliant MCMs Available
■ Decoupling Capacitors and Multiple Grounds for Low
Noise
■ Industrial and Military Temperature Ranges
■ Industry Standard Pinouts
FLASH MEMORY FEATURES
■ Sector Architecture (Each Die)
● 8 Equal Sectors of 16K bytes each
● Any combination of sectors can be erased with one
command sequence.
■ +5V Programing, 5V ±10% Supply
■ Embedded Erase and Program Algorithms
■ Hardware and Software Write Protection
■ Internal Program Control Time.
■ 10,000 Erase/Program Cycles
Note: Programming information available upon request
Block Diagram – PGA Type Package (P3,P7) and CQFP (F18)
Pin Description
SWE1 SCE1 SWE2 SCE2 FWE1 FCE1 FWE2 FCE2
FI/O0-15
Flash Data I/O
SRAM Data I/O
Address Inputs
OE
A0 – A16
SI/O0-15
A0–16
128Kx8
SRAM
128Kx8
SRAM
128Kx8
Flash
128Kx8
Flash
FWE1-2 Flash Write Enables
SWE1-2 SRAM Write Enables
FCE1-2 Flash Chip Enables
SCE1-2 SRAM Chip Enables
8
8
8
8
SI/O0-7
SI/O8-15
FI/O0-7
FI/O8-15
OE
NC
Output Enable
Not Connected
Power Supply
Ground
VCC
GND
eroflex Circuit Technology - Advanced Multichip Modules © SCD1677 REV A 4/28/98
Absolute Maximum Ratings
Symbol
TC
Rating
Range
-55 to +125
-65 to +150
-0.5 to +7
300
Units
°C
Case Operating Temperature
TSTG
VG
°C
Storage Temperature
V
Maximum Signal Voltage to Ground
Maximum Lead Temperature (10 seconds)
TL
°C
Parameter
Flash Data Retention
10 Years
10,000
Flash Endurance (Write/Erase Cycles)
Normal Operating Conditions
Symbol
VCC
Parameter
Minimum
Maximum
Units
+4.5
+2.2
-0.5
+5.5
VCC + 0.3
+0.8
V
V
V
Power Supply Voltage
Input High Voltage
Input Low Voltage
VIH
VIL
Capacitance
(VIN = 0V, f = 1MHz, TC = 25°C)
Symbol Parameter
Maximum
Units
pF
CAD
50
50
20
20
20
A0 – A16 Capacitance
COE
pF
OE Capacitance
F/S CWE1,2
F/S CCE1,2
F/S CI/O
pF
F/S Write Enable Capacitance
F/S Chip Enable Capacitance
I/O0 – I/O15 Capacitance
pF
pF
These parameters are guaranteed by design but not tested
DC Characteristics
(VCC = 5.0V, VSS= 0V, TC= -55°C to +125°C, unless otherwise indicated)
Parameter
Sym
Conditions
Min
Max Units
ILI
10
µA
Input Leakage Current
VCC = Max, VIN = 0 to VCC
FCE = SCE = VIH, OE = VIH,
VOUT = 0 to VCC
ILO
ICCx16
ISB
10
µA
Output Leakage Current
SCE = VIL, OE = VIH, f = 5MHz, VCC
Max, FCE = VIH
=
250 mA
SRAM Operating Supply Current x 16 Mode
Standby Current
FCE = SCE = VIH, OE = VIH, f = 5MHz,
VCC = Max
40
mA
VOL
VOH
ICC1
0.4
V
V
SRAM Output Low Voltage
IOL = 8 mA, VCC = 4.5V
2.4
SRAM Output High Voltage
IOH = -4.0 mA, , VCC = 4.5V
FCE = VIL, OE = VIH, SCE = VIH
100 mA
Flash Vcc Active Current for Read (1)
Flash Vcc Active Current for Program or
Erase (2)
ICC2
130 mA
FCE = VIL, OE = VIH, SCE = VIH
VOL
VOH
VLKO
0.45
V
V
V
Flash Output Low Voltage
Flash Output High Voltage
Flash Low Vcc Lock Out Voltage
IOL = 12 mA, VCC = 4.5V, SCE = VIH
IOH = -2.5 mA, , VCC = 4.5V, SCE = VIH
0.85 x VCC
3.2
Notes: 1) The ICC current listed includes both the DC operating current and the frequency dependent component (at 5MHz). The frequency component typically is less
than 2mA/MHz, with OE at VIH 2) ICC active while Embedded Algorithim (program or erase) is in progress 3) DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V
2
Aeroflex Circuit Technology
SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700
SRAM AC Characteristics
(VCC = 5.0V, VSS= 0V, TC = -55°C to +125°C)
Read Cycle
Parameter
–025
–035
Min Max
35
Symbol
Units
Min Max
25
tRC
tAA
tACE
tOH
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
25
25
35
Address Access Time
35
Chip Select Access Time
0
0
Output Hold from Address Change
Output Enable to Output Valid
Chip Select to Output in Low Z *
Output Enable to Output in Low Z *
Chip Deselect to Output in High Z *
Output Disable to Output in High Z *
* Parameters guaranteed by design but not tested
tOE
15
20
tCLZ
tOLZ
tCHZ
tOHZ
3
0
3
0
12
12
20
20
Write Cycle
Parameter
–025
–035
Min Max
35
Symbol
Units
Min Max
tWC
tCW
tAW
tDW
tWP
tAS
25
20
20
15
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
25
25
20
25
0
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
tOW
tWHZ
tDH
0
0
Output Active from End of Write *
Write to Output in High Z *
Data Hold from Write Time
Address Hold Time
10
20
0
0
tAH
0
0
* Parameters guaranteed by design but not tested
SRAM Truth Table
Mode
Standby
Read
SCE
OE
SWE
Data I/O
Power
H
L
L
L
X
X
H
H
L
High Z
Data Out
High Z
Standby
Active
Active
Active
L
Output Disable
Write
H
X
Data In
3
Aeroflex Circuit Technology
SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700
Timing Diagrams — SRAM
Read Cycle Timing Diagrams
Write Cycle Timing Diagrams
Write Cycle (SWE Controlled, OE = VIH)
Read Cycle 1 (SCE = OE = VIL, SWE = VIH)
tWC
tRC
A0-18
A0-18
tAA
tAW
tCW
tAH
tOH
DI/O
SCE
Previous Data Valid
Data Valid
tAS
tWP
SWE
tDW
tDH
tWHZ
tDW
SEE NOTE
DI/O
Data Valid
Read Cycle 2 (SWE = VIH)
tRC
Write Cycle (SCE Controlled, OE = VIH )
A0-18
tWC
tAA
A0-18
tAH
tAW
SCE
tAS
tACE
tCW
tWP
tCHZ
SEE NOTE
SCE
tCLZ
SEE NOTE
OE
tOHZ
tOE
SWE
SEE NOTE
tOLZ
SEE NOTE
tDW
tDH
DI/O
Data Valid
High Z
DI/O
Data Valid
Note: Guaranteed by design, but not tested.
DON’T CARE
UNDEFINED
AC Test Circuit
Current Source
IOL
AC Test Conditions
Parameter
Typical
0 – 3.0
5
Units
Input Pulse Level
Input Rise and Fall
V
ns
V
VZ ~ 1.5 V (Bipolar Supply)
To Device Under Test
CL = 50 pF
Input and Output Timing Reference Level
1.5
IOH
Current Source
Notes:
1) VZ is programmable from -2V to +7V. 2) IOL and IOH programmable from 0 to 16 mA. 3) Tester Impedance
ZO = 75Ω. 4) VZ is typically the midpoint of VOH and VOL. 5) IOL and IOH are adjusted to simulate a typical resistance
load circuit. 6) ATE Tester includes jig capacitance.
4
Aeroflex Circuit Technology
SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700
Flash AC Characteristics – Read Only Operations
(Vcc = 5.0V, Vss = 0V, TC = -55°C to +125°C)
Symbol
–60
–70
–90
Parameter
Units
JEDEC Stand’d Min Max Min Max Min Max
Read Cycle Time
tAVAV
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tAXQX
tRC
tACC
tCE
tOE
tDF
60
70
90
ns
ns
ns
ns
ns
ns
ns
Address Access Time
60
60
30
20
20
70
70
35
20
20
90
90
40
25
25
Chip Enable Access Time
Output Enable to Output Valid
Chip Enable to Output High Z (1)
Output Enable High to Output High Z(1)
Output Hold from Address, CE or OE Change, Whichever is First
Note 1. Guaranteed by design, but not tested
tDF
tOH
0
0
0
Flash AC Characteristics – Write/Erase/Program Operations, FWE Controlled
(Vcc = 5.0V, Vss = 0V, TC = -55°C to +125°C)
Symbol
–60
–70
–90
Parameter
Units
JEDEC Stand’d Min Max Min Max Min Max
Write Cycle Time
tAVAC
tELWL
tWC
tCE
60
0
70
0
90
0
ns
ns
Chip Enable Setup Time
Write Enable Pulse Width
Address Setup Time
tWLWH
tAVWL
tWP
tAS
30
0
35
0
45
0
ns
ns
Data Setup Time
tDVWH
tWHDX
tWLAX
tWHEH
tWHWL
tWHWH1
tWHWH2
tWHWH3
tGHWL
tDS
30
0
30
0
45
0
ns
Data Hold Time
tDH
tAH
tCH
tWPH
ns
Address Hold Time
45
0
45
0
45
0
ns
Chip Enable Hold Time
Write Enable Pulse Width High
Duration of Byte Programming Operation
Sector Erase Time
ns
20
20
20
ns
14 TYP 14 TYP 14 TYP
µs
60
60
60
Sec
Sec
µs
Chip Erase Time
120
120
120
Read Recovery Time before Write
Vcc Setup Time
0
0
0
tVCE
tOES
tOEH
50
50
50
µs
Output Enable Setup Time
12.5
12.5
12.5
Sec
ns
1
Output Enable Hold Time
10
10
10
Note: 1. For Toggle and Data Polling.
Flash AC Characteristics – Write/Erase/Program Operations, FCE Controlled
(Vcc = 5.0V, Vss = 0V, TC = -55°C to +125°C)
Symbol
–60
–70
–90
Parameter
Units
JEDEC Stand’d Min Max Min Max Min Max
Write Cycle Time
tAVAC
tWLEL
tELEH
tWC
tWS
tCP
60
0
70
0
90
0
ns
ns
Write Enable Setup Time
Chip Enable Pulse Width
Address Setup Time
35
0
35
0
50
0
ns
tAVEL
tAS
ns
Data Setup Time
tDVEH
tDS
30
0
30
0
50
0
ns
Data Hold Time
tEHDX
tDH
tAH
tWH
tCPH
ns
Address Hold Time
tELAX
45
0
45
0
50
0
ns
Write Enable Hold from Write Enable High
Chip Enable Pulse Width High
Duration of Byte Programming
Sector Erase Time
tEHWH
tEHEL
ns
20
20
20
ns
tWHWH1
tWHWH2
tWHWH3
14 TYP 14 TYP 14 TYP
µs
60
60
60
Sec
Sec
ns
Chip Erase Time
120
120
120
Read Recovery Time
Chip Programming Time
tGHEL
0
0
0
12.5
12.5
12.5
Sec
5
Aeroflex Circuit Technology
SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700
AC Waveforms for Flash Memory Read Operations
tRC
Addresses
FCE
Addresses Stable
tACC
tDF
OE
tOE
FWE
tCE
tOH
High Z
High Z
Outputs
Output Valid
Write/Erase/Program
Operation for Flash Memory, FWE Controlled
Data Polling
Addresses
5555H
PA
PA
tRC
tWC
tAH
tAS
FCE
OE
tGHWL
tWP
tWHWH1
tWPH
FWE
tCE
tDF
tOH
tOE
tDH
AOH
PD
D7
DOUT
Data
5.0V
tDS
tCE
Notes:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. D7 is the 0utput of the complement of the data written to the deviced.
4. Dout is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
6
Aeroflex Circuit Technology
SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700
AC Waveforms Chip/Sector
Erase Operations for Flash Memory
Data Polling
5555H
tAS
tAH
5555H
2AAAH
5555H
2AAAH
SA
Addresses
FCE
OE
tGHWL
tWP
FWE
tWPH
tDH
tCE
AAH
55H
80H
AAH
55H
10H/30H
Data
VCC
tDS
tVCE
Notes:
1. SA is the sector address for sector erase.
AC Waveforms for Data Polling
During Embedded Algorithm Operations for Flash Memory
tCH
FCE
tDF
tOE
OE
tOEH
tCE
FWE
tOH
*
High Z
DQ7=
Valid Data
DQ7
DQ7
tWHWH1 or 2
DQ0–DQ6
Valid Data
DQ0-DQ6
DQ0–DQ6=Invalid
tOE
* DQ7=Valid Data (The device has completed the Embedded operation).
7
Aeroflex Circuit Technology
SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700
Write/Erase/Program Operation for Flash Memory, FCE Controlled
Data Polling
5555H
PA
PA
Addresses
tWC
tAS
tAH
FWE
OE
tGHWL
tCP
tWHWH1
FCE
tCPH
tWS
tDH
AOH
PD
D7
DOUT
Data
5.0V
tDS
Notes:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. D7 is the 0utput of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
8
Aeroflex Circuit Technology
SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700
Pin Numbers & Functions
66 Pins — PGA-Type
Pin #
1
Function
SI/O8
SI/O9
SI/O10
A13
Pin #
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Function
Pin #
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Function
FI/O9
FI/O10
A6
Pin #
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
Function
FWE1
FCE1
GND
FI/O3
FI/O15
FI/O14
FI/O13
FI/O12
A0
A12
2
Vcc
3
SCE1
NC
4
A7
5
A14
SI/O3
SI/O15
SI/O14
SI/O13
SI/O12
OE
NC
6
A15
A8
7
A16
A9
8
NC
FI/O0
FI/O1
FI/O2
VCC
9
SI/O0
SI/O1
SI/O2
SWE2
SCE2
GND
SI/O11
A10
10
11
12
13
14
15
16
17
A1
NC
A2
SWE1
SI/O7
SI/O6
SI/O5
SI/O4
FI/O8
FCE2
FWE2
FI/O11
A3
FI/O7
FI/O6
FI/O5
FI/O4
A4
A11
A5
"P3" — 1.08" SQ PGA Type (without shoulder) Package
"P7" — 1.08" SQ PGA Type (with shoulder) Package
Bottom View (P7 & P3)
Side View
(P7)
Side View
(P3)
1.085 SQ
MAX
.185
1.000
MAX
Pin 1
.600
.025
.035
Pin 56
.050
.100
1.030
1.040
1.030
1.040
.100
1.000
.020
.016
.020
.016
Pin 66
Pin 11
.180
TYP
.100
.180
TYP
.160
MAX
All dimensions in inches
9
Aeroflex Circuit Technology
SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700
Pin Numbers & Functions
68 Pins — Dual-Cavity CQFP
Pin #
1
Function
GND
FCE1
A5
Pin #
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Function
GND
SI/O8
SI/O9
SI/O10
SI/O11
SI/O12
SI/O13
SI/O14
SI/O15
Vcc
Pin #
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Function
OE
Pin #
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Function
GND
FI/O7
FI/O6
FI/O5
FI/O4
FI/O3
FI/O2
FI/O1
FI/O0
VCC
2
SCE2
NC
3
4
A4
SWE2
FWE1
FWE2
NC
5
A3
6
A2
7
A1
8
A0
NC
9
NC
NC
10
11
12
13
14
15
16
17
SI/O0
SI/O1
SI/O2
SI/O3
SI/O4
SI/O5
SI/O6
SI/O7
FI/O15
FI/O14
FI/O13
FI/O12
FI/O11
FI/O10
FI/O9
FI/O8
A11
A10
A12
A9
A13
A8
A14
A7
A15
A6
A16
SWE1
FCE2
SCE1
"F18" — CQFP Package
.140
MAX
.990 SQ
±.010
.015
±.002
.940 SQ
±.010
Pin 9
Pin 61
Pin 10
Pin 60
.008
±.002
.010
±.008
.040
.015
±.002
Detail “A”
.900 SQ
REF
.640 SQ
REF
Metal spacer
Pin 26
Pin 27
Pin 44
Pin 43
.800 REF
See Detail “A”
All dimensions in inches
10
Aeroflex Circuit Technology
SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700
C I R C U I T T E C H N O L O G Y
Ordering Information
Model Number
DESC SMD Number
5462-96900*
5462-96900*
5462-96900*
5462-96900*
5462-96900*
5462-96900*
5462-96900*
5462-96900*
5462-96900*
Speed
Package
25(S) / 60(F) ns
35(S) / 70(F) ns
35(S) / 90(F) ns
25(S) / 60(F) ns
35(S) / 70(F) ns
35(S) / 90(F) ns
25(S) / 60(F) ns
35(S) / 70(F) ns
35(S) / 90(F) ns
1.08"SQ PGA-Type
1.08"SQ PGA-Type
1.08"SQ PGA-Type
1.08"SQ PGA-Type
1.08"SQ PGA-Type
1.08"SQ PGA-Type
.94"sq CQFP
ACT–SF128K16N –26P3Q
ACT–SF128K16N –37P3Q
ACT–SF128K16N –39P3Q
ACT–SF128K16N –26P7Q
ACT–SF128K16N –37P7Q
ACT–SF128K16N –39P7Q
ACT–SF128K16N –26F18Q
ACT–SF128K16N –37F18Q
ACT–SF128K16N –39F18Q
.94"sq CQFP
.94"sq CQFP
Note: (S) = Speed for SRAM, (F) = Speed for FLASH
* Pending
Part Number Breakdown
ACT– S F 128K 16 N– 26 P7 Q
Aeroflex Circuit
Technology
Screening
C = Commercial Temp, 0°C to +70°C
I = Industrial Temp, -40°C to +85°C
T = Military Temp, -55°C to +125°C
Memory Type
S (SRAM) & F (FLASH) Combo
M = Military Temp, -55°C to +125°C, Screening *
Q = MIL-PRF-38534 Compliant / SMD
Memory Depth
Options, N = none
Package Type & Size
Surface Mount Packages
F18 = .94"SQ 68 Lead Dual-Cavity
CQFP
Thru-Hole Packages
Memory Width, Bits
Memory Speed cODE
P3 = 1.085"SQ PGA 66 Pins
with out shoulder
P7 = 1.085"SQ PGA 66 Pins
with shoulder
26 = 25ns SRAM & 60ns FLASH
37 = 35ns SRAM & 70ns FLASH
39 = 35ns SRAM & 90ns FLASH
*
Screened to the individual test methods of MIL-STD-883
Specification subject to change without notice
Aeroflex Circuit Technology
35 South Service Road
Plainview New York 11830
Aeroflex Circuit Technology
Telephone: (516) 694-6700
FAX: (516) 694-6715
Toll Free Inquiries: 1-(800) 843-1553
11
SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700
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