UT54ACS138 [AEROFLEX]
3-Line to 8-Line Decoders/Demultiplexers;
| 型号： | UT54ACS138 |
| 厂家： | 
AEROFLEX CIRCUIT TECHNOLOGY |
| 描述： | 3-Line to 8-Line Decoders/Demultiplexers |
| 文件： | 总10页 (文件大小：244K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Standard Products
UT54ACS138/UT54ACTS138
3-Line to 8-Line Decoders/Demultiplexers
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
PINOUTS
16-Pin DIP
Top View
1.2μ CMOS
- Latchup immune
High speed
A
1
16
VDD
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 16-pin DIP
- 16-lead flatpack
UT54ACS138 - SMD 5962-96544
UT54ACTS138 - SMD 5962-96545
B
C
2
3
4
5
6
7
8
15
14
13
12
11
10
9
Y0
Y1
Y2
Y3
Y4
Y5
Y6
G2A
G2B
G1
Y7
VSS
DESCRIPTION
16-Lead Flatpack
Top View
The UT54ACS138 and the UT54ACTS138 3-line to 8-line de-
coders/demultiplexers are designed to be used in high-perfor-
mance memory-decoding or data-routing applications requiring
very short propagation delay times.
A
1
16
VDD
B
C
2
3
4
5
6
7
8
15
14
13
12
11
10
9
Y0
Y1
Y2
Y3
Y4
Y5
Y6
The conditions at the binary select inputs and the three enable
inputs select one of eight output lines. Two active-low and one
active-high enable inputs reduce the need for external gates of
inverters when expanding. A 24-line decoder can be implement-
ed without external inverters and a 32-line decoder requiresonly
one inverter. An enable input can be used as a data input for
demultiplexing applications.
G2A
G2B
G1
Y7
VSS
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
ENABLE INPUTS
SELECT INPUTS
OUTPUT
G1
X
G2A
X
X
H
L
G2B
C
X
X
X
L
B
X
X
X
L
A
X
X
X
L
Y0
H
H
H
L
Y1
H
H
H
H
L
Y2
H
H
H
H
H
L
Y3
H
H
H
H
H
H
L
Y4
H
H
H
H
H
H
H
L
Y5
H
H
H
H
H
H
H
H
L
Y6
H
H
H
H
H
H
H
H
H
L
Y7
H
H
H
H
H
H
H
H
H
H
L
H
X
X
L
L
L
L
L
L
L
L
L
X
H
H
H
H
H
H
H
H
L
L
L
H
L
H
H
H
H
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
H
L
H
H
H
L
H
H
H
H
L
H
H
LOGIC SYMBOL
BIN/OCT
DMUX
(1)
(2)
(3)
(1)
A
1
2
4
A
B
C
1
2
4
(15)
(14)
(15)
(14)
(13)
0
1
Y0
Y1
0
1
Y0
Y1
0
7
(2)
B
---
G
(3)
(13)
(12)
(11)
C
2
3
4
Y2
Y3
Y4
2
3
4
Y2
Y3
Y4
(12)
(11)
(6)
(10)
(9)
(6)
G1
(10)
(9)
&
&
G1
5
6
7
Y5
Y6
Y7
5
6
7
Y5
Y6
Y7
(4)
(5)
(4)
EN
EN
G2A
G2A
G2B
(7)
(7)
(5)
G2B
Note:
1. Logic symbols in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12.
LOGIC DIAGRAM
(15)
(14)
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
(6)
G1
ENABLE
(13)
(12)
(11)
(10)
(4)
(5)
G2A
G2B
DATA
(1)
A
(9)
(7)
SELECT
(2)
(3)
B
C
2
1
OPERATIONAL ENVIRONMENT
PARAMETER
LIMIT
1.0E6
80
UNITS
Total Dose
rads(Si)
2
2
SEU Threshold
MeV-cm /mg
2
SEL Threshold
120
MeV-cm /mg
2
Neutron Fluence
1.0E14
n/cm
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
LIMIT
UNITS
V
Supply voltage
-0.3 to 7.0
V
DD
V
Voltage any pin
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 5 seconds)
Thermal resistance junction to case
DC input current
-.3 to V +.3
V
°C
I/O
DD
T
-65 to +150
STG
T
+175
+300
20
°C
J
T
°C
LS
Θ
°C/W
mA
W
JC
I
±10
1
I
P
Maximum power dissipation
D
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMIT
UNITS
V
Supply voltage
4.5 to 5.5
V
DD
V
Input voltage any pin
Temperature range
0 to V
V
IN
DD
T
-55 to + 125
°C
C
3
7
DC ELECTRICAL CHARACTERISTICS
6
(V = 5.0V ±10%; V = 0V , -55°C < T < +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
DD
SS
C
SYMBOL
PARAMETER
CONDITION
MIN
MAX
UNIT
1
V
IL
IH
IN
Low-level input voltage
ACTS
ACS
0.8
V
.3V
DD
1
V
High-level input voltage
ACTS
ACS
.5V
.7V
V
DD
DD
I
Input leakage current
ACTS/ACS
1
μA
V
= V or V
SS
-1
IN
DD
3
V
OL
Low-level output voltage
0.40
0.25
V
I
I
= 8.0mA
= 100μA
ACTS
ACS
OL
OL
3
V
OH
High-level output voltage
.7V
V
I
I
= -8.0mA
= -100μA
DD
OH
OH
ACTS
ACS
V
- 0.25
DD
2 ,4
I
OS
Short-circuit output current
ACTS/ACS
-200
200
mA
mA
V = V and V
O
DD
SS
10
I
V
V
= V or V
SS
8
OL
IN
DD
Output current
= 0.4V
(Sink)
OL
10
I
V
V
= V or V
SS
-8
mA
OH
IN
DD
Output current
= V - 0.4V
(Source)
OH
DD
2, 8, 9
P
I
C = 50pF
1.9
mW/
MHz
total
L
Power dissipation
Quiescent Supply Current
V
= 5.5V
DD
10
μA
DDQ
ΔI
Quiescent Supply Current Delta
ACTS
1.6
mA
DDQ
For input under test
= V - 2.1V
V
IN
DD
For all other inputs
V
V
= V or V
DD SS
IN
= 5.5V
DD
5
C
ƒ = 1MHz @ 0V
ƒ = 1MHz @ 0V
15
15
pF
pF
IN
Input capacitance
5
C
OUT
Output capacitance
4
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose ≤ 1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
5
2
AC ELECTRICAL CHARACTERISTICS
1
(V = 5.0V ±10%; V = 0V , -55°C < T < +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
DD
SS
C
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNIT
t
t
t
t
Binary Select to output Yn
Binary Select to output Yn
Enable to output Yn
2
15
ns
PHL
PLH
PHL
PLH
2
2
2
15
17
14
ns
ns
ns
Enable to output Yn
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose ≤ 1E6 rads(Si).
6
PACKAGING
Side-Brazed Packages
7
FLATPACK PACKAGES
8
UT54ACS138/UT54ACTS138: SMD
5962
*
***** ** * * *
Lead Finish: (Notes 1 & 2)
A = Solder
C = Gold
X = Optional
Package Type:
X = 16-lead ceramic bottom-brazed dual-in-line Flatpack
C = 16-lead ceramic side-brazed dip
Class Designator:
Q = QML Class Q
V = QML Class V
Device Type:
01
Drawing Number:
96544 = UT54ACS138
96545 = UT54ACTS138
Total Dose: (Notes 3 & 4)
R = 1E5 rads(Si)
F = 3E5 rads(Si)
G = 5E5 rads(Si)
H = 1E6 rads(Si)
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. For prototype inquiries, contact factory.
4. Device type 02 is only offered with a TID tolerance guarantee of 3E5 rads(Si) or 1E6 rads(Si) and is tested in accordance with MIL-STD-883 Test Method 1019
Condition A and section 3.11.2. Device type 03 is only offered with a TID tolerance guarantee of 1E5 rads(Si), 3E5 rads(Si), and 5E5 rads(Si), and is tested in
accordance with MIL-STD-883 Test Method 1019 Condition A.
9
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