UT7C138C55GPC [AEROFLEX]
4Kx8/9 Radiation-Hardened Dual-Port Static RAM with Busy Flag; 4Kx8 / 9抗辐射双口静态RAM与忙标志型号: | UT7C138C55GPC |
厂家: | AEROFLEX CIRCUIT TECHNOLOGY |
描述: | 4Kx8/9 Radiation-Hardened Dual-Port Static RAM with Busy Flag |
文件: | 总21页 (文件大小:360K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
UStaTnd7arCd P1ro3du8c/ts139 4Kx8/9 Radiation-Hardened
Dual-Port Static RAM with Busy Flag
Data Sheet
January 2002
FEATURES
INTRODUCTION
The UT7C138 and UT7C139 are high-speed radiation-
hardened CMOS 4K x 8 and 4K x 9 dual-port static RAMs.
Arbitration schemes are included on the UT7C138/139 to
handle situations when multiple processors access the same
memory location. Two ports provide independent,
asynchronous access for reads and writes to any location in
memory. The UT7C138/139 can be utilized as a stand-alone
32/36-Kbit dual-port static RAM or multiple devices can be
combined in order to function as a 16/18-bit or wider master/
slave dual-port static RAM. For applications that require
depth expansion, the BUSY pin is open-collector allowing
for wired OR circuit configuration. An M/S pin is provided
for implementing 16/18-bit or wider memory applications
without the need for separate master and slave devices or
additional discrete logic. Application areas include
interprocessor/multiprocessor designs, communications,
and status buffering.
q
q
45ns and 55ns maximum address access time
Asynchronous operation for compatibility with industry-
standard 4K x 8/9 dual-port static RAM
q
CMOS compatible inputs, TTL/CMOS compatible output
levels
q
q
q
Three-state bidirectional data bus
Low operating and standby current
Radiation-hardened process and design; total dose
irradiation testing to MIL-STD-883 Method 1019
- Total-dose: 1.0E6 rads(Si)
- Memory Cell LET threshold: 85 MeV-cm2/mg
- Latchup immune (LET >100 MeV-cm2/mg)
QML Q and QML V compliant part
Packaging options:
q
q
- 68-lead Flatpack
- 68-pin PGA
Each port has independent control pins: chip enable (CE),
read or write enable (R/W), and output enable ( OE). BUSY
signals that the port is trying to access the same location
currently being accessed by the other port.
q
q
5-volt operation
Standard Microcircuit Drawing 5962-96845
R/W
L
R/W
R
CE
OE
L
L
CE
OE
R
R
A
A
11L
10L
A
11R
10R
A
I/O (7C139)
I/O (7C139)
8R
8L
COL
SEL
COL
SEL
I/O
I/O
COLUMN
I/O
COLUMN
I/O
7R
7L
I/O
I/O
0L
0R
BUSY
A
BUSY
R
L
A
A
9L
0L
ROW
SELECT
MEMORY
ARRAY
ROW
SELECT
9R
A
0R
M/S
ARBITRATION
Figure 1. Logic Block Diagram
I/O
I/O
I/O
I/O
2L
3L
4L
5L
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
A
A
A
A
A
A
60
59
58
57
56
55
54
53
52
51
50
49
48
47
5L
4L
3L
2L
1L
0L
GND
I/O
I/O
6L
7L
NC
V
DD
7C138/139
BUSY
L
R
GND
GND
M/S
I/O
I/O
I/O
0R
1R
2R
BUSY
NC
V
DD
A
A
A
A
A
0R
1R
2R
3R
4R
I/O
I/O
I/O
I/O
3R
4R
5R
6R
46
45
44
Figure 2a. DPRAM Pinout (68-Flatpack)
(top view)
Notes:
1. I/O8R on the7C139
2. I/O8L on the 7C139
2
B11
C11
D11
E11
F11
BUSY M/S
G11
H11
NC
J11
K11
11
10
A
A
A
A
A
A
5L
4L
2L
0L
L
1R
3R
A10
B10
C10
D10
E10
NC
F10
GND
G10
BUSY
H10
J10
K10
L10
A
A
A
A
A
A
A
A
7L
6L
3L
1L
R
0R
2R
4R
5R
A9
B9
K9
L9
9
8
7
6
A
A
A
A
9L
8L
7R
6R
A8
B8
K8
L8
A
A
A
A
11L
10L
9R
8R
A7
B7
NC
K7
L7
V
A
A
DD
11R
10R
A6
NC
B6
NC
K6
GND NC
L6
7C138/139
A5
NC
B5
CE
K5
NC
L5
NC
5
4
3
L
A4
OE
B4
R/W
B3
K4
NC
L4
CE
L
L
R
A3
I/O
K3
OE
L3
R/W
L2
(2)
NC
0L
1L
R
R
A2
I/O
B2
I/O
C2
I/O
D2
GND I/O
E2
F2
GND
G2
I/O
H2
J2
I/O
K2
I/O
2
1
(1)
V
NC
2L
4L
7L
1R
DD
4R
7R
B1
I/O
C1
I/O
D1
I/O
E1
F1
I/O
G1
I/O
H1
I/O
J1
I/O
K1
I/O
V
3L
5L
6L
DD
0R
2R
3R
5R
6R
A
B
C
D
E
F
G
H
J
K
L
Figure 2b: DPRAM Pinout (68 PGA)
(top view)
Notes:
1. I/O8R on the7C139
2. I/O8L on the 7C139
PIN NAMES
LEFT PORT
RIGHT PORT
0R-7R(8R)
DESCRIPTION
I/O
I/O
Data Bus Input/Output
Address Lines
0L-7L(8L)
A
A
0R-11R
0L-11L
CE
CE
Chip Enable
L
R
OE
OE
Output Enable
L
R
R/W
R/W
Read/Write Enable
Busy Flag Input/Output
L
R
BUSY
M/S
BUSY
R
L
Master or Slave Select
Power
V
DD
GND
Ground
3
The UT7C138/139 consists of an array of 4K words of 8 or 9
bits of dual-port SRAM cells, I/O and address lines, and control
signals (CE, OE, R/W). These control pins permit independent
access for reads or writes to any location in memory. To handle
simultaneous writes/reads to the same location, a BUSY pin is
provided on each port. With the M/S pin, the UT7C138/139 can
function as a master (BUSY pins are outputs) or as a slave
(BUSY pins are inputs). Each port is provided with its own
output enable control (OE), which allows data to be read from
the device.
input, the M/S pin allows the device to be used as a master and,
therefore, the BUSY line is an output. BUSY can then be used
to send the arbitration outcome to a slave. When presented as a
LOW input, the M/S pin allows the device to be used as a slave,
and, therefore, the BUSY pin is an input.
Table 1. Non-Contending Read/Write
INPUTS
OUTPUTS
CE
H
R/W
X
OE
X
I/O0-7
OPERATION
WRITE CYCLE
High Z
High Z
Power Down
X
X
H
I/O Lines
Disabled
A combination of R/W less than VIL (max), andCE less than
VIL (max), defines a write cycle. The state of OE is a “don’t
care” for a write cycle. The outputs are placed in the high-
impedance state when eitherOE is greater than VIH (min), or
L
L
L
H
L
L
Data Out
Data In
---
Read
X
X
Write
when R/W is less than VIL (max).
X
Illegal
Condition
WRITE OPERATION
Write Cycle 1, the Write Enable-controlled Access shown in
figure 4a, is defined by a write terminated by R/W going high
with CE active. The write pulse width is defined by tPWE when
RADIATION HARDNESS
the write is initiated by R/W, and by tSCE when the write is
The UT7C138/139 incorporates special design and layout
features which allow operation in high-level radiation
environments. UTMC has developed special low-temperature
processing techniques designed to enhance the total-dose
radiation hardness of both the gate oxide and the field oxide
while maintaining the circuit density and reliability. For
transient radiation hardness and latchup immunity, UTMC
builds all radiation-hardened products on epitaxial wafers using
an advanced twin-tub CMOS process. In addition, UTMC pays
special attention to power and ground distribution during the
design phase, minimizing dose-rate upset caused by rail
collapse.
initiated byCE going active. Unless the outputs have been
previously placed in the high-impedance state byOE, the user
must wait tHZOE before applying data to the eight/nine
bidirectional pins I/O(0:7/0:8) to avoid bus contention.
Write Cycle 2, the Chip Enable-controlled Access shown in
figure 4b, is defined by a write terminated byCE going inactive.
The write pulse width is defined by tPWE when the write is
initiated by R/W, and by tSCE when the write is initiated by CE
going active. For the R/W initiated write, unless the outputs have
been previously placed in the high-impedance state by OE, the
user must wait tHZWE before applying data to the eight/nine
bidirectional pins I/O(0:7/0:8) to avoid bus contention.
Table 2. Radiation Hardness
Design Specifications1
If a location is being written by one port and the opposite port
attempts to read that location, a port-to-port flow through delay
must be met before the data is read on the output. Data will be
valid on the port wishing to read the location (tBZA + t BDD) after
Total Dose
1.0E6
85
rads(Si)
the data is written on the other port (see figure 5a).
MeV-cm2/mg
n/cm2
LET Threshold
READ OPERATION
Neutron Fluence2
3.0E14
When reading the device, the user must assert both the OE and
CE pins. Data will be available tACE after CE or tDOE afterOE
< 1.376E -2 (4Kx8) cm2
< 1.548E -2 (4Kx9)
Memory Device
Cross Section @ LET
= 120MeV-cm2/mg
is asserted (see figures 3a and 3b).
MASTER/SLAVE
A M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to theBUSY input of the slave.
Writing of slave devices must be delayed until after the BUSY
input has settled. Otherwise, the slave chip may begin a write
cycle during a contention situation. When presented as a HIGH
Notes:
1. The DPRAM will not latchup during radiation exposure under recommended
operating conditions.
2. Not tested for CMOS technology.
4
1
ABSOLUTE MAXIMUM RATINGS
(Referenced to VSS
)
SYMBOL
PARAMETER
DC supply voltage
LIMITS
VDD
-0.5 to 7.0V
VI/O
TSTG
PD
Voltage on any pin
-0.5 to (VDD + 0.3)V
-65 to +150°C
2.0W
Storage temperature
Maximum power dissipation
Maximum junction temperature2
TJ
+150°C
Thermal resistance, junction-to-case3
DC input current
QJC
3.3°C/W
II
±10 mA
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.
3. Test per MIL-STD-883, Method 1012, infinite heat sink.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
Positive supply voltage
LIMITS
VDD
4.5 to 5.5V
TC
Case temperature range
DC input voltage
-55 to +125°C
VIN
0V to VDD
5
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
(VDD = 5.0V ±10%; -55°C < TC < +125°C)
SYMBOL
PARAMETER
CONDITION
MIN
MAX
UNIT
VIH
High-level input voltage
(CMOS)
(CMOS)
0.7VDD
V
VIL
VOL
VOL
VOH
VOH
Low-level input voltage
Low-level output voltage
Low-level output voltage
High-level output voltage
High-level output voltage
Input capacitance
0.3VDD
0.4
V
V
IOL = 8mA, VDD = 4.5V (TTL)
IOL = 200mA, VDD = 4.5V (CMOS)
IOH = -4mA, VDD = 4.5V (TTL)
IOH = -200mA, VDD = 4.5V (CMOS)
¦ = 1MHz @ 0V
0.05
V
2.4
V
4.45
V
1
25
25
pF
CIN
1
Bidirectional I/O capacitance
¦ = 1MHz @ 0V
pF
CIO
IIN
Input leakage current
VIN = VDD and VSS
-10
-10
10
10
mA
mA
IOZ
Three-state output leakage current
VO = VDD and VSS
VDD = 5.5V
G = 5.5V
2,3
Short-circuit output current
VDD = 5.5V, VO = VDD
VDD = 5.5V, VO = 0V
90
mA
mA
IOS
-90
IDD(OP)4,5
IDD(OP)4,6
IDD(OP)4,5
IDD(OP)4,6
Supply current operating (both ports)
@ 22.2MHz
CMOS inputs (IOUT = 0)
VDD = 5.5V
300
mA
mA
mA
mA
mA
Supply current operating (single port)
@ 22.2 MHz
CMOS inputs (IOUT = 0)
VDD = 5.5V
150
275
138
1
Supply current operating (both ports)
@ 18.2MHz
CMOS inputs (IOUT = 0)
VDD = 5.5V
Supply current operating (single port)
@ 18.2 MHz
CMOS inputs (IOUT = 0)
VDD = 5.5V
IDD(SB)4
Supply current standby
CMOS inputs (IOUT = 0)
CE = VDD - 0.5, VDD = 5.5V
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.
1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
4. V = 5.5V, V = 0V.
IH
IL
5. I (OP) derates at 6.4mA/MHz.
DD
6. I (OP) derates at 3.4mA/MHz.
DD
6
AC CHARACTERISTICS READ CYCLE1,2
(VDD = 5.0V±10%)
7C138 - 45
7C139 - 45
7C138 - 55
7C139 - 55
MIN MAX
SYMBOL
PARAMETER
UNIT
MIN
MAX
tRC
tAA
Read cycle time
45
5
55
55
5
ns
ns
ns
ns
ns
ns
Address to data valid2
45
tOHA
tACE
tDOE
Output hold from address change
CE LOW to data valid2
OE LOW to data valid2
OE LOW to low Z
45
20
55
20
0
0
0
tLZOE
tHZOE
tLZCE
tHZCE
OE HIGH to high Z
CE LOW to low Z
CE HIGH to high Z
20
20
20
ns
ns
ns
0
20
Notes:
1. Test conditions assume signal transition time of 5ns or less, timing reference levels of V /2, input pulse levels of 0.5V to V -0.5V, and output
DD
DD
loading of the specified I /I and 50-pF load capacitance.
OL OH
2. AC test conditions use V /V =V /2 + 500mV.
OH OL
DD
7
tRC
Address
tAA
tOHA
Data Out
Previous Data Valid
Data Valid
Assumptions:
1.R/W is HIGH for read cycle
2.Device is continuously selected CE=LOW and OE=LOW
Figure 3a. Read Cycle 1
CE
tACE
OE
tHZCE
tHZOE
tDOE
tLZOE
tLZCE
Data Out
Assumptions:
1. Address valid prior to or coincident with CE transition LOW
2. R/W is HIGH for read cycle
Figure 3b. Read Cycle 2
tWC
Address
R/WR
MATCH
tPWE
tHD
tSD
DataINR
VALID
AddressL
MATCH
tDDD
VALID
DATAOUTL
tWDD
Assumptions:
1. BUSY = HIGH for the writing port
2. CE = CE = LOW
L
R
Figure 3c. Read Timing with Port-to-Port Delay
8
AC CHARACTERISTICS WRITE CYCLE1
(VDD = 5.0V±10%)
7C138 - 45
7C139 - 45
7C138 - 55
7C139 - 55
SYMBOL
PARAMETER
UNIT
MIN
MAX
MIN
MAX
tWC
tSCE
tAW
tHA
Write cycle time
CE LOW to write end
Address set-up to write end
Address hold from write end
Address set-up to write start
Write pulse width
45
40
40
0
55
50
50
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSA
0
0
tPWE
tSD
40
40
0
50
50
0
Data set-up to write end
Data hold from write end
R/W LOW to high Z
tHD
20
20
tHZWE
tLZWE
tWDD
R/W HIGH to low Z
Write pulse to data delay
Write data valid to read data valid
Write disable time
0
95
95
5
0
ns
ns
ns
ns
105
105
5
tDDD
tWHWL
Notes:
1. For information on part-to-part delay through DPRAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform (see figure 3c).
9
tWC
Address
CE
tSCE
tAW
tHA
R/W
tPWE
tSD
tHD
tSA
Data in
DATA VALID
tHZOE
OE
HIGH IMPEDANCE
tLZOE
Data out
Assumptions:
1. The internal write time of memory is defined by the overlap of CE
LOW and R/W LOW. Both signals must be LOW to initiate a write,
and either signal can terminate a write by going HIGH. The data input
set-up and hold timing should be referenced to the rising edge of the
signal that terminates the write.
2. If OE is LOW during a R/W controlled write cycle, the write pulse
width must be the larger of t
or (t
+ t ) to allow the I/O
HZWE SD
PWE
drivers to turn off and data to be placed on the bus for the required t
.
SD
If OE is HIGH during a R/W controlled write cycle (as in this exam-
ple), this requirement does not apply and the write pulse can be as
short as the specified t
.
PWE
3. R/W must be HIGH during all address transactions.
Figure 4a. Write Cycle 1: OE Three-States Data I/Os (Either Port)
10
tWC
Address
CE
tHA
tSCE
tAW
tWHWL
R/W
tSA
tPWE
tSD
tHD
Data in
DATA VALID
tLZWE
tHZWE
HIGH IMPEDANCE
Data out
Assumptions:
1. The internal write time of memory is defined by the overlap of CE
LOW and R/W LOW. Both signals must be LOW to initialize a write,
and either signal can terminate a write by going HIGH. The data input
set-up and hold timing should be referenced to the rising edge of the sig-
nal that terminates the write.
2. R/W must be HIGH during all address transactions.
3. Data I/O pins enter high impedance even if OE is held LOW during
write.
Figure 4b. Write Cycle 2: R/W Three-States Data I/Os (Either Port)
11
AC CHARACTERISTICS BUSY CYCLE 1
(VDD = 5.0V±10%)
7C138 - 45
7C139 - 45
7C138 - 55
7C139 - 55
MIN MAX
SYMBOL
PARAMETER
UNIT
MIN
MAX
tBLA
tBZA
tBLC
tBZC
BUSY LOW from address match
BUSY HIGH-Z from address mismatch
BUSY LOW from CE LOW
25
25
25
25
30
ns
ns
ns
ns
ns
30
30
BUSY HIGH from CE HIGH
Port set-up for priority
30
2,3
5
5
tPS
tWB
tWH
tBDD
R/W LOW after BUSY LOW
R/W HIGH after BUSY HIGH
BUSY HIGH to data valid
0
0
ns
ns
ns
40
50
45
55
Notes:
1. Test conditions assume signal transition time of 5ns or less, timing reference levels of V /2, input pulse levels of 0.5V to V -0.5V, and output
DD
DD
loading of the specified I /I and 50-pF load capacitance.
OL OH
2. Violation of t (with addresses matching) results in at least one of the two busy output signals asserting, only one port remains busy.
PS
3. When violating t , the busy signal asserts on one port or the other; there is no guarantee on which port the busy signal asserts.
PS
12
tWC
AddressR
R/WR
MATCH
tPWE
tHD
tSD
Data InR
VALID
tPS
AddressL
BUSYL
MATCH
tBLA
tBZA
tBDD
tDDD
DataOUTL
VALID
Assumptions:
tWDD
1. CE = CE = LOW
L
R
Figure 5a. Read Timing with BUSY (M/S=HIGH)
R/W
tPWE
tWB
tWH
BUSY
Figure 5b. Write Timing withBUSY (M/S=LOW)
13
CEL Valid First:
AddressL,R
ADDRESS MATCH
CEL
tPS
CER
tBLC
tBZC
BUSYR
CER Valid First:
AddressL,R
ADDRESS MATCH
CER
tPS
CEL
BUSYL
tBLC
tBZC
Assumptions:
1. If t is violated, the BUSY signal will be asserted on
PS
one side or the other, but there is no guarantee on which
side BUSY will be asserted.
Figure 5c. BUSY Timing Diagram No. 1 (CE Arbitration)
14
Left Address Valid First:
tRC or tWC
AddressL
AddressR
BUSYR
ADDRESS MATCH
ADDRESS MISMATCH
tPS
tBLA
tBZA
Right Address Valid First:
tRC or tWC
ADDRESS MATCH
tPS
AddressR
AddressL
ADDRESS MISMATCH
tBLA
tBZA
BUSYL
Assumptions:
1. If t is violated, the BUSY signal will be asserted on
PS
one side or the other, but there is no guarantee on which
side BUSY will be asserted.
Figure 5d. BUSY Timing Diagram No. 2 (Address Arbitration)
15
DATA RETENTION CHARACTERISTICS (Pre-Radiation)
(TC = 25°C)
SYMBOL
PARAMETER
MINIMUM
MAXIMUM UNIT
VDD
2.5V
@
VDR
VDD for data retention
2.5
--
--
400
V
1
Data retention current
mA
IDDR
1,2
Chip deselect to data retention time
Operation recovery time
0
ns
ns
tEFR
1,2
tWC or tRC
tR
Notes:
1. CE equals V
all other inputs equal V
or V .
SS
DR,
DR
2. Guaranteed but not tested.
DATA RETENTION MODE
VDR 2.5V
VDD
4.5V
tEFR
4.5V
tR
V
< 1.5V CMOS
VDR
IN
CE
Figure 6. Low VDD Data Retention Waveform
CMOS
460 ohms
90%
V
-0.5V
DD
V
/2
DD
10%
0.5V
50pF
< 5ns
< 5ns
Input Pulses
Notes:
1. 50pF including scope probe and test socket.
2. Measurement of data output occurs at the low to high or high to low transition mid-point
(CMOS input = V /2).
DD
Figure 7. AC Test Loads and Input Waveforms
16
Notes:
1. All package finishes are per MIL-PRF-38535.
2. Letter designations are for cross-reference to MIL-STD-1835.
3. All leads increase max limit by 0.003 measured at the center of the
flat, when lead finish A (solder) is applied.
4. ID mark: Configuration is optional.
5. Lettering is not subject to marking criteria.
6. Total weight is approximately 4.5 grams.
Figure 8. 68-lead Flatpack
17
L
K
J
H
G
F
E
D
C
B
A
11 10 9 8 7 6 5 4 3 2 1
L
K
J
H
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10 11
Notes:
1. All packages finishes are per MIL-PRF-38535.
2. True position applies at base plane (Datum C).
3. True position applies at pin tips.
4. Letter designations are for cross-reference to MIL-STD-1835.
5. Total weight is approximately 7.0 grams.
Figure 9. 68-pin PGA
18
ORDERING INFORMATION
UT7C138/UT7C139 Dual-Port SRAM: SMD
5962 * 96845 *
*
*
*
Lead Finish:
(A)
(C)
=
=
Solder
Gold
(X)
=
Optional
Case Outline:
(X)
(Y)
=
=
68-pin PGA
68-lead Flatpack
Class Designator:
(Q)
(V)
=
=
Class Q
Class V
Device Type
(01) = 4Kx8, CMOS Compatible Inputs, 45ns
(02) = 4Kx9, CMOS Compatible Inputs, 45ns
(03) = 4Kx8, CMOS Compatible Inputs, 55ns
(04) = 4Kx9, CMOS Compatible Inputs, 55ns
Drawing Number: 96845
Total Dose:
(H)
(G)
(F)
(R)
=
=
=
=
1E6 rads(Si)
5E5 rads(Si)
3E5 rads(Si)
1E5 rads(Si)
Federal Stock Class Designator: No options
Notes:
1. Lead finish (A, C, or X) must be specified.
2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.
19
UT7C138/UT7C139 Dual-Port SRAM
UT **** *** * * * * * *
Total Dose:
( ) = None
Lead Finish:
(A)
(C)
(X)
=
=
=
Solder
Gold
Optional
Screening:
(C)
(P)
=
=
Military Temperature Range flow
Prototype flow
Package Type:
(G) 68-lead PGA
=
(W) = 68-lead Flatpack
Access Time:
(45) = 45ns access time
(55) = 55ns access time
Device Type Modifier:
(C)
= CMOS-compatible Inputs, 5.0V operation
Device Type:
(7C138) = 4Kx8 Dual-Port SRAM
(7C139) = 4Kx9 Dual-Port SRAM
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Military Temperature Range flow per UTMC Manufacturing Flows Document. Radiation characteristics are neither tested nor guaranteed and may
not be specified.
4. Prototypes are produced to UTMC’s prototype flow and are tested at 25°C only. Radiation characteristics are neither tested nor guaranteed. Lead finish
is GOLD only.
20
UTMC Main Office
4350 Centennial Blvd.
Colorado Springs, CO 80907-3486
800-MIL-UTMC
European Sales Office
1+719-594-8166
1+719-594-8468 FAX
http://www.utmc.com
Boston Sales Office
40 Mall Road, Suite 203
Burlington, MA 01830
781-221-4122
800-645-8862
http://www.utmc.com
Melbourne Sales Office
1901 S. Harbor City Blvd., Suite 802
Melbourne, FL 32901
South LA Sales Office
101 Columbia Street, Suite 130
Aliso Viejo, CA 92656
714-362-2260
407-951-4164
UTMC Microelectronic Systems Inc. (UTMC) reserves the right to make changes to any products and services herein at any time without notice. Consult UTMC
or an authorized sales representative to verify that the information in this data sheet is current before using this product. UTMC does not assume any responsibility
or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by UTMC; nor does the purchase,
lease, or use of a product or service from UTMC convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of
UTMC or of third parties.
Copyright 1996 & 1997 by UTMC Microelectronic Systems Inc.
DUALPORT-2-12-97
All rights reserved
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