UT7C139C45GPX [AEROFLEX]

4Kx8/9 Radiation-Hardened Dual-Port Static RAM with Busy Flag; 4Kx8 / 9抗辐射双口静态RAM与忙标志


型号：	UT7C139C45GPX
厂家：	AEROFLEX CIRCUIT TECHNOLOGY
描述：	4Kx8/9 Radiation-Hardened Dual-Port Static RAM with Busy Flag 4Kx8 / 9抗辐射双口静态RAM与忙标志内存集成电路静态存储器
文件：	总21页 (文件大小：360K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

U^StaT^nd7^arC^{d P}1^ro3^du8^c/^ts139 4Kx8/9 Radiation-Hardened

Dual-Port Static RAM with Busy Flag

Data Sheet

January 2002

FEATURES

INTRODUCTION

The UT7C138 and UT7C139 are high-speed radiation-

hardened CMOS 4K x 8 and 4K x 9 dual-port static RAMs.

Arbitration schemes are included on the UT7C138/139 to

handle situations when multiple processors access the same

memory location. Two ports provide independent,

asynchronous access for reads and writes to any location in

memory. The UT7C138/139 can be utilized as a stand-alone

32/36-Kbit dual-port static RAM or multiple devices can be

combined in order to function as a 16/18-bit or wider master/

slave dual-port static RAM. For applications that require

depth expansion, the BUSY pin is open-collector allowing

for wired OR circuit configuration. An M/S pin is provided

for implementing 16/18-bit or wider memory applications

without the need for separate master and slave devices or

additional discrete logic. Application areas include

interprocessor/multiprocessor designs, communications,

and status buffering.

45ns and 55ns maximum address access time

Asynchronous operation for compatibility with industry-

standard 4K x 8/9 dual-port static RAM

CMOS compatible inputs, TTL/CMOS compatible output

levels

Three-state bidirectional data bus

Low operating and standby current

Radiation-hardened process and design; total dose

irradiation testing to MIL-STD-883 Method 1019

- Total-dose: 1.0E6 rads(Si)

- Memory Cell LET threshold: 85 MeV-cm²/mg

- Latchup immune (LET >100 MeV-cm²/mg)

QML Q and QML V compliant part

Packaging options:

- 68-lead Flatpack

- 68-pin PGA

Each port has independent control pins: chip enable (CE),

read or write enable (R/W), and output enable ( OE). BUSY

signals that the port is trying to access the same location

currently being accessed by the other port.

5-volt operation

Standard Microcircuit Drawing 5962-96845

R/W

11L

10L

11R

10R

I/O (7C139)

COL

SEL

COL

SEL

I/O

COLUMN

I/O

COLUMN

I/O

BUSY

ROW

SELECT

MEMORY

ARRAY

ROW

SELECT

M/S

ARBITRATION

Figure 1. Logic Block Diagram

I/O

GND

I/O

7C138/139

BUSY

GND

M/S

I/O

BUSY

I/O

Figure 2a. DPRAM Pinout (68-Flatpack)

(top view)

Notes:

1. I/O8R on the7C139

2. I/O8L on the 7C139

B11

C11

D11

E11

F11

BUSY M/S

G11

H11

J11

K11

A10

B10

C10

D10

E10

F10

GND

G10

BUSY

H10

J10

K10

L10

11L

10L

11R

10R

GND NC

7C138/139

R/W

I/O

R/W

(2)

I/O

GND I/O

GND

I/O

(1)

I/O

Figure 2b: DPRAM Pinout (68 PGA)

(top view)

Notes:

1. I/O8R on the7C139

2. I/O8L on the 7C139

PIN NAMES

LEFT PORT

RIGHT PORT

0R-7R(8R)

DESCRIPTION

I/O

Data Bus Input/Output

Address Lines

0L-7L(8L)

0R-11R

0L-11L

Chip Enable

Output Enable

R/W

Read/Write Enable

Busy Flag Input/Output

BUSY

M/S

BUSY

Master or Slave Select

Power

GND

Ground

The UT7C138/139 consists of an array of 4K words of 8 or 9

bits of dual-port SRAM cells, I/O and address lines, and control

signals (CE, OE, R/W). These control pins permit independent

access for reads or writes to any location in memory. To handle

simultaneous writes/reads to the same location, a BUSY pin is

provided on each port. With the M/S pin, the UT7C138/139 can

function as a master (BUSY pins are outputs) or as a slave

(BUSY pins are inputs). Each port is provided with its own

output enable control (OE), which allows data to be read from

the device.

input, the M/S pin allows the device to be used as a master and,

therefore, the BUSY line is an output. BUSY can then be used

to send the arbitration outcome to a slave. When presented as a

LOW input, the M/S pin allows the device to be used as a slave,

and, therefore, the BUSY pin is an input.

Table 1. Non-Contending Read/Write

INPUTS

OUTPUTS

R/W

I/O_0-7

OPERATION

WRITE CYCLE

High Z

Power Down

I/O Lines

Disabled

A combination of R/W less than V_IL(max), andCE less than

V_IL(max), defines a write cycle. The state of OE is a “don’t

care” for a write cycle. The outputs are placed in the high-

impedance state when eitherOE is greater than V_IH(min), or

Data Out

Data In

---

Read

Write

when R/W is less than V_IL(max).

Illegal

Condition

WRITE OPERATION

Write Cycle 1, the Write Enable-controlled Access shown in

figure 4a, is defined by a write terminated by R/W going high

with CE active. The write pulse width is defined by t_PWEwhen

RADIATION HARDNESS

the write is initiated by R/W, and by t_SCEwhen the write is

The UT7C138/139 incorporates special design and layout

features which allow operation in high-level radiation

environments. UTMC has developed special low-temperature

processing techniques designed to enhance the total-dose

radiation hardness of both the gate oxide and the field oxide

while maintaining the circuit density and reliability. For

transient radiation hardness and latchup immunity, UTMC

builds all radiation-hardened products on epitaxial wafers using

an advanced twin-tub CMOS process. In addition, UTMC pays

special attention to power and ground distribution during the

design phase, minimizing dose-rate upset caused by rail

collapse.

initiated byCE going active. Unless the outputs have been

previously placed in the high-impedance state byOE, the user

must wait t_HZOEbefore applying data to the eight/nine

bidirectional pins I/O(0:7/0:8) to avoid bus contention.

Write Cycle 2, the Chip Enable-controlled Access shown in

figure 4b, is defined by a write terminated byCE going inactive.

The write pulse width is defined by t_PWEwhen the write is

initiated by R/W, and by t_SCEwhen the write is initiated by CE

going active. For the R/W initiated write, unless the outputs have

been previously placed in the high-impedance state by OE, the

user must wait t_HZWEbefore applying data to the eight/nine

bidirectional pins I/O(0:7/0:8) to avoid bus contention.

Table 2. Radiation Hardness

Design Specifications¹

If a location is being written by one port and the opposite port

attempts to read that location, a port-to-port flow through delay

must be met before the data is read on the output. Data will be

valid on the port wishing to read the location (t_BZA+ t _BDD) after

Total Dose

1.0E6

rads(Si)

the data is written on the other port (see figure 5a).

MeV-cm²/mg

n/cm²

LET Threshold

READ OPERATION

Neutron Fluence²

3.0E14

When reading the device, the user must assert both the OE and

CE pins. Data will be available t_ACEafter CE or t_DOEafterOE

< 1.376E ^-2(4Kx8) cm²

< 1.548E ^-2(4Kx9)

Memory Device

Cross Section @ LET

= 120MeV-cm²/mg

is asserted (see figures 3a and 3b).

MASTER/SLAVE

A M/S pin is provided in order to expand the word width by

configuring the device as either a master or a slave. The BUSY

output of the master is connected to theBUSY input of the slave.

Writing of slave devices must be delayed until after the BUSY

input has settled. Otherwise, the slave chip may begin a write

cycle during a contention situation. When presented as a HIGH

Notes:

1. The DPRAM will not latchup during radiation exposure under recommended

operating conditions.

2. Not tested for CMOS technology.

ABSOLUTE MAXIMUM RATINGS

(Referenced to V_SS

)

SYMBOL

PARAMETER

DC supply voltage

LIMITS

V_DD

-0.5 to 7.0V

V_I/O

T_STG

P_D

Voltage on any pin

-0.5 to (V_DD+ 0.3)V

-65 to +150°C

2.0W

Storage temperature

Maximum power dissipation

Maximum junction temperature²

T_J

+150°C

Thermal resistance, junction-to-case³

DC input current

Q_JC

3.3°C/W

I_I

±10 mA

Notes:

1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device

at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.

3. Test per MIL-STD-883, Method 1012, infinite heat sink.

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

Positive supply voltage

LIMITS

V_DD

4.5 to 5.5V

T_C

Case temperature range

DC input voltage

-55 to +125°C

V_IN

0V to V_DD

DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*

(V_DD= 5.0V ±10%; -55°C < T_C< +125°C)

SYMBOL

PARAMETER

CONDITION

MIN

MAX

UNIT

V_IH

High-level input voltage

(CMOS)

0.7V_DD

V_IL

V_OL

V_OH

Low-level input voltage

Low-level output voltage

High-level output voltage

Input capacitance

0.3V_DD

0.4

I_OL= 8mA, V_DD= 4.5V (TTL)

I_OL= 200mA, V_DD= 4.5V (CMOS)

I_OH= -4mA, V_DD= 4.5V (TTL)

I_OH= -200mA, V_DD= 4.5V (CMOS)

¦ = 1MHz @ 0V

0.05

2.4

4.45

C_IN

Bidirectional I/O capacitance

¦ = 1MHz @ 0V

C_IO

I_IN

Input leakage current

V_IN= V_DDand V_SS

-10

I_OZ

Three-state output leakage current

V_O= V_DDand V_SS

V_DD= 5.5V

G = 5.5V

2,3

Short-circuit output current

V_DD= 5.5V, V_O= V_DD

V_DD= 5.5V, V_O= 0V

I_OS

-90

I_DD(OP)^4,5

I_DD(OP)^4,6

I_DD(OP)^4,5

I_DD(OP)^4,6

Supply current operating (both ports)

@ 22.2MHz

CMOS inputs (I_OUT= 0)

V_DD= 5.5V

300

Supply current operating (single port)

@ 22.2 MHz

CMOS inputs (I_OUT= 0)

V_DD= 5.5V

150

275

138

Supply current operating (both ports)

@ 18.2MHz

CMOS inputs (I_OUT= 0)

V_DD= 5.5V

Supply current operating (single port)

@ 18.2 MHz

CMOS inputs (I_OUT= 0)

V_DD= 5.5V

I_DD(SB)⁴

Supply current standby

CMOS inputs (I_OUT= 0)

CE = V_DD- 0.5, V_DD= 5.5V

Notes:

* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.

1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.

2. Supplied as a design limit but not guaranteed or tested.

3. Not more than one output may be shorted at a time for maximum duration of one second.

4. V = 5.5V, V = 0V.

5. I (OP) derates at 6.4mA/MHz.

6. I (OP) derates at 3.4mA/MHz.

AC CHARACTERISTICS READ CYCLE^1,2

(V_DD= 5.0V±10%)

7C138 - 45

7C139 - 45

7C138 - 55

7C139 - 55

MIN MAX

SYMBOL

PARAMETER

UNIT

MIN

MAX

t_RC

t_AA

Read cycle time

Address to data valid²

t_OHA

t_ACE

t_DOE

Output hold from address change

CE LOW to data valid²

OE LOW to data valid²

OE LOW to low Z

t_LZOE

t_HZOE

t_LZCE

t_HZCE

OE HIGH to high Z

CE LOW to low Z

CE HIGH to high Z

Notes:

1. Test conditions assume signal transition time of 5ns or less, timing reference levels of V /2, input pulse levels of 0.5V to V -0.5V, and output

loading of the specified I /I and 50-pF load capacitance.

OL OH

2. AC test conditions use V /V =V /2 + 500mV.

OH OL

t_RC

Address

t_AA

t_OHA

Data Out

Previous Data Valid

Data Valid

Assumptions:

1.R/W is HIGH for read cycle

2.Device is continuously selected CE=LOW and OE=LOW

Figure 3a. Read Cycle 1

t_ACE

t_HZCE

t_HZOE

t_DOE

t_LZOE

t_LZCE

Data Out

Assumptions:

1. Address valid prior to or coincident with CE transition LOW

2. R/W is HIGH for read cycle

Figure 3b. Read Cycle 2

t_WC

Address

R/W_R

MATCH

t_PWE

t_HD

t_SD

Data_INR

VALID

Address_L

MATCH

t_DDD

VALID

DATA_OUTL

t_WDD

Assumptions:

1. BUSY = HIGH for the writing port

2. CE = CE = LOW

Figure 3c. Read Timing with Port-to-Port Delay

AC CHARACTERISTICS WRITE CYCLE¹

(V_DD= 5.0V±10%)

7C138 - 45

7C139 - 45

7C138 - 55

7C139 - 55

SYMBOL

PARAMETER

UNIT

MIN

MAX

MIN

MAX

t_WC

t_SCE

t_AW

t_HA

Write cycle time

CE LOW to write end

Address set-up to write end

Address hold from write end

Address set-up to write start

Write pulse width

t_SA

t_PWE

t_SD

Data set-up to write end

Data hold from write end

R/W LOW to high Z

t_HD

t_HZWE

t_LZWE

t_WDD

R/W HIGH to low Z

Write pulse to data delay

Write data valid to read data valid

Write disable time

105

t_DDD

t_WHWL

Notes:

1. For information on part-to-part delay through DPRAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform (see figure 3c).

t_WC

Address

t_SCE

t_AW

t_HA

R/W

t_PWE

t_SD

t_HD

t_SA

Data in

DATA VALID

t_HZOE

HIGH IMPEDANCE

t_LZOE

Data out

Assumptions:

1. The internal write time of memory is defined by the overlap of CE

LOW and R/W LOW. Both signals must be LOW to initiate a write,

and either signal can terminate a write by going HIGH. The data input

set-up and hold timing should be referenced to the rising edge of the

signal that terminates the write.

2. If OE is LOW during a R/W controlled write cycle, the write pulse

width must be the larger of t

or (t

+ t ) to allow the I/O

HZWE SD

PWE

drivers to turn off and data to be placed on the bus for the required t

If OE is HIGH during a R/W controlled write cycle (as in this exam-

ple), this requirement does not apply and the write pulse can be as

short as the specified t

PWE

3. R/W must be HIGH during all address transactions.

Figure 4a. Write Cycle 1: OE Three-States Data I/Os (Either Port)

t_WC

Address

t_HA

t_SCE

t_AW

t_WHWL

R/W

t_SA

t_PWE

t_SD

t_HD

Data in

DATA VALID

t_LZWE

t_HZWE

HIGH IMPEDANCE

Data out

Assumptions:

1. The internal write time of memory is defined by the overlap of CE

LOW and R/W LOW. Both signals must be LOW to initialize a write,

and either signal can terminate a write by going HIGH. The data input

set-up and hold timing should be referenced to the rising edge of the sig-

nal that terminates the write.

2. R/W must be HIGH during all address transactions.

3. Data I/O pins enter high impedance even if OE is held LOW during

write.

Figure 4b. Write Cycle 2: R/W Three-States Data I/Os (Either Port)

AC CHARACTERISTICS BUSY CYCLE ¹

(V_DD= 5.0V±10%)

7C138 - 45

7C139 - 45

7C138 - 55

7C139 - 55

MIN MAX

SYMBOL

PARAMETER

UNIT

MIN

MAX

t_BLA

t_BZA

t_BLC

t_BZC

BUSY LOW from address match

BUSY HIGH-Z from address mismatch

BUSY LOW from CE LOW

BUSY HIGH from CE HIGH

Port set-up for priority

2,3

t_PS

t_WB

t_WH

t_BDD

R/W LOW after BUSY LOW

R/W HIGH after BUSY HIGH

BUSY HIGH to data valid

Notes:

1. Test conditions assume signal transition time of 5ns or less, timing reference levels of V /2, input pulse levels of 0.5V to V -0.5V, and output

loading of the specified I /I and 50-pF load capacitance.

OL OH

2. Violation of t (with addresses matching) results in at least one of the two busy output signals asserting, only one port remains busy.

3. When violating t , the busy signal asserts on one port or the other; there is no guarantee on which port the busy signal asserts.

t_WC

Address_R

R/W_R

MATCH

t_PWE

t_HD

t_SD

Data In_R

VALID

t_PS

Address_L

BUSY_L

MATCH

t_BLA

t_BZA

t_BDD

t_DDD

Data_OUTL

VALID

Assumptions:

t_WDD

1. CE = CE = LOW

Figure 5a. Read Timing with BUSY (M/S=HIGH)

R/W

t_PWE

t_WB

t_WH

BUSY

Figure 5b. Write Timing withBUSY (M/S=LOW)

CE_LValid First:

Address_L,R

ADDRESS MATCH

CE_L

t_PS

CE_R

t_BLC

t_BZC

BUSY_R

CE_RValid First:

Address_L,R

ADDRESS MATCH

CE_R

t_PS

CE_L

BUSY_L

t_BLC

t_BZC

Assumptions:

1. If t is violated, the BUSY signal will be asserted on

one side or the other, but there is no guarantee on which

side BUSY will be asserted.

Figure 5c. BUSY Timing Diagram No. 1 (CE Arbitration)

Left Address Valid First:

t_{RC or}t_WC

Address_L

Address_R

BUSY_R

ADDRESS MATCH

ADDRESS MISMATCH

t_PS

t_BLA

t_BZA

Right Address Valid First:

t_{RC or}t_WC

ADDRESS MATCH

t_PS

Address_R

Address_L

ADDRESS MISMATCH

t_BLA

t_BZA

BUSY_L

Assumptions:

1. If t is violated, the BUSY signal will be asserted on

one side or the other, but there is no guarantee on which

side BUSY will be asserted.

Figure 5d. BUSY Timing Diagram No. 2 (Address Arbitration)

DATA RETENTION CHARACTERISTICS (Pre-Radiation)

(T_C= 25°C)

SYMBOL

PARAMETER

MINIMUM

MAXIMUM UNIT

V_DD

2.5V

V_DR

V_DDfor data retention

2.5

400

Data retention current

I_DDR

1,2

Chip deselect to data retention time

Operation recovery time

t_EFR

1,2

t_WCor t_RC

t_R

Notes:

1. CE equals V

all other inputs equal V

or V .

DR,

2. Guaranteed but not tested.

DATA RETENTION MODE

V_DR2.5V

V_DD

4.5V

t_EFR

4.5V

t_R

< 1.5V CMOS

V_DR

Figure 6. Low V_DDData Retention Waveform

CMOS

460 ohms

90%

-0.5V

10%

0.5V

50pF

< 5ns

Input Pulses

Notes:

1. 50pF including scope probe and test socket.

2. Measurement of data output occurs at the low to high or high to low transition mid-point

(CMOS input = V /2).

Figure 7. AC Test Loads and Input Waveforms

Notes:

1. All package finishes are per MIL-PRF-38535.

2. Letter designations are for cross-reference to MIL-STD-1835.

3. All leads increase max limit by 0.003 measured at the center of the

flat, when lead finish A (solder) is applied.

4. ID mark: Configuration is optional.

5. Lettering is not subject to marking criteria.

6. Total weight is approximately 4.5 grams.

Figure 8. 68-lead Flatpack

11 10 9 8 7 6 5 4 3 2 1

1 2 3 4 5 6 7 8 9 10 11

Notes:

1. All packages finishes are per MIL-PRF-38535.

2. True position applies at base plane (Datum C).

3. True position applies at pin tips.

4. Letter designations are for cross-reference to MIL-STD-1835.

5. Total weight is approximately 7.0 grams.

Figure 9. 68-pin PGA

ORDERING INFORMATION

UT7C138/UT7C139 Dual-Port SRAM: SMD

5962 * 96845 *

Lead Finish:

(A)

(C)

Solder

Gold

(X)

Optional

Case Outline:

(X)

(Y)

68-pin PGA

68-lead Flatpack

Class Designator:

(Q)

(V)

Class Q

Class V

Device Type

(01) = 4Kx8, CMOS Compatible Inputs, 45ns

(02) = 4Kx9, CMOS Compatible Inputs, 45ns

(03) = 4Kx8, CMOS Compatible Inputs, 55ns

(04) = 4Kx9, CMOS Compatible Inputs, 55ns

Drawing Number: 96845

Total Dose:

(H)

(G)

(F)

(R)

1E6 rads(Si)

5E5 rads(Si)

3E5 rads(Si)

1E5 rads(Si)

Federal Stock Class Designator: No options

Notes:

1. Lead finish (A, C, or X) must be specified.

2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).

3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.

UT7C138/UT7C139 Dual-Port SRAM

UT **** *** - * * * * * *

Total Dose:

( ) = None

Lead Finish:

(A)

(C)

(X)

Solder

Gold

Optional

Screening:

(C)

(P)

Military Temperature Range flow

Prototype flow

Package Type:

(G) 68-lead PGA

(W) = 68-lead Flatpack

Access Time:

(45) = 45ns access time

(55) = 55ns access time

Device Type Modifier:

(C)

= CMOS-compatible Inputs, 5.0V operation

Device Type:

(7C138) = 4Kx8 Dual-Port SRAM

(7C139) = 4Kx9 Dual-Port SRAM

Notes:

1. Lead finish (A,C, or X) must be specified.

2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).

3. Military Temperature Range flow per UTMC Manufacturing Flows Document. Radiation characteristics are neither tested nor guaranteed and may

not be specified.

4. Prototypes are produced to UTMC’s prototype flow and are tested at 25°C only. Radiation characteristics are neither tested nor guaranteed. Lead finish

is GOLD only.

UTMC Main Office

4350 Centennial Blvd.

Colorado Springs, CO 80907-3486

800-MIL-UTMC

European Sales Office

1+719-594-8166

1+719-594-8468 FAX

http://www.utmc.com

Boston Sales Office

40 Mall Road, Suite 203

Burlington, MA 01830

781-221-4122

800-645-8862

http://www.utmc.com

Melbourne Sales Office

1901 S. Harbor City Blvd., Suite 802

Melbourne, FL 32901

South LA Sales Office

101 Columbia Street, Suite 130

Aliso Viejo, CA 92656

714-362-2260

407-951-4164

UTMC Microelectronic Systems Inc. (UTMC) reserves the right to make changes to any products and services herein at any time without notice. Consult UTMC

or an authorized sales representative to verify that the information in this data sheet is current before using this product. UTMC does not assume any responsibility

or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by UTMC; nor does the purchase,

lease, or use of a product or service from UTMC convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of

UTMC or of third parties.

DUALPORT-2-12-97

UT7C139C45GPX [AEROFLEX]

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