VRG8692-901-1S [AEROFLEX]

Adjustable 7.5A Positive LDO Regulator Radiation Tolerant;
VRG8692-901-1S
型号: VRG8692-901-1S
厂家: AEROFLEX CIRCUIT TECHNOLOGY    AEROFLEX CIRCUIT TECHNOLOGY
描述:

Adjustable 7.5A Positive LDO Regulator Radiation Tolerant

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Standard Products  
VRG8691/92  
Adjustable 7.5A Positive LDO Regulator  
Radiation Tolerant  
www.aeroflex.com/voltreg  
November 12, 2013  
FEATURES  
Radiation performance  
Enable Input - TTL / CMOS Compatible  
- Total dose: 100 krads(Si),  
Slow Start capability  
Stable with multiple ceramic output capacitors  
Packaging – Hermetic metal  
- Thru-hole or Surface mount  
- 12 Leads, 0.900"L x 1.000"W x .205"Ht  
- Power package  
Dose rate = 50 - 300 rads(Si)/s  
Output voltage adjustable: 1.0V to 3.3V  
Output current: 7.5A  
Dropout voltage: 0.5V at 7.5Amps  
Voltage reference: 1.0V ±0.5%  
Load regulation: 0.5% max  
Line regulation: 0.2% max  
Ripple rejection: >80dB  
- Weight - 18 gm max  
Designed for aerospace and high reliability space  
applications  
Aeroflex Plainview’s Radiation Hardness Assurance Plan is DLA Certified to MIL-PRF-38534, Appendix G.  
DESCRIPTION  
The Aeroflex Plainview VRG8691/92 is capable of supplying in excess of 7.5Amps over the output voltage range as  
defined under recommended operating conditions. The regulator is exceptionally easy to set-up, requiring only 2  
external resistors to set the output voltage. The module design has been optimized for excellent regulation and low  
drop-out voltage. Figures 2 through 5 illustrate setting output voltage, setting current limits and choosing a slow start  
capacitor. The VRG8691/92 serves a wide variety of applications including local on-card regulation, programmable  
output voltage regulation or precision current regulation.  
The VRG8691/92 has been specifically designed to meet exposure to radiation environments. The VRG8691 is  
configured for a Thru-Hole 12 lead metal power package and the VRG8692 is configured for a Surface Mount 12 lead  
metal power package. It is guaranteed operational from -55°C to +125°C. Available screened to MIL-STD-883, the  
VRG8691/92 is ideal for demanding military and space applications.  
CURRENT LIMIT (ICL)  
The VRG8691/92 features internal current limiting making them virtually blowout-proof against overloads. The limit  
is nominally 11.5A @ Vin = 5V (see Table 2), but may be increased or decreased with the addition of one external  
resistor (see Application Note 2).  
1
2
3
12  
11  
10  
VIN  
VOUT  
VRG8691/92  
VBIAS  
4
9
VSENSE  
5
6
Current Limit  
Slow Start  
8
7
ENABLE  
GND  
FIGURE 1 – BLOCK DIAGRAM / SCHEMATIC  
SCD8691 Rev H  
ABSOLUTE MAXIMUM RATINGS  
PARAMETER  
RANGE  
-55 to +150  
300  
UNITS  
°C  
Operating (Junction) Temperature Range  
Lead Temperature (soldering, 10 sec)  
Storage Temperature Range  
VBIAS, VIN  
°C  
-65 to +150  
7
°C  
V
Thermal Resistance (Junction to case JC)  
Power  
1
°C/W  
W
25 1/  
1/ Based on pass transistor limitations of (VIN - VO) x IO and JC < 1°C/W with 25°C max TJ rise and TC = +125°C.  
NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings  
only; functional operation beyond the “Operation Conditions” is not recommended and extended exposure beyond the “Operation  
Conditions” may effect device reliability.  
RECOMMENDED OPERATING CONDITIONS  
PARAMETER  
RANGE  
UNITS  
Output Voltage Range  
1.0 to 3.3  
VDC  
°C  
Case Operating Temperature Range  
-55 to +125  
Output Current  
VBIAS  
0 to 7.5  
A
3.3 to 5.5 1/  
1.8 to 5.5 2/  
VDC  
VDC  
VIN  
1/ VBIAS must maintain a level equal or above VIN but not fall below 3.3V  
2/ Depending upon VOUT setting.  
ELECTRICAL PERFORMANCE CHARACTERISTICS 1/  
PARAMETER  
SYM  
CONDITIONS  
MIN  
MAX UNITS  
Reference Voltage  
VREF  
VIN = VBIAS = 5V, ENABLE = 0, 0A < IOUT < 7.5A  
2V < VIN < 3V, VOUT = 1.0V, CIN > 47µF,  
0.985 1.015  
V
VOUT  
VIN  
Line Regulation  
Load Regulation  
-
-
0.2  
0.5  
%/V  
4.3V < VIN < 5.3V, VOUT = 3.3V, COUT > 47µF,  
0A < IOUT < 7.5A, CIN > 47µF, COUT > 47µF,  
VOUT  
IOUT  
%
f = 120Hz, CLOAD = 47µF,  
Ripple Rejection Ratio  
VIN + VRIP > VOUT + VDROP(MAX) @ 5A,  
VIN = 4.3V, VRIP = 1VP-P, VOUT = 3.3V  
80  
-
dB  
Dropout Voltage  
VDROP  
IADJ  
IMIN  
@VOUT = 1%, 0A < IOUT < 7.5A  
-
-
0.5  
3
V
µA  
mA  
A
Adjustment Pin Current  
Minimum Load Current  
Current Limit 2/  
-
0
ICL  
9.5  
13.5  
VOUT  
TIME  
Long Term Stability 3/  
-
-
1
%
Supply Current (VBIAS)  
Notes:  
IBIAS  
15  
mA  
1/ Unless otherwise specified, these specifications apply for post radiation: VBIAS = VIN = 5V, VOUT = 3.3V, IOUT = 7.5A and -55°C < Tc <+125°C, Min  
Input/Output capacity of 47µF Tant with 1µF ceramic in parallel.  
2/ Current Limit is adjustable as shown in Application Note 2, Figures 3 and 4.  
3/ Not tested. Shall be guaranteed to the specified limits after 1000hr life test.  
SCD8691 Rev H 11/12/13  
Aeroflex Plainview  
2
APPLICATION NOTE 1  
BASIC SET-UP  
Setting the output voltage (VOUT):  
4
VBIAS  
0.1µF  
VBIAS  
VRG8691/92  
1
2
10  
11  
VIN  
VOUT  
VIN  
VOUT  
1µF  
+ 47µF  
TANT  
3
12  
CER  
1µF  
+
8
5
7
CLOAD  
47µF  
CURR. LIMIT  
CURR. LIMIT  
ENABLE  
S
LOW  
S
TART  
CER  
R1  
R2  
0.1µF  
TANT  
ENABLE 1/  
GND  
VSENSE  
6
9
IADJ  
VREF (=1V)  
To set the output voltage for a particular Vout:  
- Choose an R2 value. (Recommended value = 1k  
- Then use the following formula to determine the value of R1.  
VOUT - VREF  
(R2 x IADJ) + VREF  
, where VREF = 1v, IADJ typ = 10pA  
R1 = R2 x  
Table 1 shows example values for R1 and R2 to achieve some standard voltages.  
Table 2 shows the nominal current limit settings if the ’CURR. LIMIT’ function (pin 8) is left open.  
Table 2  
2/  
Table 1  
Example R1 & R2 for typical VOUT  
VIN  
5V  
ICL NOM  
VOUT  
3.3V  
2.5V  
1.8V  
1.0V  
R2  
R1  
11.5A  
7.5A  
5.7A  
4.1A  
1k  
1k  
1k  
1k  
2.3k  
1.5k  
800  
0  
3.3V  
2.5V  
1.8V  
Notes:  
1/ ENABLE should be asserted after both VIN and VBIAS are applied.  
(See Application Note 3, Figure 5 for the configuration where a separate ENABLE control line is NOT required).  
2/ ICL varies directly with VIN.  
(See Application Note 2 for adjusting the Current Limit, ICL).  
FIGURE 2 –SETTING OUTPUT VOLTAGE  
SCD8691 Rev H 11/12/13  
3
Aeroflex Plainview  
APPLICATION NOTE 2  
SETTING THE CURRENT LIMIT  
To Increase the Current Limit (ICL):  
4
VBIAS  
VBIAS  
0.1µF  
VRG8691/92  
1
10  
VIN  
VOUT  
2
11  
12  
V
IN  
VOUT  
47µF  
1µF  
+
3
5
CER  
TANT  
1µF  
+
7
CLOAD  
47µF  
TANT  
ENABLE  
ENABLE  
S
LOW  
START  
CER  
R1  
R2  
0.1µF  
8
CURR. LIMIT  
GND  
VSENSE  
6
9
RINC  
IADJ  
VREF (=1V)  
- If the ’CURR. LIMIT’ function (pin 8) is left open, the ICL decreases from 11.5 A(NOM) as VIN is decreased from 5V (Table 3).  
Table 3  
VIN  
5V  
RINC  
Open  
Open  
Open  
Open  
ICL NOM  
11.5 A  
7.5 A  
3.3V  
2.5V  
1.8V  
5.7 A  
4.1 A  
- To increase the current limit above the nominal setting for any VIN and ICL combination, use the following formula:  
30 x VIN  
RINC(K-OHMS) =  
30 x ICL  
( )  
69  
- VIN  
- To maintain ICL at the 11.5 A setting, for commonly found VIN voltages, apply RINC value found in Table 4.  
Table 4  
VIN  
5V  
RINC  
Open  
56k  
30k  
16k  
ICL NOM  
11.5 A  
11.5 A  
11.5 A  
11.5 A  
3.3V  
2.5V  
1.8V  
FIGURE 3 – INCREASING THE CURRENT LIMIT (ICL)  
SCD8691 Rev H 11/12/13  
Aeroflex Plainview  
4
APPLICATION NOTE 2 (CONTINUED)  
SETTING THE CURRENT LIMIT  
To Decrease the Current Limit (ICL):  
4
VBIAS  
VBIAS  
0.1µF  
VRG8691/92  
1
10  
VIN  
VOUT  
2
11  
VIN  
VOUT  
1µF  
47µF  
+
3
12  
RDEC  
CER  
TANT  
1µF  
+
8
5
7
CLOAD  
47µF  
TANT  
CURR. LIMIT  
ENABLE  
CURR. LIMIT  
ENABLE  
S
LOW  
S
TART  
CER  
R1  
R2  
0.1µF  
GND  
VSENSE  
6
9
IADJ  
VREF (=1V)  
- As shown in Table 3, if the ’CURR. LIMIT’ function (pin 8) is left open, the ICL decreases from 11.5 A(NOM) as VIN is  
decreased from 5V.  
- To achieve any ICL, less than nominal, use RDEC which can be calculated using the following formula:  
31 x VIN  
RDEC(K-OHMS) =  
69 x VIN  
- ICL  
( )  
30  
FIGURE 4 – DECREASING THE CURRENT LIMIT (ICL)  
SCD8691 Rev H 11/12/13  
Aeroflex Plainview  
5
APPLICATION NOTE 3  
START UP SEQUENCE  
Recommended Power Supply Sequencing Options:  
- OPTION 1: Controlling the ENABLE line with a Digital signal (TTL / CMOS compatible).  
- Prior to applying power, disable the regulator by setting the ENABLE control line to a HIGH state.  
- Apply VIN and VBIAS. 1/  
- Wait until both VIN and VBIAS supplies have reached their operating levels.  
- Toggle the ENABLE control line to a LOW state to turn on VOUT of the regulator.  
- OPTION 2: Controlling the ENABLE line using the CDELAY feature.  
- Connect a CDELAY capacitor between VBIAS and the ENABLE as shown in Figure 5 below. 2/  
- Apply VIN and VBIAS. 1/  
- CDELAY causes the regulator to self-enable after VBIAS has reached operating level.  
NOTE: The ENABLE should always be asserted AFTER VIN and VBIAS have reached operating level.  
4
VBIAS  
VBIAS  
0.1µF  
VRG8691/92  
1
10  
VIN  
VOUT  
2
2/  
11  
12  
VIN  
VOUT  
1µF  
+
47µF  
3
+
CDELAY  
CER  
TANT  
1µF  
+
1/  
8
5
7
CLOAD  
47µF  
TANT  
CURR. LIMIT  
ENABLE  
SLOW  
START  
CER  
R1  
R2  
0.1µF  
GND  
VSENSE  
6
9
IADJ  
VREF (=1V)  
NOTES:  
1/ VIN should be applied before VBIAS if the Slow Start feature is used.  
2/ CDELAY capacitor of 10uF is adequate for VBIAS rise times of up to 50ms.  
FIGURE 5 – DELAYED ENABLE  
SCD8691 Rev H 11/12/13  
Aeroflex Plainview  
6
APPLICATION NOTE 4  
VOUT START UP RISE TIME CONTROL  
Utilizing the Slow Start option:  
When the VRG8691/92 is first powered up, using the Slow Start function controls the rate at which VOUT rises to the  
required voltage set by R1 and R2.  
Note: VIN should be applied before VBIAS when the Slow Start feature is used.  
4
VBIAS  
VBIAS  
0.1µF  
VRG8691/92  
1
10  
VIN  
VOUT  
2
11  
VIN  
VOUT  
1µF  
47µF  
+
3
12  
CER  
TANT  
1µF  
+
8
5
7
CLOAD  
47µF  
CURR. LIMIT  
ENABLE  
S
LOW  
S
TART  
CER  
0.1µF  
R1  
R2  
TANT  
ENABLE  
+
0
CSS  
GND  
VSENSE  
6
9
IADJ  
VREF (=1V)  
If it is desirable to control the output rise time, a capacitor (CSS) can be asserted on the Slow Start pin to adjust the rise  
time for the following:  
A. Large load capacitance will cause high surge currents which will trip the current limit circuitry.  
The use of CSS will allow the output voltage to rise slowly thus mitigate the surge current phenomenon.  
VOUT NOM  
ICL - ILOAD NOM  
CSS  
CLOAD  
>
X
(0.4 X 0.0014)  
B. CSS may be used solely to control VOUT RISE TIME (Tr), when CLOAD is not an issue.  
CSS X 2.5  
Note: CSS in Farads and TR in seconds.  
TR =  
( )  
0.0014  
C. CSS is effective only when VIN is applied prior to VBIAS or ENABLE.  
FIGURE 6 – SLOW START  
SCD8691 Rev H 11/12/13  
7
Aeroflex Plainview  
PIN NUMBERS vs FUNCTION  
PIN  
FUNCTION  
PIN  
FUNCTION  
1
2
3
4
5
6
VIN  
7
8
Slow Start  
Current Limit  
VSENSE  
VOUT  
VIN  
VIN  
9
VBIAS  
ENABLE  
GROUND  
10  
11  
12  
VOUT  
VOUT  
Notes:  
1. Dimension Tolerance: ±.005 inches  
2. Package contains BeO substrate  
3. Case electrically isolated  
FIGURE 3 – PACKAGE OUTLINE — VRG8691 THRU-HOLE POWER PACKAGE  
SCD8691 Rev H 11/12/13  
Aeroflex Plainview  
8
PIN NUMBERS vs FUNCTION  
PIN  
FUNCTION  
PIN  
FUNCTION  
1
2
3
4
5
6
VIN  
7
8
Slow Start  
Current Limit  
VSENSE  
VOUT  
VIN  
VIN  
9
VBIAS  
ENABLE  
GROUND  
10  
11  
12  
VOUT  
VOUT  
Notes:  
1. Dimension Tolerance: ±.005 inches  
2. Package contains BeO substrate  
3. Case electrically isolated  
FIGURE 4 – PACKAGE OUTLINE — VRG8692 SURFACE MOUNT POWER PACKAGE  
SCD8691 Rev H 11/12/13  
Aeroflex Plainview  
9
ORDERING INFORMATION  
MODEL  
DLA SMD #  
SCREENING  
PACKAGE  
VRG8691-7  
-
Commercial Flow, +25°C testing only  
Military Temperature, -55°C to +125°C  
Screened in accordance with the individual Test Methods  
of MIL-STD-883 for Space Applications  
VRG8691-S  
-
12 Lead  
Thru-Hole  
Power Pkg  
VRG8691-201-1S  
VRG8691-201-2S  
VRG8691-901-1S  
VRG8691-901-2S  
VRG8692-7  
5962-0923701KXC  
5962-0923701KXA  
5962R0923701KXC  
5962R0923701KXA  
-
In accordance with DLA SMD  
In accordance with DLA Certified RHA Program Plan to RHA  
Level "R", 100krads(Si)  
Commercial Flow, +25°C testing only  
Military Temperature, -55°C to +125°C  
Screened in accordance with the individual Test Methods  
of MIL-STD-883 for Space Applications  
VRG8692-S  
-
12 Lead  
Surface Mount  
Power Pkg  
VRG8692-201-1S  
VRG8692-201-2S  
VRG8692-901-1S  
VRG8692-901-2S  
5962-0923701KYC  
5962-0923701KYA  
5962R0923701KYC  
5962R0923701KYA  
In accordance with DLA SMD  
In accordance with DLA Certified RHA Program Plan to RHA  
Level "R", 100krads(Si)  
EXPORT CONTROL:  
EXPORT WARNING:  
This product is controlled for export under the International Traffic in  
Arms Regulations (ITAR). A license from the U.S. Department of  
State is required prior to the export of this product from the United  
States.  
Aeroflex’s military and space products are controlled for export under  
the International Traffic in Arms Regulations (ITAR) and may not be  
sold or proposed or offered for sale to certain countries. (See ITAR  
126.1 for complete information.)  
PLAINVIEW, NEW YORK  
INTERNATIONAL  
NORTHEAST  
Tel: 603-888-3975  
Fax: 603-888-4585  
Toll Free: 800-THE-1553  
Tel: 805-778-9229  
Fax: 516-694-6715  
Fax: 805-778-1980  
SE AND MID-ATLANTIC  
Tel: 321-951-4164  
WEST COAST  
Tel: 949-362-2260  
CENTRAL  
Tel: 719-594-8017  
Fax: 321-951-4254  
Fax: 949-362-2266  
Fax: 719-594-8468  
w w w . a e r o f l e x . c o m  
i n f o - a m s @ a e r o f l e x . c o m  
Aeroflex Microelectronic Solutions reserves the right to  
change at any time without notice the specifications, design,  
function, or form of its products described herein. All  
parameters must be validated for each customer's application  
by engineering. No liability is assumed as a result of use of  
this product. No patent licenses are implied.  
Our passion for performance is defined by three  
attributes represented by these three icons:  
solution-minded, performance-driven and customer-focused  
SCD8691 Rev H 11/12/13  
10  

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