L-FW32206T100_技术文档

Data Sheet, Rev. 1

December 2005

™

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

— Provides two fully compliant cable ports, each

supporting 400 Mbits/s, 200 Mbits/s, and

100 Mbits/s traffic

— Supports extended BIAS_HANDSHAKE time for

enhanced interoperability with camcorders

— While unpowered and connected to the bus, will not

drive TPBIAS on a connected port even if receiving

incoming bias voltage on that port

— Does not require external filter capacitor for PLL

— Supports link-on as a part of the internal

PHY core-link interface

— 25 MHz crystal oscillator and internal PLL provide a

50 MHz internal link-layer controller clock as well

as transmit/receive data at 100 Mbits/s, 200 Mbits/s,

and 400 Mbits/s.

Features

1394a-2000 OHCI link and PHY core function in a sin-

gle device:

— 100-pin TQFP package (also available in a lead-free

package; see ordering information on page 85.)

— Single-chip link and PHY enable smaller, simpler,

more efficient motherboard and add-in card designs

— Enables lower system costs

— Leverages proven 1394a-2000 PHY core design

— Demonstrated compatibility with current Microsoft

Windows^®drivers and common applications

— Demonstrated interoperability with existing, as well

as older, 1394 consumer electronics and peripherals

products

— Interoperable across 1394 cable with 1394 physical

layers (PHY core) using 5 V supplies

— Provides node power-class information signaling for

system power management

— Supports ack-accelerated arbitration and fly-by

concatenation

— Supports arbitrated short bus reset to improve

utilization of the bus

— Fully supports suspend/resume

— Feature-rich implementation for high performance in

common applications

— Supports low-power system designs (CMOS imple-

mentation, power management features)

OHCI:

— Complies with the 1394 OHCI 1.1 Specification

— OHCI 1.0 backwards compatible—configurable via

EEPROM to operate in either OHCI 1.0 or OHCI 1.1

mode

— Complies with Microsoft Windows logo program

system and device requirements

— Listed on Windows hardware compatibility list

http://www.microsoft.com/hcl/results.asp

— Compatible with Microsoft Windows and MacOS^®

operating systems

— 4 Kbyte isochronous transmit FIFO

— 2 Kbyte asynchronous transmit FIFO

— 4 Kbyte isochronous receive FIFO

— 2 Kbyte asynchronous receive FIFO

— Dedicated asynchronous and isochronous

descriptor-based DMA engines

— Supports connection debounce

— Supports multispeed packet concatenation

— Supports PHY pinging and remote PHY access

packets

— Reports cable power fail interrupt when voltage at

CPS pin falls below 7.5 V

Link:

— Cycle master and isochronous resource manager

capable

— Supports 1394a-2000 acceleration features

PCI:

— Revision 2.2 compliant

— Eight isochronous transmit contexts

— Eight isochronous receive contexts

— Prefetches isochronous transmit data

— Supports posted write transactions

— Supports parallel processing of incoming physical

read and write requests

— 33 MHz/32-bit operation

— Programmable burst size thresholds for PCI data

transfer

— Supports optimized memory read line, memory read

multiple, and memory write invalidate burst

commands

— Supports PCI Bus Power Management Interface

Specification v.1.1.

— Supports notification (via interrupt) of a failed

register access

— Information normally in the EEPROM can be pro-

grammed into the system BIOS.

Note: This device does not support D3cold wakeup,

CLKRUN protocol, mini PCI^®applications, and

CardBus applications. Use the FW322 06 120-pin

TQFP device if one or more of these features are

needed.

1394a-2000 PHY core:

— Compliant with IEEE ^®1394a-2000, Standard for a

High Performance Serial Bus (Supplement)

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Data Sheet, Rev. 1

December 2005

Table of Contents

Contents

Page

Features ...................................................................................................................................................................1

Other Features....................................................................................................................................................6

FW322 Functional Overview ....................................................................................................................................6

FW322 Functional Description .................................................................................................................................7

PCI Core.............................................................................................................................................................7

OHCI Data Transfer............................................................................................................................................8

OHCI Isochronous Data Transfer .......................................................................................................................8

Isochronous Register Access .............................................................................................................................9

OHCI Asynchronous Data Transfer....................................................................................................................9

Asynchronous Register Access..........................................................................................................................9

Link Core ..........................................................................................................................................................11

PHY Core..........................................................................................................................................................13

Pin Information .......................................................................................................................................................15

Internal Registers ...................................................................................................................................................21

PCI Configuration Registers .............................................................................................................................21

Vendor ID Register ...........................................................................................................................................22

Device ID Register............................................................................................................................................22

PCI Command Register....................................................................................................................................23

PCI Status Register ..........................................................................................................................................24

Class Code and Revision ID Registers.............................................................................................................25

Latency Timer and Cache Line Size Register ..................................................................................................25

Header Type and BIST Register.......................................................................................................................26

OHCI Base Address Register...........................................................................................................................26

PCI Subsystem Identification Register .............................................................................................................27

PCI Power Management Capabilities Pointer Register ....................................................................................27

Interrupt Line and Pin Register.........................................................................................................................28

MIN_GNT and MAX_LAT Register...................................................................................................................28

PCI OHCI Control Register...............................................................................................................................29

Capability ID and Next Item Pointer Register ...................................................................................................29

Power Management Capabilities Register........................................................................................................30

Power Management Control and Status Register ............................................................................................31

Power Management CSR PCI-to-PCI Bridge Support Extensions ...................................................................32

Power Management Data.................................................................................................................................32

OHCI Registers.................................................................................................................................................33

OHCI Version Register .....................................................................................................................................36

GUID ROM Register.........................................................................................................................................37

Asynchronous Transmit Retries Register .........................................................................................................37

CSR Data Register ...........................................................................................................................................38

CSR Compare Register....................................................................................................................................38

CSR Control Register .......................................................................................................................................38

Configuration ROM Header Register................................................................................................................39

Bus Identification Register................................................................................................................................40

Bus Options Register........................................................................................................................................40

GUID High Register..........................................................................................................................................41

GUID Low Register...........................................................................................................................................41

Configuration ROM Mapping Register..............................................................................................................42

Posted Write Address Low Register .................................................................................................................43

Posted Write Address High Register ................................................................................................................43

Vendor ID Register ...........................................................................................................................................43

Host Controller Control Register.......................................................................................................................44

SelfID Buffer Pointer Register...........................................................................................................................46

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Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Table of Contents (continued)

Contents

Page

SelfID Count Register .......................................................................................................................................46

Isochronous Receive Multiple Channel Mask High (IRMultiChanMaskHi) Register.........................................47

Isochronous Receive Multiple Channel Mask Low (IRMultiChanMaskLo) Register .........................................47

Interrupt Event (IntEvent) Register ...................................................................................................................48

Interrupt Mask (IntMask) Register.....................................................................................................................50

Isochronous Transmit Interrupt Event (isoXmitIntMask) Register.....................................................................52

Isochronous Transmit Interrupt Mask (isoXmitIntMask) Register .....................................................................53

Isochronous Receive Interrupt Event (isoRecvIntEvent) Register....................................................................54

Isochronous Receive Interrupt Mask (isoRecvIntMask) Register .....................................................................55

Fairness Control Register .................................................................................................................................55

Link Control Register ........................................................................................................................................56

Node Identification Register..............................................................................................................................57

PHY Core Layer Control Register.....................................................................................................................58

Isochronous Cycle Timer Register....................................................................................................................58

Asynchronous Request Filter High Register.....................................................................................................59

Asynchronous Request Filter Low Register......................................................................................................59

Physical Request Filter High Register ..............................................................................................................60

Physical Request Filter Low Register ...............................................................................................................60

Asynchronous Context Control Register...........................................................................................................61

Asynchronous Context Command Pointer Register .........................................................................................62

Isochronous Transmit Context Control (IT DMA ContextControl) Register ......................................................63

Isochronous Transmit Context Command Pointer Register..............................................................................64

Isochronous Receive Context Control (IR DMA ContextControl) Register.......................................................65

Isochronous Receive Context Command Pointer Register...............................................................................66

Isochronous Receive Context Match (IR DMA ContextMatch) Register...........................................................67

FW322 Vendor-Specific Registers....................................................................................................................68

Isochronous DMA Control.................................................................................................................................68

Asynchronous DMA Control..............................................................................................................................69

Link Options......................................................................................................................................................70

Internal Register Configuration ...............................................................................................................................71

PHY Core Register Map ...................................................................................................................................71

PHY Core Register Fields.................................................................................................................................72

Crystal Selection Considerations ............................................................................................................................77

Load Capacitance.............................................................................................................................................77

Adjustment to Crystal Loading..........................................................................................................................77

Crystal/Board Layout ........................................................................................................................................77

Serial EEPROM Interface .......................................................................................................................................78

ac Characteristics of Serial EEPROM Interface Signals ........................................................................................78

Solder Reflow and Handling ...................................................................................................................................81

Absolute Maximum Voltage/Temperature Ratings .................................................................................................81

Electrical Characteristics ........................................................................................................................................82

Timing Characteristics ............................................................................................................................................84

Outline Diagrams ....................................................................................................................................................85

100-Pin TQFP...................................................................................................................................................85

Ordering Information ...............................................................................................................................................85

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1394a PCI PHY/Link Open Host Controller

Data Sheet, Rev. 1

December 2005

Table of Contents (continued)

Figure

Page

Figure 1. FW322 Conceptual Block Diagram ...........................................................................................................6

Figure 2. PCI Core Block Diagram ...........................................................................................................................7

Figure 3. OHCI Core Block Diagram ........................................................................................................................8

Figure 4. Link Core Block Diagram .........................................................................................................................11

Figure 5. The PHY Core Block Diagram .................................................................................................................12

Figure 6. Pin Assignments for the FW322 06 T100 ................................................................................................15

Figure 7. Crystal Circuitry .......................................................................................................................................77

Figure 8. Bus Timing ..............................................................................................................................................79

Figure 9. Write Cycle Timing ..................................................................................................................................79

Figure 10. Data Validity ..........................................................................................................................................79

Figure 11. Start and Stop Definition .......................................................................................................................80

Figure 12. Output Acknowledge .............................................................................................................................80

Table

Page

Table 1. Pin Descriptions ....................................................................................................................................... 16

Table 2. Bit-Field Access Tag Description ............................................................................................................. 21

Table 3. PCI Configuration Register Map ............................................................................................................. 21

Table 4. PCI Command Register Description ........................................................................................................ 23

Table 5. PCI Status Register ................................................................................................................................. 24

Table 6. Class Code and Revision ID Register Description .................................................................................. 25

Table 7. Latency Timer and Class Cache Line Size Register Description ........................................................... 25

Table 8. Header Type and BIST Register Description .......................................................................................... 26

Table 9. OHCI Base Address Register Description ............................................................................................... 26

Table 10. PCI Subsystem Identification Register Description ............................................................................... 27

Table 11. Interrupt Line and Pin Register Description ........................................................................................... 28

Table 12. MIN_GNT and MAX_LAT Register Description ..................................................................................... 28

Table 13. PCI OHCI Control Register Description ................................................................................................. 29

Table 14. Capability ID and Next Item Pointer Register Description ..................................................................... 29

Table 15. Power Management Capabilities Register Description ......................................................................... 30

Table 16. Power Management Control and Status Register Description .............................................................. 31

Table 17. Power Management Data Register Description .................................................................................... 32

Table 18. OHCI Register Map ............................................................................................................................... 33

Table 19. OHCI Version Register Description ....................................................................................................... 36

Table 20. GUID ROM Register Description ........................................................................................................... 37

Table 21. Asynchronous Transmit Retries Register Description ........................................................................... 37

Table 22. CSR Data Register Description ............................................................................................................. 38

Table 23. CSR Compare Register Description ...................................................................................................... 38

Table 24. CSR Control Register Description ........................................................................................................ 38

Table 25. Configuration ROM Header Register Description ................................................................................. 39

Table 26. Bus Identification Register Description .................................................................................................. 40

Table 27. Bus Options Register Description .......................................................................................................... 40

Table 28. GUID High Register Description ............................................................................................................ 41

Table 29. GUID Low Register Description ............................................................................................................. 41

Table 30. Configuration ROM Mapping Register Description ................................................................................ 42

Table 31. Posted Write Address Low Register Description ................................................................................... 43

Table 32. Posted Write Address High Register Description .................................................................................. 43

Table 33. Vendor ID Register Description ............................................................................................................. 43

Table 34. Host Controller Control Register Description ......................................................................................... 44

Table 35. SelfID Buffer Pointer Register Description ............................................................................................ 46

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Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Table of Contents (continued)

Table

Page

Table 36. SelfID Count Register Description ......................................................................................................... 46

Table 37. Isochronous Receive Channel Mask High Register Description ........................................................... 47

Table 38. Isochronous Receive Channel Mask Low Register Description ............................................................ 47

Table 39. Interrupt Event Register Description ...................................................................................................... 48

Table 40. Interrupt Mask Register Description ...................................................................................................... 50

Table 41. Isochronous Transmit Interrupt Event Register Description .................................................................. 52

Table 42. Isochronous Transmit Interrupt Event Description ................................................................................ 53

Table 43. Isochronous Receive Interrupt Event Description ................................................................................. 54

Table 44. Fairness Control Register Description ................................................................................................... 55

Table 45. Link Control Register Description ......................................................................................................... 56

Table 46. Node Identification Register Description ............................................................................................... 57

Table 47. PHY Core Layer Control Register Description ...................................................................................... 58

Table 48. Isochronous Cycle Timer Register Description ..................................................................................... 58

Table 49. Asynchronous Request Filter High Register Description ....................................................................... 59

Table 50. Asynchronous Request Filter Low Register Description ....................................................................... 59

Table 51. Physical Request Filter High Register Description ................................................................................ 60

Table 52. Physical Request Filter Low Register Description ................................................................................. 60

Table 53. Asynchronous Context Control Register Description ........................................................................... 61

Table 54. Asynchronous Context Command Pointer Register Description ........................................................... 62

Table 55. Isochronous Transmit Context Control Register Description ................................................................ 63

Table 56. Isochronous Transmit Context Command Pointer Register Description ............................................... 64

Table 57. Isochronous Receive Context Control Register Description .................................................................. 65

Table 58. Isochronous Receive Context Command Pointer Register Description ................................................ 66

Table 59. Isochronous Receive Context Match Register Description ................................................................... 67

Table 60. FW322 Vendor-Specific Registers Description ..................................................................................... 68

Table 61. Isochronous DMA Control Registers Description .................................................................................. 68

Table 62. Asynchronous DMA Control Registers Description ............................................................................... 69

Table 63. Link Options Register Description ......................................................................................................... 70

Table 64. PHY Core Register Map ........................................................................................................................ 71

Table 65. PHY Core Register Fields ..................................................................................................................... 72

Table 66. PHY Core Register Page 0: Port Status Page ...................................................................................... 74

Table 67. PHY Core Register Port Status Page Fields ........................................................................................ 75

Table 68. PHY Core Register Page 1: Vendor Identification Page ....................................................................... 76

Table 69. PHY Core Register Vendor Identification Page Fields .......................................................................... 76

Table 70. ac Characteristics of Serial EEPROM Interface Signals ....................................................................... 78

Table 71. Absolute Maximum Ratings ................................................................................................................... 81

Table 72. Analog Characteristics ........................................................................................................................... 82

Table 73. Driver Characteristics ............................................................................................................................ 83

Table 74. Device Characteristics ........................................................................................................................... 83

Table 75. Switching Characteristics ...................................................................................................................... 84

Table 76. Clock Characteristics ............................................................................................................................. 84

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FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Data Sheet, Rev. 1

December 2005

Features (continued)

Other Features

I²C serial ROM interface

CMOS process

3.3 V operation, 5 V tolerant inputs

FW322 Functional Overview

The FW322 is a high-performance, PCI bus-based open host controller designed by Agere Systems Inc. for imple-

mentation of IEEE 1394a-2000 compliant systems and devices. Link-layer functions are handled by the FW322, uti-

lizing the on-chip 1394a-2000 compliant link core and physical layer core. A high-performance and cost-effective

solution for connecting and servicing multiple IEEE 1394 (both 1394-1995 and 1394a-2000) peripheral devices can

be realized using this PHY/link OHCI device.

OHCI

ASYNCHRONOUS

DATA

TRANSFER

CABLE PORT 1

PCI

BUS

PCI

CORE

PHY

CORE

OHCI

LINK

CORE

ISOCHRONOUS

CABLE PORT 0

DATA

TRANSFER

ROM

I/F

5-6250 (F).f

Figure 1. FW322 Conceptual Block Diagram

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Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

FW322 Functional Description

The FW322 is comprised of four major functional sections (see Figure 1): PCI core, OHCI isochronous and

asynchronous data transfer, link core, and PHY core. The following is a general description of each of the major

sections.

PCI SLAVE

SLAVE

CONTROL

ADDRESS/DATA

MUX

PCI MASTER

MASTER

CONTROL

PCI BUS

PCI

CONFIGURATION

Figure 2. PCI Core Block Diagram

PCI Core

The PCI core (shown in Figure 2) serves as the interface to the PCI bus. It contains the state machines that allow

the FW322 to respond properly when it is the target of the transaction. Also, during 1394 packet transmission or

reception, the PCI core arbitrates for the PCI bus and enables the FW322 to become the bus master for reading the

different buffer descriptors and management of the actual data transfers to/from host system memory.

The PCI core also supports the PCI Bus Power Management Interface Specification v.1.1. Included in this support

is a standard power management register interface accessible through the PCI configuration space. Through this

register interface, software is able to transition the FW322 into four distinct power consumption states (D0, D1, D2,

and D3hot). This permits software to selectively increase/decrease the power consumption of the FW322 for

reasons such as periods of system inactivity or power conservation. In addition, the FW322 also includes support

for waking up the system through the generation of a power management event (PME).

The FW322 supports generation of a power management event (PME) while in the D0, D1, D2, and D3hot power

states.

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FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Data Sheet, Rev. 1

December 2005

FW322 Functional Description (continued)

ASYNCHRONOUS DATA TRANSFER

SELFID DMA

AR FIFO

ASYNC

RX

ADMIN

ASYNC_RX

DMA

PCI32 INTERFACE

ASYNC

REGISTER

ACCESS

PHYSICAL

REQUEST/

RESPONSE

DMA

PCI SLAVE

AT FIFO

REGISTER

SELECT

ASYNC

TX

ADMIN

ASYNC_TX

DMA

OHCI

INTERRUPT

HANDLER

ISOCHRONOUS DATA TRANSFER

IR FIFO

IT FIFO

ISOCH

REGISTER

ACCESS

ISOCH

RECEIVE

DMA

PCI MASTER

ARBITER

ISOCH

TRANSMIT

DMA

Figure 3. OHCI Core Block Diagram

OHCI Data Transfer

The OHCI core consists of the three blocks shown in Figure 3: the PCI interface (PCI32_interface), the isochro-

nous data transfer, and the asynchronous data transfer blocks. The PCI interface provides an interface between

the OHCI blocks and the PCI core. It contains an arbiter to select the appropriate OHCI data engine to gain access

to the PCI core. In addition, the PCI interface includes a register select function to decode slave accesses to the

OHCI core and select data from appropriate sources. The PCI interface also has an OHCI interrupt handler to ser-

vice OHCI generated interrupts, which are ultimately translated into PCI interrupts.

OHCI Isochronous Data Transfer

The isochronous data transfer logic, which is incorporated into the OHCI core, handles the transfer of isochronous

data between the link core and the PCI interface module. It consists of the Isochronous register access module, the

isochronous transmit DMA module, the isochronous receive DMA module, the isochronous transmit (IT) FIFO, and

the isochronous receive (IR) FIFO.

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Agere Systems Inc.

Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

1394 isochronous channel. However, software can

select one context to receive data on multiple chan-

nels.

FW322 Functional Description (continued)

Isochronous Register Access

When IRDMA detects that the link core has placed data

into the receive FIFO, it immediately reads out the first

word in the FIFO, which makes up the header of the

isochronous packet. IRDMA extracts the channel

number for the packet and packet filtering controls from

the header. This information is compared with the

Control registers for each context to determine if any

context is to process this packet.

The Isochronous register access module services PCI

slave accesses to OHCI registers within the isochro-

nous block. The module also maintains the status of

interrupts generated within the isochronous block and

sends the isochronous interrupt status to the OHCI

interrupt handler block.

Isochronous Transmit DMA (ITDMA)

If a match is found, IRDMA will request access to the

PCI bus. When granted PCI access, a descriptor block

is fetched from host memory. The descriptor provides

information about the host memory block allocated for

the incoming packet. IRDMA then reads the packet

from the receive FIFO and writes the data to host

memory via the PCI bus.

The isochronous transmit DMA (ITDMA) module

moves data from host memory to the link core, which

will then send the data via the PHY core to the 1394

bus. This module consists of eight isochronous

transmit contexts, each of which is independently

configurable by software, and is capable of sending

data on a separate 1394 isochronous channel.

If no match is found, IRDMA will read the remainder of

the packet from the receive FIFO, but not process the

data in any way.

During each 1394 isochronous cycle, the ITDMA

module will service each of the contexts and attempt to

process one 1394 packet for each active context. While

processing an active context, ITDMA will request

access to the PCI bus. When granted PCI access, a

descriptor block is fetched from host memory. This data

is decoded by ITDMA to determine how much data is

required and where in host memory the data resides.

ITDMA initiates another PCI access to fetch this data,

which is placed into the isochronous transmit FIFO for

processing by the link core. If the context is not active,

it is skipped by ITDMA for the current cycle.

OHCI Asynchronous Data Transfer

The asynchronous data transfer block within the OHCI

core is functionally partitioned into blocks responsible

for processing incoming SelfID packet streams, trans-

mitting and receiving asynchronous 1394 packets, pro-

cessing incoming physical request packets and

outgoing physical response packets, and servicing

accesses to OHCI registers within the respective asyn-

chronous blocks.

After processing each context, ITDMA writes a cycle

marker word in the transmit FIFO to indicate to the link

core that there is no more data for this isochronous

cycle. As a summary, the major steps for the FW322

ITDMA to transmit a packet are the following:

Asynchronous Register Access

The Asynchronous register access module operates on

PCI slave accesses to OHCI registers within the asyn-

chronous block. The module also maintains the status

of interrupts generated within the asynchronous block

and sends the asynchronous interrupt status to the

OHCI interrupt handler block.

1. Fetch a descriptor block from host memory.

2. Fetch data specified by the descriptor block from

host memory, and place it into the isochronous

transmit FIFO.

3. Data in FIFO is read by the link and sent to the PHY

core device interface.

Isochronous Receive DMA (IRDMA)

The isochronous receive DMA (IRDMA) module moves

data from the isochronous receive FIFO to host

memory. It consists of eight isochronous contexts, each

of which is independently controlled by software.

Normally, each context can process data on a single

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FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Data Sheet, Rev. 1

December 2005

The header of the received packet is processed to

determine, among other things, the following:

FW322 Functional Description (continued)

Asynchronous Transmit DMA (ASYNC_TX DMA,

ASYNC_TX_ADMIN)

1. The type of packet received.

2. The source and destinations.

3. The data and size, if any.

The ASYNC_TX DMA and ASYNC_TX_ADMIN blocks

of the FW322 manage the asynchronous transmission

of either request or response packets. The mechanism

for asynchronous transmission of requests and

responses is similar. The only difference is the system

memory location of the buffer descriptor list when

processing the two contexts. Therefore, the discussion

below, which pertains to asynchronous transmit

requests, parallels that of asynchronous transmit

responses.

4. Any required operation, for example, compare and

swap operation.

The asynchronous data transfer block also handles

DMA transfers of SelfID packets during the 1394 bus

initialization phase and block transactions associated

with physical requests.

Physical Request/Response DMA

The Physical DMA block within the FW322 is responsi-

ble for processing incoming physical requests and out-

going physical responses. When an incoming

The FW322 asynchronous transmission of packets

involves the following steps:

asynchronous packet is received, the FW322 will pro-

cess the packet automatically without software inter-

vention if the packet meets a set of criteria defined

within the OHCI specification. When the criteria are

met, the asynchronous packet is reclassified as a phys-

ical packet. Requests that do not meet the criteria

remain asynchronous packets and are processed as

described above in the Asynchronous Receive DMA

section. Processing packets as physical requests/

responses allows the FW322 to either receive or trans-

mit an asynchronous packet without the use of DMA

descriptors. Instead, the FW322 directly writes or reads

data to/from memory using the address defined within

the packet header. Since physical packets can be pro-

cessed independently of the system’s software and

CPU, processing a packet as physical results in a sys-

tem performance optimization.

1. Fetch complete buffer descriptor block from host

memory.

2. Get data from system memory and store into

asynchronous transmit (AT) FIFO.

3. Request transfer of data from FIFO to the link core.

4. Handle retries, if any.

5. Handle errors in steps 1 to 4.

6. End the transfer if there are no errors.

Asynchronous Receive DMA (ASYNC_RX DMA,

ASYNC_RX_ADMIN)

The ASYNC_RX DMA and ASYNC_RX_ADMIN blocks

of the FW322 manage the processing of received

packets. Data packets are parsed and stored in a

dedicated asynchronous receive (AR) FIFO. Command

descriptors are read through the PCI interface to

determine the disposition of the data arriving through

the 1394 link.

SelfID DMA

The SelfID DMA block within the FW322 is responsible

for receiving SelfID packets during the bus initialization

process. The received SelfID packets are written into a

software-defined host memory buffer.

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Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

FW322 Functional Description (continued)

ISOCH

CONTROL

TIMER

AT FIFO

TX

IT FIFO

PHYDATA

DATAMUX

CRC

AR FIFO

PHYCTL

PHY - LINK

INTERFACE

RX

IRFIFO

ADDRESS

DECODER

LINK CONTROL

STATE

MACHINE

PHYLREQ

PCI SLAVE

INTERFACE

CONTROL

Figure 4. Link Core Block Diagram

Link Core

The link core shown in Figure 4 consists of the following blocks:

Link Control State Machine: main link state machine that controls all other link core modules.

Transmit (TX): reads from the AT and IT FIFOs and forms 1394 packets for transmit.

Receive (RX): pipes incoming 1394 packet data to appropriate FIFO (if any).

Address Decoder: decodes the destination ID of an incoming 1394 packet to determine if an acknowledge is

needed.

CRC: calculates and checks CRC on outgoing and incoming packets.

Isochronous Control Timer: contains the logic for the 1394 cycle timer.

DataMUX: pipes 1394 data to and from various modules.

Interface Control: contains interrupt and registers for the link core. Interfaces with the slave control block of the

PCI core.

PHY-Link Interface: interfaces with the 1394 physical layer.

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FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Data Sheet, Rev. 1

December 2005

To become aware of data to be sent outbound on the

1394 bus, the link must monitor the OHCI FIFOs look-

ing for packets in need of transmission. Based on data

received from the OHCI block, the link will form packet

headers for the 1394 bus. The link will alert the PHY

core regarding the availability of the outbound data. It is

the link’s function to generate CRC for the outbound

data. The link also provides PHY core register access

for the OHCI.

FW322 Functional Description (continued)

It is the responsibility of the link to ascertain if a

received packet is to be forwarded to the OHCI for

processing. If so, the packet is directed to a proper

inbound FIFO for either the isochronous block or the

asynchronous block to process. The link is also

responsible for CRC generation on outgoing packets

and CRC checking on received packets.

RECEIVED

CPS

LPS*

BIAS

VOLTAGE

AND

CURRENT

GENERATOR

DATA

R0

R1

DECODER/

RETIMER

SYSCLK*

LREQ*

CTL0*

CTL1*

LINK

INTERFACE

I/O

D0*

D1*

D2*

D3*

D4*

D5*

D6*

D7*

TPA0+

TPA0–

ARBITRATION

AND

TPBIAS0

CONTROL

STATE

LKON*

PC0*

MACHINE

LOGIC

CABLE PORT 0

PC1*

PC2

CONTENDER*

SE

TPB0+

TPB0–

SM

TPA1+

TPA1–

TPBIAS1

TPB1+

TPB1–

CABLE PORT 1

TRANSMIT

DATA

ENCODER

RESETN

CRYSTAL

OSCILLATOR,

PLL SYSTEM,

AND

XI

XO

CLOCK

GENERATOR

5-5459.i(F) R.01

* Internal points, unaccessible via external package pins.

Figure 5. The PHY Core Block Diagram

122

Agere Systems Inc.

Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Both the TPA and TPB cable interfaces incorporate

differential comparators to monitor the line states dur-

ing initialization and arbitration. The outputs of these

comparators are used by the internal logic to deter-

mine the arbitration status. The TPA channel monitors

the incoming cable common-mode voltage. The value

of this common-mode voltage is used during arbitra-

tion to set the speed of the next packet transmission.

FW322 Functional Description (continued)

PHY Core

The PHY core in Figure 5 on the preceding page pro-

vides the analog physical layer functions needed to

implement a two-port node in a cable-based IEEE

1394-1995 and IEEE 1394a-2000 network.

In addition, the TPB channel monitors the incoming

cable common-mode voltage for the presence of the

remotely supplied twisted-pair bias voltage. This

monitor is called bias-detect.

Each cable port incorporates two differential line trans-

ceivers. The transceivers include circuitry to monitor

the line conditions as needed for determining connec-

tion status, for initialization and arbitration, and for

packet reception and transmission. The PHY core

interfaces with the link core.

The TPBIAS circuit monitors the value of incoming

TPA pair common-mode voltage when local TPBIAS is

inactive. Because this circuit has an internal current

source and the connected node has a current sink, the

monitored value indicates the cable connection status.

The monitor is called connect-detect.

The PHY core requires either an external 24.576 MHz

crystal or crystal oscillator. The internal oscillator

drives an internal phase-locked loop (PLL), which gen-

erates the required 393.216 MHz reference signal. The

393.216 MHz reference signal is internally divided to

provide the 49.152 MHz, 98.304 MHz, and

196.608 MHz clock signals that control transmission of

the outbound encoded strobe and data information.

The 49.152 MHz clock signal is also supplied to the

associated link layer controller (LLC) for synchroniza-

tion of the link with the PHY core and is used for

resynchronization of the received data.

Both the TPB bias-detect monitor and TPBIAS

connect-detect monitor are used in suspend/resume

signaling and cable connection detection.

The PHY core provides a 1.86 V nominal bias voltage

for driver load termination. This bias voltage, when

seen through a cable by a remote receiver, indicates

the presence of an active connection. The value of this

bias voltage has been chosen to allow interoperability

between transceiver chips operating from 5 V or 3 V

nominal supplies. This bias voltage source should be

stabilized by using an external filter capacitor of

approximately 0.33 µF.

The PHY/link interface is a direct connection and does

not provide isolation.

Data bits to be transmitted through the cable ports are

received from the LLC on two, four, or eight data lines

(D[0:7]), and are latched internally in the PHY in syn-

chronization with the 49.152 MHz system clock. These

bits are combined serially, encoded, and transmitted at

98.304 Mbits/s, 196.608 Mbits/s, or 393.216 Mbits/s as

the outbound data-strobe information stream. During

transmission, the encoded data information is transmit-

ted differentially on the TPA and TPB cable pair(s).

The port transmitter circuitry and the receiver circuitry

are disabled when the port is disabled, suspended, or

disconnected.

The line drivers in the PHY core operate in a high-

impedance current mode and are designed to work

with external 112 Ω line-termination resistor networks.

One network is provided at each end of each twisted-

pair cable. Each network is composed of a pair of

series-connected 56 Ω resistors. The midpoint of the

pair of resistors that is directly connected to the

twisted-pair A (TPA) signals is connected to the

TPBIAS voltage signal. The midpoint of the pair of

resistors that is directly connected to the twisted-pair B

(TPB) signals is coupled to ground through a parallel

RC network with recommended resistor and capacitor

values of 5 kΩ and 220 pF, respectively. The values of

the external resistors are specified to meet the 1394a-

2000 Specification when connected in parallel with the

internal receiver circuits.

During packet reception, the TPA and TPB transmit-

ters of the receiving cable port are disabled, and the

receivers for that port are enabled. The encoded data

information is received on the TPA and TPB cable pair.

The received data strobe information is decoded to

recover the receive clock signal and the serial data

bits. The serial data bits are split into two (for S100),

four (for S200), or eight (for S400) parallel streams,

resynchronized to the local system clock, and sent to

the associated LLC. The received data is also transmit-

ted (repeated) out of the other active (connected) cable

ports.

Agere Systems Inc.

13

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Data Sheet, Rev. 1

December 2005

Note: All gap counts on all nodes of a 1394 bus must

be identical. The software accomplishes this by

issuing PHY core configuration packets (see

Section 4.3.4.3 of IEEE 1394-1995 and 1394a-

2000 standards) or by issuing two bus resets,

which resets the gap counts to the maximum

level (3Fh).

FW322 Functional Description (continued)

An external resistor sets the driver output current,

along with other internal operating currents. This

resistor is connected between the R0 and R1 signals

and has a value of 2.49 kΩ ± 1%.

The C bit (20) in the SelfID packet (see Section 4.3.4.1

of the IEEE 1394a-2000 specification for more details)

has a default value of 0 which means this node is not a

contender for bus manager. A value of 0 still allows this

node to be considered by software for bus manager.

The internal link power status (LPS) signal works with

the internal LKON signal to manage the LLC power

usage of the node. The LPS signal indicates if the LLC

of the node is powered up or down. If LPS is inactive

for more than 1.2 µs and less than 25 µs, the internal

PHY/link interface is reset.

The least significant bit (23) in the Power Class (Pwr)

field in the SelfID packet is set to the value of the PC2

pin. The two most significant bits (21 and 22) in the

Pwr field are set to a default of 00. The PC2 pin is tied

low or high to create a Pwr field of 000 (PC2 low) or

001 (PC2 high). See Section 4.3.4.1 of the IEEE

1394a-2000 specification for additional details.

If LPS is inactive for greater than 25 µs, the PHY will

disable the internal PHY/link interface to save power.

The FW322 continues its repeater function even when

the PHY/link interface is disabled. If the PHY then

receives a link-on packet, the internal LKON signal is

activated to output a 6.114 MHz signal, which can be

used by the LLC to power itself up. Once the LLC is

powered up, the internal LPS signal communicates this

to the PHY and the internal PHY/link interface is

enabled. The internal LKON signal is turned off when

the LCtrl bit is set. (For more information on this bit,

refer to the Table 65 on PHY Core Register Fields in

this data sheet.)

When the power supply of the PHY core is removed

while the twisted-pair cables are connected, the PHY

core transmitter and receiver circuitry has been

designed to present a high impedance to the cable in

order to not load the TPBIAS signal voltage on the

other end of the cable.

Whenever the TPA±/TPB± signals are wired to a

connector, they must be terminated using the normal

termination network. This is required for reliable

operation. For those applications when one or more of

the FW322 ports are not wired to a connector, those

unused ports may be left unconnected without normal

termination. When a port does not have a cable

connected, internal connect-detect circuitry will keep

the port in a disconnected state.

Six of the FW322 pins are used to set up various test

conditions used only during the device manufacturing

process. These pins are SE, SM, TEST0, TEST1,

TEST2, and PTEST.

14

Agere Systems Inc.

Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Pin Information

TEST2

TEST1

ROM_CLK

ROM_AD

TEST0

PCI_INTAN

PCI_PRSTN

PCI_GNTN

PCI_REQN

PCI_PMEN

PCI_PCLK

V^SS

PCI_AD[31]

PCI_AD[30]

PCI_AD[29]

PCI_AD[28]

V^DD

PCI_AD[27]

PCI_AD[26]

PCI_AD[25]

PCI_AD[24]

V^SS

PCI_CBEN[3]

PCI_IDSEL

PCI_AD[23]

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

V^DDA

VSSA

CPS

V^DD

2

3

PIN #1 IDENTIFIER

4

5

PC2

6

PCI_VIOS

PCI_AD[0]

PCI_AD[1]

VDD

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

V^SS

PCI_AD[2]

PCI_AD[3]

PCI_AD[4]

V^SS

PCI_AD[5]

PCI_AD[6]

PCI_AD[7]

PCI_CBEN[0]

V^DD

PCI_AD[8]

PCI_AD[9]

PCI_AD[10]

AGERE FW322 06 T100

PCI_AD[11]

VSS

PCI_AD[12]

5-7338 (F)r.2

Note: Active-low signals within this document are indicated by an N following the symbol names.

Figure 6. Pin Assignments for the FW322 06 T100

Agere Systems Inc.

15

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Data Sheet, Rev. 1

December 2005

Pin Information (continued)

Table 1. Pin Descriptions

Symbol*

Type

Description

1

TEST2

I

Test. Used by Agere for device manufacturing testing. This pin must

be tied high for normal operation. Do not tie this pin to VSS.

2

TEST1

I

Test. Used by Agere for device manufacturing testing. Tie to VSS for

normal operation.

3

4

5

ROM_CLK

ROM_AD

TEST0

I/O

I

ROM Clock.

ROM Address/Data.

Test. Used by Agere for device manufacturing testing. Tie to VSS for

normal operation.

6

7

PCI_INTAN

PCI_PRSTN

PCI_GNTN

PCI_REQN

PCI_PMEN

O

I

PCI Interrupt (Active-Low).

PCI Reset (Active-Low).

8

I

PCI Grant Signal (Active-Low).

PCI Request Signal (Active-Low).

9

O

10

PCI Power Management Event (Active-Low). A PCI power man-

agement event will be indicated if this signal is low.

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

PCI_PCLK

VSS

I

PCI Clock Input. 33 MHz.

Digital Ground.

—

PCI_AD[31]

PCI_AD[30]

PCI_AD[29]

PCI_AD[28]

VDD

I/O

—

PCI Address/Data Bit.

Digital Power.

PCI_AD[27]

PCI_AD[26]

PCI_AD[25]

PCI_AD[24]

VSS

I/O

—

PCI Address/Data Bit.

Digital Ground.

PCI_CBEN[3]

PCI_IDSEL

PCI_AD[23]

PCI_AD[22]

VDD

I/O

I

PCI Command/Byte Enable (Active-Low).

PCI ID Select.

I/O

—

PCI Address/Data Bit.

Digital Power.

PCI_AD[21]

PCI_AD[20]

PCI_AD[19]

PCI_AD[18]

VDD

I/O

—

PCI Address/Data Bit.

Digital Power.

VSS

—

Digital Ground.

PCI_AD[17]

PCI_AD[16]

PCI_CBEN[2]

PCI_FRAMEN

I/O

PCI Address/Data Bit.

PCI Command/Byte Enable Signal (Active-Low).

PCI Frame Signal (Active-Low).

* Active-low signals within this document are indicated by an N following the symbol names.

166

Agere Systems Inc.

Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Pin Information (continued)

Table 1. Pin Descriptions (continued)

Symbol*

Type

Description

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

VSS

PCI_IRDYN

PCI_TRDYN

PCI_DEVSELN

PCI_STOPN

VDD

—

I/O

—

Digital Power.

PCI Initiator Ready Signal (Active-Low).

PCI Target Ready Signal (Active-Low).

PCI Device Select Signal (Active-Low).

PCI Stop Signal (Active-Low).

Digital Power.

PCI_PERRN

PCI_SERRN

PCI_PAR

PCI_CBEN[1]

PCI_AD[15]

PCI_AD[14]

PCI_AD[13]

PCI_AD[12]

VSS

I/O

—

PCI Parity Error Signal (Active-Low).

PCI System Error Signal (Active-Low).

PCI Parity Signal.

PCI Command/Byte Enable Signal (Active-Low).

PCI Address/Data Bit.

Digital Ground.

PCI_AD[11]

PCI_AD[10]

PCI_AD[9]

PCI_AD[8]

VDD

I/O

—

PCI Address/Data Bit.

Digital Power.

PCI_CBEN[0]

PCI_AD[7]

PCI_AD[6]

PCI_AD[5]

VSS

I/O

—

PCI Command/Byte Enable Signal (Active-Low).

PCI Address/Data Bit.

Digital Ground.

PCI_AD[4]

PCI_AD[3]

PCI_AD[2]

VSS

I/O

—

PCI Address/Data Bit.

Digital Ground.

VDD

—

Digital Power.

PCI_AD[1]

PCI_AD[0]

PCI_VIOS

I/O

—

PCI Address/Data Bit.

PCI Signaling Indicator. For PCI applications that use a universal

expansion board (see PCI Local Bus Specification, Rev. 2.2, Sec-

tion 4.1.1), connect this pin to the VI/O pin. For other cases, con-

nect this pin to 3.3 V for PCI buses using 3.3 V signaling or to 5 V

for PCI buses using 5 V signaling.

* Active-low signals within this document are indicated by an N following the symbol names.

Agere Systems Inc.

17

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Data Sheet, Rev. 1

December 2005

Pin Information (continued)

Table 1. Pin Descriptions (continued)

Symbol*

Type

Description

71

PC2

I

Power-Class Indicator. On hardware reset (RESETN), this input

sets the default value of the least significant bit in the Power Class

field (Pwr) in the SelfID packet (see Section 4.3.4.1 of the 1394a-

2000 Specification). This bit can be tied to VDD (high) or to

VSS (low) as required for particular power consumption and source

characteristics. The two most significant Pwr bits in the SelfID are

internally set to zero. As an example, for a Pwr field value of 001,

PC2 = 1.

72

73

VDD

—

I

Digital Power.

CPS

Cable Power Status. CPS is normally connected to the cable

power through a 400 kΩ resistor. This circuit drives an internal

comparator that detects the presence of cable power. This informa-

tion is maintained in one internal register and is available to the

LLC by way of a register read (see IEEE 1394a-2000, Standard for

a High Performance Serial Bus, Sections 4.2.2.7 and 5B.1).

Note: This pin can be left unconnected for applications that do not

use 1394 bus power (VP). When this pin is grounded, the

PWR_FAIL bit in PHY register 01012 will set.

74

75

76

77

78

VSSA

VDDA

—

Analog Circuit Ground. All VSSA signals should be tied together

to a low-impedance ground plane.

Analog Circuit Power. VDDA supplies power to the analog portion

of the device.

VSSA

Analog Circuit Ground. All VSSA signals should be tied together to

a low-impedance ground plane.

TPB1–

TPB1+

Analog I/O Port 1, Port Cable Pair B. TPB1± is the port B connection to the

twisted-pair cable. Board traces from each pair of positive and nega-

tive differential signal pins should be kept matched and as short as

possible to the external load resistors and to the cable connector.

When the FW322’s 1394 port pins are not wired to a connector, the

unused port pins may be left unconnected. Internal connect-detect

circuitry will keep the port in a disconnected state.

79

80

TPA1–

TPA1+

Analog I/O Port 1, Port Cable Pair A. TPA1± is the port A connection to the

twisted-pair cable. Board traces from each pair of positive and nega-

tive differential signal pins should be kept matched and as short as

possible to the external load resistors and to the cable connector.

When the FW322’s 1394 port pins are not wired to a connector, the

unused port pins may be left unconnected. Internal connect-detect

circuitry will keep the port in a disconnected state.

* Active-low signals within this document are indicated by an N following the symbol names.

188

Agere Systems Inc.

Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Pin Information (continued)

Table 1. Pin Descriptions (continued)

Symbol*

Type

Description

81

TPBIAS1

Analog I/O Port 1, Twisted-Pair Bias. TPBIAS1 provides the 1.86 V nominal

bias voltage needed for proper operation of the twisted-pair cable

drivers and receivers and for sending a valid cable connection signal

to the remote nodes. When the FW322’s 1394 port pins are not

wired to a connector, the unused port pins may be left unconnected.

Internal connect-detect circuitry will keep the port in a disconnected

state.

82

83

TPB0–

TPB0+

Analog I/O Port 0, Port Cable Pair B. TPB0± is the port B connection to the

twisted-pair cable. Board traces from each pair of positive and nega-

tive differential signal pins should be kept matched and as short as

possible to the external load resistors and to the cable connector.

When the FW322’s 1394 port pins are not wired to a connector, the

unused port pins may be left unconnected. Internal connect-detect

circuitry will keep the port in a disconnected state.

84

85

TPA0–

TPA0+

Analog I/O Port 0, Port Cable Pair A. TPA0± is the port A connection to the

twisted-pair cable. Board traces from each pair of positive and nega-

tive differential signal pins should be kept matched and as short as

possible to the external load resistors and to the cable connector.

When the FW322’s 1394 port pins are not wired to a connector, the

unused port pins may be left unconnected. Internal connect-detect

circuitry will keep the port in a disconnected state.

86

TPBIAS0

Analog I/O Port 0, Twisted-Pair Bias. TPBIAS0 provides the 1.86 V nominal

bias voltage needed for proper operation of the twisted-pair cable

drivers and receivers and for sending a valid cable connection signal

to the remote nodes. When the FW322’s 1394 port pins are not

wired to a connector, the unused port pins may be left unconnected.

Internal connect-detect circuitry will keep the port in a disconnected

state.

87

88

89

VSSA

VDDA

R0

—

I

Analog Circuit Ground. All VSSA signals should be tied together to

a low-impedance ground plane.

Analog Circuit Power. VDDA supplies power to the analog portion of

the device.

Current Setting Resistor. An internal reference voltage is applied to

a resistor connected between R0 and R1 to set the operating current

and the cable driver output current. A low temperature-coefficient

resistor (TCR) with a value of 2.49 kΩ ± 1% should be used to meet

the IEEE 1394-1995 standard requirements for output voltage limits.

90

91

R1

PLLVDD

—

Power for PLL Circuit. PLLVDD supplies power to the PLL circuitry

portion of the device.

92

PLLVSS

Ground for PLL Circuit. PLLVSS is tied to a low-impedance ground

plane.

* Active-low signals within this document are indicated by an N following the symbol names.

Agere Systems Inc.

19

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Data Sheet, Rev. 1

December 2005

Pin Information (continued)

Table 1. Pin Descriptions (continued)

Symbol*

Type

Description

93

XI

Analog I/O Crystal Oscillator. XI and XO connect to a 24.576 MHz parallel

resonant fundamental mode crystal. Although when a 24.576 MHz

clock source is used, it can be connected to XI with XO left uncon-

nected. The optimum values for the external shunt capacitors are

dependent on the specifications of the crystal used. It is necessary to

add an external series resistor to the XO pin. The value of the resistor

is nominally 400 Ω. For more details, refer to the Crystal Selection

Considerations section in this data sheet. Note that it is very impor-

tant to place the crystal as close as possible to the XO and XI pins,

i.e., within 0.5 in./1.27 cm. For more important details regarding the

crystal, refer to the FW323/FW322 Hardware Implementation Design

Guideline Application Note.

94

95

XO

RESETN

I

Reset (Active-Low). When RESETN is asserted low (active), a 1394

bus reset condition is set on the active cable ports and the FW322 is

reset to the reset start state. To guarantee that the PHY will reset, this

pin must be held low for at least 2 ms. An internal pull-up resistor,

connected to VDD, is provided, so only an external delay capacitor

(0.1 µF) and resistor (510 kΩ), in parallel, are required to connect this

pin to ground. This circuitry will ensure that the capacitor will be

discharged when PHY power is removed. The input is a standard

logic buffer and can also be driven by an open-drain logic output

buffer. Do not leave this pin unconnected. This pin is also used with

the EEPROM interface. It is the powerup reset pin. This pin is

asserted low (active) to indicate a powerup reset. Refer to the

FW322 06/FW323 06 EEPROM Interface and Start-up Behavior

Application Note sections titled Initiation of EEPROM Load and Initial

Powerup.

96

97

98

PTEST

SM

I

Test. Used by Agere for device manufacturing testing. Tie to VSS for

normal operation.

Test Mode Control. SM is used during Agere’s manufacturing test

and should be tied to VSS for normal operation.

SE

Test Mode Control. SE is used during Agere’s manufacturing test

and should be tied to VSS for normal operation.

99

VDD

VSS

—

Digital Power.

100

Digital Ground.

* Active-low signals within this document are indicated by an N following the symbol names.

Note: For those applications when one or more FW322 ports are not wired to a connector, those unused ports may be left unconnected without

normal termination. When a port does not have a cable connected, internal connect-detect circuitry will keep the port in a disconnected state.

200

Agere Systems Inc.

Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Internal Registers

This section provides a summary of the internal registers within the FW322, including both PCI Configuration regis-

ters and OHCI registers. Register default values, registers and bits that have not been implemented in the FW322,

and other information specific to the FW322 will be noted.

Please refer to the PCI Local Bus Specification v.2.2, PCI Bus Power Management Interface Specification, v.1.1,

1394 OHCI specification v.1.1, and the IEEE standard 1394a-2000 Specification for further details concerning these

registers.

Table 2 describes the field access tags that are designated in the Type column of the register tables in this

document.

Table 2. Bit-Field Access Tag Description

Access Tag

Name

Description

R

W

S

Read Field may be read by software.

Write Field may be written by software to any value.

Set Field may be set by a write of 1. Writes of 0 have no effect.

C

U

Clear Field may be cleared by a write of 1. Writes of 0 have no effect.

Update Field may be autonomously updated by the FW322.

PCI Configuration Registers

Table 3 illustrates the PCI configuration header that includes both the predefined portion of the configuration space

and the user-definable registers.

Table 3. PCI Configuration Register Map

Register Name [default]

Offset

00h

Device ID [5811h]

Status [02901h]

Vendor ID [11C1h]

Command [0000h]

04h

Class Code [0C0010h]

Header Type [00h]

Revision ID [6xh]^*

08h

BIST [00h]

Latency Timer^†[00h]

Cache Line Size^†

[00h]

0Ch

OHCI Base Address Register [0000 0000h]

10h

14h

18h

1Ch

20h

24h

28h

2Ch

30h

34h

Reserved

CardBus CIS Pointer [0000 0000h]

Subsystem ID^†[0000h]

Subsystem Vendor ID^†[0000h]

Reserved

PCI Power Manage-

ment Capabilities

Pointer [44h]

Reserved

38h

Maximum Latency^†

[18h]

Minimum Grant^†

[0Ch]

Interrupt Pin [01h]

Interrupt Line [00h]

3Ch

* x is a minor revision number of the FW322 06 T100 and may be any value from 0 hex to F hex.

† Values for this register can be loaded from a serial EEPROM during the powerup sequence.

Agere Systems Inc.

21

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Data Sheet, Rev. 1

December 2005

Internal Registers (continued)

Table 3. PCI Configuration Register Map (continued)

Register Name [default]

Offset

†

PCI OHCI Control Register [0000 0000h]

40h

44h

†

Power Management Capabilities [7E02h]

Next Item Pointer

[00h]

Capability ID [01h]

†

‡

Pm Data [00h]

Pmcsr_bse [00h]

Reserved

Power Management CSR [0000h]

48h

4C—FCh

† Values for this register can be loaded from a serial EEPROM during the powerup sequence.

Vendor ID Register

The Vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the device.

The vendor ID assigned to Agere is 11C1h.

Offset:

00h

Default:

Type:

11C1h

Read only

Reference:

PCI Local Bus Specification, Rev. 2.2, Section 6.2.1

Device ID Register

The Device ID register contains a value assigned to the FW322 by Agere. The device identification for the FW322

is 5811h.

Offset:

02h

Default:

Type:

5811h

Read only

Reference:

PCI Local Bus Specification, Rev. 2.2, Section 6.2.1

22

Agere Systems Inc.

Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Internal Registers (continued)

PCI Command Register

The Command register provides control over the FW322 interface to the PCI bus. All bit functions adhere to the

definitions in the PCI Local Bus Specification, as in the following bit descriptions.

Offset:

04h

Default:

Type:

0000h

Read/write

Reference:

PCI Local Bus Specification, Rev. 2.2, Section 6.2.2 and 1394 Open Host Controller Interface

Specification, Rev. 1.1, Section A.3.1

Table 4. PCI Command Register Description

Bit

Field Name

Type

Description

15:10

9

Reserved

FBB_ENB

R

Reserved. Bits 15:10 return 0s when read.

Fast Back-to-Back Enable. The FW322 does not generate fast back-

to-back transactions; thus, this bit returns 0 when read.

8

SERR_ENB

RW

SERR Enable. When this bit is set, the FW322 SERR driver is enabled.

PCI_SERRN can be asserted after detecting an address parity error on

the PCI bus.

7

6

5

4

STEP_ENB

PERR_ENB

VGA_ENB

MWI_ENB

R

RW

R

Address/Data Stepping Control. The FW322 does not support

address/data stepping; thus, this bit is hardwired to 0.

Parity Error Enable. When this bit is set, the FW322 is enabled to drive

PERR response to parity errors through the PCI_PERRN signal.

VGA Palette Snoop Enable. The FW322 does not feature VGA palette

snooping. This bit returns 0 when read.

RW

Memory Write and Invalidate Enable. When this bit is set, the FW322

is enabled to generate MWI PCI bus commands. If this bit is reset, then

the FW322 generates memory write commands instead.

3

2

1

SPECIAL

R

Special Cycle Enable. The FW322 function does not respond to special

cycle transactions. This bit returns 0 when read.

MASTER_ENB

MEMORY_ENB

RW

Bus Master Enable. When this bit is set, the FW322 is enabled to

initiate cycles on the PCI bus.

Memory Response Enable. Setting this bit enables the FW322 to

respond to memory cycles on the PCI bus. This bit must be set to access

OHCI registers.

0

IO_ENB

R

I/O Space Enable. The FW322 does not implement any I/O mapped

functionality; thus, this bit returns 0 when read.

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FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Data Sheet, Rev. 1

December 2005

Internal Registers (continued)

PCI Status Register

The Status register provides status information for PCI bus related events. All bit functions adhere to the

definitions in the PCI Local Bus Specification, v.2.2, Table 6.2.

Offset:

06h

Default:

Type:

0290h

Read/write

Reference:

PCI Local Bus Specification, Rev. 2.2, Section 6.2.3 and 1394 Open Host Controller Interface

Specification, Rev. 1.1, Section A.3.2

Table 5. PCI Status Register

Description

Field

Name

Bit

Type

15

14

13

PAR_ERR

SYS_ERR

MABORT

RCU

Detected Parity Error. This bit must be set by the device whenever it

detects a parity error, even if parity error handling is disabled.

RCU

Signaled System Error. This bit must be set whenever the device

asserts SERR#.

Received Master Abort. This bit must be set by a master device

whenever its transaction (except for special cycle) is terminated with

master-abort.

12

11

TABORT_REC

TABORT_SIG

PCI_SPEED

RCU

R

Received Target Abort. This bit must be set by a master device

whenever its transaction is terminated with target-abort.

Signaled Target Abort. This bit must be set by a target device

whenever it terminates a transaction with target-abort.

10:9

DEVSEL Timing. Bits 9 and 10 encode the timing of DELSEL# (see

Section 3.6.1 of the PCI Specification). These bits must indicate the

slowest time that a device asserts DEVSEL# for any bus command

except configuration read and configuration write. The default timing is

01 (medium).

8

7

DATAPAR

FBB_CAP

RCU

R

Master Data Parity Error. See Table 6-2 of the PCI Specification for

more information.

Fast Back-to-Back Capable. Indicates whether or not the target is

capable of accepting fast back-to-back transactions when the

transactions are not to the same agent. The FW322 does not support

back-to-back transactions.

6

5

Reserved

66MHZ

R

Reserved.

66 MHz Capable. Indicates whether or not this device is capable of

running at 66 MHz as defined in Chapter 7 of the PCI Specification. The

FW322 reports a value of zero in this field indicating that 66 MHz

functionality is not supported.

4

CAPLIST

Reserved

R

Capabilities List. Indicates whether or not this device implements the

pointer for a New Capabilities linked list at offset 34h. A value of zero

indicates that no New Capabilities linked list is available. A value of one

indicates that the value read at offset 34h is a point in Configuration

Space to a linked list of new capabilities. (See Section 6.7 of the PCI

Specification for more details.)

3:0

Reserved.

244

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Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Internal Registers (continued)

Class Code and Revision ID Registers

The Class Code register and Revision ID register categorize the FW322 as a serial bus controller (0Ch),

controlling an IEEE 1394 bus (00h), with an OHCI programming model (10h). Furthermore, the chip revision is

indicated in the lower byte.

Offset:

08h

Default:

Type:

0C00 106xh*

Read only

Reference:

PCI Local Bus Specification, Rev. 2.2, Section 6.2.1 and 1394 Open Host Controller Interface

Specification, Rev. 1.1, Section A.3.3 and A.3.4.

Table 6. Class Code and Revision ID Register Description

Bit

Field Name

Type

Description

31:24

BASECLASS

R

Base Class. This field returns 0Ch when read, which classifies the func-

tion as a serial bus controller.

23:16

15:8

SUBCLASS

PGMIF

R

Subclass. This field returns 00h when read, which specifically classifies

the function as an IEEE 1394 serial bus controller.

Programming Interface. This field returns 10h when read, indicating

that the programming model is compliant with the 1394 Open Host

Controller Interface Specification.

7:0

CHIPREV

R

Silicon Revision. This field returns 6xh* when read, indicating the

silicon revision of the FW322.

* x is a minor revision number of the FW322 06 T100 and may be any value from 0 hex to F hex.

Latency Timer and Cache Line Size Register

The Latency Timer and Class Cache Line Size register is programmed by host BIOS to indicate system cache line

size and the latency timer associated with the FW322. If a serial EEPROM is detected, then the contents of this

register are loaded from the serial EEPROM interface after a PCI reset. If no serial EEPROM is detected, then this

register returns a default value of 0000h.

Offset:

0Ch

Default:

Type:

0000h

Read/write

Reference:

PCI Local Bus Specification, Rev. 2.2, Section 6.2.4

Table 7. Latency Timer and Class Cache Line Size Register Description

Bit

Field Name

Type

Description

15:8

LATENCY_TIMER

RW

PCI Latency Timer. The value in this register specifies the latency

timer, in units of PCI clock cycles, for the FW322. When the FW322 is

a PCI bus initiator and asserts FRAME, the latency timer begins

counting from zero. If the latency timer expires before the FW322

transaction has terminated, then the FW322 terminates the transac-

tion when its PCI_GNTN is deasserted.

7:0

CACHELINE_SZ

RW

Cache Line Size. This value is used by the FW322 during memory

write and invalidate, memory read line, and memory read multiple

transactions.

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FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Data Sheet, Rev. 1

December 2005

Internal Registers (continued)

Header Type and BIST Register

The Header Type and BIST register indicates the FW322 PCI header type.

Offset:

0Eh

Default:

Type:

0000h

Read only

Reference:

PCI Local Bus Specification, Rev. 2.2, Sections 6.2.1 and 6.2.4

Table 8. Header Type and BIST Register Description

Bit

Field Name

Type

Description

15:8

BIST

R

Built-In Self-Test. The FW322 does not include a built-in self-test;

thus, this field returns 00h when read.

7:0

HEADER_TYPE

R

PCI Header Type. The FW322 includes the standard PCI header, and

this is communicated by returning 00h when this field is read.

OHCI Base Address Register

The OHCI Base Address register is programmed with a base address referencing the memory-mapped OHCI con-

trol. When BIOS writes all 1s to this register, the value read back is FFFF F000h, indicating that 4 Kbytes of mem-

ory address space are required for the OHCI registers.

Offset:

10h

Default:

Type:

0000 0000h

Read/write

Reference:

PCI Local Bus Specification, Rev. 2.2, Sections 6.2.5 and 1394 Open Host Controller Interface

Specification, Rev. 1.1, Section A.3.5

Table 9. OHCI Base Address Register Description

Bit

Field Name

Type

Description

31:12

OHCIREG_PTR

RW

OHCI Register Pointer. Specifies the upper 20 bits of the 32-bit OHCI

base address.

11:4

3

OHCI_SZ

OHCI_PF

R

OHCI Register Size. This field returns 0s when read, indicating that

the OHCI registers require a 4 Kbyte region of memory.

OHCI Register Prefetch. This bit returns 0 when read, indicating that

the OHCI registers are not prefetchable.

2:1

OHCI_MEMTYPE

OHCI Memory Type. This field returns 0s when read, indicating that

the OHCI Base Address register is 32 bits wide and mapping can be

done anywhere in the 32-bit memory space.

0

OHCI_MEM

R

OHCI Memory Indicator. This bit returns 0 when read, indicating that

the OHCI registers are mapped into system memory space.

266

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Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Internal Registers (continued)

PCI Subsystem Identification Register

The PCI Subsystem Identification register is used to uniquely identify the card or system in which the FW322

resides. If a serial EEPROM is present, these values are loaded from the EEPROM during the powerup

sequence. Subsystem vendor IDs can be obtained from the PCI SIG. Values for the subsystem ID are vendor

specific.

By default, the PCI Subsystem ID and PCI Subsystem Vendor ID registers are read only. However, if a serial

EEPROM is not interfaced to the FW322 06, bit 0 (SubSystemWriteEn) of the PCI Config register, offset 4Ch can

be set to enable writes to the PCI Subsystem ID and PCI Subsystem Vendor ID so that these registers can be

customized to the correct ID values. After the IDs have been written, the SubSystemWriteEn bit should be reset to

protect the data from being overwritten.

Offset:

2Ch

Default:

Type:

0000 0000h

Read/write

Reference:

PCI Local Bus Specification, Rev. 2.2, Section 6.2.4

Table 10. PCI Subsystem Identification Register Description

Bit

Field Name

Type

Description

31:16

15:0

SSID

RU

Subsystem ID. This field indicates the subsystem ID.

SSVID

Subsystem Vendor ID. This field indicates the subsystem vendor ID.

PCI Power Management Capabilities Pointer Register

The PCI Power Management Capabilities Pointer register provides a pointer into the PCI configuration header

where the PCI Power Management register block resides. The FW322 configuration words at offsets 44h and 48h

provide the Power Management registers. This register is read only and returns 44h when read.

Offset:

34h

Default:

Type:

44h

Read only

Reference:

PCI Local Bus Specification, Rev. 2.2, Section 6.2.4 and 6.7 and 1394 Open Host Controller

Interface Specification, Rev. 1.1, Section A.3.6.

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Data Sheet, Rev. 1

December 2005

Internal Registers (continued)

Interrupt Line and Pin Register

The Interrupt Line and Pin register is used to communicate interrupt line routing information.

Offset:

3Ch

Default:

Type:

0100h

Read only

Reference:

PCI Local Bus Specification, Rev. 2.2, Section 6.2.4 and 6.7

Table 11. Interrupt Line and Pin Register Description

Bit

Field Name

Type

Description

15:8

INTR_PIN

R

Interrupt Pin Register. This register returns 01h when read, indi-

cating that the FW322 PCI function signals interrupts on the INTA pin.

7:0

INTR_LINE

RW

Interrupt Line Register. This register is programmed by the system

and indicates to software to which interrupt line the FW322 INTA is

connected.

MIN_GNT and MAX_LAT Register

The MIN_GNT and MAX_LAT register is used to communicate to the system the desired setting of the Latency

Timer register. If a serial EEPROM is detected, then the contents of this register are loaded from the serial

EEPROM interface after a PCI reset. If no serial EEPROM is detected, then this register returns a default value

that corresponds to the MIN_GNT = 0Ch, MAX_LAT = 18h.

Offset:

3Eh

Default:

Type:

180Ch

Read only

Reference:

PCI Local Bus Specification, Rev. 2.2, Section 6.2.4

Table 12. MIN_GNT and MAX_LAT Register Description

Bit

Field Name

Type

Description

15:8

MAX_LAT

RU

Maximum Latency. The contents of this register may be used by host

BIOS to assign an arbitration priority level to the FW322. The default

for this register (18h) indicates that the FW322 may need to access

the PCI bus as often as every 0.25 µs; thus, an extremely high-priority

level is requested. The contents of this field may also be loaded from

the serial ROM.

7:0

MIN_GNT

RU

Minimum Grant. The contents of this register may be used by host

BIOS to assign a Latency Timer register value to the FW322. The

default (0Ch) for this register indicates that the FW322 may need to

sustain burst transfers for nearly 64 µs; thus, requesting a large value

be programmed in the FW322 Latency Timer register. The contents of

this field may also be loaded from the serial ROM.

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Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Internal Registers (continued)

PCI OHCI Control Register

The PCI OHCI Control register is defined in Section A.3.7 of the 1394 Open Host Controller Interface

Specification and provides a bit for big-endian PCI support. Note that the GLOBAL_SWAP bit is loaded from the

serial EEPROM on powerup.

Offset:

40h

Default:

Type:

0000 0000h

Read/write

Reference:

1394 Open Host Controller Interface Specification, Rev. 1.1, Section A.3.7

Table 13. PCI OHCI Control Register Description

Bit

Field Name

Type

Description

31:1

0

Reserved

R

Reserved. Bits 31:1 return 0s when read.

GLOBAL_SWAP

RW

When this bit is set, all quadlets read from the FW322 as well as any

data written to the PCI bus by the FW322 is byte swapped. This

excludes PCI Config registers and CardBus Function Event registers

(they are not swapped under any circumstances). However, OHCI

registers are byte swapped when this bit is set.

Capability ID and Next Item Pointer Register

The Capability ID and Next Item Pointer register identifies the linked list capability item and provides a pointer to

the next capability item.

Offset:

44h

Default:

Type:

0001h

Read only

Reference:

PCI Local Bus Specification, Rev. 2.2, Sections 6.8.1.1, 6.8.1.2 and 1394 Open Host Controller

Interface Specification, Rev. 1.1, Sections A.3.8.1 and A.3.8.2

Table 14. Capability ID and Next Item Pointer Register Description

Bit

Field Name

Type

Description

15:8

NEXT_ITEM

R

Next Item Pointer. The FW322 supports only one additional capability

that is communicated to the system through the extended capabilities

list; thus, this field returns 00h when read.

7:0

CAPABILITY_ID

R

Capability Identification. This field returns 01h when read, which is

the unique ID assigned by the PCI SIG for PCI power management

capability.

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1394a PCI PHY/Link Open Host Controller

Data Sheet, Rev. 1

December 2005

Internal Registers (continued)

Power Management Capabilities Register

The Power Management Capabilities register indicates the capabilities of the FW322 related to PCI power man-

agement. The default value of this register can be selectively programmed by the serial EEPROM. However, the

D3cold and AUX_PWR fields cannot be changed from the default of 0 by the EEPROM.

Offset:

46h

Default:

Type:

7E02h

Read only

Reference:

PCI Bus Power Management Interface Specification, Rev. 1.1, Section 3.2.3 and 1394 Open Host

Controller Interface Specification, Rev. 1.1, Section A.3.8.3

Table 15. Power Management Capabilities Register Description

Bit

Field Name

Type

Description

15

PME_D3COLD

R

PME Support from D3cold. Set to 0, indicating that the FW322

cannot generate a PME event in D3cold.

14

13

12

11

10

9

PME_D3HOT

PME_D2

R

PME Support from D3hot. Set to 1, indicating that the FW322 can

generate a PME event in the D3hot state.

PME Support from D2. Set to 1, indicating that the FW322 can

generate a PME in D2.

PME_D1

PME Support from D1. Set to 1, indicating that the FW322 can

generate a PME in D1.

PME_D0

PME Support from D0. Set to 1, indicating that the FW322 can

generate a PME in D0.

D2_SUPPORT

D1_SUPPORT

AUX_PWR

DSI

D2 Support. This bit returns a 1 when read, indicating that the FW322

supports the D2 power state.

D1 Support. This bit returns a 1 when read, indicating that the FW322

supports the D1 power state.

8:6

5

Auxiliary Power Source. This field reports the Vaux power require-

ments for the Open HCI function. This field is always 0.

Device-Specific Initialization. This bit returns 0 when read, indi-

cating that the FW322 does not require special initialization beyond

the standard PCI configuration header before a generic class driver is

able to use it.

4

3

Reserved

PME_CLK

R

Reserved. Bit returns 0 when read.

PME Clock. This bit returns 0 when read, indicating that no host bus

clock is required for the FW322 to generate PME.

2:0

PM_VERSION

R

Power Management Version. This field returns 010b when read, indi-

cating that the FW322 is compatible with the registers described in the

PCI Power Management Interface Specification, Rev.1.1.

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Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Internal Registers (continued)

Power Management Control and Status Register

The Power Management Control and Status register implements the control and status of the PCI power manage-

ment function. This register is not affected by the internally generated reset caused by the transition from the D3hot

to D0 state. All bits within this register, will be reset by a PCI reset.

Offset:

48h

Default:

Type:

XX00h

Read/write

Reference:

PCI Bus Power Management Interface Specification, Rev. 1.1, Section 3.2.4 and 1394 Open Host

Controller Interface Specification, Rev. 1.1, Section A.3.8.4

Table 16. Power Management Control and Status Register Description

Bit

Field Name

Type

Description

15

PME_STS

RC This bit is set when the FW322 would normally be asserting the PME

signal, independent of the state of the PME_ENB bit. This bit is

cleared by a writeback of 1, and this also clears the PME signal driven

by the FW322. Writing a 0 to this bit has no effect.

14:13

12:9

8

DATA_SCALE

DATA_SELECT

PME_ENB

R

This 2-bit field indicates a scaling factor that is to be used when inter-

preting the value of the PM_DATA register within the Power Manage-

ment Extension register. The value and meaning of this field will vary

depending on the value that has been selected by the DATA_SELECT

field.

R

This 4-bit field is used to select which data values are to be reported

through the PM_DATA field in the Power Management Extension

register and the DATA_SCALE fields. Valid values are 0—7, which

map to power consumption/dissipation ratings for the FW322 within

the PM_DATA/DATA_SCALE fields.

RW PME Enable. This bit enables the function to assert PME. If this bit is

cleared, then assertion of PME is disabled.

7:5

4

Reserved

R

Reserved. Bits 7:5 return 0s when read.

DYN_DATA

Dynamic Data. This bit returns 0 when read, since the FW322 does

not report dynamic data.

3:2

1:0

Reserved

R

Reserved. Bits 3:2 return 0s when read.

PWR_STATE

RW Power State. This 2-bit field is used to set the FW322 device power

state and is encoded as follows:

00 = current power state is D0.

01 = current power state is D1.

10 = current power state is D2.

11 = current power state is D3.

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FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Data Sheet, Rev. 1

December 2005

Internal Registers (continued)

Power Management CSR PCI-to-PCI Bridge Support Extensions

This register returns 00h when read since the FW322 does not provide PCI-to-PCI bridging.

Offset:

Default:

Type:

4Ah

00h

Read only

Reference:

PCI Bus Power Management Interface Specification, Rev. 1.1, Section 3.2.5 and 1394 Open Host

Controller Interface Specification, Rev. 1.1, Section A.3.8.5 and A.3.8.6

Power Management Data

The Power Management (PM) Data register set is comprised of 16 eight-bit registers, providing more detailed

power management information about the device. All 16 registers will return 00h by default. The first eight registers

are assigned to single function devices, and the second eight are reserved for use by multifunction devices (see

Table 17). The FW322 supports programmability, via the serial EEPROM, of the first eight registers in the PM data

complex. Software uses the DATA_SELECT and DATA_SCALE fields within the Power Management Control and

Status register to select and scale the desired PM data entry. Note that if the serial EEPROM is used to program

nonzero values into PM DATA, then the AUX_PWR field should be programmed to a zero value via the serial

EEPROM and vice versa. This is to comply with the PCI Specification, which states that these two functions must

be implemented mutually exclusive of one another. The FW322 does not enforce this, and therefore, it is up to the

creator of the serial EEPROM image to ensure that these two fields are used mutually exclusive of one another.

Offset:

4Bh

Default:

Type:

00h

Read Only

Reference:

PCI Bus Power Management Interface Specification, Rev. 1.1, Section 3.2.6 and 1394 Open Host

Controller Interface Specification, Rev. 1.1, Section A.3.8.5 and A.3.8.6

Table 17. Power Management Data Register Description

(Derived from Table 10 of the PCI Power Management Interface Specification, Revision 1.1.)

Value in

Data_Select

Data Reported

Data_Scale

Interpretation

Units/Accuracy

0

D0 Power Consumed

D1 Power Consumed

D2 Power Consumed

D3 Power Consumed

D0 Power Dissipated

D1 Power Dissipated

D2 Power Dissipated

D3 Power Dissipated

0 = Unknown

1 = 0.1x

Watts

1

2

2 = 0.01x

3

3 = 0.001x

4

5

6

7

8—15

Reserved (unused by FW322

and will return 00h when read)

Reserved

TBD

322

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Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Internal Registers (continued)

OHCI Registers

The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory mapped into a

2 Kbyte region of memory pointed to by the OHCI Base Address register located at offset 10h in PCI configuration

space. These registers are the primary interface for controlling the FW322 IEEE 1394 OHCI function. This section

provides a summary of the registers within this interface and a description of the individual bit fields within each

register. For more details regarding these registers and bits, please refer to the 1394 Open Host Controller Inter-

face Specification, Rev. 1.1.

In addition to regular read/write registers, there are several pairs of set and clear registers implemented within the

OHCI register interface. For each pair of set and clear registers, there are two addresses that correspond to indi-

vidual set/clear registers: RegisterSet and RegisterClear. Refer to Table 18 for a listing of these registers. A 1 bit

written to RegisterSet causes the corresponding bit in the register to be set, while a 0 bit leaves the corresponding

bit unaffected. A 1 bit written to RegisterClear causes the corresponding bit in the register to be reset, while a 0 bit

leaves the corresponding bit unaffected. Typically, a read from either RegisterSet or RegisterClear returns the con-

tents of the set or clear register. However, in some instances, reading the RegisterClear provides a masked version

of the set or clear register. The Interrupt Event register is an example of this behavior.

The following FW322 OHCI register definitions are based on version 1.1 of the 1394 Open Host Controller

Specification.

Table 18. OHCI Register Map

OHCI

Specification

Reference

DMA

Context

Register Name

Abbreviation

Offset

—

OHCI Version

Global Unique ID ROM

Asynchronous Transmit Retries

CSR Data

Version

GUID_ROM

ATRetries

CSRData

00h

04h

5.2

5.3

08h

5.4

0Ch

10h

5.5.1

CSR Compare Data

CSR Control

CSRCompareData

CSRControl

ConfigROMhdr

BusID

14h

Configuration ROM Header

Bus Identification

18h

5.5.2

5.5.3

5.5.4

5.5.5

1Ch

20h

Bus Options

BusOptions

GUIDHi

Global Unique ID High

Global Unique ID Low

Reserved

24h

GUIDLo

28h

—

2Ch

30h

—

Reserved

—

Configuration ROM Map

Posted Write Address Low

Posted Write Address High

Vendor Identification

Reserved

ConfigROMmap

PostedWriteAddressLo

PostedWriteAddressHi

VendorID

34h

5.5.6

13.2.8.1

38h

3Ch

40h

5.6

—

Reserved

50h

Host Controller Control

HCControlSet

HCControlClear

—

5.7

54h

Reserved

58h

—

5Ch

60h

—

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FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Data Sheet, Rev. 1

December 2005

Internal Registers (continued)

Table 18. OHCI Register Map (continued)

OHCI

Specification

Reference

DMA

Register Name

Context

Abbreviation

Offset

SelfID

—

SelfID Buffer

SelfID Count

SelfIDBuffer

SelfIDCount

64h

68h

11.1

11.2

Reserved

—

6Ch

—

Isochronous Receive Channel Mask High

IRChannelMaskHiSet

IRChannelMaskHiClear

IRChannelMaskLoSet

IRChannelMaskLoClear

IntEventSet

70h

10.4.1.1

74h

Isochronous Receive Channel Mask Low

Interrupt Event

78h

7Ch

80h

6.1

6.2

IntEventClear

84h

Interrupt Mask

IntMaskSet

88h

IntMaskClear

8Ch

Isochronous Transmit

Interrupt Event

IsoXmitIntEventSet

IsoXmitIntEventClear

IsoXmitIntMaskSet

IsoXmitIntMaskClear

IsoRecvIntEventSet

IsoRecvIntEventClear

IsoRecvIntMaskSet

IsoRecvIntMaskClear

InitialBandwidthAvailable

InitialChannelsAvailableHi

InitialChannelsAvailableLo

—

90h

6.3.1

6.3.2

6.4.1

6.4.2

5.8

94h

Isochronous Transmit

Interrupt Mask

98h

9Ch

—

Isochronous Receive

Interrupt Event

A0h

A4h

Isochronous Receive

Interrupt Mask

A8h

ACh

B0h

Bus Management CSR Initialization

B4h

B8h

Reserved

Fairness Control

Link Control

BCh:D8h

DCh

E0h

—

5.9

FairnessControl

LinkControlSet

5.10

LinkControlClear

E4h

Node Identification

PHY Core Layer Control

Isochronous Cycle Timer

Reserved

NodeID

E8h

5.11

5.12

5.13

—

PhyControl

ECh

F0h

IsoCycTimer

—

F4h:FCh

100h

104h

108h

10Ch

110h

114h

118h

11Ch

120h

124h:17Ch

Asynchronous Request Filter High

AsyncRequestFilterHiSet

AsyncRequestFilterHiClear

AsyncRequestFilterLoSet

AsyncRequestFilterloClear

PhysicalRequestFilterHiSet

PhysicalRequestFilterHiClear

PhysicalRequestFilterLoSet

PhysicalRequestFilterloClear

PhysicalUpperBound

—

5.14.1

Asynchronous Request Filter Low

Physical Request Filter High

Physical Request Filter Low

5.4.2

Physical Upper Bound

Reserved

5.15

—

344

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Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Internal Registers (continued)

Table 18. OHCI Register Map (continued)

OHCI

DMA Context

Register Name

Abbreviation

Offset

Specification

Reference

Asynchronous

Request Transmit

[ATRQ]

Context Control

ContextControlSet

ContextControlClear

—

180h

184h

3.1, 7.2.2

Reserved

Command Pointer

Reserved

188h

—

CommandPtr

—

18Ch

3.1.2, 7.2.1

—

Asynchronous

Response

Transmit

190h:19Ch

1A0h

Context Control

ContextControlSet

ContextControlClear

—

3.1, 7.2.2

1A4h

[ATRS]

Reserved

Command Pointer

Reserved

1A8h

—

3.1.2, 7.2.1

—

CommandPtr

—

1ACh

Asynchronous

Request

1B0h:1BCh

1C0h

Context Control

ContextControlSet

ContextControlClear

—

3.1, 8.3.2

Receive

[ARRQ]

1C4h

Reserved

Command Pointer

Reserved

1C8h

—

CommandPtr

—

1CCh

3.1.2, 8.3.1

—

Asynchronous

Response

Receive

1D0h:1DFh

1E0h

Context Control

ContextControlSet

ContextControlClear

—

3.1, 8.3.2

1E4h

[ARRS]

Reserved

Command Pointer

Reserved

1E8h

—

3.1.2, 8.3.1

—

CommandPtr

—

1ECh

Isochronous

Transmit

Context n

n = 0:7

1F0h:1FFh

200h + 16 * n

204h + 16 * n

208h + 16 * n

20Ch + 16 * n

400h + 32 * n

404h + 32 * n

408h + 32 * n

40Ch + 32 * n

410h + 32 * n

Context Control

ContextControlSet

ContextControlClear

—

3.1, 9.2.2

Reserved

—

Command Pointer

Context Control

CommandPtr

ContextControlSet

ContextControlClear

—

3.1.2, 9.2.1

3.1, 10.3.2

Isochronous

Receive

Context n

n = 0:7

Reserved

Command Pointer

Context Match

Reserved

—

3.1.2, 10.3.1

10.3.3

CommandPtr

ContextMatch

—

414h + 32 * n –

41Ch + 32 * n

—

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Data Sheet, Rev. 1

December 2005

Internal Registers (continued)

OHCI Version Register

This register indicates the OHCI version supported, and whether or not the serial EEPROM is present. To support

backwards compatibility with existing hardware and software, the version and revision fields default to 8’h01 and

8’h00 respectively. These values denote compatibility with version 1.0 of the OHCI specification. However, both the

version and revision fields are programmable via the serial EEPROM. This functionality allows these fields to be

optionally updated to 8’h01 and 8’h10 respectively to indicate compatibility with version 1.1 of the OHCI

specification. Note that if the version and revision fields are programmed with OHCI 1.1 values, then the

LinkOptions register (see Table 60) should also be programmed to properly enable OHCI 1.1 features within the

FW322.

Offset:

00h

Default:

Type:

0X01 0000h

Read/write

Reference:

1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.2

Table 19. OHCI Version Register Description

Bit

Field Name

Type

Description

31:25

24

Reserved

GUID_ROM

Version

R

Reserved.

The FW322 sets this bit if the serial EEPROM is detected.

23:16

Major Version of the OHCI. The FW322 is compliant with both

version 1.0 and version 1.1 of the 1394 Open Host Controller Interface

Specification. This field defaults to 01h, but can be reconfigured via

the serial EEPROM.

15:8

7:0

Reserved

Revision

R

Reserved.

Minor Version of the OHCI. The FW322 is compliant with both

version 1.0 and version 1.1 of the 1394 Open Host Controller Interface

Specification. This field defaults to 00h, but can be reconfigured via

the serial EEPROM.

36

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Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Internal Registers (continued)

GUID ROM Register

The GUID ROM register is used to access the serial EEPROM, and is only applicable if bit 24 (GUID_ROM) in the

OHCI Version register is set.

Offset:

04h

Default:

Reference:

00XX 0000h

1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.3

Table 20. GUID ROM Register Description

Bit

Field Name

Type

Description

31

addrReset

RWU

Software sets this bit to reset the GUID ROM address to 0. When the

FW322 completes the reset, it clears this bit.

30:26

25

Reserved

rdStart

R

Reserved. Bits 30:26 return 0s when read.

RWU

A read of the currently addressed byte is started when this bit is set.

This bit is automatically cleared when the FW322 completes the read

of the currently addressed GUID ROM byte.

24

Reserved

rdData

R

Reserved. Bit 24 returns 0 when read.

23:16

RU

This field represents the data read from the GUID ROM and is only

valid when rdStart = 0.

15:8

7:0

Reserved

miniROM

R

Reserved. Bits 15:8 return 0s when read.

Indicates the first byte location of the miniROM image in the GUID

ROM. A value of 0 is returned if no miniROM is implemented.

Asynchronous Transmit Retries Register

The Asynchronous Transmit Retries register indicates the number of times the FW322 attempts a retry for

asynchronous DMA request transmit and for asynchronous physical and DMA response transmit.

Offset:

08h

Default:

Reference:

0000 0000h

1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.4

Table 21. Asynchronous Transmit Retries Register Description

Bit

Field Name

Type

Description

31:29

secondLimit

R

The second limit field returns 0s when read, since outbound dual-

phase retry is not implemented.

28:16

cycleLimit

R

The cycle limit field returns 0s when read, since outbound dual-

phase retry is not implemented.

15:12

11:8

Reserved

R

Reserved. Bits 15:12 return 0s when read.

maxPhysRespRetries

RW

This field tells the physical response unit how many times to

attempt to retry the transmit operation for the response.

7:4

3:0

maxATRespRetries

maxATReqRetries

RW

This field tells the asynchronous transmit DMA response unit how

many times to attempt to retry the transmit operation for the

response.

This field tells the asynchronous transmit DMA request unit how

many times to attempt to retry the transmit operation for the

response.

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1394a PCI PHY/Link Open Host Controller

Data Sheet, Rev. 1

December 2005

Internal Registers (continued

CSR Data Register

The CSR Data register is used to access the bus management CSR registers from the host through compare-swap

operations. This register contains the data to be stored in a CSR if the compare is successful.

Offset:

0Ch

Default:

Reference:

XXXX XXXXh

1394 Open Host Controller Interface Specification, Rev. 1.1, Sections 5.5.1.

Table 22. CSR Data Register Description

Bit

Field Name

Type

Description

31:0

csrData

RWU

At start of operation, the data to be stored if the compare is

successful.

CSR Compare Register

The CSR Compare register is used to access the bus management CSR registers from the host through compare-

swap operations. This register contains the data to be compared with the existing value of the CSR resource.

Offset:

10h

Default:

Reference:

XXXX XXXXh

1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.5.1

Table 23. CSR Compare Register Description

Bit

Field Name

Type

Description

31:0

csrCompare

RW

The data to be compared with the existing value of the CSR

resource.

CSR Control Register

The CSR Compare register is used to access the bus management CSR registers from the host through compare-

swap operations. Bits in this register are used to initiate a compare-and-swap operation on a selected resource and

signal when that operation is complete.

Offset:

14h

Default:

Reference:

8000 000Xh

1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.5.1

Table 24. CSR Control Register Description

Bit

Field Name

Type

Description

31

csrDone

RU

This bit is set by the FW322 when a compare-swap operation is

complete. It is reset whenever this register is written.

30:2

1:0

Reserved

csrSel

R

Reserved. Bits 30:2 return 0s when read.

RW

This field selects the CSR resource as follows:

00 = BUS_MANAGER_ID

01 = BANDWIDTH_AVAILABLE

10 = CHANNELS_AVAILABLE_HI

11 = CHANNELS_AVAILABLE_LO

388

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Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Internal Registers (continued)

Configuration ROM Header Register

The Configuration ROM Header register externally maps to the first quadlet of the 1394 configuration ROM, offset

48’hFFFF_F000_0400.

Offset:

18h

Default:

Reference:

0000 0000h

1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.5.2

Table 25. Configuration ROM Header Register Description

Bit

Field Name

Type

Description

31:24

info_length

RW

IEEE 1394 Bus Management Field. Must be valid when bit 17 (linkEn-

able) of the Host Controller Control register is set (see Table 34).

23:16

15:0

crc_length

RW

IEEE 1394 Bus Management Field. Must be valid when bit 17 (linkEn-

able) of the Host Controller Control register is set (see Table 34).

IEEE 1394 Bus Management Field. Must be valid at any time bit 17

(linkEnable) of the Host Controller Control register is set (see Table 34).

rom_crc_value

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Data Sheet, Rev. 1

December 2005

Internal Registers (continued)

Bus Identification Register

The Bus Identification register externally maps to the first quadlet in the Bus_Info_Block and is addressable at

FFFF_F000_0404. This register is read locally at the offset specified below.

Offset:

1Ch

Default:

Reference:

3133 3934h

1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.5.3

Table 26. Bus Identification Register Description

Bit

Field Name

Type

Description

31—0

busID

R

Contains the constant 32’h31333934, which is the ASCII value for

1394.

Bus Options Register

The Bus Options register externally maps to the second quadlet of the Bus_Info_Block and is 1394 addressable

at FFFF_F000_0408.

Offset:

20h

Default:

Reference:

0000 A002h

1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.5.4

Table 27. Bus Options Register Description

Bit

Field Name

Type

Description

31:16

Reserved

R or RW Reserved. Bits return 0s when read; 23:16 and 31:27 are RW and

undefined.

15:12

max_rec

RW

IEEE 1394 Bus Management Field. Hardware initializes this field

to indicate the maximum number of bytes in a block request packet

that is supported by the implementation. This value,

max_rec_bytes, must be 512 or greater and is calculated by

(max_rec + 1)

2

. Software may change this field; however, this field

must be valid at any time bit 17 (linkEnable) of the Host Controller

Control register is set. A received block write request packet with a

length greater than max_rec_bytes may generate an

ack_type_error. This field is not affected by a soft reset, and

defaults to value indicating 2048 bytes on a hard reset.

11:3

2:0

Reserved

Lnk_spd

R

Reserved. Bits 11:3 return 0s when read.

Link Speed. This field returns 010, indicating that the link speeds

of 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s are supported.

400

Agere Systems Inc.

Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Internal Registers (continued)

GUID High Register

The GUID High register represents the upper quadlet in a 64-bit global unique ID (GUID), which maps to the third

quadlet in the Bus_Info_Block 1394, addressable at FFFF_F000_0410. This register contains node_vendor_ID

and chip_ID_hi fields. This register initializes to 0s on a hardware reset, which is an illegal GUID value. If a serial

EEPROM is detected, then the contents of this register are loaded through the serial EEPROM interface after a

PCI reset. If no serial EEPROM is detected, then the contents of this register can be loaded with a single PCI

write to either of two configuration registers, executed after a PCI reset. The two configuration registers are

located at offset 0x70, for new PCI applications, and offset 0x80, for backward compatibility with FW322 05 PCI

applications only. After one of these load mechanisms has completed, this register becomes read only.

Offset:

24h

Default:

Reference:

0000 0000h

1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.5.5

Table 28. GUID High Register Description

Bit

Field Name

Type

Description

31:8

node_vendor_ID

RWU

IEEE 1394 Bus Management Fields. Firmware or hardware must

ensure that this register is valid whenever HCCControl.linkEnable

bit is set.

7:0

chip_ID_hi

RWU

Firmware or hardware must ensure that this register is valid when-

ever HCCControl.linkEnable bit is set.

GUID Low Register

The GUID Low register represents the lower quadlet in a 64-bit global unique ID (GUID), which maps to

chip_ID_lo in the Bus_Info_Block 1394, addressable at FFFF_F000_0414. This register initializes to 0s on a

hardware reset and behaves identical to the GUID High register. If no serial EEPROM is detected, then the

contents of this register can be loaded with a PCI configuration write to either offset 0x74 or 0x84, as described

above.

Offset:

28h

Default:

Reference:

0000 0000h

1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.5.5

Table 29. GUID Low Register Description

Bit

Field Name

Type

Description

31:0

chip_ID_lo

R

IEEE 1394 Bus Management Fields. Firmware or hardware must

ensure that this register is valid whenever HCCControl.linkEnable

bit is set.

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Data Sheet, Rev. 1

December 2005

Internal Registers (continued)

Configuration ROM Mapping Register

The Configuration ROM Mapping register contains the start address within system memory that maps to the start

address of 1394 configuration ROM for this node.

Offset:

34h

Default:

Reference:

0000 0000h

1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.5.6

Table 30. Configuration ROM Mapping Register Description

Bit

Field Name

Type

Description

31:10

configROMaddr

RW

If a quadlet read request to 1394 offset 48’hFFFF_F000_0400

through offset 48’hFFFF_F000_07FF is received, then the low-

order 10 bits of the offset are added to this register to determine

the host memory address of the read request.

9:0

Reserved

R

Reserved. Bits 9:0 return 0s when read.

422

Agere Systems Inc.

Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Internal Registers (continued)

Posted Write Address Low Register

The Posted Write Address Low register is used to communicate error information if a write request is posted and

an error occurs while writing the posted data packet.

Offset:

38h

Default:

Reference:

XXXX XXXXh

1394 Open Host Controller Interface Specification, Rev. 1.1, Section 13.2.8.1.

Table 31. Posted Write Address Low Register Description

Bit

Field Name

Type

Description

31:0

offsetLo

RU

The lower 32 bits of the 1394 destination offset of the write request

that was posted and failed.

Posted Write Address High Register

The Posted Write Address High register is used to communicate error information if a write request is posted and

an error occurs while writing the posted data packet.

Offset:

3Ch

Default:

Reference:

XXXX XXXXh

1394 Open Host Controller Interface Specification, Rev. 1.1, Section 13.2.8.1.

Table 32. Posted Write Address High Register Description

Bit

Field Name

Type

Description

31:16

sourceID

RU

This field is the bus and node number of the node that issued the

write request that was posted and failed.

15:0

offsetHi

RU

The upper 16 bits of the 1394 destination offset of the write

request that was posted and failed.

Vendor ID Register

The Vendor ID register holds the company ID of an organization that specifies any vendor-unique registers.

Offset:

40h

Default:

Reference:

0000 0000h

1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.6

Table 33. Vendor ID Register Description

Bit

Field Name

Type

Description

31:24

vendorUnique

R

Returns 0 when read, since the FW322 does not specify any

vendor unique registers.

23:0

vendorCompanyID

R

Returns 0 when read, since the FW322 does not specify any

vendor unique registers.

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Data Sheet, Rev. 1

December 2005

Internal Registers (continued)

Host Controller Control Register

The Host Controller Control set/clear register pair provides flags for controlling the OHCI portion of the FW322.

Offset:

50h set register

54h clear register

Default:

X08X 0000h

Reference:

1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.7

Table 34. Host Controller Control Register Description

Bit

Field Name

Type

Description

31

BIBimageValid

RSU

This bit is used to enable both OHCI response to block read

requests to host configuration ROM and the OHCI mechanism for

automatically updating configuration ROM. When this bit is 0, the

OHCI returns a ack_type_error on block read requests to configu-

ration ROM and does not update the configROMmap register or

ConfigROMheader and BusOptions registers when a 1394 bus

reset occurs. When this bit is 1, the physical response unit handles

block reads of host configuration ROM and the mechanism for

automatically updating configuration ROM is enabled.

30

29

noByteSwapData

ackTardyEnable

RSC

This bit is used to control byte swapping during host bus accesses

involving the data portion of 1394 packets. Data is swapped if

equal to 0, not swapped when equal to 1.

This bit is used to control the acknowledgment of ack_tardy. When

this bit is set to one, ack_tardy may be returned as an acknowl-

edgement to configuration ROM accesses from 1394 to OHCI

including accesses to the bus_info_block. The host controller will

return ack_tardy to all other asynchronous packets addressed to

the OHCI node.

28:24

23

Reserved

R

Reserved. Bits 28:24 return 0s when read.

programPhyEnable

RC

This bit informs upper-level software that lower-level software has

consistently configured the 1394a-2000 enhancements in the link

and PHY core. When this bit is 1, generic software such as the

OHCI driver is responsible for configuring 1394a-2000 enhance-

ments in the PHY core and bit 22 (aPhyEnhanceEnable) in the

FW322. When this bit is 0, the generic software may not modify

the 1394a-2000 enhancements in the FW322 and cannot interpret

the setting of bit 22 (aPhyEnhanceEnable). When a serial

EEPROM is present, this bit is initialized from the EEPROM.

Otherwise, this bit is initialized to the hardware default value.

22

aPhyEnhanceEnable

RSC

When bits 23 (programPhyEnable) is 1 and 17 (linkEnable) is 0,

the OHCI driver can set this bit to use all 1394a-2000 enhance-

ments. When bit 23 (programPhyEnable) is set to 0, the software

does not change PHY enhancements or this bit.

21:20

19

Reserved

LPS

R

Reserved. Bits 21:20 return 0s when read.

RSU

Link Power Status. This bit drives the LPS signal to the PHY core

within the FW322 (see Section 5.7 of the OHCI 1.1 Specification

for additional details).

18

postedWriteEnable

RSC

This bit is used to enable (1) or disable (0) posted writes. Software

should change this bit only when bit 17 (linkEnable) is 0.

444

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Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Internal Registers (continued)

Table 34. Host Controller Control Register Description (continued)

Bit

Field Name

Type

Description

17

linkEnable

RSU

This bit is cleared to 0 by either a hardware or software reset. Soft-

ware must set this bit to 1 when the system is ready to begin oper-

ation and then force a bus reset. This bit is necessary to keep

other nodes from sending transactions before the local system is

ready. When this bit is cleared, the FW322 is logically and immedi-

ately disconnected from the 1394 bus, no packets are received or

processed, and no packets transmitted.

16

SoftReset

Reserved

RSU

R

When this bit is set, all FW322 states are reset, all FIFOs are

flushed, and all OHCI registers are set to their hardware reset

values unless otherwise specified. PCI registers are not affected

by this bit. This bit remains set while the softReset is in progress

and reverts back to 0 when the reset has completed.

15:0

Reserved. Bits 15:0 return 0s when read.

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1394a PCI PHY/Link Open Host Controller

Data Sheet, Rev. 1

December 2005

Internal Registers (continued)

SelfID Buffer Pointer Register

The SelfID Buffer Pointer register points to the 2 Kbyte aligned base address of the buffer in host memory where

the SelfID packets are stored during bus initialization. Bits 31:11 are read/write accessible.

Offset:

64h

Default:

Reference:

XXXX XX00h

1394 Open Host Controller Interface Specification, Rev. 1.1, Section 11.1

Table 35. SelfID Buffer Pointer Register Description

Bit

Field Name

Type

Description

31:11

SelfIDBufferPtr

RW

Contains the 2 Kbyte aligned base address of the buffer in host

memory where received SelfID packets are stored.

10:0

Reserved

R

Reserved.

SelfID Count Register

The SelfID Count register keeps a count of the number of times the SelfID process has occurred. The register

also flags any SelfID errors and maintains a count of the amount of SelfID data in the SelfID buffer.

Offset:

68h

Default:

Reference:

X0XX 0000h

1394 Open Host Controller Interface Specification, Rev. 1.1, Section 11.2

Table 36. SelfID Count Register Description

Bit

Field Name

Type

Description

31

selfIDError

RU

When this bit is 1, an error was detected during the most recent

SelfID packet reception. The contents of the SelfID buffer are

undefined. This bit is cleared after a SelfID reception in which no

errors are detected. Note that an error can be a hardware error or

a host bus write error.

30:24

23:16

Reserved

R

Reserved. Bits 30:24 return 0s when read.

selfIDGeneration

RU

The value in this field increments each time a bus reset is

detected. This field rolls over to 0 after reaching 255.

15:11

10:2

Reserved

selfIDSize

R

Reserved. Bits 15:11 return 0s when read.

RU

This field indicates the number of quadlets that have been written

into the SelfID buffer for the current bits 23:16 (SelfIDGeneration

field). This includes the header quadlet and the SelfID data. This

field is cleared to 0 when the SelfID reception begins.

1:0

Reserved

R

Reserved. Bits 1:0 return 0s when read.

466

Agere Systems Inc.

Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Internal Registers (continued)

Isochronous Receive Multiple Channel Mask High (IRMultiChanMaskHi) Register

The Isochronous Receive Multiple Channel Mask High set/clear register is used to enable packet receives from

the upper 32 isochronous data channels. A read from either the set register or clear register returns the content of

the Isochronous Receive Multiple Channel Mask High register.

Offset:

70h set register

74h clear register

Default:

XXXX XXXXh

Reference:

1394 Open Host Controller Interface Specification, Rev. 1.1, Section 10.4.1.1

Table 37. Isochronous Receive Channel Mask High Register Description

Bit Field Name Type Description

31:0 isoChannel(N + 32) RSC If bit N (where N = a bit number 0—31) is set, iso

channel number (N + 32) is enabled.

Isochronous Receive Multiple Channel Mask Low (IRMultiChanMaskLo) Register

The Isochronous Receive Channel Mask Low set/clear register is used to enable packet receives from the lower

32 isochronous data channels.

Offset:

78h set register

7Ch clear register

Default:

XXXX XXXXh

Reference:

1394 Open Host Controller Interface Specification, Rev. 1.1, Section 10.4.1.

Table 38. Isochronous Receive Channel Mask Low Register Description

Bit

Field Name

Type

Description

31:0

isoChannel N

RSC If bit N (where N = a bit number 0—31) is set, iso

channel number N is enabled.

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Data Sheet, Rev. 1

December 2005

Internal Registers (continued)

Interrupt Event (IntEvent) Register

The Interrupt Event set/clear register reflects the state of the various FW322 interrupt sources. The interrupt bits

are set by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the

set register. The only mechanism to clear the bits in this register is to write a 1 to the corresponding bit in the clear

register. Reading the IntEventSet register returns the current state of the IntEvent register. Reading the

IntEventClear register returns the masked version of the IntEvent register, i.e., the bit-wise AND function of

IntEvent and IntMask.

Offset:

80h set register

84h clear register

Default:

XXXX 0XXXh

Reference:

1394 Open Host Controller Interface Specification, Rev. 1.1, Section 6.1.

Table 39. Interrupt Event Register Description

Bit

Field Name

Type

Description

31

30

Reserved

R

Reserved. Bit 31 returns 0 when read.

vendorSpecific

RSCU This vendor-specific interrupt event is reported when serial EEPROM

read is complete.

29

SoftInterrupt

RSC

Soft Interrupt. This bit may be used by software to generate a host

controller interrupt for its own use.

28

27

Reserved

ack_Tardy

R

Reserved. Bit 28 returns 0 when read.

RSCU This bit will be set when the ackTardyEnable bit of the HC Control

register (see Table 34) is set to 1 and any of the following conditions

occur:

a. Data is present in a FIFO that is to be delivered to the host.

b. The physical response unit is busy processing requests or sending

responses.

c. The host controller sent an ack_tardy acknowledgment.

26

25

phyRegRcvd

cycleTooLong

RSCU The FW322 has received a PHY Core register data byte, which can be

read from the PHY Core Layer Control register.

RSCU If bit 21 (cycleMaster) of the Link Control register (see Table 45) is set,

then this indicates that over 125 µs have elapsed between the start of

sending a cycle start packet and the end of a subaction gap. The Link

Control register bit 21 (cycleMaster) is cleared by this event.

24

23

22

unrecoverableError RSCU This event occurs when the FW322 encounters any error that forces it

to stop operations on any or all of its subunits, for example, when a

DMA context sets its dead bit. While this bit is set, all normal interrupts

for the context(s) that caused this interrupt are blocked from being set.

cycleInconsistent

cycleLost

RSCU A cycle start was received that had values for cycleSeconds and

cycleCount fields that are different from the values in bits 31:25 (cycle-

Seconds field) and bits 24:12 (cycleCount field) of the Isochronous

Cycle Timer register (see Table 48).

RSCU A lost cycle is indicated when no cycle_start packet is sent/received

between two successive cycleSynch events. A lost cycle can be

predicted when a cycle_start packet does not immediately follow the

first subaction gap after the cycleSynch event or if an arbitration reset

gap is detected after a cycleSynch event without an intervening cycle

start. This bit may be set either when it occurs or when logic predicts

that it will occur.

488

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Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Internal Registers (continued)

Table 39. Interrupt Event Register Description (continued)

Bit

Field Name

Type

Description

21

cycle64Seconds

RSCU Indicates that the seventh bit of the cycleSeconds (see Table 48)

counter has changed.

20

cycleSynch

RSCU Indicates that a new isochronous cycle has started. This bit is set when

the low-order bit of the cycleCount (see Table 48) toggles.

19

18

PHY

RSCU Indicates the PHY core requests an interrupt through a status transfer.

regAccessFail

RSCU Indicates that an OHCI register access failed due to a missing SCLK

clock signal from the PHY. When a register access fails, this bit will be

set before the next register access.

17

16

busReset

RSCU Indicates that the PHY core chip has entered bus reset mode.

selfIDcomplete

RSCU A SelfID packet stream has been received. It is generated at the end of

the bus initialization process. This bit is turned off simultaneously when

bit 17 (busReset) is turned on.

15

SelfIDcomplete2

RSCU Secondary indication of the end of a SelfID packet stream. This bit will

be set by the OHCI when it sets SelfIDcomplete, and will retain state

independent of the busReset bit of this register.

14:10

9

Reserved

R

Reserved. Bits 14:10 return 0s when read.

lockRespErr

RSCU Indicates that the FW322 sent a lock response for a lock request to a

serial bus register, but did not receive an ack_complete.

8

7

postedWriteErr

isochRx

RSCU Indicates that a host bus error occurred while the FW322 was trying to

write a 1394 write request, which had already been given an

ack_complete, into system memory.

RU

Isochronous Receive DMA Interrupt. Indicates that one or more

isochronous receive contexts have generated an interrupt. This is not a

latched event; it is the ORing of all bits in the Isochronous Receive

Interrupt Event and Isochronous Receive Interrupt Mask registers. The

Isochronous Receive Interrupt Event register (see Table 43) indicates

which contexts have interrupted.

6

isochTx

RU

Isochronous Transmit DMA Interrupt. Indicates that one or more

isochronous transmit contexts have generated an interrupt. This is not

a latched event; it is the ORing of all bits in the Isochronous Transmit

Interrupt Event (see Table 41) and Isochronous Transmit Interrupt

Mask (see Table 42) registers. The Isochronous Transmit Interrupt

Event register indicates which contexts have interrupted.

5

4

3

2

RSPkt

RQPkt

ARRS

ARRQ

RSCU Indicates that a packet was sent to an asynchronous receive response

context buffer and the descriptor’s xferStatus and resCount fields have

been updated.

RSCU Indicates that a packet was sent to an asynchronous receive request

context buffer and the descriptor’s xferStatus and resCount fields have

been updated.

RSCU Asynchronous Receive Response DMA Interrupt. This bit is condi-

tionally set upon completion of an ARRS DMA context command

descriptor.

RSCU Asynchronous Receive Request DMA Interrupt. This bit is condi-

tionally set upon completion of an ARRQ DMA context command

descriptor.

1

0

respTxComplete

reqTxComplete

RSCU Asynchronous Response Transmit DMA Interrupt. This bit is condi-

tionally set upon completion of an ATRS DMA command.

RSCU Asynchronous Request Transmit DMA Interrupt. This bit is condi-

tionally set upon completion of an ATRQ DMA command.

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Data Sheet, Rev. 1

December 2005

Internal Registers (continued)

Interrupt Mask (IntMask) Register

The Interrupt Mask set/clear register is used to enable/disable the various FW322 interrupt sources. Reads from

either the set register or the clear register always return the contents of the Interrupt Mask register. In all cases

except masterIntEnable (bit 31), the enables for each interrupt event align with the Interrupt Event (IntEvent)

register bits (see Table 39). A one bit in the IntMask register enables the corresponding IntEvent register bit to

generate a processor interrupt. A zero bit in IntMask disables the corresponding IntEvent register bit from

generating a processor interrupt. A bit is set in the IntMask register by writing a one to the corresponding bit in the

IntMaskSet address and cleared by writing a one to the corresponding bit in the IntMaskClear address.

Offset:

88h set register

8Ch clear register

Default:

XXXX 0XXXh

Reference:

1394 Open Host Controller Interface Specification, Rev. 1.1, Section 6.2.

Table 40. Interrupt Mask Register Description

Bit

Field Name

Type

Description

31

masterIntEnable

RSCU Master Interrupt Enable. If this bit is set, then external interrupts

are generated in accordance with the Interrupt Mask register. If this

bit is cleared, then external interrupts are not generated, regardless

of the Interrupt Mask register settings. The value of masterIntEnable

has no effect on the value returned by reading the IntEventClear.

30

29

vendorSpecific

softInterrupt

RSC

When this bit is set, this vendor-specific interrupt mask enables

interrupt generation when bit 30 (vendorSpecific) of the Interrupt

Event register (Table 39) is set.

Soft Interrupt. This bit may be used by software to generate a host

controller interrupt for its own use. When set, this bit enables the

corresponding IntEvent register bit to generate a processor inter-

rupt.

RSC

28

27

Reserved

ack_Tardy

R

Reserved. Bit 28 returns 0 when read.

RSCU A one bit enables the corresponding IntEvent register bit to

generate a processor interrupt. A zero bit disables the

corresponding IntEvent register bit from generating a processor

interrupt.

26

phyRegRcvd

cycleTooLong

unrecoverableError

cycleInconsistent

cycleLost

25

24

23

22

21

cycle64Seconds

cycleSynch

20

19

PHY

18

regAccessFail

busReset

17

16

selfIDcomplete

SelfIDcomplete2

Reserved

15

14:10

R

Reserved. Bits 14:10 return 0s when read.

500

Agere Systems Inc.

Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Internal Registers (continued)

Table 40. Interrupt Mask Register Description (continued)

Bit

Field Name

Type

Description

9

8

7

6

5

4

3

2

1

0

lockRespErr

postedWriteErr

isochRx

RSCU When set, these bits enable the corresponding IntEvent register bits

to generate a processor interrupt.

isochTx

RSPkt

RQPkt

ARRS

ARRQ

respTxComplete

reqTxComplete

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Data Sheet, Rev. 1

December 2005

Internal Registers (continued)

Isochronous Transmit Interrupt Event (isoXmitIntMask) Register

The Isochronous Transmit Interrupt Event (isoXmitIntMask) set/clear register reflects the interrupt state of the iso-

chronous transmit contexts. An interrupt is generated on behalf of an isochronous transmit context if an

OUTPUT_LAST command completes and its interrupt bits are set. Upon determining that the Interrupt Event regis-

ter isochTx (bit 6) (see Table 39) interrupt has occurred, software can check this register to determine which con-

text(s) caused the interrupt. The interrupt bits are set by an asserting edge of the corresponding interrupt signal, or

by writing a 1 in the corresponding bit in the set register. The only mechanism to clear the bits in this register is to

write a 1 to the corresponding bit in the clear register.

Reading the isoXmitIntEventSet register returns the current state of the isoXmitIntEvent register. Reading the

isoXmitIntEventClear register returns the masked version of the isoXmitIntEvent register, i.e., the bit-wise AND

function of isoXmitIntEvent and isoXmitIntMask.

Offset:

90h

set register

94h

clear register

Default:

0000 00XXh

Reference:

1394 Open Host Controller Specification, Rev. 1.1, Section 6.3

Table 41. Isochronous Transmit Interrupt Event Register Description

Bit

Field Name Type

Description

Reserved. Bits 31:8 return 0s when read.

31:8

7

Reserved

isoXmit7

R

RSCU Isochronous transmit channel 7 caused the interrupt event register bit 6 (isochTx)

interrupt.

6

5

4

3

2

1

0

isoXmit6

isoXmit5

isoXmit4

isoXmit3

isoXmit2

isoXmit1

isoXmit0

RSCU Isochronous transmit channel 6 caused the interrupt event register bit 6 (isochTx)

interrupt.

RSCU Isochronous transmit channel 5 caused the interrupt event register bit 6 (isochTx)

interrupt.

RSCU Isochronous transmit channel 4 caused the interrupt event register bit 6 (isochTx)

interrupt.

RSCU Isochronous transmit channel 3 caused the interrupt event register bit 6 (isochTx)

interrupt.

RSCU Isochronous transmit channel 2 caused the interrupt event register bit 6 (isochTx)

interrupt.

RSCU Isochronous transmit channel 1 caused the interrupt event register bit 6 (isochTx)

interrupt.

RSCU Isochronous transmit channel 0 caused the interrupt event register bit 6 (isochTx)

interrupt.

522

Agere Systems Inc.

Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Internal Registers (continued)

Isochronous Transmit Interrupt Mask (isoXmitIntMask) Register

The Isochronous Transmit Interrupt Mask set/clear register is used to enable the isochTx interrupt source on a

per-channel basis. Reads from either the set register or the clear register, always return the contents of the

Isochronous Transmit Interrupt Mask register. In all cases, the enables for each interrupt event align with the

event register bits detailed in Table 42.

Offset:

98h set register

9Ch clear register (returns IsoXmitEvent and IsoXmitMask when read)

0000 00XXh

Default:

Reference:

1394 Open Host Controller Specification, Rev. 1.1, Section 6.3

Table 42. Isochronous Transmit Interrupt Event Description

Bit

Field Name

Type

Description

31:8

7:0

Reserved

R

Reserved. Bits 31:8 return 0s when read.

isoXmit7:isoXmit0

RSCU

Setting one of these bits enables the corresponding interrupt

event in the isoXmitIntEvent register. Clearing a bit in this register

disables the corresponding interrupt event in the isoXmitIntEvent

register.

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Data Sheet, Rev. 1

December 2005

Internal Registers (continued)

Isochronous Receive Interrupt Event (isoRecvIntEvent) Register

The Isochronous Receive Interrupt Event set/clear register reflects the interrupt state of the isochronous receive

contexts. An interrupt is generated on behalf of an isochronous receive context if an INPUT_* command completes

and its interrupt bits are set. Upon determining that the interrupt event register isochRx (bit 7) interrupt has

occurred, software can check this register to determine which context(s) caused the interrupt. The interrupt bits are

set by an asserting edge of the corresponding interrupt signal, or by writing a 1 in the corresponding bit in the set

register. The only mechanism to clear the bits in this register is to write a 1 to the corresponding bit in the clear reg-

ister.

The isoRecvIntMask register is ANDed with the isoRecvIntEvent register to enable selected bits to generate pro-

cessor interrupts. Reading the isoRecvIntEventSet register returns the current state of the isoRecvIntEvent regis-

ter. Reading isoRecvIntEventClear register returns the masked version of the isoRecvIntEvent register, i.e., the bit-

wise AND function of isoRecvtIntEvent and isoRecvtIntMask.

Offset:

A0h set register

A4h clear register

Default:

0000 0000h

Reference:

1394 Open Host Controller Specification, Rev. 1.1, Section 6.4

Table 43. Isochronous Receive Interrupt Event Description

Bit

Field Name

Type

Description

31:8

Reserved

isoRecv7

R

Reserved. Bits 31:8 return 0s when read.

RSCU

Isochronous receive context 7 caused the interrupt event register bit

7 (isochRx) interrupt.

7

6

5

4

3

2

1

0

isoRecv6

isoRecv5

isoRecv4

isoRecv3

isoRecv2

isoRecv1

isoRecv0

RSCU

Isochronous receive context 6 caused the interrupt event register bit

7 (isochRx) interrupt.

Isochronous receive context 5 caused the interrupt event register bit

7 (isochRx) interrupt.

Isochronous receive context 4 caused the interrupt event register bit

7 (isochRx) interrupt.

Isochronous receive context 3 caused the interrupt event register bit

7 (isochRx) interrupt.

Isochronous receive context 2 caused the interrupt event register bit

7 (isochRx) interrupt.

Isochronous receive context 1 caused the interrupt event register bit

7 (isochRx) interrupt.

Isochronous receive context 0 caused the interrupt event register bit

7 (isochRx) interrupt.

54

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Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Internal Registers (continued)

Isochronous Receive Interrupt Mask (isoRecvIntMask) Register

The Isochronous Receive Interrupt Mask set/clear register is used to enable the isochRx interrupt source on a

per-channel basis. Reads from either the set register or the clear register always return the contents of the

Isochronous Transmit Interrupt Mask register. In all cases, the enables for each interrupt event correspond to the

isoRecvIntEvent register bits. Setting a bit in this register enables the corresponding interrupt event in the

isoRecvIntEvent register. Clearing a bit in this register disables the corresponding interrupt event in the

isoRecvIntEvent register.

Offset:

A8h set register

ACh clear register

Default:

Reference:

0000 000Xh

1394 Open Host Controller Specification, Rev. 1.1, Section 6.4

Fairness Control Register

The Fairness Control register provides a mechanism by which software can direct the host controller to transmit

multiple asynchronous requests during a fairness interval, as specified by the IEEE-1394a Specification.

Offset:

DCh

Default:

Reference:

0000 0000h

1394 Open Host Controller Specification, Rev. 1.1, Section 5.9

Table 44. Fairness Control Register Description

Bit

Field Name Type

Description

Reserved. Bits 31:8 return 0s when read.

31:8

7:0

Reserved

pri_req

R

RW This field specifies the maximum number of priority arbitration requests for asyn-

chronous request packets that the link is permitted to make of the PHY core during

the fairness interval.

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Data Sheet, Rev. 1

December 2005

Internal Registers (continued)

Link Control Register

The Link Control register provides flags to enable and configure the link core cycle timer and receiver portions of

the FW322.

Offset:

E0h set register

E4h clear register

Default:

00X0 0X00h

Reference:

1394 Open Host Controller Specification, Rev. 1.1, Section 5.10

Table 45. Link Control Register Description

Bit

Field Name

Type

Description

31:23

22

Reserved

R

Reserved. Bits 31:23 return 0s when read.

cycleSource

RSC

Set to 0, since the FW322 does not support an external cycle

timer.

21

cycleMaster

RSCU When this bit is set, and the FW322 PHY core has notified the

OHCI core that it is root, the OHCI generates a cycle start packet

every time the cycle timer rolls over, based on the setting of bit 22.

When this bit is cleared, the OHCI accepts received cycle start

packets to maintain synchronization with the node that is sending

them. This bit is automatically reset when bit 25 (cycleTooLong) of

the Interrupt Event register (see Table 39) is set and cannot be set

until bit 25 (cycleTooLong) is cleared.

20

CycleTimerEnable

RSC

When this bit is set, the cycle timer offset counts cycles of the

24.576 MHz clock and rolls over at the appropriate time based on

the settings of the above bits. When this bit is cleared, the cycle

timer offset does not count.

19:11

10

Reserved

R

Reserved. Bits 19:11 return 0s when read.

RcvPhyPkt

RSC

When this bit is set, the receiver accepts incoming PHY core

packets into the AR request context if the AR request context is

enabled. This does not control receipt of self-identification packets

received outside of the SelfID phase of bus initialization.

9

RcvSelfID

RSC

When this bit is set, the receiver accepts incoming self-identifica-

tion packets. Before setting this bit to 1, software must ensure that

the SelfID Buffer Pointer register contains a valid address.

8:7

6

Reserved

R

Reserved.

tag1SyncFilterLock

RS

When this bit is set, the tag1SyncFilter bit of the IR Context Match

register (see Table 59) equals one for all IR contexts. When this bit

is cleared, the tag1SynchFilter bit has read/write access. A hard-

ware reset clears this bit to 0. A soft reset has no effect.

5:0

Reserved

R

Reserved. Bits 5:0 return 0s when read.

566

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Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Internal Registers (continued)

Node Identification Register

The Node Identification register contains the address of the node on which the OHCI resides, and indicates the

valid node number status. The 16-bit combination of the busNumber field (bits 15:6) and the NodeNumber field

(bits 5:0) is referred to as the node ID.

Offset:

E8h

Default:

Reference:

0000 FFXXh

1394 Open Host Controller Specification, Rev. 1.1, Section 5.11

Table 46. Node Identification Register Description

Bit

Field Name Type

Description

31

iDValid

RU This bit indicates whether or not the FW322 has a valid node number. It is cleared

when a 1394 bus reset is detected and set when the FW322 receives a new node

number from the PHY core.

30

29:28

27

root

RU This bit is set during the bus reset process if the attached PHY core is root.

Reserved

CPS

R

Reserved. Bits 29:28 return 0s when read.

RU Set if the PHY core is reporting that cable power status is OK.

Reserved. Bits 26:16 return 0s when read.

26:16

15:6

Reserved

R

busNumber RWU This number is used to identify the specific 1394 bus to which the FW322 belongs

when multiple 1394-compatible buses are connected via a bridge.

5:0

NodeNumber RU This number is the physical node number established by the PHY core during

self-identification. It is automatically set to the value received from the PHY core

after the self-identification phase. If the PHY core sets the nodeNumber to 63,

then software should not set the run bit of the ContextControl register for either of

the AT DMA contexts (see Table 53).

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Data Sheet, Rev. 1

December 2005

Internal Registers (continued)

PHY Core Layer Control Register

The PHY Core Layer Control register is used to read or write a PHY Core register.

Offset:

ECh

Default:

Reference:

0000 0000h

1394 Open Host Controller Specification, Rev. 1.1, Section 5.12

Table 47. PHY Core Layer Control Register Description

Bit

Field Name Type

Description

31

rdDone

RU This bit is cleared to 0 by the FW322 when either bit 15 (rdReg) or bit 14 (wrReg)

is set. This bit is set when a register transfer is received by the OHCI core from

the PHY core and rdData is updated.

30:28

27:24

23:16

15

Reserved

rdAddr

rdData

rdReg

R

Reserved. Bits 30:28 return 0s when read.

RU This is the address of the register most recently received from the PHY core.

RU This field is the contents of a PHY Core register, which have been read at rdAddr.

RWU This bit is set by software to initiate a read request to a PHY Core register and is

cleared by hardware when the request has been sent. Bit 14 (wrReg) must not be

set when bit 15 (rdReg) is set.

14

wrReg

RWU This bit is set by software to initiate a write request to a PHY Core register and is

cleared by hardware when the request has been sent. Bit 15 (rdReg) must not be

set when bit 14 (wrReg) is set.

13:12

11:8

7:0

Reserved

regAddr

wrData

R

Reserved. Bits 13:12 return 0s when read.

RW This field is the address of the PHY Core register to be written or read.

RW This field is the data to be written to a PHY Core register and is ignored for reads.

Isochronous Cycle Timer Register

The Isochronous Cycle Timer register indicates the current cycle number and offset. When the FW322 is cycle

master, this register is transmitted with the cycle start message. When the FW322 is not cycle master, this register

is loaded with the data field in an incoming cycle start. In the event that the cycle start message is not received, the

fields can continue incrementing on their own (if programmed) to maintain a local time reference.

Offset:

F0h

Default:

Reference:

XXXX XXXXh

1394 Open Host Controller Specification, Rev. 1.1, Section 5.13

Table 48. Isochronous Cycle Timer Register Description

Bit

Field Name

Type

Description

31:25

cycleSeconds

RWU This field counts seconds [rollovers from bits 24:12 (cycleCount field)]

modulo 128.

24:12

11:0

cycleCount

cycleOffset

RWU This field counts cycles [rollovers from bits 11:0 (cycleOffset field)] modulo

8000.

RWU This field counts 24.576 MHz clocks modulo 3072, i.e., 125 ms. If an

external 8 kHz clock configuration is being used, then this bit must be set to

0 at each tick of the external clock.

588

Agere Systems Inc.

Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Internal Registers (continued)

Asynchronous Request Filter High Register

The Asynchronous Request Filter High set/clear register is used to enable asynchronous receive requests on a

per-node basis, and handles the upper node IDs. When a packet is destined for either the physical request context

or the ARRQ context, the source node ID is examined. If the bit corresponding to the node ID is not set in this reg-

ister, then the packet is not acknowledged and the request is not queued. The node ID comparison is done if the

source node is on the same bus as the FW322. All nonlocal bus-sourced packets are not acknowledged unless

bit 31 in this register is set.

Offset:

100h set register

104h clear register

Default:

0000 0000h

Reference:

1394 Open Host Controller Specification, Rev. 1.1, Section 5.14

Table 49. Asynchronous Request Filter High Register Description

Bit Field Name Type Description

31 asynReqResourceAll RSCU If this bit is set, then all asynchronous requests received by the FW322 from

nonlocal bus nodes are accepted and the values of all asynReqResourceN

bits will be ignored. Set/Clear operations to this register while the

IntEvent.busReset bit (see Table 39) is asserted will have no effect. A bus

reset will not affect the value of the asynReqResourceAll bit.

30:0 asynReqResourceN RSCU If this bit is set, then asynchronous requests received from node N (where

N = the bit number + 32) on local bus are accepted by FW322. All asyn-

ReqResourceN bits will be cleared to zero when a bus reset occurs. Set/

Clear operations to this register while the IntEvent.busReset bit (see Table

39) is asserted will have no effect.

Asynchronous Request Filter Low Register

The Asynchronous Request Filter Low set/clear register is used to enable asynchronous receive requests on a

per-node basis, and handles the lower node IDs. Other than filtering different node IDs, this register behaves

identically to the Asynchronous Request Filter High register.

Offset:

108h set register

10Ch clear register

Default:

0000 0000h

Reference:

1394 Open Host Controller Specification, Rev. 1.1, Section 5.14

Table 50. Asynchronous Request Filter Low Register Description

Bit Field Name Type Description

31:0 asynReqResourceN RSCU If this bit is set for local bus node number N (where N = the bit number from

0 to 31), then asynchronous requests received by the FW322 from that node

are accepted. All asynReqResourceN bits will be cleared to zero when a bus

reset occurs. Set/Clear operations to this register while the

IntEvent.busReset bit (see Table 39) is asserted will have no effect.

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Data Sheet, Rev. 1

December 2005

Internal Registers (continued)

Physical Request Filter High Register

The Physical Request Filter High set/clear register is used to enable physical receive requests on a per-node

basis and handle the upper-node IDs. When a packet is destined for the physical request context and the node ID

has been compared against the ARRQ registers, then the comparison is done again with this register. If the bit

corresponding to the node ID is not set in this register, then the request is handled by the ARRQ context instead

of the physical request context.

Offset:

110h set register

114h clear register

Default:

0000 0000h

Reference:

1394 Open Host Controller Specification, Rev. 1.1, Section 5.14.2

Table 51. Physical Request Filter High Register Description

Bit Field Name Type

Description

31 physReqResourceAllBuses RSC If this bit is set, then all asynchronous requests received by the FW322

from nonlocal bus nodes are accepted. Set/Clear operations to this

register while the IntEvent.busReset bit (see Table 39) is asserted will

have no effect. A bus reset will not affect the value of the physReqRe-

sourceAllBuses bit.

30:0

physReqResourceN

RSC If this bit is set, requests received by the FW322 from local bus node N

(where N = bit number + 32) will be handled through the physical

request context. Set/Clear operations to this register while the

IntEvent.busReset bit (see Table 39) is asserted will have no effect. All

physReqResourceN bits will be cleared to zero when a bus reset

occurs.

Physical Request Filter Low Register

The Physical Request Filter Low set/clear register is used to enable physical receive requests on a per-node

basis and handle the lower-node IDs. When a packet is destined for the physical request context and the node ID

has been compared against the Asynchronous Request Filter registers, then the node ID comparison is done

again with this register. If the bit corresponding to the node ID is not set in this register, then the request is

handled by the asynchronous request context instead of the physical request context.

Offset:

118h set register

11Ch clear register

Default:

0000 0000h

Reference:

1394 Open Host Controller Specification, Rev. 1.1, Section 5.14.2

Table 52. Physical Request Filter Low Register Description

Bit Field Name Type

Description

31:0 physReqResourceN RSC If this bit is set, requests received by the FW322 from local bus node N

(where N = bit number) will be handled through the physical request context.

Set/Clear operations to this register while the IntEvent.busReset bit (see

Table 39) is asserted will have no effect. All physReqResourceN bits will be

cleared to zero when a bus reset occurs.

600

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Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Internal Registers (continued)

Asynchronous Context Control Register

The Asynchronous Context Control set/clear register controls the state and indicates status of the DMA context.

Offset:

180h

184h

1A0h

1A4h

1C0h

1C4h

1E0h

1E4h

set register (ATRQ)

clear register (ATRQ)

set register (ATRS)

clear register (ATRS)

set register (ARRQ)

clear register (ARRQ)

set register (ARRS)

clear register (ARRS)

Default:

0000 X0XXh

Reference:

1394 Open Host Controller Specification, Rev. 1.1, Section 7.22, 8.3.2, 3.1.1

Table 53. Asynchronous Context Control Register Description

Bit

Field Name

Type

Description

31:16

15

Reserved

run

R

Reserved. Bits 31:16 return 0s when read.

RSCU This bit is set by software to enable descriptor processing for the

context and cleared by software to stop descriptor processing. The

FW322 changes this bit (i.e., sets it to 0) only on a hardware or soft-

ware reset.

14:13

12

Reserved

wake

R

Reserved. Bits 14:13 return 0s when read.

RSU Software sets this bit to cause the FW322 to continue or resume

descriptor processing. The FW322 clears this bit on every descriptor

fetch.

11

dead

RU

The FW322 sets this bit when it encounters a fatal error and clears the

bit when software resets bit 15 (run).

10

9:8

7:5

active

RU

R

The FW322 sets this bit to 1 when it is processing descriptors.

Reserved

Reserved. Bits 9:8 return 0s when read.

spd

RU

This field indicates the speed at which a packet was received or trans-

mitted, and only contains meaningful information for receive contexts.

This field is encoded as:

(Note: These bits are

reserved, undefined

for the ATRQ and

ATRS contexts.)

000 = 100 Mbits/s.

001 = 200 Mbits/s.

010 = 400 Mbits/s.

All other values are reserved. Software should not attempt to interpret

the contents of this field while the active or wake bits are set.

4:0

eventcode

RU

This field holds the acknowledge sent by the link core for this packet or

an internally generated error code if the packet was not transferred

successfully.

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Data Sheet, Rev. 1

December 2005

Internal Registers (continued)

Asynchronous Context Command Pointer Register

The Asynchronous Context Command Pointer register contains a pointer to the address of the first descriptor block

that the FW322 accesses when software enables the context by setting the Asynchronous Context Control register

bit 15 (run).

Offset:

18Ch (ATRQ)

1ACh (ATRS)

1CCh(ARRQ)

1ECh (ARRS)

Default:

XXXX XXXXh

Reference:

1394 Open Host Controller Specification, Rev. 1.1, Sections 3.1.2, 7.2.1, 8.3.1

Table 54. Asynchronous Context Command Pointer Register Description

Bit

Field Name

Type

Description

31:4

descriptorAddress

RWU Contains the upper 28 bits of the address of a 16-byte aligned

descriptor block.

3:0

Z

RWU Indicates the number of contiguous descriptors at the address pointed

to by the descriptor address. If Z is 0, then it indicates that the descrip-

torAddress field (bits 31:4) is not valid. Valid values for z are context

specific. Refer to the OHCI specification for more details.

62

Agere Systems Inc.

Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Internal Registers (continued)

Isochronous Transmit Context Control (IT DMA ContextControl) Register

The Isochronous Transmit Context Control set/clear register controls options, state, and status for the

isochronous transmit DMA contexts. The n value in the following register addresses indicates the context number

(n = 0:7).

Offset:

200h + (16 * n) set register

204h + (16 * n) clear register

Default:

XXXX X0XXh

Reference:

1394 Open Host Controller Specification, Rev. 1.1, Sections 9.2, 3.1.1

Table 55. Isochronous Transmit Context Control Register Description

Bit

Field Name

Type

Description

31

cycleMatchEnable

RSCU When this bit is set to 1, processing occurs such that the packet

described by the context’s first descriptor block is transmitted in the

cycle whose number is specified in the cycleMatch field (bits 30:16).

The cycleMatch field (bits 30:16) must match the low-order 2 bits of

cycleSeconds and the 13-bit cycleCount field in the cycle start packet

that is sent or received immediately before isochronous transmission

begins. Since the isochronous transmit DMA controller may work

ahead, the processing of the first descriptor block may begin slightly in

advance of the actual cycle in which the first packet is transmitted. The

effects of this bit, however, are impacted by the values of other bits in

this register and are explained in the 1394 Open Host Controller Inter-

face Specification. Once the context has become active, hardware

clears this bit.

30:16

cycleMatch

RSC Contains a 15-bit value, corresponding to the low-order 2 bits of the

bus isochronous Cycle Time register cycleSeconds field (bits 31: 25)

and the cycleCount field (bits 24:12) (see Table 48). If bit 31

(cycleMatchEnable) is set, then this isochronous transmit DMA context

becomes enabled for transmits when the low-order 2 bits of the bus

Isochronous Cycle Timer register cycleSeconds field (bits 31:25) and

the cycleCount field (bits 24:12) value equal this field’s (cycleMatch)

value.

15

run

RSCU This bit is set by software to enable descriptor processing for the

context and cleared by software to stop descriptor processing. The

FW322 changes this bit only on a hardware or software reset.

14:13

12

Reserved

wake

R

Reserved. Bits 14:13 return 0s when read.

RSU Software sets this bit to cause the FW322 to continue or resume

descriptor processing. The FW322 clears this bit on every descriptor

fetch.

11

dead

RU

The FW322 sets this bit when it encounters a fatal error and clears the

bit when software resets bit 15 (run).

10

9:5

4:0

active

RU

R

The FW322 sets this bit to 1 when it is processing descriptors.

Reserved

event code

Reserved. Bits 9:5 return 0s when read.

RU

Following an OUTPUT_LAST* command, the error code is indicated in

this field. Possible values are ack_complete, evt_descriptor_read,

evt_data_read, and evt_unknown.

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Data Sheet, Rev. 1

December 2005

Internal Registers (continued)

Isochronous Transmit Context Command Pointer Register

The Isochronous Transmit Context Command Pointer register contains a pointer to the address of the first descrip-

tor block that the FW322 accesses when software enables an isochronous transmit context by setting the Isochro-

nous Transmit Context Control register bit 15 (run). The n value in the following register addresses indicates the

context number (n = 0:7).

Offset:

20Ch + (16 * n)

Default:

Reference:

XXXX XXXXh

1394 Open Host Controller Specification, Rev. 1.1, Sections 9.2.1, 3.1.2

Table 56. Isochronous Transmit Context Command Pointer Register Description

Bit

Field Name

Type

Description

31:4

descriptorAddress

RWU Address of the context program, which will be executed when a DMA

context is started. All descriptors are 16-byte aligned, so the four least

significant bits of any descriptor address must be zero.

3:0

Z

RWU Indicates how many physically contiguous descriptors are pointed to by

descriptorAddress.

644

Agere Systems Inc.

Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Internal Registers (continued)

Isochronous Receive Context Control (IR DMA ContextControl) Register

The Isochronous Receive Context Control set/clear register controls options, state, and status for the isochronous

receive DMA contexts. The n value in the following register addresses indicates the context number (n = 0:7).

Offset:

400h + (32 * n) set register

404h + (32 *n) clear register

Default:

X000 X0XXh

Reference:

1394 Open Host Controller Specification, Rev. 1.1, Sections 10.3, 3.1.2

Table 57. Isochronous Receive Context Control Register Description

Bit

Field Name

Type

Description

31

bufferFill

RSC When this bit is set, received packets are placed back-to-back to com-

pletely fill each receive buffer. When this bit is cleared, each received

packet is placed in a single buffer. If bit 28 (multiChanMode) is set to 1,

then this bit must also be set to 1. The value of this bit must not be

changed while bit 10 (active) or bit 15 (run) is set.

30

isochHeader

RSC When this bit is 1, received isochronous packets include the complete

4-byte isochronous packet header seen by the link layer. The end of the

packet is marked with an xferStatus in the first doublet, and a 16-bit

timeStamp indicating the time of the most recently received (or sent)

cycleStart packet. When this bit is cleared, the packet header is stripped

off of received isochronous packets. The packet header, if received,

immediately precedes the packet payload. The value of this bit must not

be changed while bit 10 (active) or bit 15 (run) is set.

29

28

cycleMatchEnable

multiChanMode

RSCU When this bit is set, the context begins running only when the 15-bit

cycleMatch field (bits 26:12) in the IRContext Match register (see Table

59) matches the two low-order bits of the CycleSeconds field and the

13-bit CycleCount field in the CycleTimer register. The effects of this bit,

however, are impacted by the values of other bits in this register. Once

the context has become active, hardware clears this bit. The value of this

bit must not be changed while bit 10 (active) or bit 15 (run) is set.

RSC When this bit is set, the corresponding isochronous receive DMA context

receives packets for all isochronous channels enabled in the Isochro-

nous Receive Channel Mask High and Isochronous Receive Channel

mask Low registers. The isochronous channel number specified in the

isochronous receive DMA Context Match register is ignored. When this

bit is cleared, the isochronous receive DMA context receives packets for

the channel number specified in the Context Match register. Only one

isochronous receive DMA context may use the Isochronous Receive

Channel Mask registers. If more than one Isochronous Receive Context

Control register has this bit set, then results are undefined. The value of

this bit must not be changed while bit 10 (active) or bit 15 (run) is set to 1.

27

dualBufferMode

Reserved

RSC When this bit is set, received packets are separated into first and second

payload and streamed independently to the first buffer series and second

buffer series (see OHCI v.1.1, 10.2.3). Both multiChanMode and buffer

fill must be programmed to zero when this bit is set. The value of

dualBufferMode will not be changed while active or run is set.

26:16

R

Reserved. Bits 26:16 return 0s when read.

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65

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Data Sheet, Rev. 1

December 2005

Internal Registers (continued)

Table 57. Isochronous Receive Context Control Register Description (continued)

Bit

Field Name

Type

Description

15

run

RSCU This bit is set by software to enable descriptor processing for the context

and cleared by software to stop descriptor processing. The FW322

changes this bit only on a hardware or software reset.

14:13

12

Reserved

wake

R

Reserved. Bits 14:13 return 0s when read.

RSU Software sets this bit to cause the FW322 to continue or resume descrip-

tor processing. The FW322 clears this bit on every descriptor fetch.

11

dead

RU

The FW322 sets this bit when it encounters a fatal error and clears the

bit when software resets bit 15 (run).

10

9:8

7:5

active

Reserved

spd

RU

R

The FW322 sets this bit to 1 when it is processing descriptors.

Reserved. Bits 9:8 return 0s when read.

RU

This field indicates the speed at which the packet was received.

000 = 100 Mbits/s.

001 = 200 Mbits/s.

010 = 400 Mbits/s.

All other values are reserved.

4:0

event code

RU

Following an INPUT_* command, the error or status code is indicated in

this field (see OHCI v.1.1, 10.3.2 and Table 3-2).

Isochronous Receive Context Command Pointer Register

The Isochronous Receive Context Command Pointer register contains a pointer to the address of the first

descriptor block that the FW322 accesses when software enables an isochronous receive context by setting the

Isochronous Receive Context Control register bit 15 (run). The n value in the following register addresses

indicates the context number (n = 0:7).

Offset:

40Ch + (32 * n)

Default:

Reference:

XXXX XXXXh

1394 Open Host Controller Specification, Rev. 1.1, Sections 10.3, 3.1.2

Table 58. Isochronous Receive Context Command Pointer Register Description

Bit

Field Name

Type

Description

31:4

descriptorAddress

RWU Address of the context program which will be executed when a DMA

context is started.

3:0

Z

RWU Indicates how many physically contiguous descriptors are pointed to by

descriptor address. In buffer full mode, Z will be either one or zero. In

packet-per-buffer mode, Z will be from zero to eight.

666

Agere Systems Inc.

Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Internal Registers (continued)

Isochronous Receive Context Match (IR DMA ContextMatch) Register

The Isochronous Receive Context Match register is used to control on which isochronous cycle the context should

start. The register is also used to control which packets are accepted by the context.

Offset:

410Ch + (32 * n)

Default:

Reference:

XXXX XXXXh

1394 Open Host Controller Specification, Rev. 1.1, Section 10.3. 3.

Table 59. Isochronous Receive Context Match Register Description

Bit

Field Name

Type

Description

31

tag3

RW

If this bit is set, then this context matches on iso receive packets with a

tag field of 11b.

30

29

28

tag2

tag1

tag0

RW

If this bit is set, then this context matches on iso receive packets with a

tag field of 10b.

If this bit is set, then this context matches on iso receive packets with a

tag field of 01b.

If this bit is set, then this context matches on iso receive packets with a

tag field of 00b.

27

Reserved

R

Reserved. Bit 27 returns a 0 when read.

26:12

cycleMatch

RW

Contains a 15-bit value, corresponding to the low-order 2 bits of cycle-

Seconds and the 13-bit cycleCount field in the cycleStart packet. If Iso-

chronous Receive Context Control register bit 29 (cycleMatchEnable)

is set, then this context is enabled for receives when the 2 low-order

bits of the Bus Isochronous Cycle Timer register cycleSeconds field

(bits 31:25) and cycleCount field (bits 24:12) value equal this field’s

(cycleMatch) value.

11:8

sync

RW

This field contains the 4-bit field, which is compared to the sync field of

each isochronous packet for this channel when the command descrip-

tor’s w field is set to 11b.

7

6

Reserved

R

Reserved. Bit 7 returns 0 when read.

tag1SyncFilter

RW

If this bit and bit 29 (tag1) are set, then packets with tag2’b01 are

accepted into the context if the two most significant bits of the packets

sync field are 00b. Packets with tag values other than 01b are filtered

according to tag0, tag2, and tag3 (bits 28, 30, and 31, respectively)

without any additional restrictions. If this bit is cleared, then this context

matches on isochronous receive packets as specified in bits 28:31

(tag0:tag3) with no additional restrictions. If the tag1SyncFilterLock bit

of the Link Control register is set, then this bit is read only and is set to

one by the OHCI.

5:0

channelNumber

RW

This 6-bit field indicates the isochronous channel number for which this

isochronous receive DMA context accepts packets.

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Data Sheet, Rev. 1

December 2005

Internal Registers (continued)

FW322 Vendor-Specific Registers

The FW322 contains a number of vendor-defined registers used for diagnostics and control of low-level hardware

functionality. These registers are addressable in the upper 2K of the 4K region defined by PCI Base Address

register 0 (registers defined by the OHCI specification reside in the lower 2K of this region). These registers are

also programmable via the serial EEPROM. These control registers should not be changed when the link is

enabled.

Table 60. FW322 Vendor-Specific Registers Description

Offset

Register Name

Description

12’h800

IsoDMACtrl

Controls PCI access for the isochronous DMA engines. Initial values

are loaded from serial EEPROM, if present (see Table 61 of this data

sheet).

12’h808

12’h840

AsyDMACtrl

LinkOptions

Controls PCI access and AT FIFO threshold for the asynchronous DMA

engines. Initial values are loaded from serial EEPROM, if present (see

Table 62 of this data sheet).

Controls low-level functionality of the link core. Initial values are loaded

from serial EEPROM, if present (see Table 63 of this data sheet).

Isochronous DMA Control

The fields in this register control when the isochronous DMA engines access the PCI bus and how much data they

will attempt to move in a single PCI transaction. The actual PCI burst sizes will also be affected by 1394 packet size,

host memory buffer size, FIFO constraints, and the PCI cache line size.

Offset:

800h

Default:

0000 7373h

Table 61. Isochronous DMA Control Registers Description

Bits

Field

Description

15:12

IT Maximum Burst The maximum number of quadlets that will be fetched by the IT DMA in

one PCI transaction. The maximum burst is 16 * (n + 1) quadlets;

n defaults to 7 (128 quadlets). Max value of n is 0xf.

11:8

IT Threshold

This field defines the amount of available space that is needed in the IT

FIFO, before the IT DMA will request access to the PCI bus. The

threshold is 16 * (n + 1) quadlets; n defaults to 3 (64 quadlets). Note,

however, that the IT DMA may request access to the PCI bus sooner if

the amount of data to be fetched from memory is less than the amount

of space available in the IT FIFO. Max value of n is 0xf.

7:4

3:0

IR Maximum Burst The maximum number of quadlets that will be written by the IR DMA in

one PCI transaction. The maximum burst is 16 * (n + 1) quadlets;

n defaults to 7 (128 quadlets). Max value of n is 0xf.

IR Threshold

This field defines the amount of available data that is needed in the IR

FIFO, before the IR DMA will request access to the PCI bus. The

threshold is 16 * (n + 1) quadlets; n defaults to 0 (16 quadlets). Note,

however, that the IR DMA may request access to the PCI bus sooner if

the amount of data available in the FIFO exceeds the space remaining

in the current host memory buffer or a complete packet resides in the

FIFO. Max value of n is 0xf.

688

Agere Systems Inc.

Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Internal Registers (continued)

Asynchronous DMA Control

The fields in this register control the functionality within the asynchronous and physical DMA engines. Accesses to

the PCI bus and how much data the DMA engines will attempt to move in a single PCI transaction can be con-

trolled. The actual PCI burst sizes will also be affected by 1394 packet size, host memory buffer size, FIFO con-

straints, and the PCI cache line size.

Offset:

808h

Default:

0010 7373h

Table 62. Asynchronous DMA Control Registers Description

Bits

Field

Description

24

Retry Threshold When this bit is set, a packet being retried, e.g., due to an ack_busy on the

Max. Enable

initial attempt, will behave as if the AT FIFO threshold value was set to the

maximum (n = 0x20). The purpose of this feature is to prevent a packet that

previously experienced a FIFO underrun on the initial transmit attempt from

failing again due to a FIFO underrun on the retry attempt. If this bit is not set,

retried packets will use the same AT FIFO threshold as the initial transmit

attempt. The default value of this field is 0x0.

23:16

AT FIFO Threshold This field defines the number of quadlets of packet data that must be available

in the AT FIFO before the link will be notified that there is an asynchronous

packet to be transmitted. (The link will also be signaled that a packet is available

for transmission if the entire packet is in the FIFO, regardless of its size.) The

threshold is 16 * n quadlets; n defaults to a value of 0x10 (256 quadlets). Max

size of n is 0x20 (512 quadlets).

15:12

11:8

AT Maximum Burst The maximum number of quadlets that will be fetched by the AT or physical

read response DMAs in one PCI transaction. The maximum burst is 16 * (n + 1)

quadlets; n defaults to 7 (128 quadlets). Max value of n is 0xf.

AT Threshold

This field defines the amount of available space that is needed in the AT FIFO,

before the AT or physical read response units will request access to the PCI

bus. The threshold is 16 * (n + 1) quadlets; n defaults to 0 (16 quadlets). Note,

however, that the AT or physical DMAs may request access to the PCI bus

sooner if the amount of data to be fetched from memory is less than the amount

of space available in the AT FIFO. Max value of n is 0xf.

7:4

3:0

AR Maximum Burst The maximum number of quadlets that will be written by the AR and physical

write DMAs in one PCI transaction. The maximum burst is 16 * (n + 1) quadlets;

n defaults to 7 (128 quadlets). Max value of n is 0xf.

AR Threshold

This field defines the amount of available data that is needed in the AR FIFO,

before the AR DMA will request access to the PCI bus. The threshold is

16 * (n + 1) quadlets; n defaults to 0 (16 quadlets). However, the AR DMA may

request access to the PCI bus sooner if the amount of data available in the

FIFO exceeds the space remaining in the current host memory buffer or a

complete packet resides in the FIFO. Max value of n is 0xf.

Agere Systems Inc.

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Data Sheet, Rev. 1

December 2005

Internal Registers (continued)

Link Options

The values in this register provide low-level control of configurable features within the FW322 that are beyond

those stated in 1394 and OHCI specifications.

Offset:

840h

Default:

0000 0020h

Table 63. Link Options Register Description

Bits

Field

Description

Enables general features of OHCI 1.1 that are not covered by any of the bits below.

Reserved for internal use by the FW322. Must be set to 0x0.

Enables RegAccessFailEn interrupt for SCLK register accesses that fail.

31

30

29

28

OHCI1.1En

Reserved

RegAccessFailEn

InitBMEnable

Enables usage of initial registers for loading Bus Management registers on a bus

reset.

Enables retry processing as defined in OHCI 1.1.

27

26

RetryEnable

Enables config ROM management, including config ROM block reads, as defined

in OHCI 1.1.

ConfigROMEnable

Enables IR dual-buffer mode processing as defined in OHCI 1.1

25

24

DualBufferEnable

ITChangeEnable

Enables skip and FIFO underrun processing in the IT context as defined in

OHCI 1.1.

Reserved for internal use by the FW322. Must be set to 0x0.

23

22

Reserved

Read-only status bit. Reserved for internal use by the FW322. Will read back as

0x0.

Reserved for internal use by the FW322. Must be set to 0x0.

21

Reserved

20

19:6

Reserved

5:3

Posted Writes

Number of physical posted writes the link is allowed to queue in the asynchronous

receive FIFO. These three bits [5:3] default to 100b, which is the maximum value.

Values greater than 100b will disable all physical posted writes.

2:0

Cycle Timer

Control

Selects the value the FW322 will use for its isochronous cycle period when the

FW322 is the root node. This value is for debugging purposes only and should not

be set to any value other than its default value in a real 1394 network. This value

defaults to 0.

If 0, cycle = 125 µs.

If 1, cycle = 62.5 µs.

If 2, cycle = 31.25 µs.

If 3, cycle = 15.625 µs.

If 4, cycle = 7.8125 µs.

700

Agere Systems Inc.

Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Internal Register Configuration

PHY Core Register Map

The PHY Core register map is shown below in Table 64.

Reference:

IEEE Standard 1394a-2000, Annex J2

Table 64. PHY Core Register Map

Address

Contents

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

R

Bit 7

PS

00002

00012

00102

00112

01002

01012

01102

01112

10002

Physical_ID

RHB

IBR

Extended (7)

Max_speed

Contender

ISBR

Gap_count

Total_ports

Delay

Pwr_class

Timeout Port_event Enab_accel Enab_multi

XXXXX

Jitter

LCtrl

Watchdog

Loop

Pwr_fail

XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX

Page_select

Port_select

XXXXX

Register 0 Page_select

11112

Register 7 Page_select

REQUIRED

RESERVED

XXXXX

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Data Sheet, Rev. 1

December 2005

Internal Register Configuration (continued)

PHY Core Register Fields

Table 65. PHY Core Register Fields

Field

Size

(In Bits)

Type PowerReset

Value

Description

Physical_ID

6

R

000000

The address of this node is determined during self-identification. A

value of 63 indicates a misconfigured bus; therefore, the link will not

transmit any packets.

R

1

R

0

When set to one, indicates that this node is the root.

PS

—

Cable Power Active. The PHY core sets this bit when cable power

measured at the connector is at least 7.5 V. The PHY core clears

this bit when the detectable voltage is below this value.

RHB

IBR

1

RW

0

Root Hold-Off Bit. When set to one, the force_root variable is

TRUE. This instructs the PHY core to attempt to become the root

during the next tree identify process.

Initiate Bus Reset. When set to one, instructs the PHY core to set

ibr TRUE and reset_time to RESET_TIME. These values, in turn,

cause the PHY core to initiate a bus reset without arbitration; the

reset signal is asserted for 166 µs. This bit is self-clearing.

Gap_count

6

RW

3F16

Used to configure the arbitration timer setting to optimize gap times

according to the topology of the bus. See Section 4.3.6 of IEEE

Standard 1394a-2000 for the encoding of this field.

Extended

Total_ports

Max_speed

3

4

3

R

7

2

This field has a constant value of seven, which indicates the

extended PHY Core register map.

The number of ports implemented by this PHY core. This count

reflects the number.

0102

Indicates the speed(s) this PHY core supports:

0002 = 98.304 Mbits/s.

0012 = 98.304 and 196.608 Mbits/s.

0102 = 98.304, 196.608, and 393.216 Mbits/s.

0112 = 98.304, 196.608, 393.216, and 786.43 Mbits/s.

1002 = 98.304, 196.608, 393.216, 786.432, and

1,572.864 Mbits/s.

1012 = 98.304, 196.608, 393.216, 786.432, 1,572.864, and

3,145.728 Mbits/s.

All other values are reserved for future definition.

Delay

LCtrl

4

1

R

0000

1

Worst-case repeater delay; total worst-case repeater delay = [144 +

(delay * 20)] ns.

RW

Link Active. Cleared or set by software to control the value of the L

bit transmitted in the node’s SelfID packet 0, which will be the logical

AND of this bit and LPS active.

Contender

Jitter

1

3

RW

R

See

Cleared or set by software to control the value of the C bit transmit-

description ted in the SelfID packet. Powerup reset value is 0.

000

The difference between the fastest and slowest repeater data delay

= [(Jitter + 1) * 20] ns.

Pwr_class

RW

See

Power Class. Controls the value of the pwr field transmitted in the

description SelfID packet. See Section 4.3.4.1 of IEEE Standard 1394a-2000 for

the encoding of this field. The PC2 pin determines the least signifi-

cant bit of the power reset value. The two most significant bits

default to a power reset value of 00.

722

Agere Systems Inc.

Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Internal Register Configuration (continued)

Table 65. PHY Core Register Fields (continued)

Field

Size Type Power Reset Value

Description

Watchdog

1

RW

0

When set to one, the PHY core will set Port_event to one if

resume operations commence for any port.

ISBR

1

RW

0

Initiate Short (Arbitrated) Bus Reset. A write of one to this bit

instructs the PHY core to set ISBR true and reset_time to

SHORT_RESET_TIME. These values, in turn, cause the PHY

core to arbitrate and issue a short bus reset. This bit is self-

clearing.

Loop

1

RW

0

1

Loop Detect. A write of one to this bit clears it to zero.

Pwr_fail

Cable Power Failure Detect. Set to one when the PS bit

changes from one to zero. A write of one to this bit clears it to

zero.

Timeout

1

RW

0

Arbitration State Machine Time-Out. A write of one to this bit

clears it to zero (see MAX_ARB_STATE_TIME).

Port_event

Port Event Detect. The PHY core sets this bit to one if any of

connected, bias, disabled, or fault change for a port whose

Int_enable bit is one. The PHY core also sets this bit to one if

resume operations commence for any port and watchdog bit is

one. A write of one to this bit clears it to zero.

Enab_accel

1

RW

0

Enable Arbitration Acceleration. When set to one, the PHY

core will use the enhancements specified in clause 4.4 of

1394a-2000 Specification. PHY core behavior is unspecified if

the value of Enab_accel is changed while a bus request is

pending.

Enab_multi

Page_select

1

3

RW

0

Enable Multispeed Packet Concatenation. When set to one,

the link will signal the speed of all packets to the PHY core.

000

Selects which of eight possible PHY Core register pages are

accessible through the window at PHY Core register addresses

10002 through 11112, inclusive.

Port_select

4

RW

0000

If the page selected by Page_select presents per-port informa-

tion, this field selects which port’s registers are accessible

through the window at PHY Core register addresses 10002

through 11112, inclusive. Ports are numbered monotonically

starting at zero, p0.

Agere Systems Inc.

73

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Data Sheet, Rev. 1

December 2005

Internal Register Configuration (continued)

The port status page is used to access configuration and status information for each of the PHY core’s ports. The

port is selected by writing zero to Page_select and the desired port number to Port_select in the PHY Core register

at address 01112. The format of the port status page is illustrated by Table 66 below; reserved fields are shown as

XXXXX. The meanings of the register fields in the port status page are defined as type RSC.

Table 66. PHY Core Register Page 0: Port Status Page

Address

Contents

Bit 3 Bit 4

Bit 0

Bit 1

Bit 2

Bit 5

Bit 6

Bias

Bit 7

10002

10012

10102

10112

11002

11012

11102

11112

AStat

Negotiated_speed

BStat

Int_enable

Child

Fault

Connected

Disabled

XXXXX XXXXX XXXXX

XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX

REQUIRED

RESERVED

XXXXX

744

Agere Systems Inc.

Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Internal Register Configuration (continued)

The meaning of the register fields in the port status page are defined by Table 67 below.

Table 67. PHY Core Register Port Status Page Fields

Field

Size Type Power Reset

Value

Description

AStat

2

R

—

TPA line state for the port:

002 = invalid.

012 = 1.

102 = 0.

112 = Z.

BStat

Child

2

1

R

—

0

TPB line state for the port (same encoding as AStat).

If this bit is equal to one, the port is a child; otherwise, a par-

ent. The meaning of this bit is undefined from the time a bus

reset is detected until the PHY core transitions to state T1:

child handshake during the tree identify process (see Section

4.4.2.2 in IEEE Standard 1394a-2000).

Connected

Bias

1

3

R

0

If equal to one, the port is connected.

If equal to one, incoming TPBIAS is detected.

If equal to one, the port is disabled.

Disabled

RW

R

0

Negotiated_speed

000

Indicates the maximum speed negotiated between this PHY

core port and its immediately connected port; the encoding is

the same as for the PHY Core Register Max_speed field (see

Table 65).

Int_enable

Fault

1

RW

0

Enable Port Event Interrupts. When set to one, the PHY

core will set Port_event to one if any of connected, bias, dis-

abled, or fault (for this port) change state.

Set to one if an error is detected during a suspend or resume

operation. A write of one to this bit clears it to zero.

Agere Systems Inc.

75

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Data Sheet, Rev. 1

December 2005

Internal Register Configuration (continued)

The vendor identification page is used to identify the PHY core’s vendor and compliance level. The page is

selected by writing one to Page_select in the PHY Core register at address 01112. The format of the vendor identi-

fication page is shown in Table 68; reserved fields are shown as XXXXX.

Table 68. PHY Core Register Page 1: Vendor Identification Page

Address

Contents

Bit 3 Bit 4

Compliance_level

Bit 0

Bit 1

Bit 2

Bit 5

Bit 6

Bit 7

10002

10012

10102

10112

11002

11012

11102

11112

XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX

Vendor_ID

Product_ID

REQUIRED

RESERVED

XXXXX

Note: The meaning of the register fields within the vendor identification page are defined by Table 69.

Table 69. PHY Core Register Vendor Identification Page Fields

Field

Size Type

Description

Compliance_level

8

r

Standard to which the PHY core implementation complies:

0 = not specified

1 = IEEE 1394a-2000

Agere’s FW322 compliance level is 1.

All other values reserved for future standardization.

Vendor_ID

Product_ID

24

r

The company ID or organizationally unique identifier (OUI) of the manufacturer

of the PHY core. Agere’s vendor ID is 00601Dh. This number is obtained from

the IEEE registration authority committee (RAC). The most significant byte of

Vendor_ID appears at PHY Core register location 10102 and the least significant

at 11002.

The meaning of this number is determined by the company or organization that

has been granted Vendor_ID. Agere’s FW322 PHY core product ID is 03236x16*.

The most significant byte of Product_ID appears at PHY Core register location

11012 and the least significant at 11112.

* x is a minor revision number of the FW322 06 T100 and may be any value from 0 hex to F hex.

Note: The vendor-dependent page provides access to information used in the manufacturing test of the FW322.

76

Agere Systems Inc.

Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Crystal Selection Considerations

The FW322 is designed to use an external 24.576 MHz parallel resonant fundamental mode crystal connected

between the XI and XO terminals to provide the reference for an internal oscillator circuit. The IEEE 1394a-2000

standard requires that FW322 have less than ±100 ppm total variation from the nominal data rate, which is directly

influenced by the crystal. To achieve this, it is recommended that an oscillator with a nominal 50 ppm or less fre-

quency tolerance be used.

The total frequency variation must be kept below ±100 ppm from nominal with some allowance for error introduced

by board and device variations. Trade-offs between frequency tolerance and stability may be made as long as the

total frequency variation is less than ±100 ppm.

Load Capacitance

The frequency of oscillation is dependent upon the load capacitance specified for the crystal, in parallel resonant

mode crystal circuits. Total load capacitance (CL) is a function of not only the discrete load capacitors, but also

capacitances from the FW322 board traces and capacitances of the other FW322 connected components. The val-

ues for load capacitors (CA and CB) should be calculated using this formula:

CA = CB = (CL – Cstray) × 2

CA

XI

RL

CB

XO

A

Where:

CL = load capacitance specified by the crystal manufacturer.

Cstray = capacitance of the board and the FW322, typically 2 pF—3 pF.

RL = load resistance; nominal value is 400 Ω; the best value to be used can be determined by customer testing.

Figure 7. Crystal Circuitry

Adjustment to Crystal Loading

The resistor (RL) in Figure 7 is recommended for fine-tuning the crystal circuit. The nominal value for this resistor is

approximately 400 Ω. A more precise value for this resistor is dependent on the specific crystal used. Please refer to

the crystal manufacturer’s data sheet and application notes to determine an appropriate value for RL. A more precise

value for this resistor can be obtained by placing different values of RL on a production board and using an oscillo-

scope to view the resultant clock waveform at node A for each resistor value. The desired waveform should have the

following characteristics: the waveform should be sinusoidal, with an amplitude as large as possible, but not greater

than 3.3 V or less than 0 V.

Crystal/Board Layout

The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency and minimizing

noise introduced into the FW322 PLL. The crystal and two load capacitors (CA + CB) should be considered as a unit

during layout. They should be placed as close as possible to one another, while minimizing the loop area created by

the combination of the three components. Minimizing the loop area minimizes the effect of the resonant current that

flows in this resonant circuit. This layout unit (crystal and load capacitors) should then be placed as close as possible

to the PHY XI and XO terminals to minimize trace lengths. Vias should not be used to route the XI and XO signals.

Agere Systems Inc.

77

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Data Sheet, Rev. 1

December 2005

Serial EEPROM Interface

The FW322 features an I²C compliant serial ROM interface that allows for the connection of an external serial

EEPROM. The interface provides a mechanism to store configurable data such as the global unique identification

(GUID) within an external EEPROM.

The interface consists of the ROM_AD and ROM_CLK pins. ROM_CLK is an output clock provided by the FW322

to the external EEPROM. ROM_AD is bidirectional and is used for serial data/control transfers between the FW322

and the external EEPROM.

The FW322 uses this interface to read the contents of the serial EEPROM in response to the first PCI reset after

powerup. The FW322 also makes the serial ROM interface visible to software through the OHCI defined GUID

ROM register. When the FW322 is operational, the GUID ROM register allows software to initiate reads to the

external EEPROM.

The FW322 EEPROM interface has a number of new and updated features that were not present in earlier

revisions of the chip:

1. Improved external interface timing.

2. OHCI soft reset and D3-to-D0 device state transition will not initiate an EEPROM load.

3. Retry of PCI/OHCI/vendor register accesses during an EEPROM load.

4. Load failure and quick EEPROM detection.

5. EEPROM cache.

6. Automatic update of the OHCI 1394 MiniROM field of the GUID_ROM register.

7. Additional EEPROM image formats.

For additional detail, refer to the FW322/FW323 06 EEPROM Interface and Start-Up Behavior Application Note.

ac Characteristics of Serial EEPROM Interface Signals

Table 70. ac Characteristics of Serial EEPROM Interface Signals

Symbol

Parameter

Min

Max

Unit

fROM_CLK

tPW_LOW

Frequency of Serial Clock

—

100

—

kHz

µs

Width of Serial Clock Pulse Low

Width of Serial Clock Pulse High

4.7

4.0

0.1

tPW_HIGH

tDATA_VALID

—

Time from When Serial Clock Transitions Low Until EEPROM

Returns Valid Data

4.5

µs

2

tFREE

Time I C Bus Must Be Idle Before a New Transaction Can Be

4.7

—

µs

Started

tHOLD_START FW322 Hold Time for a Valid Start Condition

tSETUP_START FW322 Setup Time for a Valid Start Condition

4.0

4.7

0

—

µs

ns

µs

ns

µs

ns

tHOLD_DATA

Data Out Hold Time for the FW322

—

tSETUP_DATA Data Out Setup Time for the FW322

200

—

tRISE_TIME

tFALL_TIME

Rise Time for Serial Clock and Data Out from the FW322

Fall Time for Serial Clock and Data Out from the FW322

1.0

300

—

tSETUP_STOP FW322 Setup Time for a Valid Stop Condition

tHOLD_EEPROM Data Out Hold Time for EEPROM

4.7

100

—

788

Agere Systems Inc.

Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

ac Characteristics (continued)

tPW_LOW

tPW_HIGH

tFALL_TIME

tRISE_TIME

tPW_LOW

ROM_CLK

tHOLD_START

tSETUP_STOP

tSETUP_DATA

tSETUP_START

tHOLD_DATA

ROM_AD IN

tDATA_VALID

tFREE

tHOLD_EEPROM

ROM_AD OUT

ROM_CLK: serial clock, ROM_AD: serial data I/O.

1313 (F) R.02

Figure 8. Bus Timing

ROM_CLK

ROM_AD

8TH BIT

WORD n

ACK

tWR(1)

STOP

START

ROM_CLK: serial clock, ROM_AD: serial data I/O.

1314 (F) R.02

Figure 9. Write Cycle Timing

ROM_AD

ROM_CLK

STABLE

CHANGE

ROM_CLK: serial clock, ROM_AD: serial data I/O.

1310 (F) R.02

Figure 10. Data Validity

Agere Systems Inc.

79

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Data Sheet, Rev. 1

December 2005

ac Characteristics (continued)

ROM_AD

ROM_CLK

START

STOP

ROM_CLK: serial clock, ROM_AD: serial data I/O.

1311 (F) R.02

Figure 11. Start and Stop Definition

ROM_CLK

DATA IN

1

8

9

DATA OUT

START

ACK

ROM_CLK: serial clock.

1312 (F) R.02

Figure 12. Output Acknowledge

800

Agere Systems Inc.

Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Solder Reflow and Handling

The FW322 has a moisture sensitivity classification of 3, which is determined in accordance with the standard IPC/

JEDEC J-STD-020, Revision A, titled Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Sur-

face Mount Devices. Handling of this device should be in accordance with standard IPC/JEDEC J-STD-033, titled

Standard for Handling, Packing, Shipping and Use of Moisture/Reflow Sensitive Surface Mount Devices.

Up to three reflows may be performed using a temperature profile that meets the requirements of Table 3 in stan-

dard IPC/JEDEC J-STD-020. The requirements of IPC/JEDEC J-STD-033 must be met. The maximum allowable

body temperature for the FW322 is 220 °C—225°C. This is the actual tolerance that Agere uses to test the devices

during preconditioning.

Absolute Maximum Voltage/Temperature Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-

lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess

of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended

periods can adversely affect device reliability.

Table 71. Absolute Maximum Ratings

Parameter

Supply Voltage Range

Symbol

Min

Max

Unit

VDD

VI

3.0

−0.5

0

3.6

VDD + 0.5

70

V

Input Voltage Range

Output Voltage Range at Any Output

Operating Free Air Temperature

Storage Temperature Range

VO

TA

V

°C

Tstg

–65

150

Agere Systems Inc.

81

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Data Sheet, Rev. 1

December 2005

Electrical Characteristics

Table 72. Analog Characteristics

Parameter

Supply Voltage

Test Conditions

Symbol

Min Typ Max Unit

Source power node

VDD—SP

VID—100

VID—200

VID—400

VID—ARB

VCM

3.0

142

3.3

—

3.6

260

V

Differential Input Voltage

Cable inputs, 100 Mbits/s operation

Cable inputs, 200 Mbits/s operation

Cable inputs, 400 Mbits/s operation

Cable inputs, during arbitration

mV

V

132

260

100

260

168

265

Common-mode Voltage

Source Power Mode

TPB cable inputs,

speed signaling off

1.165

2.515

TPB cable inputs,

S100 speed signaling on

VCM—SP—100

VCM—SP—200

VCM—SP—400

VCM

1.165

0.935

0.532

1.165

—

2.515

2.015

1.08

V

TPB cable inputs,

S200 speed signaling on

TPB cable inputs,

S400 speed signaling on

V

Common-mode Voltage

Nonsource Power Mode*

TPB cable inputs,

speed signaling off

V

TPB cable inputs,

S100 speed signaling on

VCM—NSP—100 1.165

VCM—NSP—200 0.935

VCM—NSP—400 0.532

V

TPB cable inputs,

S200 speed signaling on

V

TPB cable inputs,

S400 speed signaling on

V

Receive Input Jitter

Receive Input Skew

TPA, TPB cable inputs,

100 Mbits/s operation

—

89

ns

TPA, TPB cable inputs,

200 Mbits/s operation

0.5

TPA, TPB cable inputs,

400 Mbits/s operation

—

0.315 ns

Between TPA and TPB cable inputs,

100 Mbits/s operation

—

0.8

0.55

0.5

ns

Between TPA and TPB cable inputs,

200 Mbits/s operation

—

Between TPA and TPB cable inputs,

400 Mbits/s operation

—

ns

Positive Arbitration

Comparator Input

Threshold Voltage

—

VTH+

168

mV

Negative Arbitration

Comparator Input

Threshold Voltage

—

VTH−

–168

—

–89

mV

Speed Signal Input

Threshold Voltage

200 Mbits/s

400 Mbits/s

VTH—S200

VTH—S400

IO

45

266

–5

—

139

445

2.5

mV

mA

V

Output Current

TPBIAS outputs

At rated I/O current

—

TPBIAS Output Voltage

VO

1.665

—

2.015

76

Current Source for

ICD

µA

Connect Detect Circuit

* For a node that does not source power (see Section 4.2.2.2 in IEEE 1394-1995 Standard).

822

Agere Systems Inc.

Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Electrical Characteristics (continued)

Table 73. Driver Characteristics

Parameter

Test Conditions

Symbol

Min

Typ

Max

Unit

Differential Output Voltage

Off-state Common-mode Voltage

Driver Differential Current,

56 Ω load

Drivers disabled

VOD

VOFF

IDIFF

172

—

265

20

mV

mA

Driver enabled,

−1.05

1.05

TPA+, TPA−, TPB+, TPB−

speed signaling off*

Common-mode Speed Signaling

Current, TPB+, TPB−

200 Mbits/s speed

signaling enabled

ISP

−2.53

−8.1

—

−4.84

−12.4

mA

400 Mbits/s speed

signaling enabled

* Limits are defined as the algebraic sum of TPA+ and TPA− driver currents. Limits also apply to TPB+ and TPB− as the algebraic sum of driver

currents.

Table 74. Device Characteristics

Parameter

Supply Current:

Test Conditions

Symbol

Min

Typ

Max

Unit

D0, 2 Ports Active

D0, 1 Port Active

D0, No Ports Active

VDD = 3.3 V

IDD

—

112

97

78

—

mA

System in Standby

(suspend mode = S1)

VDD = 3.3 V PCI or

VDD = 3.3 Vaux

IDD

—

30

—

mA

System in Hibernate

VDD = 3.3 Vaux

IDD

—

1.3

—

mA

(suspend mode = S1 or S3) or

System in Standby

(suspend mode = S3)

High-level Output Voltage

Low-level Output Voltage

High-level Input Voltage

Low-level Input Voltage

IOH max, VDD = min

IOL min, VDD = max

CMOS inputs

VOH

VOL

VIH

VIL

II

VDD – 0.4

—

0.4

V

—

0.7 VDD

—

V

CMOS inputs

0.2 VDD

32

V

Pull-up Current,

RESETN Input

VI = 0 V

11

µA

* This IDD value may differ depending on the system board into which the FW322 06 T100 PCI add-in card is inserted.

Agere Systems Inc.

83

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Data Sheet, Rev. 1

December 2005

Timing Characteristics

Table 75. Switching Characteristics

Symbol

Parameter

Jitter, Transmit

Measured

Test Conditions Min

Typ Max Unit

—

TPA, TPB

—

0.15

ns

Transmit Skew

Between

±0.1

TPA and TPB

tr

tf

Rise Time, Transmit (TPA/TPB)

Fall Time, Transmit (TPA/TPB)

10% to 90%

RI = 56 Ω,

CI = 10 pF

—

1.2

ns

90% to 10%

RI = 56 Ω,

CI = 10 pF

Table 76. Clock Characteristics

Parameter

Symbol

Min

Typ

Max

Unit

MHz

External Clock Source Frequency

f

24.5735

24.5760

24.5785

84

Agere Systems Inc.

Data Sheet, Rev. 1

December 2005

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Outline Diagrams

100-Pin TQFP

Dimensions are in millimeters.

16.00

14.00

±

0.20

1.00 REF

PIN #1 IDENTIFIER ZONE

100

76

0.25

1

75

GAGE PLANE

SEATING PLANE

0.45/0.75

14.00

0.20

DETAIL A

±

16.00

0.20

±

25

51

26

50

0.106/0.200

DETAIL A

DETAIL B

1.40

± 0.05

0.19/0.27

1.60 MAX

SEATING PLANE

M

0.08

0.05/0.15

DETAIL B

0.50 TYP

5-2146 (F)

Ordering Information

Device Code

Package

100-Pin TQFP

100-Pin TQFP (lead-free)*^†

Comcode

FW322 06 T100

700067727

700067728

L-FW322 06 T100

* Lead free: No intentional addition of lead, and less than 1000 ppm.

† Agere Systems lead-free devices are fully compliant with the Restriction of Hazardous Substances (RoHS) directive that restricts the content

of six hazardous substances in electronic equipment in the European Union. Beginning July 1, 2006, electronic equipment sold in the Euro-

pean Union must be manufactured in accordance with the standards set by the RoHS directive.

Agere Systems Inc.

85

Microsoft and Windows are registered trademarks of Microsoft Corporation.

The FireWire logo is a trademark and MacOS is a registered trademark of Apple Computer, Inc.

IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.

Mini PCI is a registered trademark of PCI-SIG, Inc.

For additional information, contact your Agere Systems Account Manager or the following:

INTERNET:

E-MAIL:

Home: http://www.agere.com Sales: http://www.agere.com/sales

docmaster@agere.com

N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138

1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)

ASIA:

CHINA: (86) 21-54614688 (Shanghai), (86) 755-25881122 (Shenzhen), (86) 10-65391096 (Beijing)

JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6741-9855, TAIWAN: (886) 2-2725-5858 (Taipei)

Tel. (44) 1344 296 400

EUROPE:

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.

Agere, Agere Systems, and the Agere logo are registered trademarks of Agere Systems Inc.

December 2005

DS05-030CMPR-1 (Replaces DS05-030CMPR)


型号：	L-FW32206T100
厂家：	AGERE SYSTEMS
描述：	1394a PCI PHY/Link Open Host Controller 1394A PCI PHY /链接打开主机控制器外围集成电路数据传输控制器 PC 时钟
文件：	总86页 (文件大小：886K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

L-FW32206T100 [AGERE]

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