L7585G [AGERE]
Full-Feature,Low-Power SLIC and Switch; 全功能，低功耗SLIC和开关
| 型号： | L7585G |
| 厂家： | 
AGERE SYSTEMS |
| 描述： | Full-Feature,Low-Power SLIC and Switch |
| 文件： | 总22页 (文件大小：421K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
September 2001
L7585G Full-Feature, Low-Power SLIC and Switch
Features
Description
■ Low active power
The L7585G Full-Feature, Low-Power Subscriber
Loop Interface Circuit (SLIC) and Switch integrates
the battery feed, test access relay, and ringing relay
that are necessary to interface a codec to the tip and
ring of a subscriber loop into one low-power, low-cost
package. It is built using a 90 V complementary bipo-
lar (CBIC) process and a 320 V Bipolar-CMOS-
DMOS (BCDMOS) process. The device is available
in a 44-pin MQFP package.
■ Quiet tip/ring polarity reversal
■ Distortion-free on-hook transmission
■ 35 V to 60 V power supply operation
■ 14 operating states:
— Forward battery active
— Reverse battery active
— Ground start (3)
— Forward battery ring open
— Reverse battery ring open
— Reverse battery tip open
— High impedance
The device can be connected directly to the Agere
Systems Inc. T8531/T8536 16-Channel Programma-
ble Codec Chip Set without the need for any ac inter-
face components.
— Ringing (2)
— Low current (2)
— Disconnect
■ Self-test in all operating states
■ Independent, adjustable ac and dc parameters:
— Switchhook detector threshold
— Loop current limit
— dc feed resistance
— Termination impedance
■ Integrated ringing access relay
■ Integrated test-in relay
■ Integrated relay driver
■ Integrated ring trip detector
■ Thermal protection
■ 44-pin, metric quad flat package (MQFP)
Data Sheet
September 2001
L7585G Full-Feature, Low-Power SLIC and Switch
Table of Contents
Contents
Page
Figures
Page
Features ......................................................................1
Description...................................................................1
Architectural Diagram..................................................3
Pin Information ............................................................4
Operating States..........................................................7
Forward Battery Active State ....................................7
Ground Start/Tip Open State ....................................7
Ground Start/Tip Ground State.................................8
Forward Battery Ring Open State.............................8
Ringing States (2) .....................................................8
Disconnect State.......................................................8
Forward Battery Low-Current Active State ...............8
High-Impedance State ..............................................8
Reverse Battery Active State....................................8
Reverse Battery Tip Open State...............................8
Ground Start/Tip Amplifier State...............................9
Reverse Battery Ring Open State.............................9
Reverse Battery Low-Current Active State ...............9
Absolute Maximum Ratings (TA = 25 °C).....................9
Electrical Characteristics ...........................................10
On-State Switch V-I Characteristics ..........................17
Applications ...............................................................18
Tip/Ring Protection .................................................18
NDET Under Fault Conditions ................................18
Power, Clocking, and Layout ..................................18
Ring Trip .................................................................19
False On-Hook Transients......................................19
Application Diagram ..................................................20
Outline Diagram.........................................................21
44-Pin MQFP ..........................................................21
Ordering Information .................................................22
Figure 1. Architectural Diagram ................................. 3
Figure 2. 44-Pin Diagram (MQFP) ............................. 4
Figure 3. On-State Switch V-I Characteristics ......... 17
Figure 4. 16-Channel Line Card Solution ................ 20
Tables
Page
Table 1. Pin Descriptions ........................................... 5
Table 2. B0—B3 Input State Coding .......................... 7
Table 3. B4—B5 Input State Coding .......................... 7
Table 4. Operating Conditions and Powering .......... 10
Table 5. Ring Trip Detector ..................................... 10
Table 6. Battery Feed Characteristics ..................... 11
Table 7. Analog Signal Pins .................................... 12
Table 8. Transmission Characteristics .................... 13
Table 9. Data Interface and Logic (Logic Inputs
[CLK, NCS, and B0—B5] and
Outputs [NDET]) ........................................ 14
Table 10. Timing Requirements (CLK, B0—B5,
and NCS) ................................................. 14
Table 11. Relay Driver (RDO) ................................. 14
Table 12. Ringing Return Access Switch (SW1) ..... 15
Table 13. Test-In Access Switches
(SW3 and SW6) ....................................... 15
Table 14. Tip and Ring Break Switches
(SW2 and SW4) ....................................... 16
Table 15. Tip and Ring Feedback Switches
(SW2a and SW4a) ................................... 16
Table 16. Ringing Access Switch (SW5) ................. 17
2
Agere Communications Inc.
Data Sheet
September 2001
L7585G Full-Feature, Low-Power SLIC and Switch
Architectural Diagram
NCS B5 B4 B3 B2 B1 B0
AGND
VCCA
ITR
VITR
TXI
100 kΩ
+
–
+5 A
VTX
CLK
PARALLEL DATA LATCH
AND LOGIC
NPDAT
NPDAR
AAC
AX
NDET
VRTX
REF
IN
RD FB NRT
SW1—SW6
NLC
ITR/198
+5 A
RECTIFIER
GAIN = 3
OUT
2.4 V
REFERENCE
CONTROL
SWITCHHOOK
DETECTOR
+
–
50 µA
DCOUT
LCTH
FB
SW1
45 Ω
SW2a
4 kΩ
TRNG
TTI
RFT
20 Ω
SW3
45 Ω
–
RCVP
RCVN
PT
AT
ac
dc
SW2
ITR
ITR
+
25 Ω
TIP/RING
CURRENT
SENSE
VBAT
ac
NPDAT
INTERFACE
RFR
20 Ω
+
BUFFER
BUFFER
SW4
PR
AR
–
RTI
VBAT
NPDAR
SW6
SW4a
DCOUT
BUFFER
RSW
RING TRIP
DETECTOR
SW5
GTO
NRT
RRNG
FB1
FB2
dc
FEEDBACK
AND
RTS
BUFFER
CURRENT
LIMIT
RD
+5 A
RELAY
DRIVER
+5 D +10 V
VBAT
VBAT
75 µA
RDO
DGND VCCD
VSP
IPROG
DCR
CF2 CF1
VBAT BGND
12-3290.e(F)
Figure 1. Architectural Diagram
Agere Communications Inc.
3
Data Sheet
September 2001
L7585G Full-Feature, Low-Power SLIC and Switch
Pin Information
44 43 42 41 40 39 38 37 36 35 34
CF1
FB2
FB1
1
2
3
4
5
6
7
33
32
31
30
29
28
27
TXI
VITR
ITR
BGND
VBAT
BGND
VBAT
DGND
VCCD
B0
VBAT
VSP
NCS
8
26
25
24
23
CLK
B1
9
NDET
B2
10
11
DGND
B3
12 13 14 15 16 17 18 19 20 21 22
12-2571H (F)
Figure 2. 44-Pin Diagram (MQFP)
4
Agere Communications Inc.
Data Sheet
September 2001
L7585G Full-Feature, Low-Power SLIC and Switch
Pin Information (continued)
Table 1. Pin Descriptions
Pin Symbol Type
Name/Function
1
CF1
I/O Filter Capacitor 1. Connect a 0.22 µF, 100 V capacitor from this pin to pin CF2.
2
FB2
I
Forward Battery Slowdown 2. A capacitor from FB1 to AGND and from FB2 to AGND
will ramp the polarity reversal transition when quiet polarity reversal is required. If not
needed, the pin can be left open.
3
FB1
I
Forward Battery Slowdown 1. A capacitor from FB1 to AGND and from FB2 to AGND
will ramp the polarity reversal transition when quiet polarity reversal is required. If not
needed, the pin can be left open.
4
5
6
7
8
BGND
VBAT
VBAT
VSP
—
—
—
—
I
Battery Ground. Ground return for the battery (VBAT) supply.
Battery Supply. Negative high-voltage power supply.
Battery Supply. Negative high-voltage power supply.
+10 V Supply. +10 V bias supply for switch circuitry.
NCS
Not Channel Select. A low-to-high transition on this logic input stores the data on pins
B0—B5 into the input latches on the SLIC. When NCS is either high or low, the SLIC is
unaffected by data on pins B0—B5.
9
CLK
I
Clock. Clock input.
10
NDET
O
Not Detect. When low, this logic output indicates either a ring trip or an off-hook condition,
depending on the input state of the SLIC. If either the BCDMOS portion or CBIC portion
of this device enters thermal shutdown, NDET will be forced low.
11
12
DGND
RDO
—
O
Digital Ground. Ground return for VCCD and relay driver flyback current.
Relay Driver. This output drives an external relay. RDO is low (relay operated) when a
low input on B5 is latched into the SLIC.
13
14
RTS
I
Ring Trip Sense. Sense input for the ring trip detector.
RSW
O
Ring Lead Ringing Access Switch. Ringing relay connects this pin to pin RRNG. Con-
nect this pin to pin PR through a 500 Ω current-limiting resistor.
15
16
RRNG
PR
I
Ring Lead Ringing Supply. Connect this pin to the ringing supply.
I/O Protected Ring. The output of the ring driver and input to the transmit current sense cir-
cuit. Connect to the ring of the loop through overvoltage protection.
17
18
19
20
21
RTI
TTI
I
I
Ring Lead Test-In. Test-in relay connects this pin to PR. Connect RTI to the ring lead of
the test-in bus.
Tip Lead Test-In. Test-in relay connects this pin to PT. Connect TTI to the tip lead of the
test-in bus.
PT
I/O Protected Tip. The output of the tip driver and input to the transmit current sense circuit.
Connect to the tip of the loop through overvoltage protection.
TRNG
B5
O
I
Tip Lead Ringing Supply. Ringing relay connects this pin to PT. Connect TRNG to the
ringing supply return.
Bit 5. B0—B5 determine the state of the SLIC. See Operating States.
Note: On the printed-wiring board (PWB), make the leads to BGND and VBAT as wide as possible for thermal and electrical reasons. Also, max-
imize the amount of PWB copper on all leads connected to this device for the lowest operating temperature.
Agere Communications Inc.
5
Data Sheet
September 2001
L7585G Full-Feature, Low-Power SLIC and Switch
Pin Information (continued)
Table 1. Pin Descriptions (continued)
Pin Symbol Type
Name/Function
Bit 4. B0—B5 determine the state of the SLIC. See Operating States.
22
23
24
25
26
27
28
29
30
31
B4
B3
I
I
Bit 3. B0—B5 determine the state of the SLIC. See Operating States.
Bit 2. B0—B5 determine the state of the SLIC. See Operating States.
Bit 1. B0—B5 determine the state of the SLIC. See Operating States.
Bit 0. B0—B5 determine the state of the SLIC. See Operating States.
+5 V Digital dc Supply. +5 V supply for logic and switch circuitry.
Digital Ground. Ground return for VCCD.
B2
I
B1
I
B0
I
VCCD
DGND
VBAT
BGND
ITR
—
—
—
—
I
Battery Supply. Negative high-voltage power supply.
Battery Ground. Ground return for the battery (VBAT) supply.
Tip/Ring Current. A current output which is proportional to the differential current flowing
from tip to ring. Connect a resistor from this pin to VITR.
32
VITR
O
Tip/Ring Voltage Output. The voltage at this output is directly proportional to the differ-
ential tip/ring current. A resistor from this pin to ITR sets the gain.
33
34
TXI
I
Transmit ac Input. Connect a 0.1 µF capacitor from this pin to VITR.
VTX
O
Transmit ac Output Voltage. The ac voltage at this output is 7.2 times the ac voltage at
pin TXI. The dc voltage is equal to the dc voltage on pin VRTX.
35
36
37
VRTX
RCVP
RCVN
O
I
Transmit ac Reference Voltage. The dc voltage at this output (2.4 V nominal) is the dc
reference for the transmit signal output VTX.
Receive ac Signal Input (Noninverting). This high-impedance input controls the ac dif-
ferential voltage on tip and ring.
I
Receive ac Signal Input (Inverting). This high-impedance input controls the ac differen-
tial voltage on tip and ring.
38
39
40
AGND
VCCA
—
—
I
Analog Ground. Ground return for VCCA.
+5 V Analog dc Supply. +5 V supply for analog circuitry.
LCTH
Loop Closure Threshold Input. Connect a resistor to DCOUT to set the off-hook thresh-
old.
41
42
IPROG
I
Current-Limit Program Input. A resistor to DCOUT sets the dc current limit.
DCOUT
O
dc Output. This output is a voltage that is directly proportional to the differential
tip/ring current.
43
44
DCR
CF2
I
dc Resistance. Ground for dc feed resistance of 180 Ω, or short to DCOUT for 600 Ω. In-
termediate values can be set with a resistor divider from DCOUT to ground, the tap of which
is connected to DCR.
I/O Filter Capacitor 2. Connect a 0.1 µF, 100 V capacitor from this pin to AGND and a
0.22 µF, 100 V capacitor from this pin to pin CF1.
Note: On the printed-wiring board (PWB), make the leads to BGND and VBAT as wide as possible for thermal and electrical reasons. Also, max-
imize the amount of PWB copper on all leads connected to this device for the lowest operating temperature.
6
Agere Communications Inc.
Data Sheet
L7585G Full-Feature, Low-Power SLIC and Switch
Forward Battery Active State
September 2001
Operating States
The L7585 has 14 operating states. These states are
selected using 4 bits, B0—B3, according to the truth
table shown in Table 2. The operation of the L7585 is
undefined for unassigned states. Additionally, bit B4
independently operates the test-in access contacts so
that all states are available for self-test; and bit B5
independently operates a relay driver, regardless of the
status of bits B0—B4. All 6 bits are loaded via the par-
allel data interface and chip select lead NCS.
■ Normal talk and forward battery feed state.
■ All circuits are powered up and active.
■ Pin PT is positive with respect to pin PR (forward bat-
tery).
■ SW2, SW2a, SW4, and SW4a closed; SW1, SW3,
SW5, and SW6 open.
■ NDET reflects the status of the switchhook detector.
Table 2. B0—B3 Input State Coding
Ground Start/Tip Open State
B3 B2 B1 B0
State
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Forward Battery Active
Ground Start/Tip Open
Ground Start/Tip Ground
Forward Battery Ring Open
Ringing (Battery Backed)
Disconnect State
■ Ground start idle supervision state.
■ Ring lead continuity test state (tone injected at the
receive port) in forward battery.
■ Same as forward battery active state, but with SW2
and SW2a open, and the tip drive amplifier powered
down.
Forward Battery Low-Current
Active State
■ Pin PT is high impedance (>100 kΩ).
■ The ring current limit is approximately equal to the
value programmed for the high-current active state
current limit. Current limit is achieved by reducing the
ring lead voltage only (see Table 6).
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
High Impedance
Reverse Battery Active
Reverse Battery Tip Open
Ground Start/Tip Amplifier
Reverse Battery Ring Open
Ringing (Earth Backed)
Unassigned
■ NDET indicates an off-hook when the ring current
(flowing into PR) is twice the value programmed for
the switchhook detector in the forward battery active
state.
Reverse Battery Low-Current
Active State
0
0
0
0
High Impedance
Table 3. B4—B5 Input State Coding
Bit
State
B4
B5
1
0
Test-in contacts off.
Test-in contacts on.
1
0
Relay driver off.
Relay driver on.
Agere Communications Inc.
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Data Sheet
September 2001
L7585G Full-Feature, Low-Power SLIC and Switch
Forward Battery Low-Current Active State
Operating States (continued)
Ground Start/Tip Ground State
■ Ground start busy supervision state.
■ Normal talk and forward battery feed state.
■ All circuits are powered up and active.
■ Pin PT is positive with respect to pin PR (forward bat-
tery).
■ Same as ground start/tip open state but with SW1
closed.
■ SW2, SW2a, SW4, and SW4a closed; SW1, SW3,
SW5, and SW6 open.
Forward Battery Ring Open State
■ NDET reflects the status of the switchhook detector.
■ Current limit is lowered to approximately 0.66 times
the normal limit.
■ Tip lead continuity test state (tone injected at the
receive port) in forward battery.
■ Same as forward battery active state, but with SW4
and SW4a open, and the ring drive amplifier
powered down.
High-Impedance State
■ Disconnect state.
■ Pin PR is high impedance (>100 kΩ).
■ Tip and ring drive amplifiers are powered down (all
bias currents off).
■ Tip current limit is twice the low-current active state
current limit.
■ Pins PT and PR are high impedance (>100 kΩ).
■ NDET indicates an off-hook when the tip current
(flowing out of PT) is twice the value programmed for
the switchhook detector in the forward battery active
state.
■ SW1, SW2, SW2a, SW3, SW4, SW4a, SW5, and
SW6 open.
■ NDET is undefined.
Ringing States (2)
Reverse Battery Active State
■ Normal ringing state.
■ Normal talk and reverse battery feed state.
■ Tip and ring drive amplifiers are powered down.
■ Same as forward battery active state, but PR is posi-
tive with respect to PT.
■ SW1 and SW5 closed; SW2, SW2a, SW3, SW4,
SW4a, and SW6 open.
■ NDET reflects the status of the ring trip detector.
Reverse Battery Tip Open State
■ Bit B3 indicates whether the ringing voltage applied
to the ringing bus is either battery backed (B3 = 1) or
earth backed (B3 = 0). Although B3 has no direct
effect on the state of the SLIC, it can be used by the
ring trip detector to enhance ring trip detection.
■ Ring lead continuity test state (tone injected at the
receive port) in reverse battery.
■ SW2 and SW2a open and the tip drive amplifier pow-
ered down.
■ Pin PT is high impedance (>100 kΩ).
Disconnect State
■ Pin PR is held between –1.7 V and –2.3 V for PR
currents less than ±20 mA. PR current limit is the
SW4 break switch current limit (250 mA < I < 85 mA).
■ All circuits are powered up and active.
■ SW2, SW2a, SW4, and SW4a closed; SW1, SW3,
■ NDET indicates an off-hook when the ring current
(flowing out of PR) is twice the value programmed for
the switchhook detector in the reverse battery active
state.
SW5, and SW6 open.
■ PT and PR are at the same potential to deny current
to the loop.
8
Agere Communications Inc.
Data Sheet
September 2001
L7585G Full-Feature, Low-Power SLIC and Switch
Operating States (continued)
Absolute Maximum Ratings (TA = 25 °C)
Stresses exceeding the values listed under absolute
maximum ratings may cause permanent damage to the
device. This is an absolute stress rating only. Func-
tional operation of the device at these or any other con-
ditions in excess of those indicated in the operational
sections of this data sheet is not implied. Exposure to
absolute maximum rating conditions for extended peri-
ods of time may adversely affect device reliability.
Ground Start/Tip Amplifier State
■ Current limiting is achieved by reducing ring lead
voltage only. This state is the same as Ground Start/
Tip Open, but with SW2 and SW2A closed and the
tip amplifier powered up.
■ Ring lead current limit is approximately the difference
of the high-current active state limit and the current
flowing out of the tip lead.
Parameter
Value
Unit
+5 V dc Supplies (VCCA and
VCCD)
–0.5 to +7.0
V
■ On-hook transmission not to exceed –3 dBm with up
to 5 mA flowing out of the tip lead (maximum current
flow into the tip lead is permissible). Larger signal
and/or current may cause distortion.
+10 V dc Bias Supply (VSP)
Office Battery Supply (VBAT)
Logic Input Voltage
–0.5 to +15
–63 to +0.5
V
V
V
–0.5 to
VDDD + 0.5
■ NDET indicates an off-hook when the current flowing
out of the tip plus the current flowing into the ring is
twice the value programmed for the switchhook
detector.
Logic Input Clamp Diode Cur-
rent, per Pin
±20
mA
V
Logic Output Voltage
–0.5 to
VDDD + 0.5
Reverse Battery Ring Open State
Logic Output Current, per Pin
(excluding relay driver)
±35
mA
■ Tip lead continuity test state (tone injected at the
receive port) in reverse battery.
Operating Temperature Range –40 to +125
°C
°C
Storage Temperature Range
Relative Humidity Range
–40 to +125
5 to 95
±3
■ Same as reverse battery active state, but with SW4
and SW4a open, and the ring drive amplifier
powered down.
%RH
V
Ground Potential Difference
(BGND to AGND)
■ Pin PR is high impedance (>100 kΩ).
Ground Potential Difference
(DGND to AGND)
±3
V
■ Tip current limit is twice the low-current active state
current limit.
Note: Analog voltages are referenced to AGND, digital (logic) volt-
ages are referenced to DGND, and battery voltages are ref-
erenced to BGND. The IC can be damaged unless all
ground connections are applied before and are removed
after all other connections. Furthermore, when powering the
device, the user must guarantee that no external potential
creates a voltage on any pin of the device that exceeds the
device ratings. Some of the known examples of conditions
that cause such potentials during powering are the following:
1) an inductor connected to tip and ring that can force an
overvoltage on VBAT through external components if the
VBAT connection chatters; and 2) inductance in the VBAT
lead that could resonate with the VBAT filter capacitor to
cause a destructive overvoltage.
■ NDET indicates an off-hook when the tip current
(flowing into PT) is twice the value programmed for
the switchhook detector in the reverse battery active
state.
Reverse Battery Low-Current Active State
■ Normal talk and reverse battery feed state.
■ Same as forward battery active state, but PR is posi-
tive with respect to PT.
■ Current limit is lowered to approximately 0.66 times
the normal limit.
Agere Communications Inc.
9
Data Sheet
September 2001
L7585G Full-Feature, Low-Power SLIC and Switch
Electrical Characteristics
In general, minimum and maximum values are testing requirements. However, some parameters may not be
tested in production because they are guaranteed by design and device characterization. Typical values reflect the
design center or nominal value of the parameter; they are for information only and are not a requirement. Minimum
and maximum values apply across the entire temperature range (–40 °C to +85 °C) and entire battery range
(–35 V to –60 V). Unless otherwise specified, typical is defined as 25 °C, VCCA = +5.0 V, VCCD = +5.0 V,
VSP = +10 V, VBAT = –48 V. Positive currents flow into the device.
Table 4. Operating Conditions and Powering
Parameter
Min
–40
5
Typ
—
Max
85
Unit
°C
Temperature Range
Humidity Range
—
95*
%RH
Supply Voltages:
VCCA
4.75
4.75
8.0
–35
—
5.0
5.0
10
–48
—
5.5
5.5
12.0
–60
±0.5
±0.25
V
V
V
V
V
V
VCCD
VSP
VBAT
VCCA—VCCD
DGND—AGND
—
—
Supply Currents (all states, no loop current):
ICCA + ICCD (+5 V)
—
—
—
4.9
45
–3.1
7.0
200
–4.0
mA
µA
mA
IVSP (+10 V)
IBAT (–48 V)
Total Power Dissipation (all states, no loop current)
—
175
200
mW
(VCC = +5 V; VSP = +10 V; VBAT = –48 V)
Power Supply Rejection (tip/ring and transmit)†:
VCCA (500 Hz—3 kHz; 50 mVrms ripple)
VCCD (500 Hz—3 kHz; 50 mVrms ripple)
VSP (500 Hz—3 kHz; 250 mVrms ripple)
VBAT (500 Hz—3 kHz; 50 mVrms ripple)
30
45
45
45
40
—
—
—
—
—
—
—
dB
dB
dB
dB
Thermal†:
—
—
—
—
47
155
°C/W
°C
Thermal Resistance (still air)
Operating TJC
* Not to exceed 26 grams of water per kilogram of dry air.
† This parameter is not tested in production; it is guaranteed by design and device characterization.
Table 5. Ring Trip Detector
Parameter
Min
±2.5
±12
Typ
±3
Max
Unit
Voltage at input that will cause ring trip after appropriate zero crossings.
Voltage at input that will cause immediate ring trip.
±3.5
±18
V
V
±15
Ringing Source1:
Frequency (f)
dc Voltage
19
–39.5
60
20
—
—
28
–57
105
Hz
V
Vrms
ac Voltage
Ring Trip (NDET = 0)2, 3
:
2000
—
—
—
—
—
—
200
80
Ω
ms
ms
Loop Resistance
Trip Time
NDET Valid
1. The ringing source may be either of the following:
a) The ringing source consists of the ac and dc voltages added together (battery-backed ringing); the ringing return is ground. In this case,
bit B3 will always be a 1 when ringing is applied.
b) The ringing source consists of only the ac voltage (earth-backed ringing); the ringing return is the dc voltage. In this case, bit B3 will
always be a 0 when ringing is applied.
2. NDET must also indicate ring trip when the ac ringing voltage is absent (<5 Vrms) from the ringing source.
3. Pretrip ringing must not be tripped by a 10 kΩ resistor in parallel with an 8 µF capacitor applied across tip and ring.
10
Agere Communications Inc.
Data Sheet
September 2001
L7585G Full-Feature, Low-Power SLIC and Switch
Electrical Characteristics (continued)
Table 6. Battery Feed Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Tip or Ring Drive Current =
dc + Longitudinal + Signal Currents
—
65
—
—
mA
ac Signal Current
Longitudinal Current Capability per Wire1
—
—
10
—
—
—
mArms
mArms
8.5
15
dc Loop Current Limit2 (RLOOP = 100 Ω):
Programmability Range
ILIM
5
—
45
56
mA
mA
Current Limit with VBAT = –51.5 V
and RPROG = 64.9 kΩ
44
42
Low-current Mode2 (RLOOP = 100 Ω,
VBAT = –51.5 V, and RPROG = 64.9 kΩ)
Ground Start Ring Grounded (RLOOP = 100 Ω)
25
27.5
30
mA
Current Limit3:
VBAT = –51.5 V, RPROG = 64.9 kΩ
Loop Closure Current Detector Threshold4
Programming Accuracy
38
—
43
—
47
±7
mA
%
ILCD
—
Open Loop Voltages (DCR = 0 V):
Common-mode Voltage
Differential Voltage
—
(VBAT + 1.8)/2
—
V
V
|VBAT + 7.0| |VBAT + 6.5| |VBAT + 6.0|
Disconnect State PT/PR Voltage
|PT-PR|
—
—
—
±100
mV
Ground Start Ring Lead Open or Shorted to Ground:
PT and CF1 Voltage
–1.7
–2.0
–2.3
V
dc Feed Resistance:
DCR Grounded
—
—
130
480
150
505
170
630
Ω
Ω
5
DCR Connected to DCOUT
dc Gains:
PT/PR Current to DCOUT Voltage6:
Forward Battery
–118
118
3.13
—
—
3.33
–132
132
3.53
V/A
V/A
—
Reverse Battery
DCR Voltage7 to PT/PR Differential Voltage
Loop Resistance Range8
(3.17 dBm overload into 600 Ω):
ILOOP = 20 mA at VBAT = –51.5 V
—
—
—
1890
1930
—
Ω
®
Longitudinal to Metallic Balance—IEEE Std. 455:
589
48
70
66
—
—
dB
dB
50 Hz to 1 kHz
1 kHz to 3 kHz
Metallic to Longitudinal (harm) Balance:
200 Hz to 4 kHz
35
—
—
dB
1. The longitudinal current is independent of dc loop current.
2. Current limit, ILIM, is programmed by a resistor, RPROG, from pin IPROG to pin DCOUT. RPROG = 1.667 x (ILIM – 4); RPROG in kΩ and ILIM
in mA. The current limit versus loop voltage has a slope of 10 kΩ. The low-current mode current limit is approximately 0.66 times the high
current limit. The ground start ring lead ground current limit is approximately equal to the high current limit and has a slope of about 5 kΩ.
3. In transmission applications, for compliance with TR-57, ground start ring lead I-V characteristics at high battery, it is expected that the
high-current active current limit will be set to 28 mA.
4. Loop closure detector current, ILCD, is programmed by a resistor, RLCTH, from pin LCTH to pin DCOUT. RLCTH = 2.5 x ILCD; RLCTH in
kΩ and ILCD in mA. ILCD is the tip to ring (forward battery) or ring to tip (reverse battery) current at which the loop closure detector indi-
cates an off-hook.
5. dc feed resistance may be adjusted between 180 Ω and 600 Ω using a resistor divider between DCOUT and DCR. The open loop differen-
tial voltage may also be increased by applying a negative voltage to pin DCR. See dc Gains, pin DCR.
6. DCOUT gain depends on the resistor RGX1 from pin VITR to pin ITR. This gain assumes 8250 Ω, the recommended value. Positive cur-
rent is defined as the differential current flowing from PT to PR.
7. Positive voltage on pin DCR has no effect on the PT/PR voltage.
8. At tip and ring, assuming 82.5 Ω protection resistors.
9. At tip and ring with matched 82.5 Ω protection resistors when feedback is connected for either 600 Ω or 900 Ω termination impedance.
Agere Communications Inc.
11
Data Sheet
September 2001
L7585G Full-Feature, Low-Power SLIC and Switch
Electrical Characteristics (continued)
Table 7. Analog Signal Pins
Parameter
Min
Typ
Max
Unit
DCOUT:
Output Offset (no loop current)
Output Drive Current
Output Voltage Swing (+0.25 mA/–3 mA load):
Maximum
—
0.25
—
—
±200
–3.0
mV
mA
VBAT
–10
—
5
—
—
—
—
—
—
VCCA
0.5
±20
—
V
V
mA
kΩ
pF
Minimum
Output Short-circuit Current
Output Load Resistance
Output Load Capacitance1
50
VITR and VTX:
Output Offset (no loop current)2
Output Drive Current
Output Voltage Swing (±1 mA load):
Maximum
—
±1
—
—
±100
—
mV
mA
–10
±3.5
–3.5
—
4
—
—
—
—
—
—
—
VCCA
V
V
V
mA
kΩ
pF
—
VCCA – 1.0
±20
Minimum (VITR)
Minimum (VTX)
Output Short-circuit Current
Output Load Resistance
Output Load Capacitance1
—
50
VRTX:
Output Voltage
2.2
±500
—
2.4
—
—
—
2.6
—
±15
50
V
Output Drive Current
Output Short-circuit Current
Output Load Capacitance1
µA
mA
pF
—
RSW:
Impedance to Ground
3
—
—
MΩ
DCR:
Input Voltage Range3
Input Bias Current
Input Impedance
–8
—
500
—
—
—
0
±1
—
V
µA
kΩ
TXI:
Input Impedance
Input Voltage Compliance
Input Clamp Voltage
75
±0.4
±0.4
—
—
—
—
—
±0.8
kΩ
V
V
RCVP and RCVN:
Input Voltage Range
Input Bias Current
Input Impedance
–2.5
—
10
—
—
—
VCCA
±1.5
—
V
µA
MΩ
PT and PR:
Overvoltage (from external source; continuous)
—
—
±265
V
FB1 and FB2:
ac Output Impedance
Output Short-circuit Current
—
±27
—
—
10
±34
kΩ
µA
CF1 and CF2:
Output Impedance1
180
—
375
kΩ
1. This parameter is not tested in production; it is guaranteed by design and device characterization.
2. VTX offset is measured with respect to pin VRTX.
3. Positive voltages from 0 V to VCCA are permitted at input DCR; however, voltages above 0 V have no effect on either the dc feed resis-
tance or tip/ring voltage.
12
Agere Communications Inc.
Data Sheet
September 2001
L7585G Full-Feature, Low-Power SLIC and Switch
Electrical Characteristics (continued)
Transmit direction is tip/ring to VTX. Receive direction is RCVP(N) to tip/ring.
Table 8. Transmission Characteristics
Parameter
ac Termination Impedance1
Return Loss2:
200 Hz—500 Hz
Min
Typ
Max
Unit
200
—
1200
Ω
25
29
—
—
—
—
dB
dB
500 Hz—3400 Hz
Total Harmonic Distortion (200 Hz—4 kHz)3:
—
—
—
—
0.3
1
%
%
Off-hook
On-hook
Transmit Gain (f = 1 kHz)4:
–291
1.94
–300
2
–309
2.06
V/A
—
PT/PR Current to (VTX—VRTX)
Receive Gain (f = 1 kHz):
(RCVP—RCVN) to (PT—PR)
Gain vs. Frequency (transmit and receive)3
(600 Ω termination; 1 kHz reference):
200 Hz—300 Hz
–0.3
–0.05
–3.0
—
0
0
0
0.05
0.05
0.05
2.0
dB
dB
dB
dB
300 Hz—3.4 kHz
3.4 kHz—20 kHz
20 kHz—266 kHz
—
Gain vs. Level (transmit and receive; 0 dBV reference)3:
–50 dB to +3 dB
–0.05
0
0.05
dB
Transhybrid Loss2:
200 Hz—500 Hz
500 Hz—3400 Hz
25
29
—
—
—
—
dB
dB
Idle-channel Noise (tip/ring; 600 Ω termination):
Psophometric
C-message
3 kHz Flat
—
—
—
—
—
—
–77
13
20
dBmp
dBrnC
dBrn
Idle-channel Noise ((VTX—VRTX); 600 Ω termination):
Psophometric
C-message
3 kHz Flat
—
—
—
—
—
—
–77
13
20
dBmp0
dBrnC0
dBrn0
EMC, per EN 300 386-2 and EN61000-4-6 (3 Vrms, 80% mod-
ulation, 105 kHz—80 MHz, 150 Ω source impedance)3
—
—
–40
dBm, 600 Ω
1. Set by external components in conjunction with the T7531A/T7536 codecs. Any complex impedance R1 + R2 || C between 200 Ω and
1200 Ω can be synthesized.
2. Return loss and transhybrid loss are functions of device gain accuracies and the external hybrid circuit. Guaranteed performance assumes
1% tolerance external resistors and capacitors.
3. This parameter is not tested in production; it is guaranteed by design and device characterization.
4. VTX gain depends on the resistor RGX1 from pin VITR to pin ITR. This gain assumes an ideal 8250 Ω, the recommended value. Positive cur-
rent is defined as the differential current flowing from PT to PR. The transmit signal at VTX is measured with respect to pin VRTX.
Agere Communications Inc.
13
Data Sheet
September 2001
L7585G Full-Feature, Low-Power SLIC and Switch
Electrical Characteristics (continued)
Table 9. Data Interface and Logic (Logic Inputs [CLK, NCS, and B0—B5] and Outputs [NDET])
Parameter1
High-level Input Voltage
Symbol
VIH
Min
Max
VCCD
0.8
Unit
V
2
Low-level Input Voltage
VIL
0
V
Input Bias Current (high and low)
High-level Output Voltage (IOUT = –100 µA)
Low-level Output Voltage (IOUT = 180 µA)
Output Short-circuit Current (VOUT = VCCD)
Output Load Capacitance2
IIN
—
±10
VCCD
0.4
µA
V
VOH
VOL
IOSS
COL
VCCD – 1.5
0
1
0
V
35
mA
pF
50
1. Unless otherwise specified, all logic voltages are referenced to DGND.
2. This parameter is not tested in production; it is guaranteed by design and device characterization.
Table 10. Timing Requirements (CLK, B0—B5, and NCS)1, 2
Parameter
Symbol
tR, tF
CIN
Min
0
Max
50
5
Unit
ns
CLK and NCS Rise and Fall Time (10% to 90%)
Maximum Input Capacitance
—
pF
Minimum Setup Time from B0—B5 Valid to NCS
VIH = 2 V
VIH = 2.5 V
tSDS
tSDS
250
150
—
—
ns
ns
Minimum Hold Time from NCS to B0—B5 Not Valid
VIH = 2 V
VIH = 2.5 V
tHDS
tHDS
150
10
—
—
ns
ns
Minimum Pulse Width of NCS
CLK Frequency
tWCS
fCLK
195
0.9
—
2.2
—
ns
MHz
ns
Minimum Pulse Width of CLK
tWCK
195
1. Unless otherwise specified, all times are measured from the 50% point of logic transitions.
2. These parameters are not tested in production; they are guaranteed by design and device characterization.
Table 11. Relay Driver (RDO)
Parameter1
Off-state Output Current (VRDO = VCCD)
On-state Output Voltage (IRDO = 40 mA)
On-state Output Voltage (IRDO = 20 mA)
Clamp Diode Reverse Current (VRDO = 0)
Clamp Diode On Voltage (IRDO = 80 mA)
Turn-on Time2
Symbol
IOFF
VON
VON
IR
Min
—
0
Max
±10
0.60
0.40
±10
20
Unit
µA
V
0
V
—
6
µA
V
VOC
tON
—
—
10
µs
µs
Turn-off Time2
tOFF
10
1. Unless otherwise specified, all logic voltages are referenced to DGND.
2. This parameter is not tested in production; it is guaranteed by design and device characterization.
14
Agere Communications Inc.
Data Sheet
September 2001
L7585G Full-Feature, Low-Power SLIC and Switch
Electrical Characteristics (continued)
Table 12. Ringing Return Access Switch (SW1)
Parameter
Min
Typ
Max
Unit
Off-state:
±3201
±10
15
Maximum Differential Voltage
dc Leakage Current (VSW = ±320 V)
Feedthrough Capacitance2
—
—
—
—
—
—
V
µA
pF
On-state (See On-State Switch V-I Characteristics section.):
Resistance (RON)
—
—
120
200
120
2
45
—
—
—
220
90
3201
—
—
360
—
Ω
V
V
V
mA
Maximum Differential Voltage (Vmax)
Foldback Voltage Breakpoint 1 (V1)
Foldback Voltage Breakpoint 2 (V2)
Current Limit (ILIMIT1)
Current Limit (ILIMIT2)
—
mA
dV/dT Sensitivity2, 3
—
200
2000
V/µs
1. At 25 °C, maximum voltage rating has a temperature coefficient of +0.167 V/°C.
2. This parameter is not tested in production; it is guaranteed by design and device characterization.
3. Applied voltage is 100 Vp-p square wave at 100 Hz to measure dV/dt sensitivity at 200 V/µs typical with no switch turn-on. In the case of
dV/dt induced turn-on at higher dV/dt and amplitude, the design objective is no damage to at least 2000 V/µs and full voltage. A known con-
dition that can cause damage is initial current flow prior to the application of the dV/dt and the sudden application of reverse bias with dV/dt
induced switch turn-off. In this case, no damage will occur for dV/dt up to 2000 V/µs as guaranteed by design and characterization.
Table 13. Test-In Access Switches (SW3 and SW6)
Parameter
Min
Typ
Max
Unit
Off-state:
Maximum Differential Voltage
±3201
±10
15
—
—
—
—
—
—
V
µA
pF
dc Leakage Current (VSW = ±320 V)
Feedthrough Capacitance2
On-state (See On-State Switch V-I Characteristics section.):
Resistance (RON)
—
—
85
45
—
—
90
60
—
Ω
V
mA
Maximum Differential Voltage (Vmax)
Current Limit (ILIMIT) Switches SW3 and SW63
dV/dT Sensitivity2, 4
—
200
2000
V/µs
1. At 25 °C, maximum voltage rating has a temperature coefficient of +0.167 V/°C.
2. This parameter is not tested in production; it is guaranteed by design and device characterization.
3. Test in access switches current limit will be > tip and ring break switches current limit.
4. Applied voltage is 100 Vp-p square wave at 100 Hz to measure dV/dt sensitivity at 200 V/µs typical with no switch turn-on. In the case of
dV/dt induced turn-on at higher dV/dt and amplitude, the design objective is no damage to at least 2000 V/µs and full voltage. A known con-
dition that can cause damage is initial current flow prior to the application of the dV/dt and the sudden application of reverse bias with dV/dt
induced switch turn-off. In this case, no damage will occur for dV/dt up to 2000 V/µs as guaranteed by design and characterization.
Agere Communications Inc.
15
Data Sheet
September 2001
L7585G Full-Feature, Low-Power SLIC and Switch
Electrical Characteristics (continued)
Table 14. Tip and Ring Break Switches (SW2 and SW4)
Parameter
Min
Typ
Max
Unit
Off-state:
±3201
±20
50
Maximum Differential Voltage
dc Leakage Current (VSW = ±320 V)
Feedthrough Capacitance2
—
—
—
—
—
—
V
µA
pF
On-state (See On-State Switch V-I Characteristics section.):
Resistance (RON)
—
—
60
25
—
—
—
160
50
Ω
V
V
V
mA
3201
—
Maximum Differential Voltage (Vmax)
Foldback Voltage Breakpoint 1 (V1)
Foldback Voltage Breakpoint 2 (V2)
Current Limit (ILIMIT1)
V1 + 0.5
85
—
250
—
Current Limit (ILIMIT2)
2
—
mA
dV/dT Sensitivity2, 3
—
200
2000
V/µs
1. At 25 °C, maximum voltage rating has a temperature coefficient of +0.167 V/°C.
2. This parameter is not tested in production; it is guaranteed by design and device characterization.
3. Applied voltage is 100 Vp-p square wave at 100 Hz to measure dV/dt sensitivity at 200 V/µs typical with no switch turn-on. In the case of
dV/dt induced turn-on at higher dV/dt and amplitude, the design objective is no damage to at least 2000 V/µs and full voltage. A known con-
dition that can cause damage is initial current flow prior to the application of the dV/dt and the sudden application of reverse bias with dV/dt
induced switch turn-off. In this case, no damage will occur for dV/dt up to 2000 V/µs as guaranteed by design and characterization.
Table 15. Tip and Ring Feedback Switches (SW2a and SW4a)
Parameter
Min
Typ
Max
Unit
Off-state:
Maximum Differential Voltage
±3201
±10
15
—
—
—
—
—
—
V
µA
pF
dc Leakage Current (VSW = ±320 V)
Feedthrough Capacitance2
On-state (See On-State Switch V-I Characteristics section.):
Resistance (RON)
—
—
0.5
4
—
—
10
3201
20
kΩ
V
mA
Maximum Differential Voltage (Vmax)
Current Limit (ILIMIT)
dV/dT Sensitivity2, 3
—
200
2000
V/µs
1. At 25 °C, maximum voltage rating has a temperature coefficient of +0.167 V/°C.
2. This parameter is not tested in production; it is guaranteed by design and device characterization.
3. Applied voltage is 100 Vp-p square wave at 100 Hz to measure dV/dt sensitivity at 200 V/µs typical with no switch turn-on. In the case of
dV/dt induced turn-on at higher dV/dt and amplitude, the design objective is no damage to at least 2000 V/µs and full voltage. A known con-
dition that can cause damage is initial current flow prior to the application of the dV/dt and the sudden application of reverse bias with dV/dt
induced switch turn-off. In this case, no damage will occur for dV/dt up to 2000 V/µs as guaranteed by design and characterization.
16
Agere Communications Inc.
Data Sheet
September 2001
L7585G Full-Feature, Low-Power SLIC and Switch
Electrical Characteristics (continued)
Table 16. Ringing Access Switch (SW5)
Parameter
Min
Typ
Max
Unit
Off-state:
Maximum Differential Voltage
dc Leakage Current (VSW = ±500 V)
dc Leakage Current (VSW = ±250 V)
Feedthrough Capacitance1
—
—
—
—
—
—
—
1
±475
±20
±1
V
µA
µA
pF
—
On-state (See On-State Switch V-I Characteristics section.):
Crossover Offset Voltage (VOS; ISW = ±1 mA)
Resistance (RON)
—
—
—
—
—
—
—
3
10
2.5
2
V
Ω
A
Surge Current (10 µs x 1000 µs pulse)1
Release Current1
0.1
mA
dV/dT Sensitivity1, 2
—
—
200
—
2000
320
V/µs
V
Common-mode Voltage (maximum either switch terminal with
respect to ground)
1. This parameter is not tested in production; it is guaranteed by design and device characterization.
2. Applied voltage is 100 Vp-p square wave at 100 Hz to measure dV/dT sensitivity.
3. Applied voltage is 100 Vp-p square wave at 100 Hz to measure dV/dt sensitivity at 200 V/µs typical with no switch turn-on. In the case of
dV/dt induced turn-on at higher dV/dt and amplitude, the design objective is no damage to at least 2000 V/µs and full voltage. A known con-
dition that can cause damage is initial current flow prior to the application of the dV/dt and the sudden application of reverse bias with dV/dt
induced switch turn-off. In this case, no damage will occur for dV/dt up to 2000 V/µs as guaranteed by design and characterization.
On-State Switch I-V Characteristics
ISW
+ILIMIT
ISW
ISW
CURRENT
LIMITING
ILIM1
RON
2/3 RON
–VMAX –V2 –V1
–ILIM2
–1.5
ILIM2
VSW
+V1 +V2 +VMAX
2/3 RON
RON
+1.5
–VMAX
VSW
RON
–1.5 V
–VOS
VSW
+VMAX
+1.5 V
+VOS
–ILIM1
2/3 RON
RON
–ILIMIT
CURRENT
LIMITING
12-3291.a(F)
12-3292.a(F)
5-5990.c(F)
A. SW2a, SW3, SW4a, SW6
B. SW5
C. SW1, SW2, SW4
Figure 3. On-State Switch I-V Characteristics
Agere Communications Inc.
17
Data Sheet
September 2001
L7585G Full-Feature, Low-Power SLIC and Switch
■ In the ringing state, if the resistor between RSW and
PR is open, there will likely be a large voltage at the
ringing input (due to capacitive loading) and ring trip
will be asserted after the second zero crossing of
ringing. Because there is no guarantee of the load at
PR in this condition, there can be no guarantee of
the state on NDET in this condition.
Applications
Tip/Ring Protection
The L7585 SLIC has integrated overvoltage tertiary
protection diodes in the tip and ring paths. The device
also has an integrated thermal shutdown circuit which
places tip/ring drivers in a high-impedance state when
the die temperature exceeds 160 °C.
■ If the device enters into thermal shutdown due to a
fault that causes an off-hook, the off-hook indication
will be stable as the device cycles in and out of ther-
mal shutdown. If the fault does not cause an off-
hook, NDET will cycle between on- and off-hook as
the device cycles in and out of thermal shutdown.
The SLIC requires the following to survive lightning and
power cross requirements:
■ Fusible elements or PTCs
■ Current-limiting resistors
■ A secondary protector
Power, Clocking, and Layout
Thermal fuse/surge resistor modules that satisfy the
various requirements can be purchased from MMC™.
Protection resistors should have a tolerance of ±1%
and a ratio tolerance of ±0.5%. The suppressor break-
over voltage of the secondary protector should be set
as low as possible. Select a value just above the maxi-
mum peak ring signal and maximum battery voltage.
The SLIC requires +5 V (VCCA and VCCD) and a nega-
tive battery voltage (VBAT) to operate. The integrated
switches require a 10 V or 12 V supply (VSP) and a TTL
clock (CLK) to operate. CLK requires a frequency
between 1.0 MHz to 2.048 MHz with a 50% duty cycle.
SW1, SW3, and SW6 will not operate without CLK
applied.
A four- or six-layer board is recommended. Analog and
battery grounds should be laid out as a plane and a
layer, and tied together at the device. Digital ground
can also be tied to this plane or run separately. VSP is
referenced to DGND. VCC can be run as individual
traces and can reside on the same layer as signal
paths. VCCA and VCCD can be tied together at the SLIC.
Placement of the talk battery is not critical.
NDET Under Fault Condition
■ The state of NDET is not guaranteed with loss of bat-
tery.
■ In the ringing state, RRNG floating or with only dc on
the ringing source, NDET will produce an off-hook
because there are not zero crossings of ringing to
cause an on-hook.
The ring bus should be on a separate layer from the
SLIC/codec interface signal leads, and traces should
run perpendicular if the traces must cross. TXI, VITR,
and ITR are the sensitive nodes on the SLIC. Transmit
runners should be run in pairs, and receive runners
should be run in pairs between the SLIC and the
codec. A channel-to-channel spacing should be main-
tained.
■ In the ringing state with only ac (>40 Vrms) on the
ringing source, an on-hook will be produced after the
second zero crossing of the ringing waveform,
because there is no dc component to the ringing cur-
rent.
18
Agere Communications Inc.
Data Sheet
L7585G Full-Feature, Low-Power SLIC and Switch
False On-Hook Transients
September 2001
Applications (continued)
Ring Trip
■ If the L7585G is off-hook in the ground-start/tip open
state, the ground-start/tip ground state, or the
ground-start/tip amplifier state, due to an applied ring
ground, and it is switched to the forward battery
active state, it will not generate a false on-hook
longer than 10 ms in duration. This applies for loop
resistances of 0 Ω to 2000 Ω, providing that all of the
following criteria are satisfied:
Ring trip is set by the value of RS1.
The ring trip threshold at the ring trip inputs is ±2.5 V
minimum, ±3.5 V maximum.
A resistor value of 500 Ω, as shown in Figure 4, will set
the ring trip current threshold to ±6.0 mA typical.
— A loop closure is applied before the L7585G
switches to the forward battery active state.
— The loop closure resistance (telephone set) is less
than 430 Ω.
— The ring ground and loop closure are applied at
the same end of the loop.
— If the ring ground is removed while the L7585G is
in the forward battery active state, then the ring
ground resistance must be greater than 225 Ω
when the dc current limit is 40 mA, or greater than
430 Ω when the dc current is 28 mA.
Ring trip is asserted upon entering the ringing mode
until the second zero crossing of ringing. This is either
a positive-going zero crossing (between –40 V and
–30 V at –50 V VBAT) or a negative-going zero crossing
(between –10 V and –20 V at –50 V VBAT). The different
threshold for positive-going and negative-going zero
crossings is the result of hysteresis of approximately
20 V.
Ring trip will not be asserted unless the ring trip thresh-
old is exceeded for two zero crossings. This is either a
positive-going zero crossing (between –40 V and –30 V
at –50 V VBAT) or a negative-going zero crossing
(between –10 V and –20 V at –50 V VBAT). The different
threshold for positive-going and negative-going zero
crossings is the result of hysteresis of approximately
20 V.
Note that since the ringing voltage is monitored at
RSW, one zero crossing can occur at switch turn-on
depending on initial conditions.
Ring trip is asserted immediately if the ring trip input is
15 V ± 3 V.
Agere Communications Inc.
19
Data Sheet
September 2001
L7585G Full-Feature, Low-Power SLIC and Switch
Application Diagram
+10 V –48 V
+5 V
CVB
0.1 µF
CVA
0.1 µF
100 V
10 V
VSP VBAT BGND VCCA AGND
DGND
FB1*
0.047 µF
100 V
FB1
FB2*
CVD
0.047 µF
100 V
0.1 µF
SLIC 0
L7585
FB2
CF1
VCCD
RDO
+5 V
CF1
0.22 µF
100 V
RELAY
K1
CF2
CF2
TRNG
RRNG
DCR
RINGING
BUS
0.1 µF
100 V
+5 V
+5 V
+5 V
0.1 µF
DCOUT
IPROG
(SEE BELOW)
RPROG 64.9 kΩ
RLCTH 24.9 kΩ
RS1
0.1 µF
500 Ω
RSW
0.1 µF
OCTAL
CONTROL
CRTF
0.1 µF
OSFS
LCTH
RCVN
RRTF
1 MΩ
0.1 µF
INTERFACE
INTERFACE
VDD
VDDA
CHANNEL
50 V
0
OSFS
RTS
PR
UPCK
VRN0
RPR
82.5 Ω
OSCK
OSCK
OSDR0
OSDR1
OSDX0
OSDX1
CCS0
UPCS
DSP
ASIC
VRP0
MICRO-
RCVP
VTX
OSDR0
OSDR1
OSDX0
OSDX1
RING
PROCESSOR
UPDI
260 V
VTX0
UPDO
CK16
SCKSEL†
SURGE
PROTECTOR
CODEC 0
T8532
RPT
VRTX0
VRTX
82.5 Ω
PT
CHANNELS
1—7
CCS0
CDI
2.4 V
RSTB
TIP
RSTB
TXI
VITR
ITR
CDO
CB1
RTI
TTI
TEST-IN
BUS
SCK
0.1 µF
100 V
CDO
CDI
SFS
RGX1
TEST
RSTB
RSTB
PCM
BUS
1 MHz
CLOCK
SDR
SDX
CLK
8.25 kΩ
VDDD
T8531A
TEST
RSTB
NDET NCS B5 B4 B3 B2 B1 B0
CDI
STSXB
CDO
OSFS
OSCK
PCM
INTERFACE
PARALLEL DATA BUS TO MICROPROCESSOR
CCS1
CCS1
CODEC 1
T8532
CHANNELS
8—15
OSDR2
OSDR2
TRNG
OSDR3
OSDX2
OSDX3
BATTERY BACK
OSDR3
OSDX2
OSDX3
RINGING
RRNG
TRNG
EARTH BACK
VSS
VSSA
0.1 µF
+5 V
0.1 µF
RINGING
RRNG
+5 V
12-3351.R(F)
* Optional for quiet reverse battery.
† 4.096 MHz operation; for 2.048 MHz operation, tie SCKSEL to VSS.
Figure 4. 16-Channel Line Card Solution
20
Agere Communications Inc.
Data Sheet
September 2001
L7585G Full-Feature, Low-Power SLIC and Switch
Outline Diagram
44-Pin MQFP
Dimensions are in millimeters.
Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schemat-
ics to assist your design efforts, please contact your Agere Communications Sales Representative.
13.20 ± 0.20
10.00 ± 0.20
PIN #1 IDENTIFIER ZONE
34
44
33
1
13.20 ±
0.20
10.00 ±
0.20
23
11
12
22
DETAIL B
DETAIL A
1.95/2.10
2.35
MAX
SEATING
PLANE
0.10
0.80 TYP
0.25 MAX
1.60 REF
0.130/0.230
0.25
GAGE PLANE
0.30/0.45
SEATING PLANE
M
0.20
0.73/1.03
DETAIL A
DETAIL B
5-2111 (F)
Agere Communications Inc.
21
Data Sheet
September 2001
L7585G Full-Feature, Low-Power SLIC and Switch
Ordering Information
Device Part No.
Description
Package
Comcode
LUCL7585GBE-D
Full-Feature, Low-Power
SLIC and Switch
44-Pin MQFP (Dry Bag)
108559683
LUCL7585GBE-DT
Full-Feature, Low-Power
SLIC and Switch
44-Pin MQFP (Tape and Reel, Dry Bag)
108559691
IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
MMC is a trademark of Microelectronic Modules Corporation.
For additional information, contact your Agere Systems Account Manager or the following:
INTERNET:
http://www.agere.com
E-MAIL:
docmaster@agere.com
N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)
ASIA:
Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon
Tel. (852) 3129-2000, FAX (852) 3129-2020
CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen)
JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei)
Tel. (44) 7000 624624, FAX (44) 1344 488 045
EUROPE:
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
Copyright © 2001 Agere Systems Inc.
All Rights Reserved
September 2001
DS01-313ALC (Replaces DS00-217ALC)
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