TDAT04622 [AGERE]

TDAT SONET/SDH 155/622/2488 Mbits/s Data Interfaces; TDAT SONET / SDH 155/622/2488 Mb / s的数据接口


型号：	TDAT04622
厂家：	AGERE SYSTEMS
描述：	TDAT SONET/SDH 155/622/2488 Mbits/s Data Interfaces TDAT SONET / SDH 155/622/2488 Mb / s的数据接口
文件：	总310页 (文件大小：4317K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Data Addendum

May 2001

TDAT SONET/SDH

155/622/2488 Mbits/s Data Interfaces

Introduction

The TDAT data interface is available in three different configurations as summarized in Table 1.

TDAT04622

The TDAT04622 device contains a subset of the TDAT042G5 device. The TDAT04622 device functions as

described in the TDAT042G5 SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet

(DS98-193SONT-4) with the following limitations:

■ Quad OC-3 operation only or single OC-12 operation only.

■ Single UTOPIA port.

TDAT021G2

The TDAT021G2 device contains a subset of the TDAT042G5 device. The TDAT021G2 device functions as

described in the TDAT042G5 SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet

(DS98-193SONT-4) with the following limitations:

■ Quad OC-3 operation only or dual OC-12 operation only.

■ Two UTOPIA ports.

TDAT042G5

The TDAT042G5 device contains all functionality as described in the TDAT042G5 SONET/SDH 155/622/2488

Mbits/s Data Interface Data Sheet (DS98-193SONT-4).

Table 1. TDAT Device Product Line

Device

Line Ports

OC-12

UTOPIA Ports

OC-3

OC-48

Ports Present

Modes

TDAT04622

(A)

U2, U2+, U3, U3+

■ 8-bit

(A, B, C, D)

■ 16-bit

TDAT021G2

TDAT042G5

U2, U2+, U3, U3+

■ 8-bit

■ 16-bit

(A, B, C, D)

(A, B)

■ 32-bit

U2, U2+, U3, U3+

■ 8-bit

■ 16-bit

(A, B, C, D)

(16-bit parallel

multiplexed/

demultiplexed)

(A, B, C, D)

■ 32-bit

TDAT SONET/SDH

155/622/2488 Mbits/s Data Interfaces

Data Addendum

May 2001

For additional information, contact your Agere Systems Account Manager or the following:

INTERNET:

E-MAIL:

http://www.agere.com

docmaster@micro.lucent.com

N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286

1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)

ASIA PACIFIC: Agere Systems Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256

Tel. (65) 778 8833, FAX (65) 777 7495

CHINA:

Agere Systems (Shanghai) Co., Ltd., 33/F Jin Mao Tower, 88 Century Boulevard Pudong, Shanghai 200121 PRC

Tel. (86) 21 50471212, FAX (86) 21 50472266

JAPAN:

Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan

Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700

EUROPE:

Data Requests: DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148

Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot),

FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki),

ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.

Printed in U.S.A.

May 2001

DA01-010SONT (Replaces DA00-001SONT and must accompany DS98-193SONT-4)

Advisory

May 2001

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

System Programming (SP)

SP1. Required Provisioning Sequence and Clocks

The core registers must be written prior to provisioning any other registers (1) to establish the internal clock

rates for the device, and (2) because writing to certain core registers resets the remainder of the device. Cer-

tain clocks must be present to read/write registers prior to provisioning the device.

One of the following clocks must be present prior to provisioning to enable register access:

^ITxCKP and TxCKN

^IMPU clock (microprocessor interface synchronous mode only)

Provisioning must be implemented in the following sequence:

^ICore register 0x0010 (mode) must be provisioned first

^ICore register 0x0011 (channel [A—D] control) second

^IRemainder of the core registers must then be provisioned (order does not matter)

It is recommended, but not required, that the remainder of the device be provisioned in the following order:

^IOHP, PT, and DE blocks (order does not matter)

^IUT block to turn on the data source to the master and slave

Workaround

Provisioning must be implemented in the following sequence:

^IApply either TxCKP and TxCKN or MPU clock.

^IProvision core:

— Mode, register 0x0010

— Channel [A—D] control, register 0x0011

— Remainder of the core

Corrective Action

Not applicable. Use above procedure in provisioning the device.

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Advisory

May 2001

(continued)

System Programming (SP)

SP2. Behavior During Loss of Receive Line Clock

All state and counter values will be held at their current values when Rx line clock has been lost. The device will not

automatically multiplex in the Tx line clock when the Rx line clock is lost.

Workaround

System software should monitor loss of line clock bits in the receive/transmit state register (addresses 0x040A—

0x040D) and ignore all other alarms. This condition must be serviced as a major failure event.

Corrective Action

This is informational only. No corrective action is required for this condition.

SP3. PT Register Addressing

Addresses for the PT error counter registers are as follows:

^IChannel A: 0x09B3 to 0x09E3

^IChannel B: 0x09EF to 0x0A20

^IChannel C: 0x0A2C to 0x0A5C

^IChannel D: 0x0A68 to 0x0A98

The reserved address space between the error counter registers is not symmetric. (The reserved space

between channels B and C is 0x003D, and the reserved space between channels A and B and channels

C and D is 0x003C.)

Note:

Workaround

This is informational only. No workaround is available for this condition.

Corrective Action

No corrective action is required for this condition.

Agere Systems Inc.

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Advisory

May 2001

Microprocessor Interface (MPU)

MPU1. Interface to Motorola* MC68360 Processor Is Not Glueless

The interface between the Motorola MC68360 processor and TDAT042G5 requires intervening logic because of

the following incompatibilities in the specifications of these two devices. For a 33 MHz microprocessor clock rate,

the Motorola MC68360 series processors can be interfaced to TDAT042G5 without intervening glue logic, if used

without DT and if programmed for six wait-states. If a user wishes not to use the wait-states, then the chip select

applied to TDAT042G5 must be held low until the address changes. Details are given below.

Chip Select Timing

The TDAT042G5 CS input signal requirements are not compatible with the Motorola MC68360 series processor

CSx output signals. TDAT042G5 timing does not allow simultaneous deassertion of CS and ADS signals. Chip

select applied to TDAT042G5 must be held low for at least 5 ns after the MC68360 deasserts ADS.

Use external glue logic to decode the address to generate CS, or provide microprocessor interface

Workaround:

signals meeting the requirements of TDAT042G5.

DT Timing

If the Motorola MC68360 processor CSx signal is used to drive the TDAT042G5 CS, then TDAT042G5 DT output

does not satisfy the MC68360 processor DSACK timing requirement. DT is not pulled to 1 before it is placed in a

high-impedance state. This causes the next MPU cycle to be terminated early.

Place a 1 kΩ resistor from DT to VDDD.

Workaround:

Corrective Action

Corrective action for MPU1 has not been determined.

MPU2. Synchronous Microprocessor Interface Mode Is Nonfunctional

The synchronous microprocessor interface mode, MPMODE = 1 (pin D8), functions as described in the advance

data sheet, but causes data errors. Placing TDAT042G5 in the synchronous mode and placing a clock on MPCLK

(pin C8) will cause the data passing through the device to be corrupted. Data errors are generated at a rate of 1%

or less of corrupted packets.

Workaround

Use the TDAT042G5 in the asynchronous microprocessor mode, MPMODE = 0, with no clock applied to MPCLK.

Corrective Action

This condition will be resolved in version 1A of the device.

Motorola

is a registered trademark of Motorola, Inc.

Agere Systems Inc.

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Advisory

May 2001

Core Registers (CR)

CR1. Clear on Read/Clear on Write Behavior

Bit 6 of line provisioning register 0x0010 sets the functionality of the COR/W registers.

Table 1. COR/W Settings of Register 0x0010, Bit 6

Bit 6

Mode

Bit Clear Behavior of Accessed Registers

COR After COR has been set (address 0x0010, bit 6 = 1), all registers that are accessed

are cleared when read.

COW After COW has been set (address 0x0010, bit 6 = 0), a 1 must be written to a given bit

in a given register to clear that bit. Writing a 0 to a bit in a given register does not clear

that bit.

Workaround

This is informational only. No workaround is available for this condition.

Corrective Action

This condition will be described in revision 4 of the advance data sheet.

Line Interface (LI)

LI1. STS-48/STM-16 Mode Lacks Facility Loopback

There is no facility loopback function (line input to line output) available in STS-48/STM-16 mode. Facility loopback

is available only in STS-12/STM-4 and STS-3/STM-1 modes as described in the advance data sheet.

Workaround

This function is not a feature of TDAT042G5.

Corrective Action

No corrective action is required for this condition.

Agere Systems Inc.

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Advisory

May 2001

Path Terminator (PT)

PT1. Signal Degrade (SD) and Signal Fail (SF) Bit Behavior

Receive signal degrade and receive signal fail bits in the PT state registers (addresses 0x0838, 0x088A, 0x08DC,

and 0x092E, bits [1:0]) do not function as described. Until the signal degrade (SD) and signal fail (SF) thresholds

are programmed, the SD and SF bits will toggle on a frame-by-frame basis.

Workaround

Program thresholds during system software initialization.

Corrective Action

This functionality will be retained in its current state in future versions of the device. The advance data sheet will be

corrected to reflect the actual function of the registers.

PT2. Clear-After-Write Behavior of Signal Degrade Clear Bits

Signal degrade clear (bits 15—12) of the PT one-shot control parameters register (address 0x0AA4) are described

as one-shot, clear-after-write bits. Writing these bits should automatically set and then clear the bits. This one-shot

behavior is not observed.

Workaround

The bits must be set to 1 and then explicitly set to 0 to clear these signal degrade bits.

Corrective Action

This functionality will be retained in its current state in future versions of the device. The advance data sheet will be

corrected to reflect the actual function of the registers.

Agere Systems Inc.

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Advisory

May 2001

(continued)

Path Terminator (PT)

PT3. Remote Defect Indicator (RDI) Behavior

The SONET standards require that when an RDI changes value, it should hold the value for a minimum of

20 frames. This applies to a state, which should be maintained for at least 20 consecutive frames.

no error

However, it is also intended by the SONET standard that the occurrence of an

immediately.

state should be reported

error

TDAT042G5 responds to error conditions within 100 ms (ANSI T1.105 which states only that RDI-L must be gen-

erated or removed within 100 ms of detecting or terminating an incoming defect), in which case the two require-

ments become functionally the same.

Single-bit and enhanced RDI behave differently under the following conditions:

^ITransition from error state to no error state.

^IWhile in the error state, a subsequent error occurs.

The single-bit error RDI does not hold the no error state for 20 frames. However, the enhanced RDI does hold the

no error state for 20 consecutive frames.

Workaround

No workaround is available for this condition.

Corrective Action

The enhanced RDI indicator in future versions of the device will behave the same as the single-bit error indicator.

PT4. SS Pointer Interpretation Algorithm

The SDH standards do not require that the SS bits are set to binary 10 for SDH equipment. The SS bit values are

not used in determining a valid pointer value. Because of this, the SS pointer interpretation algorithm is not imple-

mented in the device. Bit 5 (RSSPTRNORM[A—D]) of PT control registers 0x0AA6, 0xAAE, 0x0AB6, and 0x0ABE

is not used. Bits 1 and 0 (RSSEXP[1:0]) of PT provisioning register 0x0AC7 are not used.

Workaround

No workaround is available for this condition.

Corrective Action

These bits will be removed from the PT registers in future revisions of the advance data sheet.

ANSI

is a registered trademark of American National Standards Institute, Inc.

Agere Systems Inc.

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Advisory

May 2001

(continued)

Path Terminator (PT)

PT5. Delta/Event Registers in COR Mode

Because there is a one-cycle delay before the PT delta event registers (0x802, 0x080F, 0x081C, 0x0829) are

cleared after being read in COR mode, new interrupts may be lost.

Workaround

No workaround is available for this condition.

Corrective Action

This condition will be addressed in future versions of the device.

Data Engine (DE)

DE1. SDL Mode—Header Error Correction in LSB

In SDL mode, the header error correction process is susceptible to single-bit errors in the least significant bit (LSB)

of the special payload.

Workaround

No workaround is available for this condition.

Corrective Action

This condition will be addressed in future versions of the device.

DE2. Incorrect ATM Loss of Cell Delineation (LCD) Implementation

Currently, the LCD is implemented in the same way that out of cell delineation (OCD) is implemented. This is not in

accordance with the ITU-TI.432-2 February 1999 standard.

Workaround

No workaround is available for this condition.

Corrective Action

A software workaround will be available with version 1A of the device.

Agere Systems Inc.

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Advisory

May 2001

(continued)

Data Engine (DE)

DE3. ATM Transmit Count of Idle Cells

For ATM mode in the transmit direction, all cells are currently counted, including the idle cells. Only the cells con-

taining data should be counted.

Workaround

No workaround is available for this condition.

Corrective Action

This condition will be addressed in version 1A of the device.

DE4. Channel Provisioning

When using the device in STS-3/STM-1 and STS-12/STM-4 modes with either PPP, CRC, or HDLC, egress config-

uration registers 0x1016, 0x1017, 0x1018, and sequencer cell state register 0x1036 of all four channels must be

provisioned, even if a channel is not being used.

Workaround

Provision all four transmit DE channels. Set DE egress configuration registers and the sequencer cell state register

as shown in Table 2.

Table 2. Transmit DE Egress and Sequencer Cell State Registers

Address

Value

STS-12/STM-4

STS-3/STM-1

0x1016

0x1017

0x4567

—

0x4567

0x0000

0x1018

0x1019—0x1021

0x1036

0x0000

Corrective Action

This condition will be addressed in future versions of the device.

Agere Systems Inc.

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Advisory

May 2001

(continued)

Data Engine (DE)

DE5. Packet Behavior in POS/SDL Mode—Dry Mode

When the device is configured in POS mode with dry mode enabled, the following conditions may persist:

^IPPP mode; STS-48/STS-12/STS-3.

When running in PPP mode, the PPP header—0xFF03 0x0021 (provisionable)—may be incorrectly inserted at

any point in a packet within the outgoing data stream when the FIFO runs dry, thereby corrupting the packet.

Packets being sent are corrupted if the FIFO runs dry.

^IPPP and CRC modes; STS-48/STS-12/STS-3.

CRC, PPP, and HDLC modes; STS-48/STS-12/STS-3.

In PPP, CRC, and HDLC dry modes, some of the packet data may be corrupted when the packet length is above

a certain size where size is dependent upon UT clock rate and low watermark setting. Either sections of the

packet may be lost or additional packets may be inserted.

Workaround

Several workarounds are possible:

^IDo not provision dry mode for this device.

^IIf dry mode is provisioned:

— Do not allow the FIFO to be emptied.

— Run the UTOPIA clock fast enough, as shown in Table 3, so that the FIFO is never empty.

— Use a larger external FIFO to buffer the data.

— Do not allow the packet size to exceed the low watermark.

Table 3. Required UTOPIA Clock (TxCLK) Rates

Mode

TxCLK and Rate

STS-48/STM-16 TxCLK > 77 MHz (U3+, 32-bit mode)

STS-12/STM-4

STS-3/STM-1

TxCLK > 40 MHz

TxCLK > 10 MHz

Corrective Action

This condition will be corrected in version 1A of the device.

Agere Systems Inc.

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Advisory

May 2001

(continued)

Data Engine (DE)

DE6. Incorrect ATM Out of Cell Delineation (OCD) Implementation

In ATM mode, the OCD reporting for channels B, C, and D is incorrect. The OCD state of channel A is reported for

channels B, C, and D. The OCD reporting is correct for channel A.

Workaround

No workaround is available for this condition.

Corrective Action

This condition will be corrected in version 1A of the device.

DE7. Incorrect Frame State of ATM Data Streams

When sending a single ATM data stream to channel A, the frame states of channels B, C, and D are incorrectly set

to sync mode. This prevents LCD errors from being reported on channel A as well. In addition, when sending a sin-

gle ATM data stream to channels B, C, or D, the frame states always remain in hunt mode. This results in LCD

errors on those channels.

Workaround

No workaround is available for this condition.

Corrective Action

A software workaround will be available with version 1A of the device.

Agere Systems Inc.

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Advisory

May 2001

(continued)

Data Engine (DE)

DE8. Clearing DE Interrupt Register (0x1002)

DE interrupt register 0x1002 is incorrectly defined in the revision 3 of the data sheet as RO. DE interrupt register

0x1002 is correctly defined as a COR/W register. However, register 0x1002 must be used in the COR mode (regis-

ter 0x0010 bit 6 set to 1). The bits of register 0x1002 are explained in detail in Table 4.

Table 4. Register 0x1002: DE Interrupt (COR/W)

Bits

Mode

Clear Behavior of Register 0x1002

15—12

To clear these SDL Rx frame state interrupt bits, read and

clear their associated interrupt source registers

(addresses 0x14E0—0x14E3).

11—0

COR or COW

To properly clear these bits, device must be in COR mode

(address 0x0010, bit 6) (address 0x0010, bit 6 = 1).

Workaround

This is informational only. No workaround is available for this condition.

Corrective Action

This behavior will be described in future revisions of the advance data sheet.

DE9. Single Packet Transmission in HDLC-CRC, SDL-CRC, and PPP Modes

When receiving in either PPP or CRC mode, a single packet may not pass through the device. This occurs when

the end of packet (which contains the CRC) never reaches the UT FIFO. The ingress channel suspends transfer to

the UT when there is no end of packet in the FIFO. These bytes are transferred to the UT when the next packet is

received. This problem will affect HDLC-CRC, SDL-CRC, and PPP modes.

Workaround

There are two possible workarounds:

^ISet ingress payload type and mode control registers (0x1040—0x1043) to CRC strip mode. However, in CRC-16

mode, single packets may still get stuck if CRC ends on bytes A or B.

^ISend a minimum 4-byte dummy packet after each packet.

Corrective Action

This condition will be addressed in future versions of the device.

Agere Systems Inc.

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Advisory

May 2001

(continued)

Data Engine (DE)

DE10. Excessive HDLC Flag Characters

The following three issues refer to HDLC flag character (0x7E) problems in the data engine:

^IAn excessive number of HDLC flag characters (0x7Es) may be inserted between packets on the transmit side if

the UTOPIA low watermark value is set above 2. This will have the effect of reducing the bandwidth of the device.

^IThe data engine operates on 32-bit boundaries. Egress packets that are not multiples of four will be filled with

0x7Es.

^IEgress packets consisting of all 0x7Es as data will be corrupted.

Workaround

Set the UTOPIA egress low watermark value in the UTOPIA egress provisioning registers (0x0212, 0x0216,

0x021A, 0x021E) to either 1 or 2 to prevent excessive 0x7Es from being inserted between packets.

Corrective Action

This condition will be addressed in future versions of the device.

UTOPIA (UT)

UT1. Polling in Multidevice MPHY Mode

When the TDAT042G5 is polled and responds, the data bus becomes enabled. In a multidevice MPHY configura-

tion, if the data bus is active from a different PHY device, response to a poll from the device will corrupt a data

transfer already in progress. TDAT042G5 MPHY always functions without data corruption in a single-device

(slave), multiple-channel configuration (point-to-point).

Workaround

No workaround is available for this condition.

Corrective Action

This condition will be addressed in future versions of the device.

Agere Systems Inc.

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Advisory

May 2001

(continued)

UTOPIA (UT)

UT2. UTOPIA Clock Limitations

The maximum speed of the UTOPIA interface is 104 MHz. When operating at clock speeds greater than 52 MHz,

RxCLK[D:A] must be placed in source mode and will use the same external clock as the corresponding

TxCLK[D:A] clock. RxCLK[D:A] source mode is set by provisioning bit 6 (CLOCK_MODE_Rx) for channel A of the

UTOPIA receive provisioning registers (address 0x020F).

When operating at speeds less than 52 MHz, separate external clocks for RxCLK[D:A] and TxCLK[D:A] may be

used.

Workaround

This is informational only. No workaround is available for this condition.

Corrective Action

This condition will be addressed in future versions of the device. Design modifications will be directed towards

allowing a maximum interface speed of 104 MHz in all cases. Note that UTOPIA Level 3 clock architecture has

changed in the ATM Forum’s UTOPIA Level 3 specification as of the July 1998 version.

UT3. PMRST Register Value Invalid After Reset

The value in PMRST_PECTx[A—D] (addresses 0x020B through 0x020E) is invalid after reset until the second

PMRST clock period is completed. After the second PMRST, the register value is valid.

Workaround

Always have the system software execute a read of PMRST_PECTx as part of the system initialization following a

reset.

Corrective Action

This condition will be addressed in future versions of the device.

Agere Systems Inc.

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Advisory

May 2001

(continued)

UTOPIA (UT)

UT4. FIFO Overflow and Error Reporting

If the RxFIFO overflows, RxEOP is not asserted as expected. Therefore, when errors occur, two packets will be

corrupted instead of one because two start of packets (SOPs) occurred without an end of packet (EOP). RxERR is

not asserted when the above overflow condition occurs. No effect is noticeable in the ATM mode. Channel A works

as expected; this problem occurs in channels B, C, and D.

Workaround

This error is detectable in the status registers. No workaround is available for this condition.

Corrective Action

This condition will be addressed in future versions of the device.

UT5. Timing Difference Between Direct and Polled Status Modes

In the receive direction of the MPHY mode, RxPA[A] shows the polled packet (or ATM) available status for all four

slices, while the RxPA[B], RxPA[C], and RxPA[D] show the direct status states of their respective FIFOs. In some

cases, the status of RxPA[A] does not agree with the status of RxPA[D:B]. The direct status indication has one

additional cycle of pipeline delay from that of the polled status.

Workaround

This is informational only. No workaround is available for this condition.

Corrective Action

No corrective action is required for this condition.

UT6. UTOPIA Interface D Nonfunctional in Some Mixed MPHY and Point-to-Point

Configurations

When TDAT042G5 is configured with slice D in a point-to-point mode, slice D is nonfunctional in one special case.

If UTOPIA interfaces A and B are configured for 32-bit MPHY operation with slice C as part of the polled channels,

interface D will be nonfunctional and cannot be independently configured in a UTOPIA Level 2 point-to-point mode.

This condition does not occur in 16-bit MPHY operation.

Workaround

For mixed MPHY and point-to-point configuration, use UTOPIA slice D for MPHY mode instead of slice C.

UTOPIA slice C will then be available for normal point-to point mode.

Corrective Action

This condition will be addressed in future versions of the device.

Agere Systems Inc.

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Advisory

May 2001

(continued)

UTOPIA (UT)

UT7. Response to 0x1F MPHY Address

TDAT042G5 MPHY currently generates a polled status response to the address 0x1F (the null address), which is

not compliant with the UTOPIA Level 2 standard. The address 0x1F is valid for UTOPIA Level 3 operation.

Workaround

No workaround is available for this condition.

Corrective Action

This condition will be addressed in future versions of the device.

UT8. Far-End Loopback Bandwidth Limitations

In the STS-48/STM-16 mode (U3, U3+), looping back data at the far end (UTOPIA interface) can only be accom-

plished without cell/packet corruption at rates below the following, as shown in Table 5.

Table 5. Cell/Packet Corruption Rates

Mode

ATM

Packet

STS-48/STM-16

STS-12/STM-4

STS-3/STM-1

300 Mbits/s

70 Mbits/s

30 Mbits/s

Rate not yet determined

When cell/packet corruption occurs, the device reports transmit FIFO underflow.

Workaround

No workaround is available for this condition.

Corrective Action

This condition will be addressed in future versions of the device.

Agere Systems Inc.

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Advisory

May 2001

(continued)

UTOPIA (UT)

UT9. Clock Requirements for MPHY Modes

When using the TDAT042G5 in MPHY mode, receive and transmit clocks must be provided for all channels (A, B,

C, and D). Also, the packet available (PA) signal for each channel must be provided on each channel’s associated

PA pin.

Workaround

It is possible to place RxCLK[D:A] into source mode by provisioning bit 6 (CLOCK_MODE_Rx) of the UTOPIA

receive provisioning registers (addresses 0x020F, 0x0213, 0x0217, 0x021B). This will eliminate the need to supply

separate receive and transmit clocks.

Corrective Action

This is informational only. No corrective action is required for this condition.

UT10. Egress Packet Mode Overflows

In the UTOPIA modes listed below, the device will report transmit packet overflow errors when no overflows have

occurred. This occurs when the egress high watermark is set for the UTOPIA modes as shown in Table 6.

Table 6. Settings at Which Overflows Reported in Error

UTOPIA Modes

Egress High Watermark Thresholds

8-bit, U3+

16-bit, U2+

32-bit, U3+

≥0x3D

≥0x3B

≥0x37

Workaround

Set the egress high watermark threshold as shown in Table 7. If there is a delay between TxPA deassertion and

TxENB deassertion, the additional cycles should also be accounted for when setting the threshold.

Table 7. Settings to Prevent Overflows Reported in Error

UTOPIA Modes

Egress High Watermark Thresholds

8-bit, U3+

16-bit, U2+

32-bit, U3+

<0x3D

<0x3B

<0x37

Corrective Action

This condition will be addressed in future versions of the device.

Agere Systems Inc.

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Advisory

May 2001

UTOPIA (UT) (continued)

UT11. Clearing UT Interrupt Register

When a UT interrupt event occurs and COW mode is enabled, writing to UT interrupt register 0x0201 does not

clear the register (this register is read-only). The interrupt is cleared by writing to the UT delta and event registers

(addresses 0x0202—0x0205).

Workaround

This is informational only. No workaround is available for this condition.

Corrective Action

No corrective action is required for this condition.

UT12. Incorrect Implementation of POS Multi-PHY Mode

Because the TDAT042G5 lacks a selected PA signal (SPA), the status of a channel that is transmitting data in POS

MPHY mode is not known during polling. Therefore, the PA signal cannot be used as a data valid signal. If the

channel transmitting data runs dry, the master side may receive invalid data.

Workaround

Use direct status polling mode only and ensure that the address of channel A is applied to the address bus at all

times, except during the clock cycle when another channel is being selected.

Corrective Action

No corrective action is required for this condition.

UT13. Invalid Extra Cycle Between EOP and SOP in CRC-16/32 Mode

When using the device in CRC-16 or CRC-32 mode, there is always an extra cycle between the end of packet

(EOP) of the previous packet and the start of packet (SOP) of the following packet.

Workaround

This is informational only. No workaround is available for this condition.

Corrective Action

This is condition will be addressed in the future version of the device.

Agere Systems Inc.

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Advisory

May 2001

UTOPIA (UT) (continued)

UT14. Nonfunctional RxPA Signal for Channels B and D in Packet Direct Status MPHY Mode

When using MPHY direct status for all operational modes (8-bit, 16-bit, and 32-bit), the RxPA signal for channels B

and D is not functional. The RxPA signal is functional only for channels A and C.

Workaround

The TDAT UTOPIA interface currently has nonfunctioning RxPAB and RxPAD output signals when used in four-

channel Multi-PHY mode as shown in Figure 1. The result of this problem is the unavailability of direct status polling

on the receive-side UTOPIA interface. To work around this problem, the following analysis is done to aid the user in

doing a round-robin data extraction procedure.

RXPAA

32-bit INTERFACE (A AND B)

RXPAB

INGRESS CHANNEL A FIFO

256 bytes DEEP

INGRESS CHANNEL B FIFO

256 bytes DEEP

INGRESS CHANNEL C FIFO

256 bytes DEEP

RXPAC

INGRESS CHANNEL D FIFO

256 bytes DEEP

RXPAD

1664 (F)

Figure 1. Receive-Side UTOPIA Interface and Channel FIFOs

The rate at which data fills and drains the receive-side UTOPIA FIFOs is calculated as follows:

^IThe data enters each UTOPIA FIFO from the data engine bytewise running on a 77.76 MHz system clock.

^IIf we assume each channel (worst case) is filled with an STS-12c rate signal, then the amount of data (excluding

SONET overhead, both section/line, path, and three stuff columns) per second is

(87 x12 x 9 x 8000) – (4 x 9 x 8000) = 74.88 Mbytes/STS-12c/s or 599.040 Mbits/STS-12c/s.

^ISince each FIFO contains a maximum of 256 bytes/FIFO, it takes on average

(256/74,880,000) = 3.4188 µs to fill a FIFO, and with a clock cycle of 77.76 MHz, it requires as a worst case,

3.2922 µs to fill the FIFO.

^ISince there are four FIFOs all receiving data at 74.88 Mbytes/s, then the total bandwidth requirements of all four

channels combined is (4 x 74,880,000) = 299.52 Mbytes/s.

^IThe servicing rate on each FIFO is based on the UTOPIA interface width and frequency. If we assume a

32-bit A/B UTOPIA interface operating at 100 MHz, then the service rate is 400 Mbytes/s to service all the

channels.

Agere Systems Inc.

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Advisory

May 2001

UTOPIA (UT) (continued)

^IThe interface can drain an entire FIFO at a rate of 400 Mbytes/s. To drain 256 bytes, it requires a maximum of

(256 / 400,000,000) = 0.64 µs to drain a FIFO that is completely full. To drain all four FIFOs, it requires

(0.64 x 4) = 2.56 µs total.

For data to be efficiently removed from each of the Rx FIFOs, a round-robin extraction method must be employed

since the RxPAB and RxPAD signals are not available for direct status polling. Since it requires a worst case total of

3.2922 µs to fill a FIFO, the master must service all FIFOs in a manner such that it does not allow any particular

FIFO to fill and hence overflow. Assuming equal servicing of each FIFO, the master must therefore not service any

particular FIFO for longer than (3.2922 / 4) = 0.8231 µs. This also must account for any dead cycles in a cycling

between channels and any dead cycles on a particular channel (single dead cycle between EOP and SOP).

When servicing four FIFOs, there is a maximum clock cycle penalty for switching between channels. For two-cycle

mode, this penalty is a maximum of four UTOPIA master clock cycles; so to switch between all four channels, a

total of up to sixteen master clock cycles may be required to perform all the switching. The value of four is worst

case, and in some cases this can be as low as one cycle. The value of four results from the case where the FIFO

drains while servicing that channel, which will be common when draining at the 100 MHz frequency. In that case,

the master must first see that the FIFO has drained by observing that RxPAA is invalid on the last cycle while drain-

ing the FIFO (best case is one cycle lost). It must then deactivate RxENB and place a new channel address on the

address bus on the following cycle (best case is one cycle lost). It must then activate RxENB for the new channel

on the following cycle and have TDAT sample RxENB low (best case is one cycle lost). The TDAT will then output

data two cycles later when using a PA response mode of two cycles (one cycle lost with data output on second

cycle). Any additional delays by the master must be added to these to calculate a worst-case condition. The best-

case condition occurs when the master stops the data flow when there are still more than two data items contained

within the FIFO. In this case, the master deactivates RxENB at some predetermined maximum 32-bit word drain

value, where the PA response on the cycle prior to deactivation had valid data. For two-cycle mode, two additional

data items will be output from the FIFO for that particular channel, if available. The master deactivates RxENB,

places the new channel address on the FIFO, and activates RxENB. On the cycle where RxENB is activated, the

last valid data item from the previous channel may be output (best case), and one dead cycle will follow this before

data for the following selected channel is output.

Given the information above, assume the worst case of four cycles between channel switching. Also assume the

FIFOs are filling at a worst-case rate, 3.2922 µs/FIFO. Assume the master is draining each FIFO using the 32-bit,

100 MHz, A/B, UTOPIA interface. Assume the master extracts a maximum of thirty 32-bit words (120 bytes) from

each FIFO before switching to an alternate channel. This requires (30 x 10) = 300 ns/FIFO, and assume that it

takes the worst-case four clock cycles to switch to alternate channels. Therefore, the total servicing time per FIFO

is (300 + 4 x 10) = 340 ns/channel, and the total servicing time per four channels is (4 x 340) = 1.36 µs per round

robin servicing of all four channels. At this round-robin rate, a maximum of 120 bytes are serviced per channel per

1.360 µs interval; so to service the total bytes per channel (74.88 Mbytes/s), it requires a total of 0.849 seconds,

which is sufficient bandwidth to service all channels.

Since the FIFOs fill at the maximum rate of 1 byte/13.355 ns, each FIFO will fill to a depth of 102 bytes in the

1.360 µs interval between channel servicing. This is well below the overflow threshold, which is set by the user to a

value near the top of the FIFO (high watermark, 0x36 (216 bytes) default) and is below the number of bytes ser-

viced by the master per channel per round-robin servicing (120 bytes). Each customer’s servicing characteristics

will depend on the master’s behavior and how fast it performs the channel switching. If it cannot switch in the worst-

case, four-cycle manner described above, performance will degrade.

One item not accounted for in the above analysis is the fact that TDAT may place a dead cycle between packets (in

CRC and PPP modes, not in HDLC mode). In this case, there can be a maximum of three dead cycles per FIFO

(assuming 40-byte packets worst case and 102 bytes in FIFO between round-robin cycle). This will be taken up by

the slack provided above, where (102 bytes + 4 bytes/dead cycle x 3 dead cycles) = 114 bytes, which still falls

below the servicing rate of 120 bytes per round-robin servicing.

Agere Systems Inc.

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Advisory

May 2001

UTOPIA (UT) (continued)

The logical flow of the above procedure is shown in Figure 2 below:

SELECT NEXT

CHANNEL

HOLD ADDRESS OF SELECTED

CHANNEL ON ADDRESS BUS

PA = 1

YES

COUNT < 30

DEACTIVATE

ENB

1665 (F)

Figure 2. Master Control Flow Chart

Select channel

If PA = 1 continue

If count = 30 words, then deactivate RxENB and switch to new channel

Else continue with current channel

Else deactivate RxENB and switch to next channel

Return to selection of new channel

Corrective Action

This is condition will be addressed in the future version of the device.

Agere Systems Inc.

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Advisory

May 2001

Overhead Processor (OHP)

OHP1. Maximum BER Count

The maximum number of errors the device can report is limited to 5.00E-04 in STS-12/STM-4 mode and 1.00E-04

in STS-48/STM-16 mode. This applies to the SDLSET, SDLCLEAR, SFLSET, and SFLCLEAR bits of the signal

degrade and signal fail BER algorithm OHP registers. These bits are shown in Table 8.

Table 8. Signal Degrade and Signal Fail Algorithm OHP Registers [6:3]

OHP Bits*

Addresses

OHP_SDLSET[A—D][3:0]

OHP_SDLCLEAR[A—D][3:0]

OHP_SFLSET[A—D][3:0]

OHP_SFLCLEAR[A—D][3:0]

0x043B, 0x043D, 0x043F, 0x0441

0x0447, 0x0449, 0x044B, 0x044D

0x0453, 0x0455, 0x0457, 0x0459

0x045F, 0x0461, 0x0463, 0x0465

* The OHP prefix shown here will be added to the current bit names in revision 4 of the advance data

sheet.

Workaround

This is informational only. No workaround is available for this condition.

Corrective Action

No corrective action is required for this condition.

OHP2. RDI-L Reporting

When the device is initially powered up, it defaults to STS-48/STM-16 mode. This locks a counter value into trans-

mit control registers for channels B, C, and D. When the device is configured for STS-3/STM-1 mode, the counter

does not automatically clear.

Workaround

During STS-3/STM-1 OHP configuration in the system code, manually clear transmit control registers 0x0431,

0x0433, and 0x0435 for channels B, C, and D. In order to clear these transmit control registers, the bits must be

toggled. The following pseudocode shows how to clear the bits on channels B, C, and D:

Set address 0x0431 to 0x007F # set bits on channel B

Set address 0x0431 to 0x0000 # clear bits on channel B

Set address 0x0433 to 0x007F # set bits on channel C

Set address 0x0433 to 0x0000 # clear bits on channel C

Set address 0x0435 to 0x007F # set bits on channel D

Set address 0x0435 to 0x0000 # clear bits on channel D

Corrective Action

This is informational only. No corrective action is required for this condition.

Agere Systems Inc.

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Advisory

May 2001

(continued)

Overhead Processor (OHP)

OHP3. M1 Error Counter in STS-48/STM-16 Mode

When the device receives REI-L errors in the STS-48/STM-16 mode, no M1 errors are reported.

Workaround

There are several workarounds for this problem:

^IPass the B2 error count value to the far end through system software.

^IProcess the M1 byte from the receive TOAC with an external FPGA.

^IPass the B2 error count from the receive to the transmit direction using transmit TOAC capability. The error count

must be inserted into the eleventh Z2 byte in an STS-48/STM-16 transmit signal. The transmit TOAC signal is

driven by an external device with software insert capability.

^IPass the B2 error count from the receive to the transmit direction in the section overhead byte. The device has F1

and S1 monitor capability; the protocol for sending the error message to the far end with F1 or S1 bytes is user-

defined.

Corrective Action

This condition will be addressed in future versions of the device.

Packaging and Pinouts (P)

P1. Pin F5 (Previously JTEST) Is No Connect (NC)

Item deleted. Corrected in the advance data sheet.

P2. Modified Pinout and Power Supply Configuration—Future Versions

Item deleted. No modifications to the power supply configuration will be made.

P3. Change to TDAT042G5 Version 1 Pinout

Item deleted. All devices conform to power pin assignments as listed in the advance data sheet.

Agere Systems Inc.

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Advisory

May 2001

(continued)

Packaging and Pinouts (P)

P4. Power Dissipation

The worst-case power dissipation of TDAT042G5 is currently estimated to be 7.5 W. The minimum and maximum

power dissipation is listed in Table 9, as well as the relative package thermal characteristics.

Table 9. Power Dissipation and Relative Package Thermal Characteristics

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Power Dissipation:

Minimum

STS-3/STM-1 line rate

STS-12/STM-4 and STS-48/

STM-16 line rates

—

Maximum

Thermal Performance

(JEDEC standard

conditions)*

θ^JA

Standard JEDEC 4-layer PWB:

^IStandard natural convection

^I200 LFPM airflow

—

6.5

—

°C/W

^I800 LFPM airflow

Correlation Factor

ψ^JC

Standard JEDEC 4-layer PWB:

^IStandard natural convection

^I200 LFPM airflow

—

Between Die and Case

—

0.3

0.4

0.5

°C/W

†

Temperatures

^I800 LFPM airflow

* θ^JA= (TJ – TA)/PD: TJ = junction temperature, TA = ambient temperature of medium surrounding the package, PD = electrical power dissipated

by the device.

†ψ^JC= (TJ – TC)/PD: TJ = junction temperature, TC = package temperature (top, dead-center), PD = electrical power dissipated by the device.

Maximum junction temperature of TDAT042G5 is 125 °C. Therefore, maximum case temperature under natural

convection conditions must be less than approximately 50 °C, and in this case, an external heat sink is required.

References

Jeff Weiss, 600 LBGA Thermal Test Report, February 25, 1999.

HL250C 3.3 Volt 0.25 µm CMOS Standard-Cell Library (MN98-060ASIC-02), pages 2-2 and 2-3.

Workaround

An external heat sink is required.

Corrective Action

Power consumption will be addressed in future versions of the device.

Agere Systems Inc.

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Advisory

May 2001

Data Addenda

DA1. Incorrect PT Control Register Mapping

TDAT042G5 SONET/SDH 155/622/2488 Mbits/s Data Interface Advance Data Sheet, Rev. 3 lists the following bit

mapping for PT control registers 0x0AAA, 0x0AB2, 0x0ABA, and 0x0AC2:

bit #9 TRDIP_PLMPINH[A—D]

bit #8 TRDIP_UNEQUIPINH[A—D]

bit #7 TRDIP_LCDINH[A—D]

The correct bit mapping is the following:

bit #9 TRDIP_LCDINH[A—D]

bit #8 TRDIP_PLMPINH[A—D]

bit #7 TRDIP_UNEQUIPINH[A—D]

Workaround

No workaround is available for this condition.

Corrective Action

This correct bit mapping will be included in July 2000 of the advance data sheet.

DA2. Variable Change

TDAT042G5 SONET/SDH 155/622/2488 Mbits/s Data Interface

Advance Data Sheet, Rev. 3 lists the variable

TRD_LCDINH[A—D], which has been changed to TRD_LCD[A—D] in the January 2001 revision.

Workaround

No workaround is available for this condition.

Corrective Action

This correction will be included in January 2001 of the advance data sheet.

Agere Systems Inc.

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Advisory

May 2001

AY99-013SONT-2 Replaces AY99-013SONT to Incorporate the Following Updates

1. Page 1, SP1. Required Provisioning Sequence and Clocks, added new issue.

2. Page 8, DE4. Channel Provisioning, added new issue.

3. Page 9, DE5. Packet Behavior in POS/SDL Mode—Dry Mode, added new issue.

4. Page 15, UT8. Far-End Loopback Bandwidth Limitations, added new issue.

5. Page 16, advance data sheet document number corrected.

AY99-013SONT-3 Replaces AY99-013SONT-2 to Incorporate the Following Updates

1. Page 1, notice that the advisory issues still apply to the advance data sheet which has just been updated.

AY99-013SONT-4 Replaces AY99-013SONT-3 to Incorporate the Following Updates

1. Replaced OC- designation with STS- and STM- throughout advisory.

2. Page 2, SP2. Behavior During Loss of Receive Line Clock, added new issue.

3. Page 2, SP3. PT Register Addressing, added new issue.

4. Page 4, CR1. Clear on Read/Clear on Write Behavior, added new issue.

5. Page 5, PT2. Clear-After-Write Behavior of Signal Degrade Clear Bits, corrected description.

6. Page 6, PT4. SS Pointer Interpretation Algorithm, added new issue.

7. Page 7, PT5. Delta/Event Registers in COR Mode, added new issue.

8. Page 7, DE2. Incorrect ATM Loss of Cell Delineation (LCD) Implementation, identified the specific ITU stan-

dard with which the LCD implementation does not comply.

9. Page 8, DE4. Channel Provisioning, Table Transmit DE Egress and Sequencer Cell State Registers, corrected

10. Page 9, DE5. Packet Behavior in POS/SDL Mode—Dry Mode, identified dry mode issues.

11. Page 10, DE6. Incorrect ATM Out of Cell Delineation (OCD) Implementation, added new issue.

12. Page 10, DE7. Incorrect Frame State of ATM Data Streams, added new issue.

13. Page 11, DE8. Clearing DE Interrupt Register (0x1002), added new issue.

14. Page 11, DE9. Single Packet Transmission in HDLC-CRC, SDL-CRC, and PPP Modes, added new issue.

15. Page 12, DE10. Excessive HDLC Flag Characters, added new issue.

16. Page 13, UT2. UTOPIA Clock Limitations, clarified wording.

17. Page 14, UT4. FIFO Overflow and Error Reporting, clarified wording.

18. Page 16, UT9. Clock Requirements for MPHY Modes, added new issue.

19. Page 16, UT10. Egress Packet Mode Overflows, added new issue.

20. Page 17, UT11. Clearing UT Interrupt Register, added new issue.

21. Page 17, UT12. Incorrect Implementation of POS Multi-PHY Mode, added new issue.

22. Page 21, OHP1. Maximum BER Count, added new issue. In addition, differentiated OHP bits from PT bits with

the same name; the names will be corrected in revision 4 of the advance data sheet.

Agere Systems Inc.

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Advisory

May 2001

AY99-013SONT-4 Replaces AY99-013SONT-3 to Incorporate the Following Updates

(continued)

23. Page 21, OHP2. RDI-L Reporting, added new issue.

24. Page 22, OHP3. M1 Error Counter in STS-48/STM-16 Mode, added new issue.

25. Page 22, removed issue P1. Pin 5 (Previously JTEST) Is No Connect (NC). Pin F5 was corrected to NC in the

accompanying advance data sheet, DS98-193SONT-3.

26. Page 22, removed issue P2. Modified Pinout and Power Supply Configuration—Future Versions. Plans for 2.5 V

power ring implementation considered, but no schedule available at this time.

27. Page 22, removed issue P3. Change to TDAT042G5 Version 1 Pinout. Listed pins have been corrected to NC in

the accompanying advance data sheet, DS98-193SONT-3.

28. Page 24, DA1. Incorrect PT Control Register Mapping, added new issue.

AY01-015SONT (Replaces AY99-013SONT-4 and Must Accompany

DS98-193SONT-4) Replaces AY99-013SONT-4 to Incorporate the Following

Updates

Change List

This change list summarizes changes across the various versions of this document starting with the version dated

1/25/01.

1/25/01

1. Page 6, PT3. Remote Defect Indicator (RDI) Behavior, clarified wording.

2. Page 12, DE 11. ATM Header Error Correction (HEC) Behavior, added entire section to document.

1/29/01

1. Page 24, DA1. Incorrect PT Control Register Mapping, changed corrective action description to include the July

2000 date.

2. Page 24, DA2. Variable Change, added entire section to document.

2/13/01

1. Page 12, updated issue on DE 11. ATM Header Error Correction (HEC) Behavior, to include more information.

2. Page 17, added issue UT13. Invalid Extra Cycle Between EOP and SOP in CRC-16/32 Mode.

3. Page 18, added issue UT14. Nonfunctional RxPA Signal for Channels B and D in Packet Direct Status MPHY

Mode.

3/1/01

1. Page 12, removed DE 11 from document.

2. Page 18, UT14. Nonfunctional RxPA Signal for Channels B and D in Packet Direct Status MPHY Mode, added

workaround to document.

Agere Systems Inc.

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Advisory

May 2001

Notes

Agere Systems Inc.

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Advisory

May 2001

For additional information, contact your Agere Systems Account Manager or the following:

INTERNET:

E-MAIL:

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Tel. (65) 778 8833, FAX (65) 777 7495

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Tel. (86) 21 50471212, FAX (86) 21 50472266

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Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.

Printed in U.S.A.

May 2001

AY01-015SONT (Replaces AY99-013SONT-4 and Must Accompany DS98-193SONT-4)

Data Sheet

May 2001

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

— ITU-T G.707: Network Node Interface for the

Synchronous Digital Hierarchy.

Features

— ITU-T G.803: Architecture of Transport Net-

works Based on the Synchronous Digital Hier-

archy.

— T1.105: SONET-Basic Description including

Multiplex Structure, Rates, and Formats.

— T1.105.02 SONET-Payload Mappings.

— T1.105.03 SONET-Jitter at Network Interfaces.

— T1.105.06 SONET Physical Layer Specifica-

tions.

^IPoint-to-point path termination device for interface

termination.

^IVersatile IC supports 155/622/2488 Mbits/s

SONET/SDH interface solutions for packet over

SONET (POS), asynchronous transfer mode

(ATM), or simplified data link (SDL) for data over

fiber applications.

^ISupports point-to-point and multi-PHY UTOPIA.

^ILow-power 3.3 V operation, CMOS technology.

— T1.105.07 SONET-Sub-STS-1 Interface Rates

and Formats Specification.

— ITU-T I.432: B-ISDN User-Network Interface-

Physical Layer Specification.

— IETF RFC 2615 (June 1999): PPP over

SONET/SDH.

— IETF RFC 1661: The Point-to-Point Protocol

(PPP).

^IHigh-speed I/O is LVPECL. All other logic has 5 V

tolerant TTL-level inputs.

^I–40 °C to +85 °C temperature range.

^I600 LBGA package.

— IETF RFC 1662: PPP in HDLC-like Framing.

SONET/SDH Interface

Data Processing

^ITermination of quad STS-3/STM-1, quad STS-12/

STM-4, or single STS-48/STM-16.

^IProvisionable data engine supports payload inser-

tion/extraction and CRC-16/-32 generation/verifica-

tion for ATM cell or PPP, SDL, or HDLC streams.

^ISupports overhead processing for transport and

path overhead bytes.

^IOptional insertion and extraction of overhead bytes

via serial overhead interface.

^IMaintains counts for cell/packet traffic (e.g., total

number of cells, number of discarded cells).

^IIntegrated UTOPIA Level 2- and UTOPIA Level 3-

compatible ATM physical layer interface with

packet extensions for all test and operations.

^IFull path termination and SPE extraction/insertion.

^ISONET/SDH compliant condition and alarm

reporting.

^IInsertion and extraction of up to four separate data

channels.

^IHandles all concatenation levels of STS-3c

through STS-48c (in multiples of 3; i.e., 3c, 6c, 9c,

etc.), STM-1 through STM-16.

^ICompliant with 1998:ATM Forum, ITU standards,

and IETF standards.

^IBuilt-in diagnostic loopback modes.

^ICompliant with the following Telcordia^†(Bellcore),

ANSI*, and ITU standards:

Microprocessor Interface

— GR-253 CORE: SONET Transport Systems:

Common Generic Criteria.

^I16-bit address and 16-bit data interface with up to

66 MHz read and write access.

^ICompatible with most industry-standard proces-

sors.

*ANSI is a registered trademark of American National Standards

Institute, Inc.

†Telcordia is a registered trademark of Bell Communications

Research, Inc.

Please see the Description section, page 11, for

details.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Table of Contents

Contents

Page

Features ...................................................................................................................................................................3

SONET/SDH Interface ...........................................................................................................................................3

Data Processing .....................................................................................................................................................3

Microprocessor Interface .......................................................................................................................................3

Description ..............................................................................................................................................................11

Pin Information .......................................................................................................................................................11

Overview .................................................................................................................................................................45

ATM/HDLC/HDLC-CRC/PPP Support .................................................................................................................47

SDL Support ........................................................................................................................................................48

Over-Fiber Mode ..................................................................................................................................................49

Test and General-Purpose I/O Support ...............................................................................................................49

External Interfaces ...............................................................................................................................................49

Functional Description ............................................................................................................................................50

Line Interface Block .............................................................................................................................................51

SONET Framer ....................................................................................................................................................53

Overhead Processor (OHP) Block .......................................................................................................................53

Path Terminator (PT) Block .................................................................................................................................62

Data Engine (DE) Block .......................................................................................................................................70

UTOPIA (UT) Interface Block ...............................................................................................................................84

JTAG (Boundary-Scan) Test Block ....................................................................................................................100

Line Interface ........................................................................................................................................................100

LVPECL I/O Termination and Load Specifications ............................................................................................100

Interface Description .............................................................................................................................................101

Microprocessor Interface ...................................................................................................................................101

General-Purpose I/O Bus (GPIO) ......................................................................................................................102

Interrupts ............................................................................................................................................................103

Reset ..................................................................................................................................................................104

Performance Monitor Reset (PMRST) ...............................................................................................................104

Loopback Operation ...........................................................................................................................................106

System Interfaces ..............................................................................................................................................107

Register Access Description .................................................................................................................................111

Register Maps ......................................................................................................................................................112

Core Registers ...................................................................................................................................................112

UT Registers ......................................................................................................................................................113

OHP Registers ...................................................................................................................................................116

PT Registers ......................................................................................................................................................126

DE Registers ......................................................................................................................................................138

Register Descriptions ...........................................................................................................................................147

Core Registers ...................................................................................................................................................147

UT Registers ......................................................................................................................................................154

OHP Registers ...................................................................................................................................................165

PT Registers ......................................................................................................................................................192

DE Registers ......................................................................................................................................................211

Absolute Maximum Ratings ..................................................................................................................................253

Handling Precautions ...........................................................................................................................................253

Operating Conditions ............................................................................................................................................254

Electrical Characteristics ......................................................................................................................................254

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Table of Contents (continued)

Contents

Page

Interface Timing Specifications .............................................................................................................................255

Microprocessor Interface Timing ........................................................................................................................255

Line Interface I/O Timing ....................................................................................................................................264

UTOPIA Interface Timing ...................................................................................................................................268

Transport Overhead Access Channel (TOAC) Interface Timing ........................................................................271

Reference of SONET/SDH Terms and Comparisons ...........................................................................................273

Definitions of SONET/SDH Bytes ......................................................................................................................273

SONET/SDH Comparisons ................................................................................................................................274

SONET/SDH New Terminology .........................................................................................................................274

Outline Diagram ....................................................................................................................................................275

600-Pin LBGA ....................................................................................................................................................275

Ordering Information .............................................................................................................................................276

DS98-193SONT-4 Replaces DS98-193SONT-3 to Incorporate the Following Updates ......................................276

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

List of Figures

Contents

Page

Figure 1. Pin Diagram of 600-Pin LBGA (Bottom View) .........................................................................................11

Figure 2. Overview Block Diagram .........................................................................................................................45

Figure 3. Interface Block Diagram ..........................................................................................................................46

Figure 4. External Interface Summary Diagram .....................................................................................................49

Figure 5. Functional Block Diagram .......................................................................................................................50

Figure 6. Signal Degrade and Failure Parameters for BER ...................................................................................56

Figure 7. Pointer Interpreter State Diagram ...........................................................................................................62

Figure 8. STS-48 Signal Carrying One STS-48c Frame ........................................................................................65

Figure 9. STS-48 Signal Carrying Four STS-12c Frames ......................................................................................66

Figure 10. Quad STS-12 Configuration With Each STS-12 Signal Carrying One STS-3c Frame ..........................66

Figure 11. Quad STS-12 Configuration With Each STS-12 Signal Carrying One STS-12c Frame (Channel A), One

STS-9c Frame (Channel B), One STS-6c Frame (Channel C), and One STS-3c Frame (Channel D) .67

Figure 12. Quad STS-3 Configuration With Each STS-3 Signal Carrying One STS-2c Frame ..............................67

Figure 13. Block Diagram of Date Engine (DE) ......................................................................................................70

Figure 14. State Diagram for the X31 Scrambler Synchronization Process ...........................................................72

Figure 15. General Structure of SDL Packets ........................................................................................................72

Figure 16. Uncompressed and Compressed PPP Packets ....................................................................................75

Figure 17. Example of Tx/Rx Sequencer Configuration: STS-48c into Single OC-48 Signal .................................78

Figure 18. Example of Tx/Rx Sequencer Configuration: 4xSTS-12c into Four Independent OC-12 Signals .........79

Figure 19. SONET Multiplexing: 2-Stage Byte Interleaving Example .....................................................................80

Figure 20. Example of Tx/Rx Sequencer Configuration: 4xSTS-3c into Four Independent OC-3 Signals .............81

Figure 21. TDAT042G5 Over-Fiber Modes: SDL, ATM (X31) ................................................................................82

Figure 22. UT Block Diagram .................................................................................................................................84

Figure 23. Receive-Side Interface Handshaking in Point-to-Point, Single Cycle Mode .........................................91

Figure 24. Receive-Side Interface Handshaking in Point-to-Point, Two-Cycle Mode ............................................92

Figure 25. Transmit-Side Interface Handshaking in Point-to-Point, Single Cycle Mode ........................................95

Figure 26. Multi-PHY Configuration of All Four Channels ......................................................................................96

Figure 27. TxPA Two-Cycle Responses of a Multi-PHY for All Four Channels ......................................................98

Figure 28. RxPA Responses of a Multi-PHY for All Four Channels (PA Response Configured for One Cycle) ....99

Figure 29. GPIO Functionality ..............................................................................................................................102

Figure 30. Interrupt Functionality ..........................................................................................................................103

Figure 31. Miscellaneous Functionality ................................................................................................................104

Figure 32. Loopback Operation ............................................................................................................................106

Figure 33. Quad ATM UTOPIA 2 ..........................................................................................................................107

Figure 34. Single ATM UTOPIA 3 ........................................................................................................................108

Figure 35. Quad POS UTOPIA 2 ..........................................................................................................................109

Figure 36. Single POS UTOPIA 3 ........................................................................................................................110

Figure 37. 32-bit MPHY UTOPIA 3 .......................................................................................................................110

Figure 38. Microprocessor Interface Synchronous Write Cycle (MPMODE (Pin D8) = 1) ....................................256

Figure 39. Microprocessor Interface Synchronous Read Cycle (MPMODE (Pin D8) = 1) ...................................258

Figure 40. Microprocessor Interface Asynchronous Write Cycle Description (MPMODE (Pin D8) = 0) ...............260

Figure 41. Microprocessor Interface Asynchronous Read Cycle (MPMODE (Pin D8) = 0) ..................................262

Figure 42. Receive Line-Side Timing Waveform ..................................................................................................264

Figure 43. Transmit Line-Side Timing Waveform—STS-48/STM-16 Contraclocking ...........................................265

Figure 44. Transmit Line-Side Timing Waveform—Frame Synch ........................................................................265

Figure 45. Transmit Line-Side Timing Waveform—STS-48/STM-16 Forward Clocking ......................................265

Figure 46. Transmit UTOPIA Interface Timing .....................................................................................................268

Figure 47. Receive UTOPIA Interface Timing ......................................................................................................269

Figure 48. Transmit TOAC Interface Timing .........................................................................................................271

Figure 49. STS-12/STM-4 and STS-48/STM-16 Receive TOAC Interface Timing ...............................................272

Figure 50. STS-3/STM-1 Receive TOAC Interface Timing ...................................................................................272

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

List of Tables

Contents

Page

Table 1. Pin Assignments for 600-Pin LBGA by Pin Number Order .......................................................................12

Table 2. Pin Assignments for 600-Pin LBGA by Signal Name ...............................................................................17

Table 3. Pin Descriptions—Line Interface Signals .................................................................................................22

Table 4. Pin Descriptions—TOH Interface Signals .................................................................................................27

Table 5. Pin Descriptions—Enhanced UTOPIA Interface Signals ..........................................................................28

Table 6. Pin Descriptions—Microprocessor Interface Signals ................................................................................40

Table 7. Pin Descriptions—General-Purpose I/O Signals: Interface Signals .........................................................41

Table 8. Pin Descriptions—JTAG Interface Signals ...............................................................................................42

Table 9. Pin Descriptions—Power Signals .............................................................................................................43

Table 10. Pin Descriptions—No Connect Pins .......................................................................................................44

Table 11. Optional Offset Field ...............................................................................................................................48

Table 12. Line Interface Modes ..............................................................................................................................51

Table 13. Clock Settings for CLKDIV Pin ...............................................................................................................52

Table 14. R/T TOH Interface Rates ........................................................................................................................53

Table 15. TOAC Byte Insertion: An STS-3/STM-1 Example ..................................................................................53

Table 16. Ns, L, M, and B Values to Set the BER Indicator ...................................................................................57

Table 17. Ns, L, M, and B Values to Clear the BER Indicator ................................................................................58

Table 18. TOAC Channel I/O vs. STS Number/Time Slot ......................................................................................59

Table 19. Types of Signal Labels ...........................................................................................................................64

Table 20. 1-bit Mode ...............................................................................................................................................64

Table 21. 3-bit Mode (Enhanced RDI) ....................................................................................................................64

Table 22. Valid Concatenation Starting Locations: STS-Mc into an STS-48c ........................................................68

Table 23. Packet Length Field ................................................................................................................................73

Table 24. UTOPIA Traffic Types ............................................................................................................................85

Table 25. Standard 53-byte ATM Cell Structure .....................................................................................................86

Table 26. Bus Format for 16-bit Interface ...............................................................................................................86

Table 27. Bus Format for 8-bit Interface .................................................................................................................87

Table 28. Bus Format for 32-bit Interface ...............................................................................................................87

Table 29. Egress High Watermark Thresholds .......................................................................................................94

Table 30. Nominal dc Power for Suggested Terminations ...................................................................................100

Table 31. MPU Modes ..........................................................................................................................................101

Table 32. PMRST Provisioning ............................................................................................................................105

Table 33. Quad ATM UTOPIA 3 Interface ............................................................................................................107

Table 34. Quad POS UTOPIA 3 Interface ............................................................................................................109

Table 35. Register Address Space .......................................................................................................................111

Table 36. Map of Core Registers ..........................................................................................................................112

Table 37. Map of UT Registers .............................................................................................................................113

Table 38. Map of OHP Registers ..........................................................................................................................116

Table 39. Map of Path Terminator Registers ........................................................................................................126

Table 40. Map of DE Registers ............................................................................................................................138

Table 41. Register 0x0000: Device Version (RO) ................................................................................................147

Table 42. Registers 0x0001—0x0005: Device Name (RO) ..................................................................................147

Table 43. Register 0x0008: Composite Interrupts (RO or COR/W) ......................................................................148

Table 44. Register 0x000A: GPIO Input (RO) ......................................................................................................148

Table 45. Register 0x000C: Block Interrupt Masks (R/W) ....................................................................................149

Table 46. Register 0x000E: Core Resets (WO) ...................................................................................................149

Table 47. Register 0x000F: GPIO Output (R/W) ..................................................................................................150

Table 48. Register 0x0010: Line Provisioning/Mode (R/W) ..................................................................................150

Table 49. Register 0x0011: Channel (A—D) Control (R/W) .................................................................................151

Table 50. Register 0x0012: Loopback Control (R/W) ...........................................................................................151

Table 51. Register 0x0013: GPIO Mode (R/W) ....................................................................................................152

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

List of Tables (continued)

Contents

Page

Table 52. Registers 0x0014, 0x0015: GPIO Output Configuration .......................................................................152

Table 53. Register 0x001F: Scratch (R/W) ...........................................................................................................153

Table 54. Register 0x0200: UT Macrocell Version Number (RO) ........................................................................154

Table 55. Register 0x0201: UT Interrupt (RO) .....................................................................................................154

Table 56. Registers 0x0202, 0x0203, 0x0204, 0x0205: Channel [A—D] (COR) ..................................................155

Table 57. Register 0x0206: Interrupt Mask (R/W) ................................................................................................156

Table 58. Registers 0x0207, 0x0208, 0x0209, 0x020A: Interrupt Mask—Channel [A—D] (R/W) ........................156

Table 59. Register 0x020B: Channel [A—D] Error Count in PMRST Mode (RO) ................................................156

Table 60. Fields of the Provisioning Registers .....................................................................................................157

Table 61. Registers 0x020F, 0x0213, 0x0217, 0x021B: Channel [A—D] Receive Provisioning Register (R/W) .158

Table 62. Registers 0x0210, 0x0214, 0x0218, 0x021C: Channel [A—D] Transmit Provisioning Register (R/W) 159

Table 63. Registers 0x0211, 0x0215, 0x0219, 0x021D: Channel [A—D] Ingress Provisioning Register (R/W) ..161

Table 64. Registers 0x0212, 0x0216, 0x021A, 0x021E: Channel [A—D] Egress Provisioning Register (R/W) ...161

Table 65. Register 0x021F: Reset Register (R/W) ...............................................................................................162

Table 66. Register 0x0220: Channel [A—D] Error Count (RO) ............................................................................162

Table 67. Register 0x0224: UT_Scratch Register (R/W) ......................................................................................162

Table 68. Register 0x0225: PA Response Register (R/W) ...................................................................................163

Table 69. Register 0x0226: Size Mode Register (R/W) ........................................................................................164

Table 70. Register 0x0400: OHP Macrocell Version Number (RO) .....................................................................165

Table 71. Register 0x0401: OHP Interrupt (RO) ..................................................................................................165

Table 72. Registers 0x0402—0x0409: Delta/Event (COR/W) ..............................................................................165

Table 73. Registers 0x040A—0x040D: Receive/Transmit State (RO) .................................................................168

Table 74. Registers 0x040E, 0x0410, 0x0412, 0x0414: Mask Bits (R/W) ............................................................169

Table 75. Registers 0x040F, 0x0411, 0x0413, 0x0415: Mask Bits (R/W) ............................................................170

Table 76. Registers 0x0416—0x0419: Toggles (R/W) .........................................................................................171

Table 77. Registers 0x041A, 0x041C, 0x041E, 0x0420: Continuous N Times Detect (CNTD) Values (R/W) .....171

Table 78. Registers 0x041B, 0x041D, 0x041F, 0x0421: Continuous N Times Detect (CNTD) Values (R/W) .....172

Table 79. Registers 0x0422—0x042D: Receive Control (R/W) ............................................................................173

Table 80. Registers 0x042E: Transmit Control Port A (R/W) ...............................................................................177

Table 81. Registers 0x042F, 0x0431, 0x0433, 0x0435: Transmit Control (R/W) .................................................180

Table 82. Registers 0x0430, 0x0432, 0x0434: Transmit Control Port [B—D] (R/W) ............................................181

Table 83. Registers 0x0436—0x0439: Transmit Control (R/W) ...........................................................................184

Table 84. Registers 0x043A—0x0451: OHP Signal Degrade BER Algorithm Parameters (R/W) ........................185

Table 85. Registers 0x0452—0x0469: OHP Signal Fail BER Algorithm Parameters (R/W) ................................186

Table 86. Ns, L, M, and B Values to Set the BER Indicator .................................................................................187

Table 87. Ns, L, M, and B Values to Clear the BER Indicator ..............................................................................188

Table 88. Registers 0x046A—0x047D: B1, B2, M1 Error Count (RO) .................................................................189

Table 89. Registers 0x047E—0x0485: Transmit F1, S1, K2, K1 OH Insert Value (R/W) ....................................189

Table 90. Registers 0x0486—0x0491: Receive F1, S1, K2, K1 Monitor Value (RO) ...........................................190

Table 91. Registers 0x0492—0x04F9: Receive J0 Monitor Value (RO) ..............................................................190

Table 92. Registers 0x0512—0x0579: Transmit J0 Insert Value (R/W) ...............................................................190

Table 93. Registers 0x05AA—0x05C1: Transmit Z0 Insert Value (R/W) .............................................................191

Table 94. Register 0x05C2: Scratch Register (R/W) ............................................................................................191

Table 95. Register 0x0800: PT Macrocell Version Number (RO) .........................................................................192

Table 96. Register 0x0801: PT Interrupt (RO) ......................................................................................................192

Table 97. Registers 0x0802, 0x080F, 0x081C, 0x0829 and 0x0803, 0x0810, 0x081D, 0x082A:

PT Delta/Event Parameters (COR/W) ..................................................................................................192

Table 98. Registers 0x0836—0x083B, 0x0868—0x0887, 0x0888—0x088D, 0x08BA—0x08D9,

0x08DA—0x08DF, 0x090C—0x092B, 0x092C—0x0931, 0x095E—0x097D:

PT State Registers (RO) ......................................................................................................................194

Table 99. Register 0x097E: PT Interrupt Mask Control (R/W) .............................................................................195

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

List of Tables (continued)

Contents

Page

Table 100. Registers 0x097F—0x0980, 0x098C—0x098D, 0x0999—0x099A, 0x09A6—0x09A7: PT Interrupt

Mask Control (R/W) ............................................................................................................................196

Table 101. Registers (0x09B3, 0x09BF, 0x09CB, 0x09D7, 0x09E3), (0x09EF, 0x09FB, 0x0A07, 0x0A14, 0x0A20),

(0x0A2C, 0x0A38, 0x0A44, 0x0A50, 0x0A5C), (0x0A68, 0x0A74, 0x0A80, 0x0A8C, 0x0A98):

Error Counters (RO) ...........................................................................................................................198

Table 102. Register 0x0AA4: PT One-Shot Control Parameters (WO) ................................................................198

Table 103. Registers 0x0AA6—0x0AAD, 0x0AAE, 0x0AB5, 0x0AB6—0x0ABD, 0x0ABE—0x0AC5:

PT Control Parameters (R/W) ............................................................................................................199

Table 104. Registers 0x0AC6—0x0AF7: PT Provisioning (R/W) .........................................................................205

Table 105. Registers 0x0ACC—0x0AD1: PT Signal Fail BER Algorithm Parameters (R/W) ...............................206

Table 106. Registers 0x0AD2—0x0AD7: PT Signal Degrade BER Algorithm Parameters (R/W) .......................207

Table 107. Ns, L, M, and B Values to Set the BER Indicator ...............................................................................208

Table 108. Ns, L, M, and B Values to Clear the BER Indicator ............................................................................209

Table 109. Registers 0x0AD8—0x0AF7: Transmit J1 Data Insert (R/W) .............................................................210

Table 110. Register 0x0AF8: Scratch Register (R/W) ..........................................................................................210

Table 111. Register 0x1000: DE Macrocell Version Number (RO) ......................................................................211

Table 112. Register 0x1001, 0x1002: DE Interrupts (0x1001 is RO, 0x1002 is RO and COR/W) .......................211

Table 113. Register 0x1004: Dry Escape Marker (R/W) ......................................................................................213

Table 114. Registers 0x1010—0x1015: Sequencer Provisioning Registers (R/W) ..............................................214

Table 115. Registers 0x1016—0x1021: Egress Configuration (R/W) ..................................................................215

Table 116. Registers 0x1022—0x102D: Ingress Configuration (R/W) .................................................................219

Table 117. Registers 0x102E—0x1031: Over-Fiber Mode (Packet-Over-Fiber or POF) Control (R/W) ..............223

Table 118. Registers 0x1032—0x1036: Sequencer Cell State Registers (R/W) ..................................................225

Table 119. Registers 0x1040—0x1043: Ingress Payload Type and Mode Control (R/W) ...................................225

Table 120. Receive Type and Mode Control Summary Table (Registers 0x1040—0x1043) ...............................226

Table 121. Registers 0x1080—0x1087: ATM Framer Idle Cell Match Mask (R/W) .............................................227

Table 122. Registers 0x1088—0x108F: ATM Idle Cell Registers (R/W) ..............................................................227

Table 123. Registers 0x1090—0x1097: ATM Unassigned Cell Match Mask (R/W) .............................................228

Table 124. Registers 0x1098—0x109F: ATM Unassigned Cell Registers (R/W) .................................................228

Table 125. Registers 0x10A0—0x10A3: ATM Framer State Registers (RO) .......................................................229

Table 126. Register 0x10A4: ATM X43 Frame Control (R/W) ..............................................................................229

Table 127. Register 0x10A5: ATM X31 Frame Control (R/W) ..............................................................................230

Table 128. Register 0x10A6: ATM X31 V/W Values (R/W) ..................................................................................230

Table 129. Register 0x10A7: ATM X31 X/Y Values (R/W) ...................................................................................231

Table 130. Register 0x10A8: ATM X31 Z Value (R/W) ........................................................................................231

Table 131. Register 0x10A9: Frame State Interrupt Mask (R/W) .........................................................................232

Table 132. Register 0x10AA: Scrambler State Interrupt Mask (R/W) ..................................................................232

Table 133. Register 0x10AB: ATM Receive Debug Register (R/W) .....................................................................233

Table 134. Registers 0x10B0—0x10B3: PPP Attach (R/W) .................................................................................234

Table 135. Registers 0x10E0—0x10E3: Egress Payload Type and Mode Control (R/W) ...................................234

Table 136. Transmit Type and Mode Control Summary Table (Registers 0x10E0—0x10E3) .............................235

Table 137. Registers 0x10F0—10FB: PPP Header Value Detach (R/W) ............................................................235

Table 138. Registers 0x10FC—0x10FF: PPP Header Detach Search (R/W) ......................................................236

Table 139. Registers 0x1100—0x1107: ATM/HDLC/SDL Framer—Condition Counter 1

(PMRST Update) (RO) .......................................................................................................................238

Table 140. Registers 0x1108—0x110F: ATM/HDLC/SDL Framer—Condition Counter 2

(PMRST Update) (RO) .......................................................................................................................239

Table 141. Registers 0x1110—0x1117: CRC Checker—Bad Packet Counter (PMRST Update) (RO) ...............240

Table 142. Registers 0x1118—0x111F: PPP Detach—Mismatched Header Counter (PMRST Update) (RO) ...241

Table 143. Registers 0x1120—0x1127: Receive Good Packet/Cell Counter (PMRST Update) (RO) .................242

Table 144. Registers 0x1128—0x112F: Transmit Good Packet/Cell Counter (PMRST Update) (RO) ................243

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

List of Tables (continued)

Contents

Page

Table 145. Registers 0x1180—0x1186: Interrupt Masks for Packet Counters (R/W) ..........................................243

Table 146. Registers 0x1181—0x1187: Interrupts for Packet Counters (COR/W) ..............................................244

Table 147. Registers 0x1200—0x1213, 0x12F0: ATM Transmit Registers (R/W) ...............................................244

Table 148. Registers 0x1400—0x1403: SDL State Registers (RO) .....................................................................246

Table 149. Registers 0x1470—0x1473: A Message Mailbox Registers (RO) ......................................................247

Table 150. Registers 0x1480—0x1483: A Message Mailbox Registers (RO) ......................................................247

Table 151. Registers 0x1490—0x1493: A Message Mailbox Registers (RO) ......................................................247

Table 152. Registers 0x14A0—0x14A3: B Message Mailbox Registers (RO) .....................................................247

Table 153. Registers 0x14B0—0x14B3: B Message Mailbox Registers (RO) .....................................................248

Table 154. Registers 0x14C0—0x14C3: B Message Mailbox Registers (RO) .....................................................248

Table 155. Registers 0x14D0—0x14D3: SDL Interrupt Masks (R/W) ..................................................................248

Table 156. Registers 0x14E0—0x14E3: SDL Interrupts (COR/W) ......................................................................249

Table 157. Register 0x14F0: SDL Receive Configuration Registers (R/W) .........................................................249

Table 158. Registers 0x1600—0x1607: SDL Transmit Registers (R/W) ..............................................................250

Table 159. Recommended Operating Conditions ................................................................................................254

Table 160. 3.3 V Logic Interface Characteristics ..................................................................................................254

Table 161. LVPECL Interface Characteristics ......................................................................................................254

Table 162. LVPECL 3.3 V Logic Interface Characteristics ...................................................................................255

Table 163. Microprocessor Interface Synchronous Write Cycle Specifications ...................................................257

Table 164. Microprocessor Interface Synchronous Read Cycle Specifications ...................................................259

Table 165. Microprocessor Interface Asynchronous Write Cycle Specifications ..................................................261

Table 166. Microprocessor Interface Asynchronous Read Cycle Specifications .................................................263

Table 167. Receive Line-Side Timing Specifications ...........................................................................................266

Table 168. Transmit Line-Side Timing Specifications ..........................................................................................267

Table 169. Transmit UTOPIA Interface Timing Specifications .............................................................................268

Table 170. Receive UTOPIA Interface Timing Specifications ..............................................................................269

Table 171. UTOPIA Interface Clock Specifications ..............................................................................................270

Table 172. Transmit TOAC Interface Timing Specifications .................................................................................271

Table 173. Receive TOAC Interface Timing Specifications ..................................................................................272

Table 174. SONET/SDH Comparisons ................................................................................................................274

Table 175. SONET/SDH New Terminology ..........................................................................................................274

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Description

The TDAT042G5 SONET/SDH interface device provides a versatile solution for quad STS-3/STM-1,

quad STS-12/STM-4, and for single STS-48/STM-16 point-to-point datacom/telecom applications. Constructed

using Agere Systems Inc.’s state-of-the-art CMOS technology, this device incorporates integrated SONET/SDH

framing, section and line overhead insertion and extraction, path termination, and generation.

The integrated circuit provides complete encapsulation and decapsulation for packet and ATM streams into and

out of SONET/SDH payloads.

Communication with the device is accomplished through a generic microprocessor interface. The device supports

separate address and data buses.

With the device, construction of all types of point-to-point STS-3/STS-12/STS-48 (STM-1/STM-4/

STM-16) data equipment is simplified and cost-reduced, allowing extremely efficient solutions.

Pin Information

TDAT042G5 is available in a 600-pin LBGA package. The pin diagram is shown in Figure 1. For convenience, pin

assignments are listed by pin order in Table 1 and by signal name in Table 2. The pin descriptions as well as the

pin assignments are listed in Table 3—Table 10 and are grouped by interface type.

11 13 15 17 19 21 23 25 27 29 31 33 35

10 12 14 16 18 20 22 24 26 28 30 32 34

5-7175(F)

Figure 1. Pin Diagram of 600-Pin LBGA (Bottom View)

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Table 1. Pin Assignments for 600-Pin LBGA by Pin Number Order

Signal Name

VDDD

GNDD

VDDD

GNDD

VDDD

GNDD

VDDD

GNDD

VDDD

GNDD

B5 NC

C5 NC

D5 NC

VDDA

GNDA

D6 NC

B7 INT

C7 RST

C8 MPCLK

C9 DS

D7 PMRST

D8 MPMODE

D9 R/W

B8 CS

A9 DATA[1]

A10 DATA[6]

A11 DATA[10]

A12 DATA[15]

A13 GNDD

A14 ADDR[8]

A15 ADDR[12]

A16 GNDD

A17 VDDD

A18 VDDD

A19 NC

B9 DATA[0]

B10 DATA[5]

B11 DATA[9]

B12 DATA[14]

B13 ADDR[3]

B14 ADDR[7]

B15 ADDR[11]

B16 ADDR[15]

B17 NC

C10 DATA[4]

C11 DATA[8]

C12 DATA[13]

C13 ADDR[2]

C14 ADDR[6]

C15 ADDR[10]

C16 ADDR[14]

C17 NC

D10 DATA[3]

D11 DATA[7]

D12 DATA[12]

D13 ADDR[1]

D14 ADDR[5]

D15 NC

D16 ADDR[13]

D17 NC

B18 NC

C18 NC

D18 NC

B19 NC

C19 NC

D19 NC

A20 GNDD

A21 NC

B20 NC

C20 NC

D20 NC

B21 NC

C21 NC

D21 NC

A22 NC

B22 NC

C22 NC

D22 NC

A23 GNDD

A24 NC

B23 NC

C23 NC

D23 NC

B24 NC

C24 NC

D24 NC

A25 NC

B25 NC

C25 NC

D25 NC

A26 NC

B26 NC

C26 NC

D26 NC

A27 GNDD

A28 GNDD

A29 GNDD

A30 VDDD

A31 VDDD

A32 GNDD

A33 GNDD

A34 VDDD

A35 VDDD

B27 NC

C27 NC

D27 VDDD

D28 NC

B28 NC

C28 NC

B29 NC

C29 NC

D29 NC

B30 NC

C30 NC

D30 NC

B31 NC

C31 NC

D31 NC

B32 GNDD

B33 GNDD

B34 VDDD

B35 VDDD

C32 GNDD

C33 VDDD

C34 GNDD

C35 GNDD

D32 VDDD

D33 GNDD

D34 GNDD

D35 GNDD

Note: NC refers to no connect. Do not connect pins so designated.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Table 1. Pin Assignments for 600-Pin LBGA by Pin Number Order (continued)

Signal Name

GNDD

VDDD

TCK

GNDD

TMS

J31 TxEOP[A]

J32 TxSOP/C[A]

J33 TxPRTY[A]

J34 TxDATA[A][15]

J35 TxDATA[A][14]

N2 TxD[6]N

VDDD PLL

GNDD PLL

VDDD

N3 TxD[6]P

N4 TxD[7]N

N5 TxD[7]P

F31 NC

TxD[12]N

TxD[12]P

TxD[13]N

TxD[13]P

VDDD

N31 RxDATA[A][15]

N32 RxDATA[A][14]

N33 RxDATA[A][13]

N34 RxDATA[A][12]

N35 GNDD

ICT

F32 NC

F33 NC

ADS

F34 NC

E10 DATA[2]

E11 VDDD

E12 DATA[11]

E13 ADDR[0]

E14 ADDR[4]

E15 ADDR[9]

E16 VDDD

E17 NC

F35 VDDD

G1 GNDD

G2 TDO

K31 TxDATA[A][13]

K32 TxDATA[A][12]

K33 TxDATA[A][11]

K34 TxDATA[A][10]

K35 TxDATA[A][9]

TxD[4]N

TxD[4]P

TxD[5]N

VDDD

G3 TRST

G4 NC

G5 TDI

TxD[5]P

G31 NC

TxD[10]N

TxD[10]P

TxD[11]N

TxD[11]P

VDDD

P31 RxDATA[A][11]

P32 RxDATA[A][10]

P33 RxDATA[A][9]

P34 RxDATA[A][8]

P35 RxDATA[A][7]

G32 TxADDR[0]

G33 TxADDR[1]

G34 TxCLK[A]

G35 GNDD

E18 NC

E19 NC

E20 VDDD

E21 NC

H2 TxCKQP

H3 GNDD

H4 CLKDIV

H5 GNDD

GNDD

L31 VDDD

VDDD

E22 NC

L32 TxDATA[A][8]

L33 TxDATA[A][7]

L34 TxDATA[A][6]

L35 TxDATA[A][5]

M1 TxD[8]N

R2 TxD[2]N/TxD[B]N

R3 TxD[2]P/TxD[B]P

R4 TxD[3]P/TxD[A]P

R5 TxD[3]N/TxD[A]N

R31 RxDATA[A][6]

R32 RxDATA[A][5]

R33 RxDATA[A][4]

R34 RxDATA[A][3]

R35 RxDATA[A][2]

E23 NC

E24 NC

E25 VDDD

E26 NC

H31 TxSZ[A]

H32 TxERR[A]

H33 TxPA[A]

H34 TxENB[A]

H35 GNDD

E27 NC

M2 TxD[8]P

E28 NC

M3 TxD[9]N

E29 NC

M4 TxD[9]P

E30 NC

VDDD

E31 VDDD

E32 NC

TxD[14]N

TxD[14]P

TxD[15]N

TxD[15]P

TxCKQN

M31 TxDATA[A][4]

M32 TxDATA[A][3]

M33 TxDATA[A][2]

M34 TxDATA[A][1]

M35 TxDATA[A][0]

GNDD

TxD[0]P/TxD[D]P

TxD[1]N/TxD[C]N

TxD[1]P/TxD[C]P

VDDD

E33 NC

E34 NC

E35 VDDD

Note: NC refers to no connect. Do not connect pins so designated.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Table 1. Pin Assignments for 600-Pin LBGA by Pin Number Order (continued)

Signal Name

GNDD

Signal Name

T31 VDDD

AC31 TxDATA[B][8]

AC32 TxDATA[B][9]

AG1 RxD[0]N

AG2 RxD[0]P

RxD[13]N/

T32 RxDATA[A][1]

RxCLK[B]N

RxD[13]P/

T33 RxDATA[A][0]

AC33 TxDATA[B][10]

AG3 ECLREFLO

RxCLK[B]P

T34 RxPRTY[A]

T35 GNDD

GNDD

VDDD

AC34 TxDATA[B][11]

AC35 GNDD

AG4 ECLREFHI

AG5 GPIO[3]

U1 TxFSYNCN

Y31 VDDD

AD1 RxD[5]N

AD2 RxD[5]P

AG31 RxDATA[B][5]

AG32 RxDATA[B][6]

U2 TxD[0]N/

TxD[D]N

Y32 TxSZ[B]

U3 TxFSYNCP

U4 TxCKP

Y33 TxCLK[B]

Y34 TxADDR[3]

Y35 GNDD

AD3 RxD[6]N

AD4 RxD[6]P

AD5 VDDD

AG33 RxDATA[B][7]

AG34 RxDATA[B][8]

AG35 RxDATA[B][9]

AH1 GNDD

U5 TxCKN

RxD[11]N/

U31 RxSOP/C[A]

AA1

AD31 TxDATA[B][3]

RxCLK[C]N

RxD[11]P/RxCLK[C]P

RxD[12]N/RxD[C]N

RxD[12]P/RxD[C]P

U32 RxEOP[A]

U33 NC

AA2

AA3

AA4

AD32 TxDATA[B][4]

AD33 TxDATA[B][5]

AD34 TxDATA[B][6]

AD35 TxDATA[B][7]

AE1 RxD[3]N

AH2 GPIO[2]

AH3 GPIO[1]

U34 RxENB[A]

U35 VDDD

AH4 GPIO[0]

AA5 GNDD

AH5 TxTOHF

VDDD

AA31 TxEOP[B]

AA32 TxSOP/C[B]

AA33 TxENB[B]

AA34 TxPA[B]

AA35 TxERR[B]

AH31 RxDATA[B][1]

AH32 RxDATA[B][2]

AH33 RxDATA[B][3]

AH34 RxDATA[B][4]

AH35 GNDD

VDDD

AE2 RxD[3]P

GNDD

RxCKN/RxD[A]N

RxCKP/RxD[A]P

AE3 RxD[4]N

AE4 RxD[4]P

AE5 VDDD

RxD[9]N/RxCLK[D]N

V31 GNDD

V32 RxERR[A]

V33 RxPA[A]

V34 NC

AB1

AB2

AB3

AB4

AE31 VDDD

AJ1 GNDD

RxD[9]P/RxCLK[D]P

RxD[10]N/RxD[D]N

RxD[10]P/RxD[D]P

AE32 RxDATA[B][15]

AE33 TxDATA[B][0]

AE34 TxDATA[B][1]

AE35 TxDATA[B][2]

AF1 RxD[1]N

AJ2 TxTOHCK

AJ3 TxTOHD[A]

AJ4 TxTOHD[B]

AJ5 TxTOHD[C]

AJ31 RxEOP[B]

AJ32 RxSOP/C[B]

V35 VDDD

W1 VDDD

AB5 VDDD

AB31 TxDATA[B][13]

AB32 TxDATA[B][12]

W2 RxD[14]N/

RxCLK[A]N

AF2 RxD[1]P

W3 RxD[14]P/

RxCLK[A]P

AB33 TxDATA[B][14]

AB34 TxDATA[B][15]

AB35 TxPRTY[B]

AF3 RxD[2]N

AF4 RxD[2]P

AF5 VDDD

AJ33 RxPRTY[B]

AJ34 RxDATA[B][0]

AJ35 GNDD

W4 RxD[15]N/

RxD[B]N

W5 RxD[15]P/

RxD[B]P

RxDATA[B][10]

RxDATA[B][11]

RxDATA[B][12]

RxDATA[B][13]

RxDATA[B][14]

W31 RxADDR[0]

W32 RxADDR[1]

W33 RxCLK[A]

W34 TxADDR[2]

W35 RxSZ[A]

AC1 GNDD

AF31

AF32

AF33

AF34

AF35

AK1 VDDD

AC2 RxD[7]N

AC3 RxD[7]P

AC4 RxD[8]N

AC5 RxD[8]P

AK2 TxTOHD[D]

AK3 RxREF

AK4 RxTOHF[A]

AK5 RxTOHCK[A]

Note: NC refers to no connect. Do not connect pins so designated.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Table 1. Pin Assignments for 600-Pin LBGA by Pin Number Order (continued)

Pin Signal Name Pin Signal Name Pin Signal Name

Signal Name

AK31 RxSZ[B]

AK32 RxERR[B]

AK33 RxPA[B]

AL31 VDDD

AM31 TxADDR[4]

AM32 VDDD

AN31 NC

AL32 RxADDR[3]

AL33 RxADDR[2]

AL34 RxCLK[B]

AL35 VDDD

AN32 GNDD

AM33 GNDD

AN33 VDDD

AK34 RxENB[B]

AK35 VDDD

AM34 GNDD

AN34 GNDD

AM35 GNDD

AN35 GNDD

AL1 VDDD

AM1 GNDD

AN1 GNDD

AP1 VDDD

AL2 RxTOHD[A]

AL3 RxTOHF[B]

AL4 RxTOHCK[B]

AL5 VDDD

AM2 GNDD

AN2 GNDD

AP2 VDDD

AM3 GNDD

AN3 VDDD

AP3 GNDD

AM4 VDDD

AN4 GNDD

AP4 GNDD

AM5 RxTOHD[B]

AM6 RxTOHD[C]

AM7 NC

AN5 RxTOHF[C]

AN6 GNDD

AP5 NC

AL6 RxTOHCK[C]

AL7 RxTOHCK[D]

AL8 NC

AP6 RxTOHF[D]

AP7 NC

AN7 RxTOHD[D]

AN8 RxSZ[D]

AM8 RxCLK[D]

AM9 RxENB[D]

AM10 RxDATA[D][1]

AM11 RxDATA[D][5]

AM12 RxDATA[D][10]

AM13 RxDATA[D][15]

AM14 TxDATA[D][2]

AM15 TxDATA[D][7]

AM16 TxDATA[D][12]

AM17 TxPRTY[D]

AM18 TxERR[D]

AM19 NC

AP8 RxERR[D]

AP9 RxSOP/C[D]

AP10 RxDATA[D][3]

AP11 RxDATA[D][7]

AP12 RxDATA[D][12]

AP13 TxDATA[D][1]

AP14 TxDATA[D][5]

AP15 TxDATA[D][10]

AP16 TxDATA[D][14]

AP17 TxDATA[D][15]

AP18 TxPA[D]

AL9 RxPA[D]

AN9 RxEOP[D]

AN10 RxDATA[D][2]

AN11 RxDATA[D][6]

AN12 RxDATA[D][11]

AN13 TxDATA[D][0]

AN14 TxDATA[D][4]

AN15 TxDATA[D][9]

AN16 TxDATA[D][13]

AN17 TxEOP[D]

AN18 TxSZ[D]

AL10 RxDATA[D][0]

AL11 VDDD

AL12 RxDATA[D][9]

AL13 RxDATA[D][14]

AL14 TxDATA[D][3]

AL15 TxDATA[D][8]

AL16 VDDD

AL17 TxSOP/C[D]

AL18 VDDD

AL19 NC

AN19 NC

AP19 TxCLK[D]

AP20 RxADDR[4]

AP21 RxPA[C]

AL20 VDDD

AM20 RxSZ[C]

AN20 RxCLK[C]

AN21 RxENB[C]

AN22 RxDATA[C][1]

AN23 RxDATA[C][5]

AN24 RxDATA[C][10]

AN25 RxDATA[C][15]

AN26 TxDATA[C][3]

AN27 TxDATA[C][8]

AN28 TxDATA[C][12]

AN29 TxPRTY[C]

AN30 TxPA[C]

AL21 RxSOP/C[C]

AL22 RxDATA[C][3]

AL23 RxDATA[C][7]

AL24 RxDATA[C][12]

AL25 VDDD

AM21 RxEOP[C]

AM22 RxDATA[C][2]

AM23 RxDATA[C][6]

AM24 RxDATA[C][11]

AM25 TxDATA[C][0]

AM26 TxDATA[C][4]

AM27 TxDATA[C][9]

AM28 TxDATA[C][13]

AM29 TxSOP/C[C]

AM30 TxERR[C]

AP22 RxDATA[C][0]

AP23 RxDATA[C][4]

AP24 RxDATA[C][9]

AP25 RxDATA[C][14]

AP26 TxDATA[C][2]

AP27 TxDATA[C][7]

AP28 TxDATA[C][11]

AP29 TxDATA[C][15]

AP30 TxENB[C]

AL26 TxDATA[C][5]

AL27 TxDATA[C][10]

AL28 TxDATA[C][14]

AL29 TxEOP[C]

AL30 TxSZ[C]

Note: NC refers to no connect. Do not connect pins so designated.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Table 1. Pin Assignments for 600-Pin LBGA by Pin Number Order (continued)

Signal Name

AP31 TxCLK[C]

AP32 GNDD

AP33 GNDD

AP34 VDDD

AP35 VDDD

AR1 VDDD

AR2 VDDD

AR3 GNDD

AR4 GNDD

AR5 VDDD

AR6 VDDD

AR16 GNDD

AR26 TxDATA[C][1]

AR27 TxDATA[C][6]

AR28 GNDD

AR29 GNDD

AR30 VDDD

AR7 GNDD

AR17 TxENB[D]

AR18 VDDD

AR8 GNDD

AR9 RxPRTY[D]

AR10 RxDATA[D][4]

AR11 RxDATA[D][8]

AR12 RxDATA[D][13]

AR13 GNDD

AR19 VDDD

AR20 GNDD

AR21 RxERR[C]

AR22 RxPRTY[C]

AR23 GNDD

AR31 VDDD

AR32 GNDD

AR33 GNDD

AR34 VDDD

AR14 TxDATA[D][6]

AR15 TxDATA[D][11]

AR24 RxDATA[C][8]

AR25 RxDATA[C][13]

AR35 VDDD

Note: NC refers to no connect. Do not connect pins so designated.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Table 2. Pin Assignments for 600-Pin LBGA by Signal Name

Signal Name

ADDR[0]

ADDR[1]

ADDR[2]

ADDR[3]

ADDR[4]

ADDR[5]

ADDR[6]

ADDR[7]

ADDR[8]

ADDR[9]

ADDR[10]

ADDR[11]

ADDR[12]

ADDR[13]

ADDR[14]

ADDR[15]

ADS

E13

D13

C13

B13

E14

D14

C14

B14

A14

E15

C15

B15

A15

D16

C16

B16

GNDD

G35

GNDD

GNDD PLL

GPIO[0]

GPIO[1]

GPIO[2]

GPIO[3]

ICT

AP3

AP32

AP33

AP4

AR3

AR4

AR7

AR8

AR13

AR16

AR20

AR23

AR28

AR29

AR32

AR33

ECLREFHI

ECLREFLO

GNDA

GNDD

AG4

AG3

H35

N35

A13

A16

A20

A23

A27

A28

A29

A32

A33

T35

V31

Y35

AA5

AC1

AC35

AH1

AH35

AJ1

CLKDIV

AH4

AH3

AH2

AG5

DATA[0]

DATA[1]

DATA[2]

DATA[3]

DATA[4]

DATA[5]

DATA[6]

DATA[7]

DATA[8]

DATA[9]

DATA[10]

DATA[11]

DATA[12]

DATA[13]

DATA[14]

DATA[15]

B32

B33

E10

D10

C10

B10

A10

D11

C11

B11

A11

E12

D12

C12

B12

A12

AJ35

AM1

AM2

AM3

AM33

AM34

AM35

AN1

AN2

AN4

AN6

AN32

AN34

AN35

INT

MPCLK

MPMODE

C32

C34

C35

A19

A21

A22

A24

A25

A26

D33

D34

D35

B17

B18

B19

Note: NC refers to no connect. Do not connect pins so designated.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Table 2. Pin Assignments for 600-Pin LBGA by Signal Name (continued)

Signal Name

RxD[6]N

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

D21

D22

D23

D24

D25

D26

D28

D29

D30

D31

V34

AL8

AD3

AD4

AC2

AC3

AC4

AC5

AB1

AB2

AB3

AB4

RxD[6]P

AL19

AM7

AM19

AN19

AN31

AP5

AP7

RxD[7]N

RxD[7]P

RxD[8]N

RxD[8]P

RxD[9]N/RxCLK[D]N

RxD[9]P/RxCLK[D]P

RxD[10]N/RxD[D]N

RxD[10]P/RxD[D]P

PMRST

R/W

RxD[11]N/RxCLK[C]N

RxD[11]P/RxCLK[C]P

RxD[12]N/RxD[C]N

RxD[12]P/RxD[C]P

RxD[13]N/RxCLK[B]N

RxD[13]P/RxCLK[B]P

RxD[14]N/RxCLK[A]N

RxD[14]P/RxCLK[A]P

RxD[15]N/RxD[B]N

RxD[15]P/RxD[B]P

RxDATA[A][0]

AA1

AA2

AA3

AA4

RST

E17

E18

E19

E21

E22

E23

E24

E26

E27

E28

E29

E30

E32

E33

E34

RxADDR[0]

RxADDR[1]

RxADDR[2]

RxADDR[3]

RxADDR[4]

RxCKN/RxD[A]N

RxCKP/RxD[A]P

RxCLK[A]

RxCLK[B]

RxCLK[C]

RxCLK[D]

RxD[0]N

RxD[0]P

RxD[1]N

RxD[1]P

RxD[2]N

RxD[2]P

RxD[3]N

RxD[3]P

RxD[4]N

RxD[4]P

RxD[5]N

RxD[5]P

W31

W32

AL33

AL32

AP20

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

C27

C28

C29

C30

C31

W33

AL34

AN20

AM8

AG1

AG2

AF1

AF2

AF3

AF4

AE1

AE2

AE3

AE4

AD1

AD2

T33

T32

R35

R34

R33

R32

R31

P35

P34

P33

P32

P31

N34

N33

N32

RxDATA[A][1]

RxDATA[A][2]

RxDATA[A][3]

RxDATA[A][4]

RxDATA[A][5]

RxDATA[A][6]

RxDATA[A][7]

F31

F32

F33

F34

RxDATA[A][8]

RxDATA[A][9]

D15

D17

D18

D19

D20

RxDATA[A][10]

RxDATA[A][11]

RxDATA[A][12]

RxDATA[A][13]

RxDATA[A][14]

G31

U33

Note: NC refers to no connect. Do not connect pins so designated.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Table 2. Pin Assignments for 600-Pin LBGA by Signal Name (continued)

Signal Name

RxDATA[A][15]

RxDATA[B][0]

RxDATA[B][1]

RxDATA[B][2]

RxDATA[B][3]

RxDATA[B][4]

RxDATA[B][5]

RxDATA[B][6]

RxDATA[B][7]

RxDATA[B][8]

RxDATA[B][9]

RxDATA[B][10]

RxDATA[B][11]

RxDATA[B][12]

RxDATA[B][13]

RxDATA[B][14]

N31

RxDATA[D][2]

RxDATA[D][3]

RxDATA[D][4]

RxDATA[D][5]

RxDATA[D][6]

RxDATA[D][7]

RxDATA[D][8]

RxDATA[D][9]

AN10

AP10

AR10

AM11

AN11

AP11

AR11

AL12

RxSOP/C[A]

RxSOP/C[B]

RxSOP/C[C]

RxSOP/C[D]

RxSZ[A]

U31

AJ32

AL21

AP9

W35

AK31

AM20

AN8

AK5

AL4

AL6

AL7

AL2

AM5

AM6

AN7

AK4

AL3

AN5

AP6

TxCLK[B]

Y33

AP31

AP19

AJ34

AH31

AH32

AH33

AH34

AG31

AG32

AG33

AG34

AG35

AF31

AF32

AF33

AF34

AF35

TxCLK[C]

TxCLK[D]

TxD[0]N/TxD[D]N

TxD[0]P/TxD[D]P

TxD[1]N/TxD[C]N

TxD[1]P/TxD[C]P

TxD[2]N/TxD[B]N

TxD[2]P/TxD[B]P

TxD[3]N/TxD[A]N

TxD[3]P/TxD[A]P

TxD[4]N

RxSZ[B]

RxSZ[C]

RxSZ[D]

RxDATA[D][10] AM12

RxDATA[D][11] AN12

RxDATA[D][12] AP12

RxDATA[D][13] AR12

RxDATA[D][14] AL13

RxDATA[D][15] AM13

RxTOHCK[A]

RxTOHCK[B]

RxTOHCK[C]

RxTOHCK[D]

RxTOHD[A]

RxTOHD[B]

RxTOHD[C]

RxTOHD[D]

RxTOHF[A]

RxTOHF[B]

RxTOHF[C]

RxTOHF[D]

TCK

TxD[4]P

TxD[5]N

RxENB[A]

RxENB[B]

RxENB[C]

RxENB[D]

RxEOP[A]

RxEOP[B]

RxEOP[C]

RxEOP[D]

RxERR[A]

RxERR[B]

RxERR[C]

RxERR[D]

RxPA[A]

U34

AK34

AN21

AM9

U32

TxD[5]P

TxD[6]N

RxDATA[B][15] AE32

TxD[6]P

RxDATA[C][0]

RxDATA[C][1]

RxDATA[C][2]

RxDATA[C][3]

RxDATA[C][4]

RxDATA[C][5]

RxDATA[C][6]

RxDATA[C][7]

RxDATA[C][8]

RxDATA[C][9]

AP22

AN22

AM22

AL22

AP23

AN23

AM23

AL23

AR24

AP24

TxD[7]N

TxD[7]P

AJ31

AM21

AN9

TxD[8]N

TxD[8]P

TDI

TxD[9]N

V32

TDO

TxD[9]P

AK32

AR21

AP8

TMS

TxD[10]N

TRST

TxD[10]P

TxADDR[0]

TxADDR[1]

TxADDR[2]

TxADDR[3]

TxADDR[4]

TxCKN

G32

G33

W34

Y34

AM31

TxD[11]N

V33

TxD[11]P

RxDATA[C][10] AN24

RxDATA[C][11] AM24

RxDATA[C][12] AL24

RxDATA[C][13] AR25

RxDATA[C][14] AP25

RxDATA[C][15] AN25

RxPA[B]

AK33

AP21

AL9

TxD[12]N

RxPA[C]

TxD[12]P

RxPA[D]

TxD[13]N

RxPRTY[A]

RxPRTY[B]

RxPRTY[C]

RxPRTY[D]

RxREF

T34

TxD[13]P

AJ33

AR22

AR9

TxCKP

TxD[14]N

TxCKQN

TxD[14]P

RxDATA[D][0]

RxDATA[D][1]

AL10

TxCKQP

TxD[15]N

AM10

AK3

TxCLK[A]

G34

TxD[15]P

Note: NC refers to no connect. Do not connect pins so designated.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Table 2. Pin Assignments for 600-Pin LBGA by Signal Name (continued)

Signal Name

TxDATA[A][0]

TxDATA[A][1]

TxDATA[A][2]

TxDATA[A][3]

TxDATA[A][4]

TxDATA[A][5]

TxDATA[A][6]

TxDATA[A][7]

TxDATA[A][8]

TxDATA[A][9]

TxDATA[A][10]

TxDATA[A][11]

TxDATA[A][12]

TxDATA[A][13]

TxDATA[A][14]

TxDATA[A][15]

TxDATA[B][0]

TxDATA[B][1]

TxDATA[B][2]

TxDATA[B][3]

TxDATA[B][4]

TxDATA[B][5]

TxDATA[B][6]

TxDATA[B][7]

TxDATA[B][8]

TxDATA[B][9]

TxDATA[B][10]

TxDATA[B][11]

TxDATA[B][12]

TxDATA[B][13]

TxDATA[B][14]

TxDATA[B][15]

TxDATA[C][0]

TxDATA[C][1]

TxDATA[C][2]

M35

M34

TxDATA[C][3]

TxDATA[C][4]

TxDATA[C][5]

TxDATA[C][6]

TxDATA[C][7]

TxDATA[C][8]

TxDATA[C][9]

TxDATA[C][10]

AN26

AM26

AL26

AR27

AP27

AN27

AM27

AL27

TxEOP[C]

TxEOP[D]

TxERR[A]

TxERR[B]

TxERR[C]

TxERR[D]

TxFSYNCN

TxFSYNCP

TxPA[A]

AL29

AN17

H32

AA35

AM30

AM18

VDDD

A17

A18

A30

A31

A34

A35

M33

M32

M31

L35

L34

L33

L32

TxDATA[C][11] AP28

TxDATA[C][12] AN28

TxDATA[C][13] AM28

H33

AA34

AN30

AP18

J33

B34

B35

K35

TxPA[B]

K34

TxPA[C]

K33

TxDATA[C][14]

AL28

TxPA[D]

C33

K32

TxDATA[C][15] AP29

TxPRTY[A]

TxPRTY[B]

TxPRTY[C]

TxPRTY[D]

TxSOP/C[A]

TxSOP/C[B]

TxSOP/C[C]

TxSOP/C[D]

TxSZ[A]

K31

TxDATA[D][0]

TxDATA[D][1]

TxDATA[D][2]

TxDATA[D][3]

TxDATA[D][4]

TxDATA[D][5]

TxDATA[D][6]

TxDATA[D][7]

TxDATA[D][8]

TxDATA[D][9]

AN13

AP13

AM14

AL14

AN14

AP14

AR14

AM15

AL15

AN15

AB35

AN29

AM17

J32

D27

D32

J35

J34

AE33

AE34

AE35

AD31

AD32

AD33

AD34

AD35

AC31

AC32

AC33

AC34

AB32

AB31

AB33

AB34

AM25

AR26

AP26

AA32

AM29

AL17

H31

Y32

E11

E16

E20

E25

E31

E35

TxSZ[B]

TxSZ[C]

AL30

AN18

AJ2

TxDATA[D][10] AP15

TxDATA[D][11] AR15

TxDATA[D][12] AM16

TxDATA[D][13] AN16

TxDATA[D][14] AP16

TxDATA[D][15] AP17

TxSZ[D]

TxTOHCK

TxTOHD[A]

TxTOHD[B]

TxTOHD[C]

TxTOHD[D]

TxTOHF

F35

AJ3

AJ4

AJ5

L31

AK2

AH5

TxENB[A]

TxENB[B]

TxENB[C]

TxENB[D]

TxEOP[A]

TxEOP[B]

H34

AA33

AP30

AR17

J31

VDDA

VDDD

T31

U35

VDDD

AA31

VDDD

Note: NC refers to no connect. Do not connect pins so designated.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Table 2. Pin Assignments for 600-Pin LBGA by Signal Name (continued)

Signal Name

VDDD

V35

VDDD

AK1

AK35

AL1

VDDD

AL35

AM4

AM32

AN3

VDDD

VDDD PLL

AR2

AR5

AR6

AL5

AR18

AR19

AR30

AR31

AR34

AR35

Y31

AB5

AD5

AE5

AE31

AF5

AL11

AL16

AL18

AL20

AL25

AL31

AN33

AP1

AP2

AP34

AP35

AR1

Note: NC refers to no connect. Do not connect pins so designated.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Note:3.3 V CMOS logic inputs are 5 V tolerant. Logic inputs can be driven from standard TTL levels, and logic out-

puts can drive standard TTL inputs. All LVPECL buffers are differential. LVPECL is compliant with low-volt-

age (3.3 V) pseudo-emitter-coupled logic interface levels. All PECL outputs, including ECLREFHI and

ECLREFLO require terminating resistors. The required termination for the PECL buffers is 50 Ω to a termi-

nating voltage of VDDD – 2 V. The Thevenin equivalent is also acceptable (130 Ω to VDDD and 82 Ω to

GNDD). Other termination styles are not recommended. LVPECL inputs with a / in the name indicate multiple

functionality. The name preceding the / is the function in STS-48/STM-16 mode. The name after the / is the

function in STS-3/STM-1 or STS-12/STM-4 mode.

Table 3. Pin Descriptions—Line Interface Signals

Unused LVPECL outputs should not be terminated to minimize power consumption. Unused inputs are internally

disabled whenever core registers 0x0010 and 0x0011 are properly provisioned. The unused inputs can be consid-

ered to be NC (no connect).

Symbol

Type

I/O

Name/Description

RxCKP/

RxD[A]P

RxCKN/

RxD[A]N

LVPECL

Receive Line Clock (STS-48/STM-16)/Receive Line Data Input Channel

A. In STS-48/STM-16 mode, these pins function as receive line clock. This

155.52 MHz clock comes from an external clock data recovery circuit. This

clock is used to clock in the RxD[15:0] receive line data inputs.

In STS-3/STM-1 or STS-12/STM-4 mode, these pins function as receive

data input channel A at 155.52 Mbits/s or 622.08 Mbits/s, respectively.

This buffer is internally disabled when not in STS-48/STM-16 mode and

channel A is disabled. This buffer is internally disabled through proper pro-

visioning when the input is not active.

AG2

AG1

AF2

AF1

AF4

AF3

AE2

AE1

AE4

AE3

AD2

AD1

AD4

AD3

AC3

AC2

AC5

AC4

AB2

RxD[0]P

RxD[0]N

RxD[1]P

RxD[1]N

RxD[2]P

RxD[2]N

RxD[3]P

RxD[3]N

RxD[4]P

RxD[4]N

RxD[5]P

RxD[5]N

RxD[6]P

RxD[6]N

RxD[7]P

RxD[7]N

RxD[8]P

RxD[8]N

LVPECL

Receive Line Data Inputs (STS-48/STM-16). In STS-48/STM-16 mode,

these pins function as receive line data inputs [0:8]. The remaining receive

line data inputs [9:15] are listed below and are multiplexed for use in the

STS-3/STM-1 or STS-12/STM-4 modes.

The 2.488 Gbits/s STS-48/STM-16 serial data stream is converted to a

155.52 Mbits/s parallel 16-bit word external to TDAT042G5 by a demulti-

plexer.

All 32 differential data input pins, RxD[15:0]P/N, are used as the parallel

data input bus in the STS-48/STM-16 mode. These pins constitute a

155.52 Mbits/s parallel 16-bit word-aligned to the RxCKP/N 155.52 MHz

receive line clock. RxD[15] is the most significant bit and is the first bit

received. RxD[0] is the least significant bit and is the last bit received.

This buffer is internally disabled through proper provisioning when the input

is not active.

RxD[9]P/

RxCLK[D]P

RxD[9]N/

Receive Line Data Input [9]/Receive Line Clock Channel D. In STS-48/

STM-16 mode, these pins function as receive line data input [9] at

155.52 Mbits/s.

AB1

RxCLK[D]N

In STS-3/STM-1 or STS-12/STM-4 mode, these pins function as receive

line clock channel D at either 155.52 MHz (STS-3/STM-1) or 622.08 MHz

(STS-12/STM-4).

This buffer is internally disabled when not in STS-48/STM-16 mode and

channel D is disabled. This buffer is internally disabled through proper pro-

visioning when the input is not active.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Table 3. Pin Descriptions—Line Interface Signals (continued)

Unused LVPECL outputs should not be terminated to minimize power consumption. Unused inputs are internally

disabled whenever core registers 0x0010 and 0x0011 are properly provisioned. The unused inputs can be consid-

ered to be NC (no connect).

Symbol

Type

I/O

Name/Description

AB4

RxD[10]P/

RxD[D]P

LVPECL

Receive Line Data Input [10]/Receive Line Data Input

Channel D. In STS-48/STM-16 mode, these pins function as

receive line data input [10] at 155.52 Mbits/s.

AB3

RxD[10]N/

RxD[D]N

In STS-3/STM-1 or STS-12/STM-4 mode, these pins function as

receive line data input channel D at either 155.52 Mbits/s (STS-3/

STM-1) or 622.08 Mbits/s (STS-12/STM-4).

This buffer is internally disabled when not in STS-48/STM-16

mode and channel D is disabled. This buffer is internally disabled

through proper provisioning when the input is not active.

AA2

AA1

RxD[11]P/

RxCLK[C]P

LVPECL

Receive Line Data Input [11]/Receive Line Clock Channel C.

In STS-48/STM-16 mode, these pins function as receive line data

input [11] at 155.52 Mbits/s.

RxD[11]N/

RxCLK[C]N

In STS-3/STM-1 or STS-12/STM-4 mode, these pins function as

receive line clock channel C at either 155.52 MHz (STS-3/STM-1)

or 622.08 MHz (STS-12/STM-4).

This buffer is internally disabled when not in STS-48/STM-16

mode and channel C is disabled. This buffer is internally disabled

through proper provisioning when the input is not active.

AA4

AA3

RxD[12]P/

RxD[C]P

Receive Line Data Input [12]/Receive Line Data Input

Channel C. In STS-48/STM-16 mode, these pins function as

receive line data input [12] at 155.52 Mbits/s.

RxD[12]N/

RxD[C]N

In STS-3/STM-1 or STS-12/STM-4 mode, these pins function as

receive line data input channel C at either 155.52 Mbits/s (STS-3/

STM-1) or 622.08 Mbits/s (STS-12/STM-4).

This buffer is internally disabled when not in STS-48/STM-16

mode and channel C is disabled. This buffer is internally disabled

through proper provisioning when the input is not active.

RxD[13]P/

RxCLK[B]P

Receive Line Data Input [13]/Receive Line Clock Channel B.

In STS-48/STM-16 mode, these pins function as receive line data

input [13] at 155.52 Mbits/s.

RxD[13]N/

RxCLK[B]N

In STS-3/STM-1 or STS-12/STM-4 mode, these pins function as

receive line clock channel B at either 155.52 MHz (STS-3/STM-1)

or 622.08 MHz (STS-12/STM-4).

This buffer is internally disabled when not in STS-48/STM-16

mode and channel B is disabled. This buffer is internally disabled

through proper provisioning when the input is not active.

RxD[14]P/

RxCLK[A]P

Receive Line Data Input [14]/Receive Line Clock Channel A.

In STS-48/STM-16 mode, these pins function as receive line data

input [14] at 155.52 Mbits/s.

RxD[14]N/

RxCLK[A]N

In STS-3/STM-1 or STS-12/STM-4 mode, these pins function as

receive line clock channel A at either 155.52 MHz (STS-3/STM-1)

or 622.08 MHz (STS-12/STM-4).

This buffer is internally disabled when not in STS-48/STM-16

mode and channel A is disabled. This buffer is internally disabled

through proper provisioning when the input is not active.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Table 3. Pin Descriptions—Line Interface Signals (continued)

Unused LVPECL outputs should not be terminated to minimize power consumption. Unused inputs are internally

disabled whenever core registers 0x0010 and 0x0011 are properly provisioned. The unused inputs can be consid-

ered to be NC (no connect).

Symbol

Type

I/O*

Name/Description

RxD[15]P/

RxD[B]P

LVPECL

Receive Line Data Input [15]/Receive Line Data Input

Channel B. In STS-48/STM-16 mode, these pins function as

receive line data input [15] at 155.52 Mbits/s.

RxD[15]N/

RxD[B]N

In STS-3/STM-1 or STS-12/STM-4 mode, these pins function as

receive line data input channel B at either 155.52 Mbits/s

(STS-3/STM-1) or 622.08 Mbits/s (STS-12/STM-4).

This buffer is internally disabled when not in STS-48/STM-16

mode and channel B is disabled. This buffer is internally disabled

through proper provisioning when the input is not active.

CLKDIV

3.3 V

(5 V tolerant)

I^uClock Division. This pin controls a divider in the line transmit

block to create a 77.76 MHz clock from either the 155.52 MHz

STS-3/STM-1 or STS-48/STM-16 transmit line clock, or the

622.08 MHz STS-12/STM-4 transmit line clock, TxCKP/N.

CLKDIV = 1 for STS-12/STM-4 (divide by 8).

CLKDIV = 0 for STS-3/STM-1 and STS-48 /STM-16 (divide by 2).

AG3

AG4

ECLREFLO

ECLREFHI

—

Reference Voltage for LVPECL I/O Buffers. ECLREFLO and

ECLREFHI are buffer outputs which provide the reference for the

output level of theLVPECL output buffers. ECLREFLO and ECL-

REFHI must be connected to a 50 Ω source of VDDD – 2 V.^†No

user-accessible signal is present on these pins.

* I = I = 50 kΩ, where I = internal pull-up resistance and I = internal pull-down resistance.

†This may be obtained from a passive voltage divider of a 130 Ω resistor connected from VDDD to one end of an 82 Ω resistor, the other end of

which is connected to GNDD.

Note: The TDAT042G5 has internal circuitry that is associated with the buffer section of the chip. This section

monitors the voltage levels of REFLO and REFHI. A very low frequency calibration process, during which

the values at the ECLREFLO and ECLREFHI pins are continuously monitored, is performed to allow the

drive capactity of remaining buffers to be adjusted within true PECL levels. Therefore, it is important to ter-

minate the ECLREFLO and ECLREFHI outputs in exactly the same way as you would terminate LVPECL

outputs.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Table 3. Pin Descriptions—Line Interface Signals (continued)

Unused LVPECL outputs should not be terminated to minimize power consumption. Unused inputs are internally

disabled whenever core registers 0x0010 and 0x0011 are properly provisioned. The unused inputs can be consid-

ered to be NC (no connect).

Symbol

Type

I/O*

Name/Description

TxCKP

TxCKN

LVPECL

Transmit Line Clock. When in STS-48/STM-16 mode, this clock

is a 155.52 MHz input and clocks out TxD[15:0]P/N or TxD[D:A].

When in STS-12/STM-4 mode, this clock is a 622.08 MHz input

and clocks out TxD[D:A]P/N.

When in STS-3/STM-1 mode, this clock is a 155.52 MHz input

and clocks out TxD[D:A]P/N.

TxFSYNCP

TxFSYNCN

LVPECL

I^dTransmit Line Frame Sync. This input is the external 8 kHz

transmit line frame sync. Driving this input is optional. If undriven

I^u

from an external source, these pins must be no connects. When

this input is used, it must be (1) synchronized to TxCKP/N, and (2)

at least one TxCKP/N cycle wide, up to a maximum of 1 frame

period minus 2 TxCKP/N cycles wide.

TxD[0]P/

TxD[D]P

Transmit Line Data Output [0]/Transmit Line Data Output

Channel D. In STS-48/STM-16 mode, the pins function as trans-

mit line data output [0] at 155.52 Mbits/s.

TxD[0]N/

TxD[D]N

In STS-3/STM-1 or STS-12/STM-4 mode, the pins function as

transmit data output channel D at either 155.52 Mbits/s or

622.08 Mbits/s.

This buffer is internally disabled through proper provisioning when

the input is not active.

TxD[1]P/

TxD[C]P

LVPECL

Transmit Line Data Output [1]/Transmit Line Data Output

Channel C. In STS-48/STM-16 mode, the pins function as trans-

mit line data output [1] at 155.52 Mbits/s.

TxD[1]N/

TxD[C]N

In STS-3/STM-1 or STS-12/STM-4 mode, the pins function as

transmit data output channel C at either 155.52 Mbits/s or

622.08 Mbits/s.

This buffer is internally disabled through proper provisioning when

the input is not active.

TxD[2]P/

TxD[B]P

Transmit Line Data Output [2]/Transmit Line Data Output

Channel B. In STS-48/STM-16 mode, the pins function as trans-

mit line data output [2] at 155.52 Mbits/s.

TxD[2]N/

TxD[B]N

In STS-3/STM-1 or STS-12/STM-4 mode, the pins function as

transmit data output channel B at either 155.52 Mbits/s or

622.08 Mbits/s.

This buffer is internally disabled through proper provisioning when

the input is not active.

TxD[3]P/

TxD[A]P

Transmit Line Data Output [3]/Transmit Line Data Output

Channel A. In STS-48/STM-16 mode, the pins function as trans-

mit line data output [3] at 155.52 Mbits/s.

TxD[3]N/

TxD[A]N

In STS-3/STM-1 or STS-12/STM-4 mode, the pins function as

transmit data output channel A at either 155.52 Mbits/s or

622.08 Mbits/s.

This buffer is internally disabled through proper provisioning when

the input is not active.

* I = I = 50 kΩ, where I = internal pull-up resistance and I = internal pull-down resistance.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Table 3. Pin Descriptions—Line Interface Signals (continued)

Unused LVPECL outputs should not be terminated to minimize power consumption. Unused inputs are internally

disabled whenever core registers 0x0010 and 0x0011 are properly provisioned. The unused inputs can be consid-

ered to be NC (no connect).

Symbol

Type

I/O

Name/Description

TxCKQP

TxCKQN

LVPECL

Transmit Line Clock Q. This 155.52 MHz clock is used to clock

out the data in the STS-48/STM-16 mode for forward-directional

timing with the 155 Mbits/s 16-bit parallel-to-2.5 Gbits/s serial

MUX.

For an STS-48/STM-16 contra-clocking interface with the

155 Mbits/s parallel-to-2.5 Gbits/s serial MUX, this clock is not

used. In the contra-clocking mode, a phase-locked version of

TxCKP/N is used to clock out the data. In the contra-clocking

mode, the transmit line clock PLL must be active (see core regis-

ter map 0x0010, bit 5 (PLL_ MODE) on page 112).

This clock is not used in the STS-3/STM-1 or STS-12/STM-4

modes.

TxD[4]P

TxD[4]N

TxD[5]P

TxD[5]N

TxD[6]P

TxD[6]N

TxD[7]P

TxD[7]N

TxD[8]P

TxD[8]N

TxD[9]P

TxD[9]N

TxD[10]P

TxD[10]N

TxD[11]P

TxD[11]N

TxD[12]P

TxD[12]N

TxD[13]P

TxD[13]N

TxD[14]P

TxD[14]N

TxD[15]P

TxD[15]N

LVPECL

Transmit Line Data Outputs (STS-48/STM-16). In STS-48/

STM-16 mode, these pins function as transmit line data outputs

[4:15]. The remaining transmit line data outputs [0:3] are listed

below and are multiplexed for use in the STS-3/STM-1 or STS-12/

STM-4 modes.

The 155.52 Mbits/s 16-bit word parallel bus is converted to a

2.488 Gbits/s serial data stream external to TDAT042G5 by a mul-

tiplexer.

All 32 differential data output pins, TxD[15:0]P/N, are used as the

parallel data output bus in the STS-48/STM-16 mode. These pins

constitute a 155.52 Mbyte/s parallel 16-bit word-aligned to the

TxCKP/N and TxCKQP/N 155.52 MHz transmit line clock.

TxD[15] is the most significant bit and is the first bit transmitted.

TxD[0] is the least significant bit and is the last bit transmitted.

This buffer is internally disabled through proper provisioning when

the input is not active.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Table 4. Pin Descriptions—TOH Interface Signals

Symbol

Type

I/O*

Name/Description

AK3

RxREF

3.3 V

Receive Line Frame. This output provides the receive 8 kHz

frame reference for external timing needs. RxREF is derived from

one of the received line clocks (user-selectable). It is a 50% duty

cycle clock when TDAT042G5 is in frame. This signal may be

used to implement line timing on a SONET ring. When not provi-

sioned, this signal must not be used. RxREF is valid only when

the SONET framer is in frame. Upon LOC or LOF, RxREF is

present but is free running. Because jitter may be present on this

signal when the device goes into and out of an LOC or LOF state,

it should not be used as a reference for TxFSYNCP/N.

AL7 RxTOHCK[D]

AL6 RxTOHCK[C]

AL4 RxTOHCK[B]

AK5 RxTOHCK[A]

3.3 V

Receive TOH Interface Clock. This clock is nominally a

5.184 MHz (STS-3/STM-1) or 20.736 MHz (STS-12/STM-4,

STS-48/STM-16) clock which provides timing for circuitry that

receives and externally processes the receive transport overhead

bytes. The duty cycle of the clock is not 50% (see Figure 49 and

Figure 50, page 272). In STS-48/STM-16 mode, all four of these

clocks are active.

RxTOHD[D]

RxTOHD[C]

RxTOHD[B]

RxTOHD[A]

AN7

AM6

AM5

AL2

Receive TOH Interface Data. This 5.184 Mbits/s or

20.736 Mbits/s signal contains all the receive transport overhead

bytes (A1, A2, J0/Z0, B1, E1, F1, D1—D3, H1—H3, K1, K2,

D4—D12, S1/Z1, M0, and E2) for all 3/12/48 STS-1s. This signal

can be used by external circuitry to process the TOH bytes.

RxTOHD is updated on the falling edge of RxTOHCK. In STS-48/

STM-16 mode, RxTOHD[A] contains all currently defined TOH

bits except for M1, which is located in RxTOHD[C].

AP6

AN5

AL3

AK4

RxTOHF[D]

RxTOHF[C]

RxTOHF[B]

RxTOHF[A]

3.3 V

Receive TOH Interface Frame. This 8 kHz framing signal is used

to locate the individual receive transport overhead bits in the

RxTOHD bit stream. RxTOHF is only high while bit 1 (MSB) of the

first framing byte (A1 during parity time in first byte) is present on

the RxTOHD output. RxTOHF is updated on the falling edge of

RxTOHCK.

AJ2

TxTOHCK

Transmit TOH Interface Clock. This clock is nominally a

5.184 MHz (STS-3/STM-1), 20.736 MHz (STS-12/STM-4,

STS-48/STM-16) clock which provides timing for circuitry that

externally generates and transmits the transmit transport over-

head bytes for inclusion in the transmit data stream. The duty

cycle of the clock is not 50% (see Figure 48, pag e271).

AK2

AJ5

AJ4

AJ3

TxTOHD[D]

TxTOHD[C] (5 V tolerant)

TxTOHD[B]

I^uTransmit TOH Interface Data. This 5.184 Mbits/s or

20.736 Mbits/s signal contains all the transmit transport overhead

bytes (A1, A2, J0/Z0, B1, E1, F1, D1—D3, H1—H3, K1, K2,

D4—D12, S1/Z1, M0, and E2) for all 3/12/48 STS-1s. This signal

is generated by external circuitry for custom TOH byte definitions.

TxTOHD is sampled on the rising edge of TxTOHCK.

TxTOHD[A]

AH5

TxTOHF

3.3 V

Transmit TOH Interface Frame. This 8 kHz framing signal is

used to align the individual transmit transport overhead bits in the

TxTOHD bit stream. TxTOHF is only high while bit 1 (MSB) of the

first framing byte (A1 during parity time in first byte) is expected

on the TxTOHD input. TxTOHF is updated on the falling edge of

TxTOHCK.

* I = I = 50 kΩ, where I = internal pull-up resistance and I = internal pull-down resistance.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Note:An external pull-up resistor of 50 kΩ—100 kΩ is required on all input pins of a disabled UTOPIA port. Either

an external pull-up resistor of 50 kΩ—100 kΩ or an external pull-down resistor of 0 Ω—1 kΩ is required on all

unused inputs of an enabled UTOPIA port. Use of either a pull-up or pull-down resistor is selected to place

the unused input pin into the inactive state.

Table 5. Pin Descriptions—Enhanced UTOPIA Interface Signals

Symbol

Type

I/O

Name/Description

AM31

Y34

W34

G33

G32

TxADDR[4]

TxADDR[3]

TxADDR[2]

TxADDR[1]

TxADDR[0]

3.3 V

(5 V tolerant)

Transmit Address. The TxADDR is driven by the UTOPIA mas-

ter to poll and select the appropriate PHY channel of

TDAT042G5 to transmit data.

Note: The PHY address (0x00 to 0x1E) for each of the four

channels in TDAT042G5 is configured via software

provisioning.

J34

J35

TxDATA[A][15]

3.3 V

Transmit Data Channel A. Used to transport data into the

UTOPIA PHY Tx block. TxDATA[A] is only valid when TxENB[A]

is asserted, and is sampled on the rising edge of TxCLK[A].

Note that TxDATA[A] is used in various UTOPIA modes. In U2 or

U2+, all 16 bits are valid. In U3 or U3+ (8-bit mode), only bits 15

to 8 are valid.

TxDATA[A][14] (5 V tolerant)

TxDATA[A][13]

TxDATA[A][12]

TxDATA[A][11]

TxDATA[A][10]

TxDATA[A][9]

TxDATA[A][8]

TxDATA[A][7]

TxDATA[A][6]

TxDATA[A][5]

K31

K32

K33

K34

K35

L32

L33

L34

L35

M31

M32

M33

M34

M35

In U3 or U3+ (32-bit mode), TxDATA[A][15:0] forms the most

significant 16 bits of the combined data bus (bits 31 to 16), and

TxDATA[B][15:0] forms the least significant 16 bits of the com-

bined data bus (bits 15 to 0).

TxDATA[A][4]

TxDATA[A][3]

TxDATA[A][2]

TxDATA[A][1]

Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB).

TxDATA[A][0]

AB34 TxDATA[B][15]

AB33 TxDATA[B][14] (5 V tolerant)

AB31 TxDATA[B][13]

AB32 TxDATA[B][12]

AC34 TxDATA[B][11]

3.3 V

Transmit Data Channel B. Used to transport data into the

UTOPIA PHY Tx block. TxDATA[B] is only valid when TxENB[B]

is asserted (TxENB[A] for U3 or U3+ (32-bit mode)), and is sam-

pled on the rising edge of TxCLK[B] (TxCLK[A] for U3 or U3+

(32-bit mode). Note that TxDATA[B] is used in various UTOPIA

modes. In U2 or U2+, all 16 bits are valid. In U3 or U3+ (8-bit

mode), only bits 15 to 8 are valid.

AC33 TxDATA[B][10]

AC32

AC31

AD35

AD34

AD33

AD32

AD31

AE35

AE34

AE33

TxDATA[B][9]

TxDATA[B][8]

TxDATA[B][7]

TxDATA[B][6]

TxDATA[B][5]

TxDATA[B][4]

TxDATA[B][3]

TxDATA[B][2]

TxDATA[B][1]

TxDATA[B][0]

In U3 or U3+ (32-bit mode), TxDATA[B][15:0] forms the least sig-

nificant 16 bits of the combined data bus (bits 15 to 0), and

TxDATA[A][15:0] forms the most significant 16 bits of the com-

bined data bus (bits 31 to 16). In this mode, channel B port must

be provisioned to the idle (default) state.

Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB).

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Table 5. Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)

Symbol

Type

I/O

Name/Description

AP29 TxDATA[C][15]

AL28 TxDATA[C][14] (5 V tolerant)

AM28 TxDATA[C][13]

AN28 TxDATA[C][12]

AP28 TxDATA[C][11]

3.3 V

Transmit Data Channel C. Used to transport data into the

UTOPIA PHY Tx block. TxDATA[C] is only valid when TxENB[C]

is asserted, and is sampled on the rising edge of TxCLK[C].

Note that TxDATA[C] is used in various UTOPIA modes. In U2

or U2+, all 16 bits are valid. In U3 or U3+ (8-bit mode), only bits

15 to 8 are valid.

AL27 TxDATA[C][10]

AM27

AN27

AP27

AR27

AL26

AM26

AN26

AP26

AR26

AM25

TxDATA[C][9]

TxDATA[C][8]

TxDATA[C][7]

TxDATA[C][6]

TxDATA[C][5]

TxDATA[C][4]

TxDATA[C][3]

TxDATA[C][2]

TxDATA[C][1]

TxDATA[C][0]

In U3 or U3+ (32-bit mode), channel C port is considered dis-

abled, and must be provisioned to the idle (default) state.

Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB).

AP17 TxDATA[D][15]

AP16 TxDATA[D][14] (5 V tolerant)

AN16 TxDATA[D][13]

AM16 TxDATA[D][12]

AR15 TxDATA[D][11]

3.3 V

Transmit Data Channel D. Used to transport data into the UTO-

PIA PHY Tx block. TxDATA[D] is only valid when TxENB[D] is

asserted, and is sampled on the rising edge of TxCLK[D]

(TxCLK[A] for U3+, 32-bit mode). Note that TxDATA[D] is used in

various UTOPIA modes. In U2 or U2+, all 16 bits are valid. In U3

or U3+ (8-bit mode), only bits 15 to 8 are valid.

AP15 TxDATA[D][10]

AN15

AL15

AM15

AR14

AP14

AN14

AL14

AM14

AP13

AN13

TxDATA[D][9]

TxDATA[D][8]

TxDATA[D][7]

TxDATA[D][6]

TxDATA[D][5]

TxDATA[D][4]

TxDATA[D][3]

TxDATA[D][2]

TxDATA[D][1]

TxDATA[D][0]

In U3 or U3+ (32-bit mode), channel D port is considered dis-

abled, and must be provisioned to the idle (default) state.

Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB).

AM17

AN29

AB35

J33

TxPRTY[D]

TxPRTY[C]

TxPRTY[B]

TxPRTY[A]

3.3 V

(5 V tolerant)

Transmit Parity. This signal indicates the parity on the

TxDATA[D:A][15:0] bus. A parity error raises an alarm but does

not cause the cell/packet to be dropped. Odd or even parity may

be provisioned through a software register. TxPRTY[D:A] is con-

sidered valid only when TxENB[D:A] is asserted, and is sam-

pled on the rising edge of TxCLK[D:A].

In U3 or U3+ (32-bit mode), the TxPRTY[A] parity pin of port A

indicates the parity for the entire 32-bit data input.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Table 5. Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)

Symbol

Type

I/O

Name/Description

AL17 TxSOP/C[D]

AM29 TxSOP/C[C] (5 V tolerant)

AA32 TxSOP/C[B]

3.3 V

Transmit Start of Packet/Cell. In ATM mode, the TxSOP/C[D:A]

signal marks the start of a cell on the TxDATA[D:A][15:0] bus.

When TxSOP/C[D:A] is active, the first word of the cell is present

on the TxDATA[D:A][15:0] bus.

J32

TxSOP/C[A]

In packet modes, the TxSOP/C[D:A] signal marks the start of a

packet on the TxDATA[D:A][15:0] bus. When TxSOP/C[D:A] is

active, the first word of the packet is present on the

TxDATA[D:A][15:0] bus.

TxSOP/C[D:A] is considered valid only when TxENB[D:A] is

asserted, and is sampled on the rising edge of TxCLK[D:A].

In U3 or U3+ (32-bit mode), only the TxSOP/C[A] pin of port A is

used to indicate a start of packet/cell for the 32-bit data input.

AP18

AN30

AA34

H33

TxPA[D]

TxPA[C]

TxPA[B]

TxPA[A]

3.3 V

Transmit Cell/Packet Available. This signal indicates when the

TDAT042G5 transmit FIFO can accept data from the master

device. If the FIFO is empty or more than the provisioned space is

available in the FIFO, TxPA[D:A] is set active.

^IOne-Cycle Delay Mode. This mode follows the UTOPIA Level

2 Standard. The TxPA response occurs one cycle after the

address is polled.

^ITwo-Cycle Delay Mode. This mode follows the UTOPIA Level

3 baselined text*. The TxPA response occurs two cycles after

the address is polled.

^ITxPA[D:A] Assertion. The TxPA[D:A] signal behavior relies on

the UTOPIA provisionable watermarks. In packet mode,

TxPA[D:A] goes high when the amount of data in the FIFO is

less than the high watermark setting. In ATM mode, TxPA[D:A]

goes high when the FIFO has space to receive a complete ATM

cell from the master. (This requires the high threshold to be set

appropriately by the user, i.e., set so that an entire cell can be

received once TxPA[D:A] goes active.)

* ATM Forum Technical Committee, UTOPIA Level 3, STR-PHY-UL3-01.00, July

1999.

(See further description on next page.)

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Table 5. Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)

Symbol

Type

I/O

Name/Description

AP18

AN30

AA34

H33

TxPA[D]

TxPA[C]

TxPA[B]

TxPA[A]

3.3 V

Transmit Cell/Packet Available. (continued)

^ITxPA[D:A] Deassertion. In packet mode, TxPA[D:A] goes low

when the amount of data in the FIFO reaches or exceeds the

high watermark. In ATM mode, TxPA[D:A] goes low when there

is not enough space in the FIFO to receive an entireATM cell.

(This requires the threshold values to be provisioned properly,

i.e., set low enough such that when the high watermark is

reached, the transmission of the current cell can be completed

without overflowing the FIFO). In ATM mode, TxPA[D:A] will be

deasserted four cycles before the end of the current cell trans-

fer if the FIFO cannot accept a complete ATM cell on the follow-

ing transmission.

TxPA[D:A] is updated on the rising edge of TxCLK[D:A].

In 32-bit mode, only the TxPA[A] pin of port A is used to indicate

the packet/cell available status.

^IMPHY Support. When the TxPA signals are used for multi-PHY

(MPHY) direct status, the corresponding TxCLK[B, C, and/or D]

must be provided. This clock will be the same as TxCLK[A].

AP19

AP31

Y33

TxCLK[D]

TxCLK[C]

TxCLK[B]

TxCLK[A]

3.3 V

(5 V tolerant)

Transmit Clock. This clock is used to write cells or packets into

the transmit FIFO. TxCLK[D:A] can operate at speeds from dc to

104 MHz.

G34

In U3 or U3+ (32-bit mode), only the TxCLK[A] input pin of port A

is used to clock the data input.

If MPHY direct status is used, then all clocks TxCLK[D:A] must be

provided.

AR17

AP30

AA33

H34

TxENB[D]

TxENB[C]

TxENB[B]

TxENB[A]

3.3 V

(5 V tolerant)

Transmit Data Enable (Active-Low). This signal is used to trans-

fer data on the TxDATA[D:A][15:0] bus into the transmit FIFOs. If

TxENB[D:A] is high, no operation is performed. If TxENB[D:A] is

low, a write occurs.

TxENB[D:A] is sampled on the rising edge of TxCLK[D:A].

TxENB[D:A] has the same meaning as data valid.

In U3 or U3+ (32-bit mode), only the TxENB[A] input pin of port A

is used to enable the transfer of data.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Table 5. Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)

Symbol

Type

I/O

Name/Description

AN18

AL30

Y32

TxSZ[D]

TxSZ[C]

TxSZ[B]

TxSZ[A]

3.3 V

(5 V tolerant)

Transmit Size. These pins are used only in U2+ and U3+

(packet) modes. This signal defines the valid bytes transmitted

and their packing within (1) TxDATA[D:A][15:0] for U2+ 16-bit

mode, and (2) TxDATA[A][15:0] and TxDATA[B][15:0] for the U3+

(32-bit mode). The meaning of these bits may be inverted

through UT register 0x0226 TxSIZE/RxSIZE mode, page 164.

H31

In U3+ (8-bit mode), TxSZ[D:A] are unused.

For U2+ 16-bit mode,

TxSZ[D:A] = 0 defines the MSByte of TxDATA[D:A][15:0], i.e.,

TxDATA[D:A][15:8], to be the last byte of the packet transmit-

ted when using the default configuration.

TxSZ[D:A] = 1 defines the LSByte of TxDATA[D:A][15:0], i.e.

TxDATA[D:A][7:0], to be the last byte of the packet transmit-

ted when using the default configuration.

For U3+ (32-bit mode), TxSZ[A] and TxSZ[B] are combined to

define four states of the transmitted data stream. TxSZ[C] and

TxSZ[D] are unused. The following states are assigned by

TxSZ[A] and TxSZ[B] when TxEOP[A] is asserted when using

the default configuration. TxSZ[D:A] is ignored when

TxEOP[D:A] is not present.

TxDATA[A]

TxDATA[B]

TxDATA[A][15:8] TxDATA[A][7:0]

TxDATA[B][15:8] TxDATA[B][7:0]

TxSZ[A] TxSZ[B] DATA[31:24] DATA[23:16]

DATA[15:8]

Not valid

Valid

DATA[7:0]

Not valid

Valid

Not valid

Valid

There is no byte swapping and the data bytes are packed into

the upper transmitted bytes first.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Table 5. Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)

Symbol

Type

I/O

Name/Description

AN17

AL29

AA31

J31

TxEOP[D]

TxEOP[C]

TxEOP[B]

TxEOP[A]

3.3 V

(5 V tolerant)

Transmit End of Packet. These pins are used only in U2+

and U3+ (packet) modes. This signal indicates that the last

word of a packet is on the TxDATA[D:A][15:0] bus.

TxEOP[D:A] is valid only when TxENB[D:A] is asserted, and

is sampled on the rising edge of TxCLK[D:A].

In U3+ (32-bit mode), only the TxEOP[A] input pin of port A

is used to indicate the end of the incoming packet.

AM18

AM30

AA35

H32

TxERR[D]

TxERR[C]

TxERR[B]

TxERR[A]

3.3 V

(5 V tolerant)

Transmit Error. These pins are used only in U2+ and U3+

(packet) modes. TxERR[D:A] is only used in packet modes,

and indicates that the current packet is to be aborted and

discarded, if possible. TxERR[D:A] is only valid when

TxEOP[D:A] and TxENB[D:A] are asserted, and is sampled

on the rising edge of TxCLK[D:A].

In U3+ (32-bit mode), the TxERR[A] and the TxERR[B] input

pin of port A is used to indicate an error on the incoming

packet.

AP20

AL32

AL33

W32

W31

RxADDR[4]

RxADDR[3]

RxADDR[2]

RxADDR[1]

RxADDR[0]

3.3 V

(5 V tolerant)

Receive Address. Receive address is driven to the MPHY

to poll and select the appropriate MPHY channel.

Note: The address for each channel is configured by the

microprocessor.

N31

N32

N33

N34

P31

P32

P33

P34

P35

R31

R32

R33

R34

R35

T32

T33

RxDATA[A][15]

RxDATA[A][14]

RxDATA[A][13]

RxDATA[A][12]

RxDATA[A][11]

RxDATA[A][10]

RxDATA[A][9]

RxDATA[A][8]

RxDATA[A][7]

RxDATA[A][6]

RxDATA[A][5]

RxDATA[A][4]

RxDATA[A][3]

RxDATA[A][2]

RxDATA[A][1]

RxDATA[A][0]

3.3 V

Receive Data Channel A. Used to transport data out of the

UTOPIA PHY Rx block. RxDATA[A][15:0] is only valid when

RxENB[A] is asserted, and is updated on the rising edge of

RxCLK[A]. Note that RxDATA[A][15:0] is used in various

UTOPIA modes. In U2 or U2+, all 16 bits are valid. In U3 or

U3+ (8-bit mode), only bits 15 to 8 are valid.

In U3 or U3+ (32-bit mode), RxDATA[A][15:0] forms the most

significant 16 bits of the combined data bus (bits 31 to 16),

and RxDATA[B][15:0] forms the least significant 16 bits of the

combined data bus (bits 15 to 0).

Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB).

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Table 5. Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)

Symbol

Type

I/O

Name/Description

AE32 RxDATA[B][15]

AF35 RxDATA[B][14]

AF34 RxDATA[B][13]

AF33 RxDATA[B][12]

AF32 RxDATA[B][11]

AF31 RxDATA[B][10]

3.3 V

Receive Data Channel B. Used to transport data out of the

UTOPIA PHY Rx block. RxDATA[B][15:0] is only valid when

RxENB[B] is asserted, and is updated on the rising edge of

RxCLK[B]. Note that RxDATA[B][15:0] is used in various UTO-

PIA modes. In U2 or U2+, all 16 bits are valid. In U3 or U3+ (8-

bit mode), only bits 15 to 8 are valid.

AG35

AG34

AG33

AG32

AG31

AH34

AH33

AH32

AH31

AJ34

RxDATA[B][9]

RxDATA[B][8]

RxDATA[B][7]

RxDATA[B][6]

RxDATA[B][5]

RxDATA[B][4]

RxDATA[B][3]

RxDATA[B][2]

RxDATA[B][1]

RxDATA[B][0]

In U3 or U3+ (32-bit mode), RxDATA[B][15:0] forms the least sig-

nificant 16 bits of the combined data bus (bits 15 to 0), and

RxDATA[A][15:0] forms the most significant 16 bits of the com-

bined data bus (bits 31 to 16). In this mode, channel B port must

be provisioned to idle.

In this mode, RxDATA[B][15:0] is valid when RxENB[A] is

asserted, and RxDATA[B][15:0] is updated on the rising edge of

RxCLK[A].

Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB).

AN25 RxDATA[C][15]

AP25 RxDATA[C][14]

AR25 RxDATA[C][13]

AL24 RxDATA[C][12]

AM24 RxDATA[C][11]

AN24 RxDATA[C][10]

3.3 V

Receive Data Channel C. Used to transport data out of the

UTOPIA PHY Rx block. RxDATA[C][15:0] is only valid when

RxENB[C] is asserted, and is updated on the rising edge of

RxCLK[C]. Note that RxDATA[C][15:0] is used in various UTO-

PIA modes. In U2 or U2+, all 16 bits are valid. In U3+ (8-bit

mode), only bits 15 to 8 are valid.

AP24

AR24

AL23

RxDATA[C][9]

RxDATA[C][8]

RxDATA[C][7]

In U3 or U3+ (32-bit mode), channel C port must be provisioned

to idle mode.

AM23 RxDATA[C][6]

Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB).

AN23

AP23

AL22

RxDATA[C][5]

RxDATA[C][4]

RxDATA[C][3]

AM22 RxDATA[C][2]

AN22

AP22

RxDATA[C][1]

RxDATA[C][0]

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Table 5. Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)

Symbol

Type

I/O

Name/Description

AM13 RxDATA[D][15]

AL13 RxDATA[D][14]

AR12 RxDATA[D][13]

AP12 RxDATA[D][12]

AN12 RxDATA[D][11]

AM12 RxDATA[D][10]

3.3 V

Receive Data Channel D. Used to transport data out of the

UTOPIA PHY Rx block. RxDATA[D][15:0] is only valid when

RxENB[D] is asserted, and is updated on the rising edge of

RxCLK[D]. Note that RxDATA[D][15:0] is used in various UTO-

PIA modes. In U2 or U2+, all 16 bits are valid. In U3+ (8-bit

mode), only bits 15 to 8 are valid.

AL12

AR11

AP11

AN11

RxDATA[D][9]

RxDATA[D][8]

RxDATA[D][7]

RxDATA[D][6]

In U3 or U3+ (32-bit mode), channel D port must be provisioned

to idle mode.

Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB).

AM11 RxDATA[D][5]

AR10

AP10

AN10

RxDATA[D][4]

RxDATA[D][3]

RxDATA[D][2]

AM10 RxDATA[D][1]

AL10

RxDATA[D][0]

AR9

AR22

AJ33

T34

RxPRTY[D]

RxPRTY[C]

RxPRTY[B]

RxPRTY[A]

3.3 V

Receive Parity. This signal indicates the parity on the

RxDATA[D:A][15:0]. Odd or even parity may be provisioned

through a software register. RxPRTY[D:A] is considered valid

only when RxENB[D:A] is asserted, and is updated on the rising

edge of RxCLK[D:A].

In U3 or U3+ (32-bit mode), the RxPRTY[A] parity pin of port A

indicates the parity for the entire 32-bit data output.

AP9

AL21

AJ32

U31

RxSOP/C[D]

RxSOP/C[C]

RxSOP/C[B]

RxSOP/C[A]

3.3 V

Receive Start of Packet/Cell. In ATM mode, RxSOP/C[D:A]

signal marks the start of a cell on the RxDATA[D:A][15:0] bus.

When RxSOP/C[D:A] is high on the clock cycle following the

latching of an active RxENB[D:A] signal, the first word of the cell

structure is present on the RxDATA[D:A][15:0] bus.

In packet modes, the RxSOP/C[D:A] signal marks the start of a

packet on the RxDATA[D:A][15:0] bus. When RxSOP/C[D:A] is

high, the first word of the packet is present on the

RxDATA[D:A][15:0] bus.

RxSOP/C[D:A] is considered valid only when RxENB[D:A] is

asserted, and is updated on the rising edge of RxCLK[D:A].

In U3 or U3+ (32-bit mode), only the RxSOP/C[A] pin of port A is

used to indicate a start of packet/cell for the 32-bit data output.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Table 5. Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)

Symbol

Type

I/O

Name/Description

AL9

AP21

AK33

V33

RxPA[D]

RxPA[C]

RxPA[B]

RxPA[A]

3.3 V

Receive Cell/Packet Available. This signal indicates when the

TDAT042G5 receive FIFO can send data to the master device.

The RxPA[D:A] signal behavior depends on the provisioned low

watermark in the UTOPIA interface.

^IOne-Cycle Delay Mode. This mode follows the UTOPIA Level

2 Standard. The RxPA response occurs one cycle after the

address is polled. RxENB is asserted to activate the selected

PHY. RxDATA and RxSOP are output one cycle after RxENB is

sampled active by the PHY device.

^ITwo-Cycle Delay Mode. This mode follows the UTOPIA Level

3 baselined text*. The RxPA response occurs two cycles after

the address is polled. RxENB is asserted to activate the

selected PHY. RxDATA and RxSOP are output two cycles after

RxENB is sampled active by the PHY device.

^IRxPA[D:A] Assertion. RxPA[D:A] goes high (is asserted)

when the amount of data in the receive FIFO has reached or

exceeded the low watermark or there is end of packet (EOP)

resident in the FIFO.

^IRxPA[D:A] Deassertion. In ATM mode, the RxPA[D:A] signal

goes low (is deasserted) when the FIFO has less than the low

threshold amount of data and there is no EOP inside the FIFO

(i.e., part of an ATM cell). Once the last byte of the current cell

is transmitted, and if the amount of data within the FIFO is still

less than the low threshold, RxPA[D:A] is deasserted.

In packet mode, the RxPA[D:A] signal goes low (is deasserted)

when the FIFO has less than the low threshold amount of data

and there is no EOP inside the FIFO.

Once the data transfer begins (since the amount of data has

reached or exceeded the low watermark), and if there is no

EOP below the low threshold (i.e., a long packet), the RxPA

signal is deasserted when the FIFO is drained by the UTOPIA

master device. In this case, the master must closely monitor the

RxPA[D:A] signals and use these signals as data valid indica-

tors to ensure that bad data is not read from the TDAT042G5.

TDAT042G5 will deassert the RxPA[D:A] signal immediately

when the FIFO is drained.

* ATM Forum Technical Committee, UTOPIA Level 3, STR-PHY-UL3-01.00, July

1999.

(See further description on next page.)

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Table 5. Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)

Symbol

Type

I/O

Name/Description

AL9

AP21

AK33

V33

RxPA[D]

RxPA[C]

RxPA[B]

RxPA[A]

3.3 V

Receive Cell/Packet Available. (continued)

^IData Transfer. A TDAT042G5 ingress channel sends data

when it has asserted RxPA[D:A] and the master device

requests data (via RxENB[D:A]). In ATM mode, if the master

device requests data using RxENB[D:A] and if the TDAT042G5

has less than the low watermark amount of data to send and

there is no end of cell in the FIFO (RxPA[D:A] is deasserted),

then the TDAT042G5 UTOPIA interface will send out data that

should be ignored by the master, i.e., it does not send data from

its internal FIFO.

In ATM mode, once an ATM cell transfer starts, the Tx or Rx

side must complete the transfer. If the transfer is not com-

pleted, then the cell will be corrupted. The transfer continues

until either (1) the end of cell is reached, when the end of cell

exists below the low watermark, or (2) the end of the FIFO is

reached. If the end of the FIFO is reached, no underflow is

flagged on the receive side. In ATM mode, the low watermark

should be set so that at least one entire cell is in the FIFO prior

to asserting RxPA[D:A].

In packet mode, once the data transfer begins, the RxPA[D:A]

signal will remain asserted until the FIFO is drained if there is

no EOP below the low watermark. During the time RxPA[D:A] is

asserted, valid data is being transferred.

RxPA[D:A] is updated on the rising edge of RxCLK[D:A].

In 32-bit mode, only the RxPA[A] pin of port A is used to indi-

cate the packet/cell available status.

^IMPHY Support. When the RxPA signals are used for MPHY

direct status, the corresponding RxCLK[B, C, and/or D] must be

provided. This clock will be the same as RxCLK[A].

AM9

AN21

AK34

U34

RxENB[D]

RxENB[C]

RxENB[B]

RxENB[A]

3.3 V

(5 V tolerant)

Receive Data Enable (Active-Low). This signal is used to indi-

cate to the UTOPIA PHY Rx block that it is selected. If

RxENB[D:A] is high, no operation is performed. If RxENB[D:A] is

low, the UTOPIA PHY Rx block sends data (not necessarily valid

data).

In U3 or U3+ (32-bit mode), only the RxENB[A] input pin of port A

is used to enable the transfer of data.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Table 5. Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)

Symbol

Type

I/O*

Name/Description

AM8

AN20

AL34

W33

RxCLK[D]

RxCLK[C]

RxCLK[B]

RxCLK[A]

3.3 V

(5 V tolerant)

I^u/O Receive Clock. This clock is used to read cells or packets from

the receive FIFO. RxCLK[D:A] can operate at speeds from dc to

104 MHz. For clock rates above 52 MHz, the receive clock must

be placed in source mode.

RxCLK[D:A] sourcing from the respective TxCLK[D:A] may be

provisioned by CLOCK_MODE_Rx (see registers 0x020F,

0x0213, 0x0217, 0x021B on pages 114—115).

In U3 or U3+ (32-bit mode), only the RxCLK[A] input/output pin of

port A is used to clock the data output.

If MPHY mode is used, then all clocks RxCLK[D:A] must be pro-

vided.

AN8

AM20

AK31

W35

RxSZ[D]

RxSZ[C]

RxSZ[B]

RxSZ[A]

3.3 V

Receive Size. These pins are used only in U2+ and U3+ (packet)

modes. This signal defines the valid bytes received and their

packing within (1) RxDATA[D:A][15:0] for U2+ 16-bit mode, and (2)

RxDATA[A][15:0] and RxDATA[B][15:0] for the U3+ (32-bit mode).

The meaning of these bits may be inverted through UT register

0x0226 TxSIZE/RxSIZE mode, page 164.

In U3+ (8-bit mode), RxSZ[D:A] are unused.

For U2+ 16-bit mode,

RxSZ[D:A] = 0 defines the MSByte of RxDATA[D:A][15:0], i.e.,

RxDATA[D:A][15:8], to be the last byte of the packet received

when using the default configuration.

RxSZ[D:A] = 1 defines the LSByte of RxDATA[D:A][15:0], i.e.,

RxDATA[D:A][7:0], to be the last byte of the packet received

when using the default configuration.

In U3+ (32-bit mode), the MSByte will be placed on RxDATA[A],

bits 15 to 8. In the 16-bit mode, the MSByte will be placed on

RxDATA[D:A], bits 15 to 8.

For U3+ (32-bit mode), RxSZ[A] and RxSZ[B] are combined to

define four states of the received data stream. RxSZ[C] and

RxSZ[D] are unused. The following states are assigned by

RxSZ[A] and RxSZ[B] when RxEOP[A] is asserted and the

default configuration is provisioned.

RxDATA[A]

RxDATA[B]

RxDATA[A][15:8] RxDATA[A][7:0]

RxDATA[B][15:8] RxDATA[B][7:0]

RxSZ[A] RxSZ[B]DATA[31:24] DATA[23:16]

DATA[15:8]

Not valid

Valid

DATA[7:0]

Not valid

Valid

Not valid

Valid

The data bytes are packed into the upper transmitted bytes first.

* I = I = 50 kΩ, where I = internal pull-up resistance and I = internal pull-down resistance.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Table 5. Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)

Symbol

Type

I/O*

Name/Description

AN9

AM21

AJ31

U32

RxEOP[D]

RxEOP[C]

RxEOP[B]

RxEOP[A]

3.3 V

Receive End of Packet. These pins are used only in U2+ and

U3+ (packet) modes. This signal indicates that the last word of a

packet is on the RxDATA[D:A][15:0] bus. RxEOP[D:A] is valid only

when RxENB[D:A] is asserted, and is updated on the rising edge

of RxCLK[D:A].

In U3+ (32-bit mode), only the RxEOP[A] output pin of port A is

used to indicate the end of the outgoing packet.

AP8

AR21

AK32

V32

RxERR[D]

RxERR[C]

RxERR[B]

RxERR[A]

3.3 V

Receive Error. These pins are used only in U2+ and U3+

(packet) modes. RxERR[D:A] is only used in POS mode, and indi-

cates that the current packet is to be aborted and discarded, if

possible. RxERR[D:A] is only valid when RxEOP[D:A] and

RxENB[D:A] are asserted, and is updated on the rising edge of

RxCLK[D:A].

If the Rx FIFO overflows, RxERR[D:A] and RxEOP[D:A] are

asserted to indicate a corrupted packet.

RxERR is asserted when a CRC error occurs in any packet mode

using CRC-16 or CRC-32. RxERR is asserted when an incoming

packet has an abort flag at the end of its stream. In both of these

cases, an RxEOP is asserted with the RxERR.

RxERR is not asserted when a header does not match in PPP

header attaching mode. In that case, no data is sent to the UTO-

PIA interface.

In U3+ (32-bit mode), only the RxERR[A] output pin of port A is

used to indicate an error on the outgoing packet.

* I = I = 50 kΩ, where I = internal pull-up resistance and I = internal pull-down resistance.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Table 6. Pin Descriptions—Microprocessor Interface Signals

Symbol

Type

I/O*

Name/Description

RST

3.3 V

(5 V tolerant)

I^uReset (Asynchronous) (Active-Low). Reset must be held

active-low for a minimum of 100 ns. After deassertion of reset, the

device is reset and available for use after 8 µs.

ICT

3.3 V

(5 V tolerant)

I^u3-State Control (Active-Low). ICT has an internal 100 kΩ pull-

up. This control 3-states the digital outputs. It does not control the

LVPECL outputs.

PMRST

3.3 V

I/O 1-Second Performance Monitor (PM) Clock. PM clock can be

(5 V tolerant)

generated on-chip. This signal will have a 50% duty cycle.

PMRST clock may be programmed by core register 0x0013,

bit 15 (PMRST_I/O_CTRL) to be either an output or input. As an

output clock, it is derived from the transmit line clock, TxCKP/N.

This clock is divided to produce a 1 second, 50% duty cycle clock

output. As an input, PMRST is under software control and can be

activated longer or shorter than once per second. In the software

control mode with PMRST an input, the minimum pulse width of

the external PMRST signal is 10 ms.

MPMODE

MPCLK

3.3 V

(5 V tolerant)

I^uMPU Mode Select. This signal is set high for a synchronous

microprocessor, or low for an asynchronous microprocessor.

I^uMPU Clock. This clock can operate from 1 Hz to 66 MHz when in

synchronous mode.

I^uChip Select (Active-Low). This signal must be low during regis-

3.3 V

(5 V tolerant)

3.3 V

(5 V tolerant)

ter access.

INT

3.3 V

Interrupt (Active-Low). This signal goes low when the device

(open drain)

generates an unmasked interrupt.

A12

B12

C12

D12

E12

A11

B11

C11

D11

A10

B10

C10

D10

E10

DATA[15]

DATA[14]

DATA[13]

DATA[12]

DATA[11]

DATA[10]

DATA[9]

DATA[8]

DATA[7]

DATA[6]

DATA[5]

DATA[4]

DATA[3]

DATA[2]

DATA[1]

DATA[0]

3.3 V

(5 V tolerant)

I^u/O Data Bus. This bus is a bidirectional data bus for writing and

reading software registers. [15:0] refers to a 16-bit data bus

(15 = MSB, 0 = LSB).

* I = I = 50 kΩ, where I = internal pull-up resistance and I = internal pull-down resistance.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Table 6. Pin Descriptions—Microprocessor Interface Signals (continued)

Symbol

Type

I/O*

Name/Description

B16

C16

D16

A15

B15

C15

E15

A14

B14

C14

D14

E14

B13

C13

D13

E13

ADDR[15]

ADDR[14]

ADDR[13]

ADDR[12]

ADDR[11]

ADDR[10]

ADDR[9]

ADDR[8]

ADDR[7]

ADDR[6]

ADDR[5]

ADDR[4]

ADDR[3]

ADDR[2]

ADDR[1]

ADDR[0]

3.3 V

(5 V tolerant)

I^uAddress Bus. This bus is used to address registers. [15:0] refers

to a 16-bit data bus (15 = MSB, 0 = LSB).

ADS

3.3 V

(5 V tolerant)

I^uAddress Strobe (Active-Low). This signal indicates the address

is valid for MPU access in the asynchronous mode, and transfer

start for the synchronous mode.

R/W

3.3 V

(5 V tolerant)

I^uRead/Write. This signal is low to indicate a write operation and is

high to indicate a read operation.

3.3 V

(5 V tolerant)

I^uData Strobe (Active-Low). This signal used in the asynchronous

mode (MPMODE = 0) indicates that the data is valid for MPU

writes.

3.3 V

Data Transfer Acknowledge (Active-Low). This signal acknowl-

edges the data transfer cycle.

* I = I = 50 kΩ, where I = internal pull-up resistance and I = internal pull-down resistance.

Table 7. Pin Descriptions—General-Purpose I/O Signals: Interface Signals

Symbol

Type

I/O*

Name/Description

AG5

AH2

AH3

AH4

GPIO[3]

GPIO[2]

GPIO[1]

GPIO[0]

3.3 V

(5 V tolerant)

I^u/O General-Purpose I/O. These programmable I/O pins may be

used to monitor or control external circuitry. These pins may also

be provisioned to cause an interrupt upon a change in their val-

ues.

* I = I = 50 kΩ, where I = internal pull-up resistance and I = internal pull-down resistance.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Table 8. Pin Descriptions—JTAG Interface Signals

Symbol

Type

I/O*

Name/Description

TCK

3.3 V

I^uJTAG Test Clock. This 10 MHz signal provides timing for test

(5 V tolerant)

operations.

TMS

TDI

3.3 V

I^uJTAG Test Mode Select. Controls test operations. TMS is sam-

(5 V tolerant)

pled on the rising edge of TCK.

I^uJTAG Test Data In. Provides a 10 Mbits/s test data input signal.

3.3 V

(5 V tolerant)

TDI is sampled on the rising edge of TCK.

TDO

3.3 V

JTAG Test Data Out. This 10 Mbits/s data output signal is

updated on the falling edge of TCK. The TDO output is 3-stated

except when scanning out test data.

TRST

3.3 V

(5 V tolerant)

I^uJTAG Test Reset (Active-Low). This signal provides an asyn-

chronous reset for the TAP. Under normal device operations,

TRST should be pulled low. TRST is a Schmitt-triggered input.

* I = I = 50 kΩ, where I = internal pull-up resistance and I = internal pull-down resistance.

Note: JTAG interface signals are used for test operations that are carried out using the IEEE P1149.1 test access port. IEEE is a registered

trademark of The Institute of Electrical and Electronics Engineers, Inc.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Table 9. Pin Descriptions—Power Signals

Symbol

Type*

I/O

Name/Description

VDDA

VDDD

—

Analog Power Supply.

A1, A2, A5, A6, A17,

A18, A30, A31, A34,

A35, B1, B2, B34, B35,

C3, C33, D4, D27, D32,

E1, E5, E11, E16, E20,

E25, E31, E35, F1, F35,

K5, L5, L31, M5, P4, R1,

T5, T31, U35, V1, V2,

V35, W1, Y5, Y31, AB5,

AD5, AE5, AE31, AF5,

AK1, AK35, AL1, AL5,

AL11, AL16, AL18,

Digital Power Supply.

AL20, AL25, AL31,

AL35, AM4, AM32, AN3,

AN33, AP1, AP2, AP34,

AP35, AR1, AR2, AR5,

AR6, AR18, AR19,

AR30, AR31, AR34,

AR35

VDDD PLL

GNDA

—

Digital Power Supply PLL.

Analog Ground.

A3, A4, A7, A8, A13,

A16, A20, A23,

GNDD

Digital Ground.

A27, A28, A29, A32,

A33, B3, B4, B32, B33,

C1, C2, C4, C32, C34,

C35, D1, D2, D3, D33,

D34, D35, F3, G1, G35,

H1, H3, H5, H35, N1,

N35, T1, T35, V3, V31,

Y1, Y4, Y35, AA5, AC1,

AC35, AH1, AH35, AJ1,

AJ35, AM1, AM2, AM3,

AM33, AM34, AM35,

AN1, AN2, AN4, AN6,

AN32, AN34, AN35,

AP3, AP4, AP32, AP33,

AR3, AR4, AR7, AR8,

AR13, AR16, AR20,

AR23, AR28, AR29,

AR32, AR33

GNDD PLL

—

Digital Ground PLL.

* P = power.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information (continued)

Table 10. Pin Descriptions—No Connect Pins

Symbol

Type

I/O

Name/Description

E6, D6

—

No Connection. Has internal pull-up resistor.

Do not connect to these pins.

A19, A21, A22, A24,

A25, A26, B5, B17, B18,

B19, B20, B21, B22,

B23, B24, B25, B26,

B27, B28, B29, B30,

B31, C5, C17, C18, C19,

C20, C21, C22, C23,

C24, C25, C26, C27,

C28, C29, C30, C31, D5,

D15, D17, D18, D19,

D20, D21, D22, D23,

D24, D25, D26, D28,

D29, D30, D31, E2, E17,

E18, E19, E21, E22,

E23, E24, E26, E27,

E28, E29, E30, E32,

E33, E34, F5, F31, F32,

F33, F34, G4, G31, U33,

V34, AL8, AL19, AM7,

AM19, AN19, AN31,

AP5, AP7

—

No Connection. Do not connect to these pins.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Overview

This device integrates the SONET/SDH interface termination functions with a generic cell/packet delineation cir-

cuit. It supports STS-48/STM-16, quad STS-12/STM-4, and quad STS-3/STM-1 interface rates. Up to four data

channels transported within an STS-N payload are processed via the SONET/SDH termination blocks and the on-

chip data encapsulation/decapsulation engine. Packet orATM data are transmitted/received by this device on the

equipment side via the enhanced UTOPIA interface. SONET/SDH streams are transmitted/received by this device

on the network side via the line interface.

Concatenation levels supported by this device range from STS-1 to STS-48c. Valid standard concatenated

SONET frame configurations for this device are STS-3c, STS6c, STS-9c, STS-12c, STS-15c, STS-18c, and STS-

48c. Non-standard concatenation levels (such as STS-4c, STS-5c, STS-7c, etc.) are supported as well. In STS-48

mode, four pointer processors are available. This allows an STS-48 frame to carry up to four concatenated sub-

frames (for example, mapping of four STS-12c payloads into an STS-48 frame). In quad STS-3 and STS-12

modes, only one pointer processor is available. Therefore, only a single subframe may be mapped into an STS-3

or STS-12 frame (mapping a single STS-3c payload into an STS-12 frame, for instance). For details, see Table 22

on page 68.

This device supports mapping for ATM cells into SONET/SDH, mapping for packet data via all existing or currently

proposed standards (e.g., PPP, SDL) into SONET/SDH streams. Via SDL mapping, this device also supports

packet over fiber or ATM over fiber, respectively. Figure 2 shows the overview block diagram, and Figure 3 shows

the interface block diagram for this device.

PAYLOAD

TERMINATION

LINE

PATH

TERMINATION TERMINATION

PACKET/CELL

SINGLE STM-16/STS-48

OR QUAD STM-4/STS-12

OR QUAD STM-1/STS-3

OVERHEAD

SPE

PROCESSOR

MAPPER

-ENCAPSULATION

-SCRAMBLING

-CRC GENERATION

INSERT

ENHANCED

UTOPIA

ENHANCED

UTOPIA

INTERFACE

COMPATIBLE

INTERFACE

(U2, U2+, U3, U3+)

PACKET/CELL

PROCESSOR

-DELINEATION

-DECAPSULATION

-UNSCRAMBLING

-CRC VERIFICATION

SINGLE STM-16/STS-48

OR QUAD STM-4/STS-12

OR QUAD STM-1/STS-3

OVERHEAD

POINTER

PROCESSOR

INTERPRETER

MONITOR

CONTROL

µP INTERFACE

5-6680(F).ar.15

Figure 2. Overview Block Diagram

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Overview (continued)

Figure 3 shows the interface diagram of the IC.

ATM/HDLC/SDL

FRAME INSERTION

SCRAMBLING

TRANSMIT

OVERHEAD

PROCESSOR

SPE

MAPPER

UTOPIA

ENCAPSULATION

STS-3/STM-1

STS-12/STM-4

STS-48/STM-16

ENHANCED

UTOPIA

INTERFACE

OVERHEAD

INTERFACE

ATM/HDLC/SDL

FRAME

UNSCRAMBLING

DECAPSULATION

RECEIVE

OVERHEAD

PROCESSOR

POINTER

INTERPRETER

UTOPIA

STS-3/STM-1

STS-12/STM-4

STS-48/STM-16

TOH

INTERFACE

MPU

INTERFACE

JTAG

INTERFACE

5-6746(F)r.11

Figure 3. Interface Block Diagram

The receive path terminates and processes section, line, and path overhead. It performs framing (A1, A2),

descrambling, detects alarm conditions, and monitors section, line, and path BIP-Ns (B1, B2, B3), accumulating

error counts for each level for performance monitoring purposes. Line and path remote error indications (M1, G1)

are also accumulated. The payload pointers (H1, H2) are interpreted, and the synchronous payload envelope

(SPE) is extracted.

The transmit path inserts section, line, and path overhead. It inserts the framing pattern (A1, A2), performs scram-

bling, inserts AIS (optionally), and calculates and inserts section, line, and path BIP-8s (B1, B2, B3). Line and path

remote failure indications (M1, G1) are inserted based on received BIP-8 errors. The payload pointers (H1, H2) are

generated, and the SPE is inserted.

When used to implement an ATM UNI, ATM cells are written into an internal 4-cell FIFO buffer using a generic

8-/16-/32-bit wide UTOPIA 2/3 compliant interface. Idle/unassigned cells are automatically inserted when the inter-

nal FIFO is empty. The device provides generation of the header check sequence and optionally scrambles the

ATM payload.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Overview (continued)

When used to implement a POS UNI, the device writes packets into an internal 256-byte FIFO buffer using a

generic 8-/16-/32-bit wide enhanced UTOPIA 2/3 compliant interface. HDLC framing performs the insertion of

flags, control escape characters, and the FCS fields. Either the CRC-ITU or CRC-32 (in regular or reversed mode)

can be computed and added to the frame. Counts of transmitted packets and errored/dropped packets are accu-

mulated for performance monitoring purposes.

ATM/HDLC/HDLC-CRC/PPP Support

TDAT042G5 supports the transfer of ATM cells or variable-length packets. Support for 52- or 53-byte cell sizes is

provided at the UTOPIA interface through register provisioning. The following three types of packet data can be

sent and received with HLDC-like framing: transparent HDLC, CRC, and PPP. Transparent HDLC contains 0x7E

framing but no CRC. CRC mode is HDLC with an attached CRC. PPP has 0x7E framing with provisionable

attached header information and CRC.

When used to implement an ATM UNI, the device performs cell delineation on the SPE. HEC error correction is

provided. Idle/unassigned cells may be dropped according to a programmable filter. Cells are also dropped upon

detection of an uncorrectable header check sequence error. The ATM cell payloads are descrambled before being

passed to a 4-cell FIFO buffer. The received cells are read from the FIFO using a generic 8-/16-/32-bit wide

UTOPIA 2/3 compliant interface. Counts of received ATM cells, uncorrectable HEC errors, and correctable HEC

errors are accumulated independently for performance monitoring purposes.

When used to implement a POS UNI, the device descrambles the SPE before extracting HDLC frames. The con-

trol escape characters are removed. Descrambling can be performed after control escape byte destuffing (or

before to control malicious HDLC expansion). The optional 16- or 32-bit error check sequence is verified for cor-

rectness. The packets are placed into a 256-byte FIFO buffer.* The received packets are read from the FIFO using

a generic 8-/16-/32-bit wide enhanced UTOPIA 2/3 compliant interface. Counts of received packets and errored/

dropped packets are accumulated independently for performance monitoring purposes. The device POS imple-

mentation also allows the optional attach/detach of a per-channel provisionable PPP header.

* FIFOs are 256 bytes per channel and cannot be reallocated.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Overview (continued)

SDL Support

Supports the simplified data link (SDL) protocol, which is currently being reviewed in standards bodies. The imple-

mentation supports 4-byte modified SDL UNI including the following:

^ICRC-16 based frame delineation with 2-byte packet field length

^IForty-eighth order scrambler

^INo HDLC-like packet expansion

^IOptional CRC-16/-32 payload check

^ICapable of packet-over-fiber operation (i.e., no SONET frame)

^ITwo user-programmable 6-byte OAM messages

^IOptional offset field from 0 to 32 bytes

TDAT042G5 provides support for a provisionable offset to the packet to allow for the attachment of layer 2 routing

information (e.g., MPLS tags). Table 11 defines the provisioned value for each offset.

Table 11. Optional Offset Field

Provisioned

Value

Route Tag Length

(Bytes)

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

0x8

0x9

0xA

0xB

0xC

0xD

0xE

0xF

The packet length value (header value that CRC is calculated over) will account for the total length of the packet

datagram as well as the associated route tags.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Overview (continued)

Over-Fiber Mode

Over-fiber mode is used for packet delivery over fiber. No SONET overhead is added in this mode. Since no

SONET overhead is added, the OHP and PT blocks must be configured for the bypass mode.

In transmitting from the TDAT042G5 to the line, the data engine maps the data payload into a full SONET frame

starting at what normally would be the first A1 byte. The data engine continues to map payload into the full SONET

frame until an end of packet or end of frame is reached, at which time the data engine halts the mapping of the

incoming data stream into the SONET frame until the next start of frame.

When TDAT042G5 is receiving from the line, the data engine must be provisioned to receive the maximum packet

size, unless the location of the last byte of the packet is known in advance. If the size of the packet is not known,

one must program the data engine to receive the entire SONET frame. The external UTOPIA interface device must

then be capable of extracting the variable length packets from the full SONET frame.

Details of the over-fiber mode are given in the Data Engine (DE) Block section, page 82.

Test and General-Purpose I/O Support

The device is provisioned, controlled, and monitored using a generic 16-bit microprocessor interface. A standard

five-signal IEEE -1149.1 compliant JTAG test port is also provided for boundary-scan purposes.

A 4-bit GPIO (general-purpose input/output) interface is provided to control and/or monitor other onboard devices.

External Interfaces

Figure 4 shows the external interfaces.

T^XTOHF

T^XTOHCK

R^XREF

R^XTOHF

R^XTOHD

T^XTOHD

R^XTOHCK

348 SIGNAL PINS

OHP

TxFSYNC

TxCK

4 x 24 Tx UTOPIA

+5 MPHY ADDRESS

T^XLINE

TxCKQ

TxD

ECLREF

RxD

4 x 24 Rx UTOPIA

+5 MPHY ADDRESS

R^XLINE

RxCLK

CLKDIV

MPU AND TEST INTERFACE

DATA

GPIO

ICT

MPMODE

ADS

ADDR

JTAG

RST PMRST

MPCLK INT

R/W

5-6745(F).br.3

Figure 4. External Interface Summary Diagram

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description

The block diagram for this device can be seen in Figure 5.

TOH I/O

OHP

Tx LINE I/O

Tx UTOPIA I/O

Rx UTOPIA I/O

Rx LINE I/O

CTRL

JTAG

GPIO

5-7055(F).br.2

Figure 5. Functional Block Diagram

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description (continued)

Line Interface Block

This device is designed to work with commonly available optoelectronic converters for OC-3, OC-12, and OC-48

line rates. It will also work with available multiplexer and demultiplexer chip sets for an STS-48/STM-16 line inter-

face rate. The line interface will operate in one of three possible modes, and is provisioned through core register

0x0010 (mode), bits 4—0. These three values of the mode register are the only values allowed.

Table 12. Line Interface Modes

Mode[4:0]

Core Register

0x0010

Interfaces

Line Interface Signals

10000

01111

STS-48/STM-16

STS-12/STM-4

RxCKP/N, RxD[15:0]P/N, TxCKP/N, TxD[15:0]P/N

RxCLK[D]P/N, RxD[D]P/N, TxCKP/N, TxD[D]P/N

RxCLK[C]P/N, RxD[C]P/N, TxCKP/N, TxD[C]P/N

RxCLK[B]P/N, RxD[B]P/N, TxCKP/N, TxD[B]P/N

RxCLK[A]P/N, RxD[A]P/N, TxCKP/N, TxD[A]P/N

00000

STS-3/STM-1

RxCLK[D]P/N, RxD[DP/N, TxCKP/N, TxD[D]P/N

RxCLK[C]P/N, RxD[C]P/N, TxCKP/N, TxD[C]P/N

RxCLK[B]P/N, RxD[B]P/N, TxCKP/N, TxD[B]P/N

RxCLK[A]P/N, RxD[A]P/N, TxCKP/N, TxD[A]P/N

This block provides the interface between the external SONET/SDH line components and the overhead processor

(OHP) block. The line interface must provide transmit/receive functions for quad STS-3/STM-1, quad STS-12/

STM-4, and STS-48/STM-16 applications. All external inputs and outputs for the TDAT042G5 line I/O block are ref-

erenced to the positive edge of the clock. When the external devices are referenced to the negative edge, the dif-

ferential input clock will need to be reversed at the TDAT042G5 input.

Receive Line Interface Summary

The following list summarizes the receive line interface operations for each STS mode:

^IIn quad STS-3/STM-1 mode, the receive line interface provides four separate STS-3/STM-1 input pin groups.

Each input group comprises a differential LVPECL 155.52 Mbits/s data input and a differential 155.52 MHz clock.

Each input group provides data to only one of four (A, B, C, or D) OHP blocks. This interface is synchronous and

requires an external CDR.

^IIn quad STS-12/STM-4 mode, the receive line interface provides four separate STS-12/STM-4 input pin groups.

Each input group comprises a differential LVPECL 622.08 Mbits/s data input and a differential 622.08 MHz clock.

Each input group provides data to only one of four (A, B, C, or D) OHP blocks. This interface is synchronous and

requires an external CDR.

^IIn the STS-48/STM-16 mode, the device provides 16 differential LVPECL data inputs at 155.52 Mbits/s with a dif-

ferential LVPECL 155.52 MHz clock. In this mode, an external 1:16 data demultiplexer with a 1/16 clock divider is

required. External barrel shifter circuitry to byte align the data is not required.

^IMultiplexers select between the terminal loopback data, the 32-bit parallel STS-48/STM-16 data bus, and the

four STS-12/STM-4 or STS-3/STM-1 8-bit parallel data buses. The controls for these MUXes are mode (register

0x0010) and loopback (register 0x0012) provided by the control block (see Table 48 and Table 50 on pages

150—151).

^IFor STS-48 mode, the 155.52 MHz input clock is divided by two to 77.76 MHz and distributed to all four multi-

plexers. For the STS-12/STM-4 mode, each 622.08 MHz input clock is divided by eight to 77.76 MHz. Each

77.76 MHz clock is distributed to the appropriate clock multiplexer (A, B, C, or D). For the STS-3/STM-1 mode,

each 155.52 MHz input clock is divided by eight to 19.44 MHz. Each 19.44 MHz clock is distributed to the appro-

priate clock multiplexer (A, B, C, or D).

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description (continued)

Line Interface Block (continued)

Transmit Line Interface Summary

The following list summarizes the transmit line interface operations for each STS mode.

^IIn quad STS-3/STM-1 and STS-12/STM-4 modes, the transmit line interface receives 8 bits of data from each

OHP block (A, B, C, and D) at 19.44 Mbits/s and 77.76 Mbits/s, respectively. An 8-to-1 parallel-to-serial conver-

sion produces output data at 155.52 Mbits/s for STS-3/STM-1 mode and 622.08 Mbits/s for STS-12/STM-4

mode. For facility loopback, the outputs are multiplexed with the corresponding data from the STS-12/STS-3

(STM-4/STM-1) receive block and sent to four differentialLVPECL buffers.

^IIn STS-48/STM-16 mode, a 32-bit data word at 77.76 Mbits/s is received from the OHP. Then a 2-to-1 parallel-to-

parallel conversion is performed producing a 16-bit word at 155.52 Mbits/s. In this mode, an external 16:1 data

demultiplexer is required. Facility loopback is not available for the STS-48/STM-16 mode.

^IThere is a single clock input, TxCKP/N, in the transmit case. The clock source rates are 622.08 MHz (STS-12/

STM-4), 155.52 MHz (STS-3/STM-1), or 155.52 MHz (STS-48/STM-16).

In the STS-48/STM-16 case, two transmit clock modes are available, contra* and forward clocking. In the contra-

clocking mode, the transmit data is sent out as commanded by TxCKP/N; in addition, an internal PLL must be

activated, core register 0x0010 bit 5, to minimize the phase delay between TxCKP/N and the transmitted data. In

the forward clocking mode, the transmit data and the clock, TxCKQ (used to clock out the data), are sent in par-

allel to the transmit multiplexer.

In STS-12/STM-4 and STS-3/STM-1 modes, the input clock is divided by eight producing the internal clock at

77.76 MHz and 19.44 MHz, respectively. In STS-48/STM-16 mode, the input clock is divided by eight to produce

an internal clock at 77.76 MHz. The CLKDIV pin (H4) controls this division. Table 13 shows the required value of

CLKDIV.

Table 13. Clock Settings for CLKDIV Pin

CLKDIV Pin

Description

CLKDIV = 1

CLKDIV = 0

When in STS-12/STM-4 (622.08 MHz divide by 8).

When in STS-3/STM-1, STS-48/STM-16 (155.52 MHz divide by 2).

^ITxFSYNCP/N is an optional external frame sync. This 8 kHz frame sync pulse must be synchronous with

TxCKP/N. It is, at minimum, a one TxCKP/N clock cycle wide pulse that is latched in at the system rate

(622.08 MHz or 155.52 MHz). TOH interface signal RxREF should not be used as a source to TxFSYNCP/N.

^IThe active edge of the transmit clock is the positive edge.

^IWhen TDAT042G5 operates in asynchronous mode (MPMODE = 0), the line block provides the microprocessor

clock to the microprocessor interface block. The CLKDIV pin must be set to ensure that the clock is always

77.76 MHz.

Line interface timing is given in the Interface Timing Specifications section (see Table 168, page 267).

* Contra refers to a type of data transmission whereby a clock signal is received by a register before the register sends data.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description (continued)

SONET Framer

The SONET framer consists of the overhead processor (OHP) and path terminator (PT) blocks. The receive

SONET framer requires 625 µs to drop frame after the line input signal is lost. Once a valid receive line input is

restored, the maximum average reframe time (MART) is 250 µs.

Overhead Processor (OHP) Block

The OHP block terminates/generates the section and line overhead bytes of the line. The data rate of the TOH

interface is given in Table 14. Timing for the TOH interface is given in the Interface Timing Specifications section

(see Table 172 and Table 173, page 271).

Table 14. R/T TOH Interface Rates

Mode

R/T TOH Interface Rate

STS-48/STM-16

STS-12/STM-4

STS-3/STM-1

20.736* Mbits/s

20.736 Mbits/s

5.184 Mbits/s

* This STS-48/STM-16 interface is a four-line interface resulting in an effective interface rate

of 82.944 Mbits/s.

All receive transport overhead bytes are output on the RTOH interface for external processing. Transmit transport

overhead bytes can optionally be inserted from the TTOH interface.

The transmit transport overhead bytes can be inserted in one of three ways selected through software provision-

ing: (1) automatically by hardware, (2) via software provisioning, or (3) through the TOAC. Table 15 defines those

overhead bytes that can be inserted via each of the three paths. In some cases, the user has the choice to insert

the byte via software registers or through the TOAC. Superscripts in the table reference these insertion methods

which are described in the footnotes.

Table 15. TOAC Byte Insertion: An STS-3/STM-1 Example

OH Parity³

(1st bit of

1st byte)

X⁶

J0⁵

Z0⁴

X⁶

D1³

X⁶

B1-2¹

D1-2¹

X⁶

B1-3¹

D2-3¹

X⁶

E1⁵

D2³

X⁶

E1-2¹

D2-2¹

X⁶

E1-3¹

D2-3¹

X⁶

F1⁵

D3³

X⁶

F1-2¹

D3-2¹

X⁶

F1-3¹

D3-3¹

X⁶

K1²

D5³

D8³

D11³

Z2³

K1-2¹

D5-2¹

D8-2¹

D11-2¹

Z2-2³

K1-3¹

D5-3¹

D8-3¹

D11-3¹

X⁶

K2²

D6³

D9³

D12³

E2³

K2-2¹

D6-2¹

D9-2¹

D12-2¹

E2-2¹

K2-3¹

D6-3¹

D9-3¹

D12-3¹

E2-3¹

D4³

D7³

D10³

S1⁵

D4-2¹

D7-2¹

D10-2¹

Z1-2³

D4-3¹

D7-3¹

D10-3¹

Z1-3³

1.Inserted via TOAC, but not part of SONET standard.

2.Inserted via software or automatically via hardware.

3.Inserted via TOAC only.

4.Inserted via software register only.

5.Inserted via TOAC or software register.

6.Inserted via TOAC hardware; should be included in TOAC interface timing.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description (continued)

Overhead Processor (OHP) Block (continued)

The TOAC inserter must insert the first bit of A1 at the TOAC input, TxTOHD[D:A], during the first clock cycle when

TxTOHF = 1. The TOAC has a built-in parity checker. For the parity check, the value of the first inserted bit of A1

must be set to the parity value of the previous frame. The remainder of the inserted bits of the A1, A2 bytes are

ignored by the transmit framer.

Receive OHP

Loss-of-Signal. The loss-of-signal block monitors the incoming scrambled data for the absence of transitions.

When an absence of transitions is detected for a programmable length of time, a loss-of-signal (LOS) is declared.

LOS is cleared when two valid framing patterns are detected, and during the intervening time, no LOS condition is

detected.

Framer. The frame block finds and locks onto the incoming A1 and A2 bytes of the SONET transport overhead.

Loss-of-frame (LOF) is declared when a defect persists for more than 3 ms. LOF is cleared when the defect is

absent for more than 3 ms. To prevent intermittent out-of-frame/in-frame conditions, the 3 ms timer is not reset to

zero until an in-frame (or out-of-frame) condition persists for 3 ms. The framer is also responsible for performing bit

rotations on the incoming data stream to ensure that the rest of the IC receives byte-aligned data.

While in-frame, the A1/A2 framing bytes in each frame are compared against the expected pattern. Out-of-frame

(OOF) is declared when five consecutive frames containing one or more framing pattern errors have been

received.

While out-of-frame, this block will monitor the receive data stream for an occurrence of the framing pattern. When a

framing pattern has been recognized, the framer performs the necessary bit rotation and verifies that an error-free

framing pattern is present in the next frame before declaring in-frame.

J0 Section Trace. The section trace message is extracted and stored in a 16-byte memory for access by software.

The first byte of the message can be provisioned to be either:

^IThe byte with the most significant bit (MSB) set high (for SDH), or

^IThe byte following a carriage return (0x0D) and line feed (0x0A) sequence (for SONET).

J0 mismatch detection is provided using one of four methods (provisionable via J0MONMODE[A—D][1:0]; see reg-

ister description, page 173).

Descrambler. The descrambler block implements the frame synchronous SONET descrambler with a generating

polynomial of 1 + x⁶+ x⁷. The framing bytes (A1, A2), the section trace bytes (J0), and the growth bytes (Z0) are

not descrambled. The descrambler may be disabled through a software register.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description (continued)

Overhead Processor (OHP) Block (continued)

Receive OHP (continued)

B1 BIP-8 Check. The SBIP block counts section BIP-8 (B1) errors. The SBIP value is calculated over the scram-

bled data of the complete previous frame. The calculated value is compared against the received B1 byte and dif-

ferences (errors) are counted. A theoretical maximum of 64,000 errors may be detected per second. The SBIP

block accumulates these errors in a 16-bit saturating counter. This counter operates in latch and clear mode to

ensure Bellcore and ITU compliance with regard to not missing any events (bit errors). It is intended that this

counter be polled at least once per second so that no error events are missed. Optionally, a maximum of only

one SBIP error per frame can be counted (provisionable via B1BITBLKCNT[A—D]; see register description,

page 174). This causes the error counter to only increment by one when one or more errors are detected.

B2 BIP-N Check. The LBIP block counts line BIP-N errors. The LBIP value is calculated over the incoming frame

and is compared to the received B2 bytes received in the next frame. The errors are counted. Optionally, a maxi-

mum of only one LBIP error per frame can be counted (B2BITBLKCNT[A—D]; see register description, page 174).

This causes the block error counter to only increment by one when one or more errors are detected. A theoretical

maximum of 3,072,000 errors may be detected per second. The LBIP block accumulates these errors in a 22-bit

saturating counter. This counter is operated in latch and clear mode to ensure Bellcore and ITU compliance with

regard to not missing any events (bit errors). It is intended that this counter be polled at least once per second so

that no error events are missed.

BER Check. The OHP block also detects provisionable signal fail (SF) and signal degrade (SD) conditions. The

SF and SD values are provisioned through a group of software registers (SF addresses 0x0452—0x0469,

SD addresses 0x043A—0x0451). The SF alarm can be provisioned for a bit error rate (BER) of between 10^–3to

10^–5; the SD alarm can be provisioned for a bit error rate (BER) of between 10^–5to 10^–9(see Table 86, page 187).

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description (continued)

Overhead Processor (OHP) Block (continued)

Receive OHP (continued)

Figure 6 illustrates the parameters used in determining the bit error detection rate.

NUMBER OF MONITORING BLOCKS SFBSET[A—D] OR SDBSET[A—D] (IN THIS CASE, 3)

NUMBER OF FRAMES IN A MONITORING BLOCK SFNSSET[A—D] OR SDNSSET[A—D],

SFNSCLEAR[A—D] OR SDNSCLEAR[A—D]

(IN THIS CASE, 7)

FRAME

BOUNDARY

BLOCK

BOUNDARY

SFLSET[A—D] OR SDLSET[A—D]

SFMSET[A—D] OR SDMSET[A—D]

SFLCLEAR[A—D] OR SDLCLEAR[A—D]

SFMCLEAR[A—D] OR SDMCLEAR[A—D]

ACCUMULATED BIP ERROR COUNT:

B1 OR B2 FOR LINE

BLOCK GOOD/BAD COUNT

B3 FOR PATH

5-7934(F)

Figure 6. Signal Degrade and Failure Parameters for BER

TDAT042G5 provides a method to monitor the BER at the line and path layers. The following explains the algo-

rithm for this method to set and clear the BER. The algorithm for this method is the same for setting and clearing

the BER, the only difference is the programmed values. TDAT042G5 includes two complete sets of identical

counters, one used to determine signal fail (SF) and one used to determine signal degrade (SD). The only differ-

ence between SF and SD is the provisioned values. The same algorithm is used for both the line and path layers of

SONET.

The algorithm uses four sets of counters: labelled Ns (number of frames), L (number of errors), M (number of

errored blocks), and B (total number of blocks). Each of these counters has different values that are provisioned to

either set the BER high or clear the BER indication. The algorithm works by counting blocks, i.e., a preset number

of SONET/SDH frames (Ns). If the number of errors in the block exceeds the provisioned level (L), then the errored

block counter is incremented by 1; otherwise, the number of blocks in error stays at its current level. At this point,

the frame counter and the error counter are reset back to 0 and start counting again. At the end of a preset number

of blocks (B), the count in the errored block counter is compared against a provisioned threshold (M). If the total

number of blocks in error equals or exceeds the provisioned threshold (M), then the BER alarm is raised. If the total

number of blocks in error is less than the provisioned amount (M), then the BER alarm is cleared.

The values used by the counters are determined by the state of the algorithm. If the BER state is low, then the SET

parameters are used. If the BER state is high, then the CLEAR parameters are used.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description (continued)

Overhead Processor (OHP) Block (continued)

Receive OHP (continued)

Table 16 and Table 17 show values of Ns, L, M, and B for STS-3/STM-1, STS-12/STM-4, and STS-48/STM-16 to

set and clear the BER indicator. SF registers are 0x0452—0x0469 and SD registers are 0x043A—0x0451. All

SF/SD set and clear values are hexadecimal.

Table 16. Ns, L, M, and B Values to Set the BER Indicator

Mode

BER

SF/SD Set Values

Actual

Number of

Frames

Probability of

Detecting L

Errors (%)

Probability of

Declaring

SF/SD (%)

Integra-

tion

Time

(s)

Max-

imum

Number

of Frames

Ns*

@BER @BER/2 @BER @BER/2

STS-3/

STM-1

1.00E-03

1.00E-04

1.00E-05

1.00E-06

1.00E-07

1.00E-08

1.00E-09

1.00E-10

99.96

72.70

71.34

69.74

68.07

56.90

—

85.13

7.28

10.08

10.09

9.44

8.82

11.25

—

97.68

96.06

95.19

95.07

98.47

96.52

—

0.00

0.16

0.52

0.13

0.82

0.60

—

0.008

0.013

0.1

104

384

800

1E0

1275

B5A4

3F7A0

—

3840

47250

465000

4160000

—

8000

80000

664000

5336000

—

667

—

†

STS-12/ 1.00E-03

STM-4

—

100.00

84.92

67.93

66.19

65.75

—

88.43

9.64

7.17

6.66

6.53

—

100.00

98.38

96.48

95.46

95.16

—

0.04

0.00

0.25

0.19

0.18

—

0.008

0.025

0.25

2.5

1.00E-04

1.00E-05

1.00E-06

1.00E-07

1.00E-08

1.00E-09

1.00E-10

117

200

1152

11475

114750

1147500

—

2000

20000

168000

1336000

—

4FB

31CE

1F20C

—

167

—

†

STS-48/ 1.00E-03

STM-16

—

100.00

99.95

90.60

77.55

75.80

74.58

82.92

—

100.00

58.97

16.25

13.09

12.15

11.54

19.71

—

100.00

96.89

96.47

96.69

95.17

98.09

97.29

—

100.00

0.00

0.01

0.18

—

0.008

0.0625

0.625

5.2

1.00E-04

1.00E-05

1.00E-06

1.00E-07

1.00E-08

1.00E-09

1.00E-10

320

480

500

13A

C1C

765C

—

4710

46500

333300

—

5000

41600

336000

—

* These are the numbers to be provisioned in TDAT042G5. The actual values of the BER algorithm are 1 greater than the actual values shown.

†These BER values cannot be provisioned because the maximum value of L is 0xF (i.e., L is a 4-bit register).

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description (continued)

Overhead Processor (OHP) Block (continued)

Receive OHP (continued)

Overhead (OH) Extract. All transport overhead (TOH) bytes are extracted and sent over the RxTOH interface for

possible external processing. The number of bits sent are as follows:

^ISTS-3/STM-1: 5,184,000 bits/s per interface

^ISTS-12/STM-4: 20,736,000 bits/s per interface

^ISTS-48/STM-16: 82,944,000 bits/s (over 4 serial lines (20,736 kbits/s each))

Table 17. Ns, L, M, and B Values to Clear the BER Indicator

Mode

BER

SF/SD Set Values

Actual

Number of

Frames

Probability of

Detecting L

Errors (%)

Probability of

Clearing

SF/SD (%)

Integra-

tion

Time

(s)

Max-

imum

Number

of Frames

Ns*

@BER*5 @BER @BER*5 @BER

STS-3/

STM-1

1.00E-03

1.00E-04

1.00E-05

1.00E-06

1.00E-07

1.00E-08

1.00E-09

1.00E-10

—

0.013

0.1

—

104

85.13

93.01

84.42

83.66

82.86

46.31

0.39

11.33

6.84

6.59

6.35

1.48

0.27

0.01

0.34

0.22

0.03

0.50

100.00

99.21

99.88

99.98

99.75

99.84

800

384

8000

1E05

1275

B5A4

3F7A0

3840

47250

465000

4160000

80000

664000

5336000

53360000

667

6670

†

STS-12/ 1.00E-03

STM-4

—

0.008

0.025

0.25

2.5

—

1.00E-04

1.00E-05

1.00E-06

1.00E-07

1.00E-08

1.00E-09

1.00E-10

100.00

98.36

87.99

87.34

87.17

51.54

20.51

8.23

7.94

7.87

0.00

0.07

0.02

0.03

99.03

100.00

99.59

99.64

99.65

200

117

2000

1152

11475

114750

1147500

20000

168000

1336000

13360000

4FB

31CE

1F20C

167

1670

†

STS-48/ 1.00E-03

STM-16

—

†

—

†

—

†

—

†

—

0.008

0.0625

0.625

5.2

—

1.00E-04

100.00

95.07

87.34

86.52

85.95

84.89

45.99

60.11

7.28

7.94

7.61

7.38

7.00

0.00

0.03

99.42

99.47

99.98

99.94

99.95

99.96

99.95

1.00E-05

1.00E-06

1.00E-07

1.00E-08

1.00E-09

1.00E-10

320

500

640

5000

41600

336000

3360000

13A

C1C

765C

6280

62000

333300

420

* These are the numbers to be provisioned inTDAT042G5. The actual values of the BER algorithm are 1 greater than the actual values shown.

†These BER values cannot be provisioned because the maximum value of L is 0xF (i.e., L is a 4-bit register).

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description (continued)

Overhead Processor (OHP) Block (continued)

Receive OHP (continued)

The OH interface consists of clock, data, and frame. The data and frame signals update on the falling edge of the

clock. The frame pulse is high for the most significant bit (MSB) of the first bit of the frame. Bytes J0, Z0, and F1

(current and previous), K1, K2, and S1 can also be extracted via software registers.

Table 18 shows the ordering of the bytes for the allowed TOAC configurations.

Table 18. TOAC Channel I/O vs. STS Number/Time Slot

Output Rate

TOAC Channel Input vs. Input STS Number/Time Slot

Time

STS-3/STM-1

3 2 1 (Channel A)

3 2 1 (Channel B)

3 2 1 (Channel C)

3 2 1 (Channel D)

STS-12/STM-4

STS-48/STM-16

12 9 6 3 11 8 5 2 10 7 4 1 (Channel A)

12 9 6 3 11 8 5 2 10 7 4 1 (Channel B)

12 9 6 3 11 8 5 2 10 7 4 1 (Channel C)

12 9 6 3 11 8 5 2 10 7 4 1 (Channel D)

39 27 15

42 30 18

45 33 21

38 26 14

41 29 17

44 32 20

37 25 13

40 28 16

43 31 19

(Channel A)

(Channel B)

(Channel C)

48 36 24 12 47 35 23 11 46 34 22 10 (Channel D)

The overhead extract block also performs the following functions:

^IError Monitors. The REI_L block counts remote error indication block errors. The M1 byte is extracted and

counted. This represents the number of LBIP errors detected by the far-end equipment. Optionally, a maximum

of only one REI-L error per frame may be counted (provisionable via M1BITBLKCNT[A—D]; register description,

page 175). This causes the block error counter to only increment by one when one or more errors are detected.

^IAutomatic Protection Switch Signaling. The APS block filters the K1 and K2 bytes (automatic protection

switching channel) and stores the validated message in software-accessible registers. The K bytes are validated

after a programmable number of consecutive frames contain identical K1 (and K2[7:3] or K2[7:0]) values. APS

protection switching byte failure is detected within this block when a programmable number of frames have

passed without valid K bytes. The protection switching byte failure is removed upon detection of a programmable

number of frames with identical K1 (and K2[7:3] or K2[7:0]) bytes. The use of K2[7:3] or K2[7:0] is provisionable

via the K1K2_2_OR_1 register bit (see register description, page 169).

^ILine Remote Defect Indicator. Bits 2, 1, and 0 of the K2 byte are monitored for the pattern 110. If this pattern

appears for 3—15 (provisionable by OHP register CNTDK2) consecutive frames, RDI-L is asserted. RDI-L is

removed when any pattern other than 110 is detected for 3—15 (provisionable by OHP register CNTDK2) con-

secutive frames. (See page 171 for register description of CNTDK2[A—D][3:0].)

^ILine Alarm Indication Signal. Bits 6, 7, and 8 of the K2 byte are monitored for the pattern 111. If this pattern

appears for 3—15 (provisionable by OHP register CNTDK2) consecutive frames, AIS-L is asserted. AIS-L is

removed when any pattern other than 111 is detected for 3—15 (provisionable by OHP register CNTDK2) con-

secutive frames. (See page 171 for register description of CNTDK2[A—D][3:0].)

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description (continued)

Overhead Processor (OHP) Block (continued)

Receive OHP (continued)

^IRx Synchronization Message. The S1 block filters the synchronization message (S1) byte and stores the vali-

dated message in a software-accessible register. The synchronization message will be validated if a programma-

ble number (in OHP register CNTDS1) of consecutive frames contain identical S1 values. An inconsistent

synchronization message alarm will be reported if a provisional number (by OHP register CNTDS1FRAME) of

consecutive frames pass without a validated message occurring. (See page 172 for register descriptions of

CNTDS1[A—D][3:0] and CNTDS1FRAME [A—D][3:0].)

^IF1 User Channel. The F1 byte is extracted by the OHP. The F1 user channel is monitored for change of state

using OHP registers 0x0402, 0x0404, 0x0406, 0x0408 (see register map, page 116). The previous and current

F1 values are stored in F1DMON1[A—D][7:0] and F1DMON0[A—D][7:0], respectively (see page 122 for register

map, page 190 for register descriptions).

^IDCC and Orderwire Bytes. The data communication channel (D1—D3, D4—D12) and orderwire bytes (E1, E2)

can only be extracted via the TOAC.

^ID1/D2/D3 Section Data Communications Channels (DCC). DCC outputs are taken from the TOAC.

^ID4—D12 Line Data Communications Channels (DCC). DCC outputs are taken from the TOAC.

^IM1 REI-L. REI-L is extracted by the OHP.

^ISupport for ATM/Packet-Over-Fiber. The transport overhead must be bypassed when operating in data-over-

fiber mode. In this mode, the TOH_BYPASS and ROH_BYPASS register bits must be set to 1. No overhead

insertion/extraction is done when in bypass mode.

Transmit OHP

Overhead Insertion. Some transport overhead (TOH) bytes can optionally be inserted via the TxTOH interface

and inserted into the TOH bytes (see Table 15, page 53). Certain bytes can be either inserted from values stored in

registers or automatically generated. The TxTOH interface controls the insertion mechanism. Software insertion

takes precedence over TOAC insertion. The number of bits received are as follows:

^ISTS-3/STM-1: 5,184,000 bits/s per interface

^ISTS-12/STM-4: 20,736,000 bits/s per interface

^ISTS-48/STM-16: 82,944,000 bits/s (over 4 serial lines (20,736 kbits/s each))

S1 Synchronization Message. The S1 block controls the insertion of the S1 byte. The byte ordering is the same

as the RxTOAC and is shown in Table 18 (see pa ge59). The S1 byte can be provisioned to come from the TxTOH

interface or from a software-settable register. Control for message insertion is from software control register

TS1INS[A—D] (see register description, page 179 and page 183).

K1K2 APS Signaling. The APS block controls the insertion of the K bytes based on software provisioned K bytes,

and alarm conditions (AIS-L, RDI-L). Inconsistent APS bytes can be inserted via register provisioning by

TAPSBABBLEINS[A—D] (see register description, page 178 and page 183).

RDI_L Generation. The following six alarms contribute to RDI_L generation: LOF, OOF, LOS, LOC, AIS_L, and

SF. They can be inhibited from contributing to RDI-L via transmit control registers (addresses 0x042F, 0x0431,

0x0433, 0x0435; see register description, page 180).

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description (continued)

Overhead Processor (OHP) Block (continued)

Transmit OHP (continued)

BIP-8 Generation. The SBIP block calculates the B1 value according to Bellcore and ITU standards. Insertion of

SBIP errors is possible through the use of software control register TB1ERRINS[A—D] (see register description,

page 180).

The LBIP block calculates the B2 values according to Bellcore and ITU standards. Insertion of LBIP errors is pos-

sible through the use of software control register TB2ERRINS[A—D] (see register description, page 180).

The REI_L block controls the insertion of the remote error indication block error count.

J0 Section Trace. The section trace message is inserted either from the TxTOH interface or from a message

stored in a 16-byte software-accessible memory. Control for message insertion is from software control register

TJ0INS[A—D] (see register description, page 177 and page 181).

SONET Scrambler. The scrambler block implements the frame synchronous SONET scrambler with a generating

polynomial of 1 + x⁶+ x⁷. The scrambler may be disabled through a software register.

A1/A2 Framing Bytes. A1 and A2 are automatically placed on the line. Errors can be inserted into A2 by setting

OHP register TA1A2ERRINS[A—D][4:0] (see register description, page 180).

E1/E2 Orderwire Bytes. The orderwire bytes for section and line are taken from the TOAC.

D1/D2/D3 Section Data Communications Channels (DCC). DCC inputs are taken from the TOAC.

D4—D12 Line Data Communications Channels (DCC). DCC inputs are taken from the TOAC.

F1 User Channel. The F1 byte can be optionally inserted from stored values in OHP register TF1INS[A—D]

(addresses 0x047E, 0x0480, 0x0482, 0x0484; see register description, page 179 and page 183).

M1 REI-L. REI-L can be automatically generated and inserted into the outgoing SONET frame, or can optionally

be inhibited. Errors can be inserted into M1 via OHP register TM1_ERR_INS[A—D] (addresses 0x042E, 0x0430,

0x0432, 0x0434; see register description, page 179 and page 183).

Support for ATM/Packet-Over-Fiber. The transport overhead must be bypassed when operating in data-over-

fiber mode. In this mode, the TOH_BYPASS and ROH_BYPASS register bits must be set to 1. No overhead inser-

tion/extraction is done when in bypass mode.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description (continued)

Path Terminator (PT) Block

The path terminator performs path overhead (POH) termination and extracts the payload for further processing by

the downstream circuitry. The path terminator block interprets the incoming H1/H2 pointer of each incoming STS

channel. The pointer interpreter supports up to four channels and performs path overhead termination on each

channel. Each channel may be either an STS-1, STS-3c, STS-6c, STS-9c, . . . , STS-45c, or STS-48c.

The pointer is validated according to Bellcore and ITU specifications. The H1/H2 pointers are used to determine

the location of the first path overhead (POH) byte (J1). The pointer interpreter consists of a finite state machine

(FSM) with four steady states. These states are defined as follows:

^INormal state

^ILoss-of-pointer (LOP)

^IAlarm indication signal (AIS)

^IConcatenation

The transition between states will require several consecutive events to protect against transient conditions caused

by bit errors during high BER conditions. The state machine is shown below in Figure 7.

1 NDF POINTER OR

3 NORMAL POINTERS

NORMAL

AIS

3 AIS INDICATIONS

8 INVALID POINTERS

3 CONC INDICATIONS

LOP

CONC

5-7935(F)

Figure 7. Pointer Interpreter State Diagram

The PT block monitors for the following conditions and takes appropriate actions:

^IPointer Increment. TDAT042G5 uses an 11-bit counter to count the number of pointer increments and updates

the associated counter holding register on the occurrence of PMRST (RPI_INC[A—D][10:0]; see register

description, page 198). A pointer increment can occur when in the normal pointer mode. The following two meth-

ods can be used to determine if the pointer increment operation should be performed: 6-of-10 or 8-of-10 majority

matching (selectable via software provisioning of register RINCDEC_6OR8MAJ [A—D]; see register description,

page 200).

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description (continued)

Path Terminator (PT) Block (continued)

^IPointer Decrement. TDAT042G5 uses an 11-bit counter to count the number of pointer decrements and

updates the associated counter holding register on the occurrence of PMRST (RPI_DEC[A—D][10:0]; see regis-

ter description, page 198). A pointer decrement can occur when in the normal pointer mode. The following two

methods can be used to determine if the pointer decrement operation should be performed: 6-of-10 or 8-of-10

majority matching (selectable via software provisioning of register RINCDEC_6OR8MAJ [A—D]; see register

description, page 200).

^ILoss-of-Pointer. LOP-P is declared as shown in the above state diagram. In an LOP-P state, none of the path

overhead bytes are extracted.

^IAIS-P. The AIS-P is declared when the H1 and H2 bytes are set to all ones. In an AIS-P state, none of the path

overhead bytes are extracted.

^IConcatenated Pointer. A concatenated pointer is detected when the new data flag is set and the pointer offset

value is all ones.

^INew Pointer. TDAT042G5 uses a 13-bit counter to count the number of new data flags that occur and updates

the associated counter holding register on the occurrence of PMRST (RNDFCNT[A—D][12:0]; see register

description, page 198). TDAT042G5 uses a 3-of-4 majority voting scheme to determine if the new data flag is

set. Valid new data flags occur when the NDF bits are either 1001, 0001, 1101, 1011, or 1000.

^INormal Pointer. A normal pointer occurs when all of the following conditions are true simultaneously:

1. NDF is not set (NDF bits are either 0110, 0111, 0100, or 0010),

2. There is no invalid pointer value,

3. There is a valid offset (0 to 782)

^IInvalid Pointer. An invalid pointer is declared when neither a new data flag nor a normal pointer is detected.

SPE Terminate

Receive Path Trace. The path trace message is extracted and stored in a 16-byte (SDH) or 64-byte (SONET)

memory for access by software. The first byte of the message can be provisioned to be either of the following:

^IFor SDH mode, the byte with the most significant bit (MSB) set high (for SDH)

^IFor SONET mode, the byte following a carriage return (0x0D) and line feed (0x0A) sequence

The framing can also be disabled.

Receive Error Monitor. The PBIP block counts path BIP-8 errors. A theoretical maximum of 64,000 errors may be

detected per second. The PBIP block accumulates these errors in a 16-bit saturating counter. This counter is oper-

ated in latch and clear mode to ensure Bellcore and ITU compliance with regard to not missing any events (bit

errors). It is intended that this counter be polled at least once per second in order that no error events are missed.

The REI_P block counts remote error indication block errors.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description (continued)

Path Terminator (PT) Block (continued)

SPE Terminate (continued)

Receive Signal Label. The C2 block will extract and validate the signal label byte (C2) and store it in a software-

accessible register. The signal label is updated when a provisionable number of consecutive detections of a new

C2 value occur (CNTDC2[A—D][3:0]; see register description, page 204). All monitoring is disabled when the

pointer is in an LOP-P or an AIS-P state. Commonly used values of C2 with their signal labels are listed below in

Table 19.

Table 19. Types of Signal Labels

C2 Value

Signal Label

0x00

0x01

0x13

0x16

Unequipped STS SPE

Equipped nonspecific payload

Mapping for ATM

Mapping for HDLC-PPP

Any value of C2 may be provisioned. If the provisioned value is not matched by the detected value, then data is not

passed to the DE. If the provisioned value does match the detected value, then data is passed to the DE.

TDAT042G5 will detect unequipped payloads (UNEQ-P) when a provisionable number of consecutive monitored

C2 bytes match the 0x00 unequipped STS SPE state. TDAT042G5 will detect mismatched payloads (PLM-P)

when a provisionable number of consecutive monitored C2 bytes do not match the provisioned expected payload

label (RC2EXPVAL[7:0]; see register description, page 205).

Receive Path Status. The G1 block extracts the path remote error indication (REI-P) bits of G1[7:4] and accumu-

lates the REI-P errors in a 16-bit saturating counter. This counter is operated in latch and clear mode to ensure

Bellcore and ITU compliance. It is intended that this counter be polled at least once per second in order that no

error events are missed.

RDI-P. This block will also validate the path remote defect indication (RDI-P) bits and store the result in a software-

accessible register. The receive path can monitor remote defect indications in either enhanced or single bit RDI-P

modes (provisionable via software bit RDIPMON_ENH_OR1B [A—D]; see register description, page 200). The

interpretation of the G1 byte is as follows.

Table 20. 1-bit Mode

G1 Bytes

Description

No RDI-P defects

AIS-P, LOP-P

G1[3:1] = 0xx

G1[3:1] = 1xx

Table 21. 3-bit Mode (Enhanced RDI)

G1 Bytes

Description

G1[3:1] = 001

G1[3:1] = 010

G1[3:1] = 101

G1[3:1] = 110

No RDI-P defects

PLM-P or LCD-P

AIS-P or LOP-P

UNEQ-P or TIM-P (TIM-P is J1 mismatch*)

* TIM-P must be accomplished through (microprocessor) software by reading the

transmit RDI-P state and inserting the G1 bit.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description (continued)

Path Terminator (PT) Block (continued)

Z5/N1, Z4/K4, Z3/F3, H4, F2 Monitoring. TDAT042G5 monitors the F2 user channel byte, the H4 VT multiframe

indicator byte, Z3/F3 growth/user byte, Z4/K4 growth/APS path byte, and the Z5/N1 tandem connection byte.

These bytes are stored in software registers. These registers are updated when a provisionable number of detec-

tions of new values occur on the associated incoming byte. All monitoring is disabled when the pointer is in an

LOP-P or an AIS-P state.

Signal Failure and Signal Degrade Monitoring. The path overhead processor also detects/clears provisionable

signal fail (SF) and signal degrade (SD) conditions. The SF and SD values are provisionable through a group of

software registers in the PT register map. The provisioning is the same as that shown in Table 16, page 57 of the

Overhead Processor (OHP) Block section.

SPE Generate

Transmit Pointer Generation. The pointer generation block generates the outgoing H1 and H2 pointer values.

Each of the four PT channels can generate one normal (valid) pointer. Therefore, in STS-3/STM-1 and STS-12/

STM-4 modes, only one normal pointer (and only one SPE) may be inserted into the transmitted SONET/SDH

frame. In STS-48/STM-12 mode, all four PT channels are used. Therefore, up to four normal pointers (and four

SPEs) may be inserted into the transmitted SONET/SDH frame.

When inserting concatenated frames, only the first H1 and H2 bytes will contain a valid pointer value. The remain-

ing H1 and H2 bytes of the channel will be set to indicate concatenation. The remaining unequipped channels will

have their H1 and H2 pointers set to a fixed pointer value.

For proper pointer generation, the appropriate values must be provisioned in the H-byte transmit state register

THx_STATE (see register description, page 203).

The following examples illustrate how the device may be configured to transmit various sub-rates and concate-

nated payloads. Each block in the following diagrams represents one STS-1 frame. Figure 8 illustrates how to pro-

vision the THx_STATE registers to transmit an STS-48c frame within an STS-48 signal. In this example, the pointer

to the first STS-1 is provisioned as a normal pointer value while the pointers to the remaining STS-1 signals are

provisioned as concatenated pointers. Figure 9 illustrates how to provision the THx_STATE registers to transmit

four STS-12c frames within an STS-48 signal. The concatenated STS-Mc frames that may be mapped into STS-N

signals (where M ≤ N) are restricted to those listed in Table 22 (see page 68).

TIME-SLOT NUMBER

NORMAL POINTER

THX_STATE[A][12—1][1:0]

THX_STATE[B][12—1][1:0]

THX_STATE[C][12—1][1:0]

THX_STATE[D][12—1][1:0]

47 CONCATENATED POINTERS

0351(F)

Figure 8. STS-48 Signal Carrying One STS-48c Frame

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description (continued)

Path Terminator (PT) Block (continued)

SPE Generate (continued)

TIME-SLOT NUMBER

FOUR NORMAL POINTERS

THX_STATE[A][12—1][1:0]

THX_STATE[B][12—1][1:0]

THX_STATE[C][12—1][1:0]

THX_STATE[D][12—1][1:0]

44 CONCATENATED POINTERS

0352(F)

Figure 9. STS-48 Signal Carrying Four STS-12c Frames

TIME-SLOT NUMBER

12a

12b

12c

12d

11a

11b

11c

11d

10a

10b

10c

10d

CONCATENATED POINTERS

THX_STATE[A][12—1][1:0]

THX_STATE[B][12—1][1:0]

THX_STATE[C][12—1][1:0]

THX_STATE[D][12—1][1:0]

NORMAL POINTERS

UNEQUIPPED

POINTERS

UNEQUIPPED

POINTERS

UNEQUIPPED

POINTERS

0353(F)

Figure 10. Quad STS-12 Configuration With Each STS-12 Signal Carrying One STS-3c Frame

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description (continued)

Path Terminator (PT) Block (continued)

SPE Generate (continued)

TIME-SLOT NUMBER

12a

12b

12c

12d

11a

11b

11c

11d

10a

10b

10c

10d

NORMAL POINTERS

THX_STATE[A][12—1][1:0]

THX_STATE[B][12—1][1:0]

THX_STATE[C][12—1][1:0]

THX_STATE[D][12—1][1:0]

0354(F)

Figure 11. Quad STS-12 Configuration With Each STS-12 Signal Carrying One STS-12c Frame

(Channel A), One STS-9c Frame (Channel B), One STS-6c Frame (Channel C), and

One STS-3c Frame (Channel D)

TIME-SLOT NUMBER

CONCATENATED POINTERS

THX_STATE[A][12—1][1:0]

THX_STATE[B][12—1][1:0]

THX_STATE[C][12—1][1:0]

THX_STATE[D][12—1][1:0]

NORMAL POINTERS

UNEQUIPPED POINTERS

0355(F)r.1

Figure 12. Quad STS-3 Configuration With Each STS-3 Signal Carrying One STS-2c Frame

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description (continued)

Path Terminator (PT) Block (continued)

SPE Generate (continued)

The general rule for mapping STS-Mc frames in STS-N signals (M ≤ N) is that the TDAT042G5 can have a maxi-

mum of four normal pointers in STS-48 mode. For M ≤ 12, the valid starting locations for mapping into an STS-48

signal are 1, 13, 25, and 37. For M >12, only one normal pointer is permitted and it must start at the first location

(the first STS-1). The TDAT042G5 allows only one normal pointer in STS-3 or STS-12 modes. The only valid start-

ing location for mapping concatenated frames into an STS-3 or STS-12 signal is 1.

Table 22. Valid Concatenation Starting Locations: STS-Mc into an STS-48c

STS-1 Number STS-3c

STS-6c

STS-9c STS-12c STS-15c STS-18c STS-48c

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description (continued)

Path Terminator (PT) Block (continued)

SPE Generate (continued)

BIP-8. The PBIP block calculates the B3 value according to Bellcore and ITU standards. Insertion of PBIP errors is

possible through the use of a software control register.

REI Generation. The REI_P block controls the insertion of the remote error indication block error count. The

received PBIP error counts are inserted into the path status (G1) byte.

RDI-P Generation. The transmit path can insert remote defect indications using either single-bit or enhanced

RDI-P modes (provisionable via software register bit TRDIP_ENH_OR1B[A—D]; see register description, page

202). The highest to lowest priority of the defect code insertion is as follows:

1. AIS-P, LOP-P (applies only to the single-bit version of RDI-P),

2. UNEQ-P,

3 . P L M - P, L C D - P,

4. No defects

TIM-P can be inserted using software through TRDIPSINS (registers 0x0AAA, 0x0AB2, 0x0ABA, or 0x0AC2,

bits 15—11; see register description, page 201). The LCD-P defect is observed in the data engine and passed to

the pointer block for transmission. Each particular defect can be inhibited from contributing to the transmitted

RDI-P insertion value via software registers 0x0AAA, 0x0AB2, 0x0ABA, and 0x0AC2. RDI_P can either be inserted

by software or automatically through hardware.

Z5/N1, Z4/K4, Z3/F3, H4, F2 Insertion. TDAT042G5 inserts the F2 user channel byte, the H4 VT multiframe indi-

cator byte, Z3/F3 growth/user byte, Z4/K4 growth/APS path byte, and the Z5/N1 tandem connection byte via soft-

ware provisioning.

Error Insertion Mechanisms. TDAT042G5 provides a method to inject via software REI-P

(TREIPERRINS[A—D]) and B3 (TB3ERRINS[A—D]) errors into the transmitted SONET frame (see register

descriptions, page 202).

Insertion of J1, F2, C2, Z3, H4, Z4, Z5, SS Values. TDAT042G5 provides paged provisionable registers to insert

the path overhead bytes into the outgoing SONET frame. The paging is done by first writing to the page provision-

ing register at location 0x0AC6 to set the port number and time slot to be provisioned, and then writing to the

appropriate insertion registers. Available time-slot values for TDAT042G5 are time slot 1 for STS-48c mode; time

slots 1, 2, 3, and 4 for STS-48 consisting of four STS-Mc (M ≤ 12) signals; and time slot 1 for quad STS-12c and

quad STS-3c modes (ports A, B, C, and D configured for quad STS-3c and quad STS-12c).

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description (continued)

Data Engine (DE) Block

The DE block processes ATM, SDL, PPP, and HDLC cells/packets at rates up to 2.488 Gbits/s. The DE block

behaves like four independent logical data channels, one for each of the four STS-12/STM-4 or STS-3/STM-1

channels, or like a separate single channel for STS-48/STM-16. The following description is for each one of these

data engines. Each of the functional elements to be described are independently provisioned.

The data engine supports both ATM cells and packet data formats.

^IThe ATM processor functions with 52-byte, 53-byte, and 56-byte ATM cells.

^IThe packet processor has three packet modes: HDLC, CRC, and PPP. All three modes use HDLC framing, i.e.,

0x7E delineates the packets. In HDLC mode, the 0x7E framing bytes are inserted or detected by the data

engine. In the CRC mode, a user-selectable 16-bit or 32-bit CRC word is appended or detected at the end of the

packet. The PPP mode places or detects a PPP header on the front of the packet as well as uses the CRC word.

The block diagram for the data engine is shown in Figure 13.

RECEIVE-SIDE DE BLOCK

CBINT

SDL

FRAMER

ATM

FRAMER

X43

POST-

UNSCRAMBLER

X43

PRE-

UNSCRAMBLER

PPP

DETACH

CRC

CHECKER

HDLC

FRAMER

SEQUENCER

INTERFACE

TRANSMIT-SIDE DE BLOCK

CBINT

SDL

INSERTER

ATM

INSERTER

X43

POST-

SCRAMBLER

PPP

ATTACH

X43

HDLC

INSERTER

CRC

GENERATOR

PRESCRAMBLER

SEQUENCER

INTERFACE

5-8385(F)r.2

Figure 13. Block Diagram of Date Engine (DE)

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description (continued)

Data Engine (DE) Block (continued)

Receive Data Engine

Receive Sequencer. The receive sequencer demaps SONET framing to four logical channels, performs the phys-

ical channel byte alignment and packing, and performs appropriate payload clock domain transfer. The receive

sequencer must be provisioned properly for correct operation. There are six registers that are fixed for each partic-

ular mode of operation (STS-3/STM-1, STS-12/STM-4, or STS-48/STM-16) and must not be modified

(SEQ_CTRL, INIT_CNTS, OH_MARKER_LO, OH_MARKER_HI, SOH_MARKER_LO, SOH_MARKER_HI). See

the register descriptions for details, page 214. Also, the appropriate time slots must be provisioned for the rate of

the payload expected for each channel. This is done via the registers Rx_TS[1—12] (see register descriptions,

page 219). An example of how to configure this for STS-48c mode is shown in the section on configuring the trans-

mit/receive sequencer (see Transmit Data Engine section, page 78).

ATM Cell Processor. The cell processor performs ATM cell delineation using the ATM header error correction

(HEC) field found in the cell header. The HEC is a CRC-8 calculation over the first four octets (total of 32 bits) of

the ATM cell header. If the TDAT042G5 is in bit-synchronous mode (data is not byte-aligned), 32 separate HEC

calculations are performed to delineate an ATM cell. If the TDAT042G5 is in byte-synchronous mode (data is byte-

aligned), four separate HEC calculations are performed to delineate an ATM cell. An alpha-delta counter is used to

track the processor’s ability to frame the ATM cells consistently. When a certain level of confidence is reached

(defined by the programmable delta counter threshold), the frame is declared in sync state, and data is passed to

subsequent blocks. If the framer is unable to frame ATM cells over a few cell periods (defined by the programma-

ble delta counter threshold), the framer resumes hunt state.

In SONET mode, the processor performs optional X⁴³unscrambling of the payload. Because the X⁴³scrambler is

self-synchronizing, the framer needs no assistance from the data in order to synchronize the scrambler. The

TDAT042G5 also supports an X³¹scrambler, compliant with I.432, which is mainly used for packet-over-fiber

applications. The state diagram for the X³¹scrambler is shown in Figure 14 on page 72. The X³¹scrambler uses

an x³¹+ x²⁸+ 1 polynomial to scramble the data. Unlike the X⁴³scrambler, the X³¹scrambler does not self-

synchronize based upon the data it receives. Thus, one-bit samples of the scrambler output are sent on the trans-

mit side and compared with the scrambler samples on the receive side every 212 bits. If the samples do not match,

the receive-side scrambler is adjusted to converge with the transmit-side scrambler. This process continues until a

certain level of confidence in the scrambler synchronization is achieved. In the X³¹mode, the ATM cell processor

does not send out any output until both the framer and the scrambler are synchronized, whereas in X³¹mode, only

the framer needs to be synchronized.

Idle ATM cells, which contain no real data, can be either left in or removed from the bit stream. The idle cell header

description can be configured, though it is set to a default value (0x00000001).ATM cells can also be filtered if the

header contents match a provisioned match register after masking with a provisionable mask register. This allows

filtering based on the contents of the GFC, PTI, and CLP fields of the header. Optionally, ATM cells may be

dropped if uncorrectable HEC errors are detected. Incoming single-bit ATM header errors can be corrected and the

cells may be passed through or dropped, depending on the software configuration.

The data engine processes only standard 53-byte ATM cells. However, the UTOPIA block processes 52-byte, 53-

byte, 54-byte, and 56-byte cells, and interfaces these to the data engine. (See UTOPIA (UT) Interface Block,

page 86, for details).

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description (continued)

Data Engine (DE) Block (continued)

Receive Data Engine (continued)

COUNTER EQUALS Y

VERIFICATION

SYNCHRONIZED

COUNTER LESS

THAN Y

COUNTER DROPS

BELOW V

COUNTER DROPS

BELOW W

COUNTER EQUALS X

ACQUISITION

COUNTER LESS

THAN X

5-8388(F)

Note: Even in synchronized mode, the confidence counter can continue to increase up to the Z value.

Figure 14. State Diagram for the X³¹Scrambler Synchronization Process

SDL Frame Processor. The SDL frame processor consists of an SDL framer, which detects the start of SDL pack-

ets, and an (optional) X⁴⁸unscrambler, which is used to unscramble payload data. SDL packets can also arrive

unscrambled, in which case the unscrambler is disabled. The SDL frame processor can frame packets in SDL form

which contain a data length between 4 and 65,535 bytes.

The SDL framer uses a CRC-16 check upon 2 bytes sequences used to determine packet length in order to frame

SDL packets. Since the framer is designed to support data that is not byte-aligned, 32 separate framers may be

used to search for the CRC-16 pattern. If the data is byte-synchronized, only four framers are needed. A confi-

dence counter is used to gauge the framer’s ability to frame SDL packets consistently. When the confidence

counters reaches a certain level (defined by the programmable SDL delta counter register), the framer is in sync

state. Single-bit error correction for the SDL headers is also supported. Shown below in Figure 15 is the general

structure of the SDL packets. In this figure, there is no interpacket fill.

PACKET

LENGTH

PACKET

LENGTH

PACKET PAYLOAD

CRC-16

PACKET PAYLOAD

CRC-16

PACKET PAYLOAD

5-8386(F)r.2

Figure 15. General Structure of SDL Packets

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description (continued)

Data Engine (DE) Block (continued)

Receive Data Engine (continued)

Interpacket fill separating packets always contains a multiple of 4 bytes. The SDL framer is able to detect inter-

packet fill since its value is fixed. (It has 4 bytes equal to 0x0000000, i.e., a packet length of 0x0000 with a CRC-16

of 0x0000.) Since the framer knows the length of a particular packet and can detect interpacket fill, it will predict the

start of the next frame and frame on it. The SDL frame processor supports SDL and SDL CRC modes. When oper-

ating in SDL CRC mode, a 2-byte or 4-byte CRC for the packet payload is attached to the end of the packet pay-

load prior to the next packet length. When operating in SDL mode, there is no 2-byte or 4-byte CRC for the packet

payload.

The SDL frame processor supports X⁴⁸scrambling of the packet payload, which is accomplished by using a primi-

tive polynomial of x⁴⁸+ x²⁸+ x²⁷+ x + 1. The X⁴⁸scrambler is not self-synchronizing. Thus, the side transmitting

SDL packets will periodically send its 48-bit scrambler state within the data stream such that the receive side can

synchronize its scrambler. Whenever the SDL frame processor receives a scrambler state, it is immediately put

into sync state, which allows it to send data out. Upon receiving additional scrambler states, the scrambler will

compare its own state with the state received. If the scrambler states match, then the scrambler remains in sync

state. However, if there is a mismatch, the scrambler is put into postsync state. In postsync state, if an additional

scrambler state mismatch occurs, the X⁴⁸scrambler is resynchronized with the scrambler state it has received.

The SDL frame processor detects scrambler state data since the packet length field of 0x001 and the length of

time separating scrambler state transmissions is programmable. Single-bit error correction for the SDL scrambler

state is incorporated within the TDAT042G5.

Both the SDL framer and the X⁴⁸scrambler must be synchronized before the SDL frame processor will send data.

Besides the SDL scrambler state being transmitted, the SDL framer will also extract special A and B messages

used by the upstream device to send link layer 1 messages to the downstream hardware. The packet length field

used to detect A and B messages are 0x0002 and 0x0003, respectively.

In addition to scrambling the data, the SDL data stream coming into the SDL frame processor is dc balanced with

the 32-bit value 0xB6AB31E0.

Table 23 below is used to describe the packet length field.

Table 23. Packet Length Field

Packet Length

Field

SDL Data Type

0x0000

0x0001

0x0002

0x0003

Interpacket fill

SDL scrambler state

A message

B message

0x0004—

0xFFFF

Length of payload region for current

packets (in bytes)

Pre-descrambler. The pre-descrambler block descrambles the payload using a self-synchronous descrambler

with a generator polynomial of 1 + x⁴³. For ATM cell traffic, only the 48-byte cell payload (and not the cell over-

head) is descrambled. For HDLC and PPP packets, the entire frame (including header and trailer) is descrambled.

Predescrambling, post-descrambling, or no descrambling may be selected through a provisionable register.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description (continued)

Data Engine (DE) Block (continued)

Receive Data Engine (continued)

HDLC Framer. The packet processor frame aligns to HDLC packets using the HDLC flag character (0x7E). Flags

are also used to fill interpacket spaces. The flags are removed and control escape destuffing is performed. The

control escape character (0x7D) is searched for and when it is found, the control escape character is removed, i.e.,

0x7D5D is unescaped to 0x7D and 0x7D5E is unescaped to 0x7E. If dry mode is enabled, then 0x7D20 is unes-

caped to a value of 0x00, which represents dry data (FIFO underflow in the middle of a packet). Any other unes-

caped sequence of 0x7D results in an errored packet.

CRC Check. An optional CRC-ITU or CRC-32 calculation on the whole POS frame is performed after byte destuff-

ing and data descrambling. The CRC-ITU generating polynomial is 1 + x⁵+ x¹²+ x¹⁶. The CRC-32 generating

polynomial is 1 + x + x²+ x⁴+ x⁵+ x⁷+ x⁸+ x¹⁰+ x¹¹+ x¹²+ x¹⁶+ x²²+ x²³+ x²⁶+ x³². The computation over

the whole packet, including the FCS field, should result in all zeros. A different value indicates an error. Packets

with FCS errors are marked as such and are discarded. CRC field stripping is optional. Both normal and reversed

CRC modes are supported.

Post-descrambler. The descrambler block descrambles the payload using a self-synchronous descrambler with a

generator polynomial of 1 + x⁴³. For ATM cell traffic, this block is bypassed. For HDLC frames, the entire frame

(including header and trailer) is descrambled. The descrambler may be disabled through the use of a software reg-

ister.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description (continued)

Data Engine (DE) Block (continued)

Receive Data Engine (continued)

PPP Header Detach. The PPP detach function matches the PPP header (corresponding to the first 4 bytes of the

PPP uncompressed frame or first 2 bytes of the PPP compressed frame) to a set of fixed or provisionable values

for each channel and outputs frames in accordance with payload control register settings. The address and control

field bytes are assumed to be 0xFF03. The block supports two fixed protocol fields (0x0021 corresponding to the

IP protocol field, and 0x8021 corresponding to the IP control protocol). Additionally, 12 provisionable registers,

PPP_Rx_HDR [0—11][15:0] (addresses 0x10F0—0x10FB), are supported on-chip to allow a large number of pro-

tocols to be recognized in the receive (ingress) data path of the chip.

The PPP detach function supports compressed or uncompressed header fields, optionally matching two fixed (one

corresponding to IP protocol) 16-bit protocol fields. This optional PPP header check allows PPP (normal or com-

pressed (i.e., no FF03)) to be checked and the header optionally stripped. Packets that fail to match one of the pro-

visioned headers or the two default headers can optionally be discarded. This function supports optionally

matching 12 programmable 16-bit protocol fields. The PPP detach function provides mismatched PPP header

count on a per-channel basis through four 28-bit counters, PM_MHC_[0—3][27:0] (addresses 0x1118—0x111F).

The function can optionally discard frames if header fields do not match on a per-channel basis. It can also option-

ally strip header fields only if they do match on a per-channel basis.

A PPP packet has the following two formats:

UNCOMPRESSED PPP PACKET

PACKET

2 bytes

NEXT PACKET

1 byte

0x7E

1 byte

≤64 Kbytes*

2 OR 4 bytes

CRC FIELD

ADDRESS FIELD

0xFF

CONTROL FIELD

0x03

PROTOCOL

FIELD

DATA

0x7E

COMPRESSED PPP PACKET

PACKET

≤64 Kbytes*

NEXT PACKET

1 byte

2 bytes

2 OR 4 bytes

CRC FIELD

1 byte

PROTOCOL

FIELD

0x7E

DATA

0x7E

5-9642 (F)

* TDAT042G5 is verified to handle packets of up to 64 Kbytes. Larger packets may be processed, but no upper bound or packet size

has been determined. Packets of less than 4 bytes are discarded by the DE.

Figure 16. Uncompressed and Compressed PPP Packets

Each channel has a 16-bit register, PPP_Rx_CHK_CH [0—3][15:0] (addresses 0x10FC—0x10FF), that can be

provisioned.

If the header bytes do not match and payload control bit 7 = 0, the entire PPP packet is discarded for a given chan-

nel. Otherwise, if the header bytes do not match and payload control bit 7 = 1, the PPP packet is marked as bad

and not discarded for a given channel.

If payload control bit 6 = 0, the header is stripped, provided it matches a provisionable value; otherwise, it is left on

for a given channel.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description (continued)

Data Engine (DE) Block (continued)

Receive Data Engine (continued)

The bad packet counting is based upon the following criteria:

^IHeader Fields. The PPP mismatched header counter, PM_MHC_[0—3][27:0] (addresses 0x1118—0x111F),

counts for PPP packets with various header errors/mismatches as provisioned in the registers.

^ICRC Field. The CRC bad packet counter, PM_BPC_n (n = 0, 1, 2, 3), increments if a CRC error is found in

channel n.

Each PPP packet not counted as a bad packet in PM_MHC_n (n = 0, 1, 2, 3) counter or PM_BPC_n counter incre-

ments the PPP good packet counter, PM_GPC_n (n = 0, 1, 2, 3), for channel n. (See register descriptions,

page 241.)

Note that each channel only has a single pair of good and bad packet counters.

Transmit Data Engine

ATM Cell Inserter. The ATM cell inserter provides X⁴³or X³¹scrambling of the payload for transport of ATM cells

over SONET. X³¹scrambling is suitable for the transport of ATM cells over fiber where bit-level cell delineation is

required. The state diagram for the X³¹scrambler is shown in Figure 14, page72. TheATM cell inserter will gener-

ate idle cells/bytes to fill the SONET/SDH payload when cells/packets are not available in the transmit direction

FIFO of the UTOPIA block. For ATM cells, the GFC, PTI, and CLP fields of the idle cell header and the idle cell pay-

load are provisionable via software registers. The idle generator generates idle cells/bytes to fill the SONET/SDH

payload when cells/packets are not available in the transmit FIFO. Idle cell HCS is automatically calculated and

inserted.

Header Check Sequence (HCS) Generator. The HCS generator performs a CRC-8 calculation over the first four

header octets of the ATM cell. The generator inserts the result into the fifth octet of the ATM header.

SDL Frame Inserter. The SDL inserter performs SDL frame generation and X⁴⁸scrambling of the payload field.

An optional CRC-16/32 field can be attached (SDL-CRC mode) and is calculated over the payload. The SDL

inserter also periodically transmits scrambler state updates through a special 6-byte message. The time between

scrambler state updates can be provisioned by software using register SDLFI_INT (see register description, page

250). The packet length header of scrambler state updates is the 16-bit word, 0x0001. Special A and B messages

can be software-provisioned to send link layer 1 messages to downstream hardware. The packet length headers

for the special A and B messages are 0x0002 and 0x0003, respectively.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description (continued)

Data Engine (DE) Block (continued)

Transmit Data Engine (continued)

Prescrambler. The prescrambler block optionally scrambles the payload using a self-synchronizing scrambler with

a generator polynomial of 1 + x⁴³for HDLC and PPP packets. For HDLC frames, the entire frame, including

header and trailer, is scrambled; however, HDLC flags are not scrambled. The scrambler may be disabled through

the use of a software register. This scrambler removes excessive 0x7D and 0x7E bytes. For ATM cell and SDL

packet traffic, this block is not used. (By randomizing the data, the scrambler prevents malicious use of the channel

due to escaping 7D and 7E sequences.)

CRC-16/-32 Generator. An optional CRC-16/-32 generator on the whole packet frame can be performed. The gen-

erating polynomial for CRC-16 is 1+ x⁵+ x¹²+ x¹⁶. The generating polynomial for CRC-32 is 1+ x + x²+ x⁴+ x⁵+

x⁷+ x⁸+ x¹⁰+ x¹¹+ x¹²+ x¹⁶+ x²²+ x²³+ x²⁶+ x³².

HDLC Inserter. The HDLC framer provides frame check sequence (FCS) generation and insertion using either the

CRC-ITU or CRC-32 generation polynomials. After optional CRC generation, the HDLC framer performs control

escape (0x7D) stuffing, flag character (0x7E) or abort character (0x7D7E) insertion, and dry mode insertion

(0x7D20, where the last two bytes (the 20 bytes of the default value of 0x7D20) are provisionable).

Postscrambler. The postscrambler block optionally scrambles the payload using a self-synchronizing scrambler

with a generator polynomial of 1 + x⁴³for HDLC and PPP packets, in accordance with RFC1619. For HDLC and

PPP packets, the entire frame, including header and trailer, is scrambled. The scrambler may be disabled through

the use of a software register. ForATM cell and SDL packet traffic, this block is not used.*

PPP Header Attach. The PPP attach function inserts the provisionable 4-byte PPP header if payload control

bit 7 = 1 (addresses 0x10E0—0x10E3). The first and second bytes are set to 0xFF03, and the third and fourth

bytes are set to a value defined by a software register in PPP_Tx_CHAN[0—3] (see register descriptions,

page 234).

If payload control bit 7 = 0 (addresses 0x10E0—0x10E3) (compressed PPP header mode), only the two provision-

able bytes defined by the software register PPP_Tx_CHAN[0—3] can be attached. Note that there is only one soft-

ware register-defined protocol value for each channel.

The PPP attach function provides good packet count on a per-channel basis through four 28-bit counters,

PM_GPC_TX_[0—3] [27:0] (addresses 0x1128—112F).

* The ATM and SDL framer inserters have their own dedicated scramblers.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description (continued)

Data Engine (DE) Block (continued)

Transmit Data Engine (continued)

Tx Sequencer. The transmit sequencer maps logical channels into SONET frames, and must be provisioned prop-

erly for correct operation. The appropriate time slots must be provisioned for the rate of the payload expected for

each channel. This is done via the registers Tx_TS[1—12] (see register descriptions, page 215).

TDAT042G5 provides 12 time slots and four channels to define how data is mapped into the 48 synchronous trans-

port signals (STS-1) of an STS-48 frame or into the 12/3 STS signals of an STS-12/3 SONET frame.

Figure 17 illustrates the mapping of the 48 STS-1 signals into an STS-48 signal and their assigned time slots. Each

STS-1 block in the figure represents a byte of data for the specific STS-1 signal. The STS signals within the 12 time

slots are ordered such that the SONET multiplexing requirements of lower rate signals into higher rate signals are

satisfied. A value of 0x4 indicates that valid data is contained in the specific byte (STS) and the data is being

received/transmitted from/to channel 0.

TIME-SLOT NUMBER

0 x 4 0 x 4 0 x 4 0 x 4 0 x 4 0 x 4 0 x 4 0 x 4 0 x 4 0 x 4 0 x 4 0 x 4

TX_TS[12—1][15:12]

TX_TS[12—1][11:8]

TX_TS[12—1][7:4]

TX_TS[12—1][3:0]

^{0 x 4}→ ^{PAYLOAD LOCATIONS}

CONFIGURE SIMILARLY

FOR RX SEQUENCER

VALID AND DIRECTED TO CHANNEL 0

5-7936(F)r.3

Figure 17. Example of Tx/Rx Sequencer Configuration: STS-48c into Single OC-48 Signal

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description (continued)

Data Engine (DE) Block (continued)

Transmit Data Engine (continued)

Figure 18 illustrates the configuration of the time-slot registers for four independent STS-12 signals. In this case,

there are 12 STS-1 signals that comprise each STS-12 signal.

TIME-SLOT NUMBER

12a

12b

12c

12d

11a

11b

11c

11d

10a

10b

10c

10d

0 x 4 0 x 4 0 x 4 0 x 4 0 x 4 0 x 4 0 x 4 0 x 4 0 x 4 0 x 4 0 x 4 0 x 4

0 x 5 0 x 5 0 x 5 0 x 5 0 x 5 0 x 5 0 x 5 0 x 5 0 x 5 0 x 5 0 x 5 0 x 5

0 x 6 0 x 6 0 x 6 0 x 6 0 x 6 0 x 6 0 x 6 0 x 6 0 x 6 0 x 6 0 x 6 0 x 6

0 x 7 0 x 7 0 x 7 0 x 7 0 x 7 0 x 7 0 x 7 0 x 7 0 x 7 0 x 7 0 x 7 0 x 7

TX_TS[12—1][15:12]

TX_TS[12—1][11:8]

TX_TS[12—1][7:4]

TX_TS[12—1][3:0]

^{0 x 4}→ ^{PAYLOAD VALID TO CHANNEL 0}

^{0 x 5}→ ^{PAYLOAD VALID TO CHANNEL 1}

^{0 x 6}→ ^{PAYLOAD VALID TO CHANNEL 2}

^{0 x 7}→ ^{PAYLOAD VALID TO CHANNEL 3}

CONFIGURE SIMILARLY

FOR RX SEQUENCER

5-7937(F)r.3

Figure 18. Example of Tx/Rx Sequencer Configuration: 4xSTS-12c into Four Independent OC-12 Signals

Agere Systems Inc.

TDAT042G5 SONET/SDH

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Data Sheet

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Functional Description (continued)

Data Engine (DE) Block (continued)

Transmit Data Engine (continued)

The multiplexing rules of SONET are illustrated in Figure 19, and are shown for the case of two-stage byte inter-

leaving of 12 STS-1 signals into an STS-12 signal. The values provisioned in the time-slot registers should obey

the SONET multiplexing rules. In Figure 18, time slots 1 through 12 of channel A represent the interleaved bytes of

the multiplexed STS-12 signal being received/transmitted in logical channel 0 (0x4). Channels B, C, and D are con-

figured similarly; however, data is being received/transmitted from logical channels 1, 2, and 3, respectively.

STS#

3:1

12TH BYTE

1ST BYTE

5-8387(F)

Figure 19. SONET Multiplexing: 2-Stage Byte Interleaving Example

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Functional Description (continued)

Data Engine (DE) Block (continued)

Transmit Data Engine (continued)

Figure 20 illustrates the configuration of the time-slot registers for four independent STS-3 signals. In this case,

there are three STS-1 signals that comprise each STS-3 signal. Since there are 12 time slots and only three are

actually required, the values in time slots 4—12 can be repetitively configured as shown in the figure or can be

configured as invalid, i.e., 0x0, 0x1, 0x2, and 0x3 for channels A, B, C, and D, respectively.

TIME-SLOT NUMBER

0 x 4 0 x 4 0 x 4 0 x 4 0 x 4 0 x 4 0 x 4 0 x 4 0 x 4 0 x 4 0 x 4 0 x 4

0 x 5 0 x 5 0 x 5 0 x 5 0 x 5 0 x 5 0 x 5 0 x 5 0 x 5 0 x 5 0 x 5 0 x 5

0 x 6 0 x 6 0 x 6 0 x 6 0 x 6 0 x 6 0 x 6 0 x 6 0 x 6 0 x 6 0 x 6 0 x 6

0 x 7 0 x 7 0 x 7 0 x 7 0 x 7 0 x 7 0 x 7 0 x 7 0 x 7 0 x 7 0 x 7 0 x 7

TX_TS[12—1][15:12]

TX_TS[12—1][11:8]

TX_TS[12—1][7:4]

TX_TS[12—1][3:0]

^{0 x 4}→ ^{PAYLOAD VALID TO CHANNEL 0}

^{0 x 5}→ ^{PAYLOAD VALID TO CHANNEL 1}

^{0 x 6}→ ^{PAYLOAD VALID TO CHANNEL 2}

^{0 x 7}→ ^{PAYLOAD VALID TO CHANNEL 3}

CONFIGURE SIMILARLY

FOR RX SEQUENCER

5-7937(F).ar2

Figure 20. Example of Tx/Rx Sequencer Configuration: 4xSTS-3c into Four Independent OC-3 Signals

Performance Monitoring

This block contains several cell/packet counters for receive/transmit data traffic. Two 28-bit saturating counters

count the number of good packets/cells that are sent out and received by the enhanced UTOPIA interface. There

are 28-bit counters used to count the number of corrected ATM HCS single bit errors, HDLC invalid sequences,

and SDL corrected headers. Also, 28-bit counters are used to count the number of uncorrectable HCS errored

ATM cells (discarded cells), HDLC short packets, SDL errored headers, packets with bad CRC checks, and mis-

matched PPP headers. These counters are operated in latch and clear mode (using PMRST) to ensure GR-256

standards compliance. It is intended that these counters be polled at least once per second so that no error events

are missed.

Agere Systems Inc.

TDAT042G5 SONET/SDH

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Data Sheet

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Functional Description (continued)

Data Engine (DE) Block (continued)

Over-Fiber Modes

In addition to the support of the normal SONET/SDH modes for different payload types such as HDLC, PPP, ATM

(X⁴³or X³¹), and SDL as shown in Figure 2 on pa ge45, this device is capable of supporting the over-fiber modes

for two payload types, SDL or ATM (X³¹). In the over-fiber mode, a 3% payload increase can be realized because

the data stream contains no SONET/SDH overhead bytes.

In the over-fiber modes, it is possible to utilize the whole bandwidth (155 Mbits/s for OC-3, 622 Mbits/s for OC-12,

or 2.5 Gbits/s for OC-48) of the optical fiber for SDL packets or ATM cells.

As can be seen in Figure 21, for over-fiber modes the device is provisioned as follows:

^IThe line termination (OHP) and path termination (PT) blocks of the device need to be provisioned in the

passthrough mode.

^IThe payload termination (DE) block needs to be set to the bit synchronization mode in the payload control regis-

ter.

^IThe transparent mode in the transmit and receive sequencers (addresses 0x102E and 0x102F; see register

description, page 223).

^IBit 12 of the mode register (address 0x0010) needs to be set to 0 so that the received clock drives the entire

receive data path. In this way, there is no need to cross the clock domain boundary. As a result, only a single

channel is allowed for OC-3, OC-12, or OC-48 when the device is operated in the over-fiber modes. In contrast,

the device is capable of supporting four OC-3/OC-12 channels or one OC-8 channel in the SONET/SDH modes.

PAYLOAD

TERMINATION

LINE

PATH

TERMINATION TERMINATION

PACKET/CELL

PROCESSOR

-ENCAPSULATION

-SCRAMBLING

-CRC GENERATION

PASSTHROUGH

SINGLE OC-48

SINGLE OC-12

SINGLE OC-3

ENHANCED

UTOPIA I/O

PACKET/CELL

PROCESSOR

-BIT SYNC

PASSTHROUGH

-DECAPSULATION

-UNSCRAMBLING

-CRC VERIFICATION

CONTROL

µP INTERFACE

5-6680(F).cr.1

Figure 21. TDAT042G5 Over-Fiber Modes: SDL, ATM (X³¹)

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TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

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Functional Description (continued)

Data Engine (DE) Block (continued)

Transparent Payload Mode

The transparent payload mode in the payload termination data engine (DE) block is one of seven basic payload

type modes in the payload control registers and allows data to pass directly through the DE. In this mode, no fram-

ing is done on the data, and the data in the SONET frame is treated as raw data. The transparent payload mode

basically disables all the functions of the framers. In contrast, the transparent mode of the sequencer (over-fiber

mode) disables the conversion function of the sequencer between the SONET/SDH framing structure and the log-

ical channel structure.

In the transparent payload mode, the data engine processes the entire payload as a single packet with no J1 byte

or other POH. An RxSOP is generated on the UTOPIA interface on the first byte following the J1 byte. The last

byte of payload occurs at an RxEOP.

If the device is set in both the transparent payload mode in the payload control registers and the transparent mode

in the sequencer, then the whole SONET/SDH frame (overhead bytes will be overwritten with zeros) will appear at

the receive UTOPIA interface as one packet. At the transmit UTOPIA side, the whole SONET/SDH frame needs to

be supplied.

Transparent Receive Mode Control. In receiving from the line, provisioning must specify the time slot and

SONET frame byte location where the last byte in the packet will occur. The following registers are used to indicate

this location.

^IRx_CHCD_FM (address 0x1030; see register description, page 224) specifies the time slot where the last byte

of a packet exists in channels C andD.

^IRx_CHAB_FM (address 0x1031; see register description, page 224) specifies the time slot where the last byte

of a packet exists in channels A and B.

^IRx_CELLA_FM (address 0x1032), Rx_CELLB_FM (address 0x1033), Rx_CELLC_FM (address 0x1034), and

Rx_CELLD_FM (address 0x1035) specify in which SONET location (0 to 809) the last byte in a packet exists in

channel A, B, C, or D, respectively. (See register descriptions, page 225.)

In the case where the location of the last byte in the frame is not known, the last byte should be provisioned for

location 809 and time slot 12, and external UTOPIA hardware must perform packet delineation on the data

stream.

Transparent Transmit Mode Control. In transmitting to the line, provisioning must specify the time slot and

SONET frame alignment. This is done through Tx_TRANS_CTRL (address 0x102F; see register description,

page 223) used in conjunction with Tx_TS[1—12] (addresses 0x1016—0x1021; see register descriptions,

page 215).

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

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Functional Description (continued)

UTOPIA (UT) Interface Block

The UT core provides buffering and UTOPIA interface functionality. This enhanced UTOPIA interface will pass U2,

U2+, U3, and U3+ protocols. In the receive direction, data is buffered from the line side, and sent out of the device

via a UTOPIA/packet-over-SONET-PHY interface. In the transmit direction, data is received by the device via a

UTOPIA/packet-over-SONET-PHY interface, and buffered before being sent to the line side. Data that is sent or

received can be either packet or ATM traffic, and is configurable on a per-channel basis. The UTOPIA slave inter-

face is designed to accommodate back-to-back ATM cell and packet data transfers in point-to-point or multi-PHY

modes.

Level-2 physical interfaces (transmit and receive) support four logical data channels as shown in Figure 22. Each

of these interfaces is independently configurable for cell or packet transfers, and can support up to STS-12/STM-4

bandwidth. Optionally, two of the interfaces, specifically A and B, can be grouped together to support a 32-bit

UTOPIA level-3 interface supporting up to STS-48/STM-16 of bandwidth. The aggregate traffic that can be carried

over these interfaces is limited to STS-48/STM-16 bandwidth.

In addition to operating as separate point-to-point streams, MPHY capabilities for up to four channels can be pro-

vided from the A interface in either 16-bit or 32-bit modes. For example, when operating as a 32-bit interface, the A

interface can support either a single STS-48c channel or four STS-12c channels. As a 16-bit interface, the MPHY

interface can support either a single STS-12c channel or four STS-3c channels.

Since each channel can be configured independently, each one can carry different traffic types at different rates,

provided that the capabilities of the active interfaces and the data engine are not exceeded.

There are two basic data paths: receive side, defined to be data going from the line side to the UTOPIA side, and

transmit side, defined to be data going from the UTOPIA side to the line side as shown in Figure 22.

EGRESS SIDE

INTERFACE A

INTERFACE B

INTERFACE C

INTERFACE D

LOOPBACKS

INTERFACE A

INTERFACE B

INTERFACE C

INTERFACE D

INGRESS SIDE

INTERNAL

CONTROL

BUS

SOFTWARE REGISTERS

UTOPIA 2/3 INTERFACE

NOTE: UTOPIA 32-bit MODE

COMBINES CHANNELS A & B

IN BOTH DIRECTIONS (Tx & Rx)

5-7056(F)r.5

Note: For MPHY support, channels are mapped to interface A only.

Figure 22. UT Block Diagram

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TDAT042G5 SONET/SDH

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Functional Description (continued)

UTOPIA (UT) Interface Block (continued)

Enhanced refers to the extensions that have been added to support packet transfers. These extensions are indica-

tions of the following: (1) an end of packet (TxEOP/RxEOP), (2) the byte on which packet ends in last word (TxSZ/

RxSZ), and (3) the signal to abort a packet early (TxERR/RxERR). An abort occurs, for example, if the check sum

at the end of a packet is bad, or the end of a packet is reached prematurely. If the receive FIFO overflows because

the master cannot process packet data fast enough, an RxERR will also be generated.

UTOPIA Loopbacks

TDAT042G5 can be placed in loopback on a channel-by-channel basis. When the TDAT042G5 is placed in far-end

loopback (FELB), data from the DE is sent to and processed by the UTOPIA interface. Instead of sending it to the

UTOPIA master, however, the data is sent to the corresponding egress channel and back to the line interface.

When the TDAT042G5 is placed in near-end loopback (NELB), data from the egress channel is transferred to the

corresponding ingress channel, instead of the DE. This data is then processed by the ingress channel and is

returned to the UTOPIA master.

UTOPIA Modes

Each UTOPIA interface mode is capable of supporting various types of traffic with different bandwidth capabilities

as summarized in Table 24. In a point-to-point operational mode, any interface can be configured independently in

any of the defined modes (e.g., channel A passes ATM cells using STS-12c, channel B passes packets, etc.).

It should be noted that the U3 or U3+ (32-bit mode) can only be supported by overloading channel A and B inter-

face pins. Only the control signals from channel A are used. The channel B size and data bits are combined with

the channel A size and data bits to form the 2-bit size and the 32-bit data words. When 32-bit mode is selected,

channels B, C, and D must be configured to be idle (so that channel B will be under the control of channel A in

32-bit mode).

Multichannel multi-PHY (MPHY) capabilities are only supported on interface A by grouping the internal FIFOs and

data paths of channels B, C, and D as needed. This operational mode is described in a later section.

Table 24. UTOPIA Traffic Types

UTOPIA Name

Interface

Width

Maximum

Speed

Aggregate

Bandwidth

Traffic Type

Maximum

Number of

Interfaces

16 bits

8 bits

52 MHz*

104 MHz

622 Mbits/s (STS-12)

ATM cells only

U2+

622 Mbits/s (STS-12) ATM cells/packets

622 Mbits/s (STS-12) ATM cells only

622 Mbits/s (STS-12) ATM cells/packets

2.5 Gbits/s (STS-48) ATM cells only

2.5 Gbits/s (STS-48) ATM cells/packets

U3, 8-bit mode

U3+, 8-bit mode

U3, 32-bit mode

U3+, 32-bit mode

8 bits

32 bits

* Maximum speed may be exceeded if nonstandard load conditions are used and the clock is sourced. See CLOCK_MODE_Rx [A—D]

(registers 0x020F, 0x0213, 0x0217, 0x021B), pages 158—159 for details.

Agere Systems Inc.

TDAT042G5 SONET/SDH

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Functional Description (continued)

UTOPIA (UT) Interface Block (continued)

UTOPIA ATM Cell Processing

The UTOPIA block will process ATM packets of 52, 53, 54, or 56 bytes. The standard 53-byte ATM cell structure is

shown in Table 25.

Table 25. Standard 53-byte ATM Cell Structure

H5 (HEC)

. . .

D48

8 bits

53 bytes

In the receive path, TDAT042G5 automatically calculates the HEC (byte 5) and overwrites this byte of the ATM cell.

It is therefore possible to transfer only 52-byte packets through the UTOPIA I/O to increase interface efficiency.

This mode will be referred to as the 52-byte mode. The 52-byte or 53-byte ATM mode is provisioned through

ATM_SIZE_Rx[A—D] (bit 4 of registers 0x020F, 0x0213, 0x0217, and 0x021B) and ATM_SIZE_Tx[A—D] (bit 4 of

registers 0x0210, 0x0214, 0x0218, and 0x021C).

U2 Modes. For U2 and U2+, both the 52-byte and 53-byte, 16-bit UTOPIA interface modes are supported forATM

cells as shown in Table 26.

Table 26. Bus Format for 16-bit Interface

53-byte Option^†

TxD[15:8] or RxD[15:8] TxD[7:0] or RxD[7:0] TxD[15:8] or RxD[15:8] TxD[7:0] or RxD[7:0]

52-byte Option (HEC Omitted)

H5 (HEC)

H5 (UDF*)

D47

D48

D47

D48

* UDF refers to the undefined H5 byte.

†This option is also called the 54-byte mode.

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TDAT042G5 SONET/SDH

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Functional Description (continued)

UTOPIA (UT) Interface Block (continued)

UTOPIA ATM Cell Processing (continued)

U3 Modes. For U3 and U3+, both the 52-byte and 53-byte, and either 8-bit or 32-bit modes are supported for ATM

cells as shown below.

For the case of an 8-bit UTOPIA interface, data is placed on the UTOPIA port as shown in Table 27.

Table 27. Bus Format for 8-bit Interface

53-byte Option

52-byte Option (HEC Omitted)

TxD[15:8] or RxD[15:8] TxD[7:0] or RxD[7:0] TxD[15:8] or RxD[15:8] TxD[7:0] or RxD[7:0]

Not used

H5 (HEC)

D48

Not used

D48

Not used

For the case of a 32-bit UTOPIA interface, parallel data is placed on the UTOPIA port as shown inTable 28.

Table 28. Bus Format for 32-bit Interface

53-byte Option^†

TxD[23:16] TxD[15:8]

or or

52-byte Option (HEC Omitted)

TxD[31:24]

TxD[7:0]

TxD[31:24]

TxD[23:16]

TxD[15:8]

TxD[7:0]

RxD[31:24] RxD[23:16]

RxD[15:8]

RxD[7:0]

RxD[31:24] RxD[23:16]

RxD[15:8]

RxD[7:0]

H5 (HEC)

H5-UDF1

H5-UDF3

H5-UDF2

D45

D46

D47

D48

D45

D46

D47

D48

* UDF refers to undefined H5 bytes.

†This option is also called the 56-byte mode.

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TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

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Functional Description (continued)

UTOPIA (UT) Interface Block (continued)

UT Clocking

TDAT042G5 is compliant with the U2 standard¹and several versions of the proposed U3 specification^2—6as a UT

slave device. The U2 standard and proposed U3 specifications define the slave device transmit path (egress) clock

as an input clock. For the U2 case, the slave transmit path clock is generated by the UT master device. For the cur-

rent version of the U3 specification⁶, the transmit path clock for both slave and master devices is generated by the

same external clock source⁷. The U2 standard and current U3 proposed specification⁶define the slave device

receive path (ingress) clock as an input clock. In the U2 case, the slave device receive path (ingress) clock is gen-

erated by the UT master device. In the U3 case, the receive clock for both the master and slave devices is gener-

ated by same external clock source. Previous proposed versions of the U3 specification provided for the case

where the receive path clock could be generated by the slave device. TDAT042G5 can be provisioned in the con-

figuration where it sources the receive path (ingress) clock.

The timing specification for the UT clock is given in the UTOPIA Interface Timing section, pages 268—270.

UT Transmit Path (Egress) Clock

In all UTOPIA modes, the transmit path clock must be provided to TxCLK[D:A] pins as described in Table 5, page

page 31.

UT Receive Path (Ingress) Clock

The receive path clock RxCLK[D:A] pins can be provisioned to be either clock inputs or outputs as described in

Table 5, page 38. Provisioning as either an input or output is done on a per-channel basis through registers

0x020F, 0x0213, 0x0217, and 0x021B (CLOCK_MODE_Rx). In the U2 mode, RxCLK is always provisioned to be

an input. To meet the latest proposed U3 specification, RxCLK is provisioned as an input. To meet special UT

requirements, RxCLK may be provisioned to be a clock output signal. When provisioned as a clock output, the

RxCLK[D:A] is derived from the corresponding TxCLK[D:A] input.

For RxCLK rates greater than 52 MHz, RxCLK must be provisioned to be an output.

1. UTOPIA Level 2, Version 1.0, AF-PHY-0039.000, June 1995.

2. UTOPIA Level 3 Baseline Text, UL3-01.04, February 1999.

3. UTOPIA Level 3 Living List, UL3-01.04, February 1999.

4. UTOPIA Level 3 Living List, LTD-PHY-UL3-01.05, April 1999.

5. UTOPIA Level 3, STR-PHY-UL3-01.00, July 1999.

6.UTOPIA Level 3, AF-PHY-136.00, October 1999.

7.Previous proposed versions of the U3 specification were similar to the U2 standard where the slave device transmit clock was generated by

the UT master device.

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TDAT042G5 SONET/SDH

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Functional Description (continued)

UTOPIA (UT) Interface Block (continued)

UT Receive Input Path (Ingress)

The UTOPIA Rx interface is designed to accommodate ATM cells as well as packet traffic. While the standard

UTOPIA interface transmits and receives ATM cells, this interface has been enhanced to carry non-ATM traffic.

The interfaces supported include the following: UTOPIA Level 2 (U2), enhanced UTOPIA Level 2 (U2+), UTOPIA

Level 3 (U3) in 8-bit mode or 32-bit mode, and enhanced UTOPIA Level 3 (U3+) in 8-bit mode or 32-bit mode.

In the receive direction, data arrives and is sent to one of four channels (A through D). Each channel buffers data

independently and, when sufficient data has been stored in its FIFO, sends the data out of the channel via its UTO-

PIA interface. There are four paths inside the UT core, corresponding to one path per channel. These paths are

labeled A to D. When using 32-bit modes, only the control signals of interface A and size signals of interfaces A

and B are used.

Note: 32-bit mode is supported using channels A and B only. When 32-bit mode is selected, channels B, C, and D

must be configured to be idle (channel B will be under the control of channel A in 32-bit mode).

In normal mode, data arrives into the ingress channel, and control and data information are written into the FIFO.

The data is extracted from the FIFO, and word-aligned on the first byte of data. After word alignment, the data is

sent out of the device via the UTOPIA interface.

Note:The start of packets must be word-aligned, and there can only be one packet per word (required by the defi-

nition of the UTOPIA interface).

FIFO. The 256-byte UTOPIA Rx FIFO is responsible for buffering data from the DE block to be sent to the UTOPIA

interface. The FIFO accommodates four ATM cells or 256 bytes of packet data. In STS-48/STM-16, only one

256-byte FIFO is used. The FIFO is required to manage the asynchronous nature of the UTOPIA interface. Over-

flow will only occur if the master device connected to the UTOPIA interface is having congestion problems. When

overflow occurs and head of line discard is performed, it is possible that part of one packet may be appended to

another (if, for example, an end of packet is discarded along with the data at the head of the FIFO). Because this is

not a desirable operation, it is necessary to discard until the start of the next packet is observed. Data is read from

the FIFO when there is sufficient data in the FIFO. Upon overflow, the RxERR and RxEOP signals are asserted to

indicate to the master the corruption of the current packet.

Sufficient data is defined to be a minimum amount of data in the FIFO (a programmable threshold, low watermark),

or at least one end of packet stored in the FIFO. If the FIFO overflows, the block is responsible for discarding data

until the next start of packet. When this occurs, an alarm is raised. Underflow in the receive direction can occur

when there is no data, or if only part of a packet has arrived and has been transmitted, and is normal behavior.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

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Functional Description (continued)

UTOPIA (UT) Interface Block (continued)

UT Receive Input Path (Ingress) (continued)

Receive Cell/Packet Available (RxPA). This signal indicates when the TDAT042G5 receive FIFO can send data

to the master device. The RxPA[D:A] signal behavior depends on the provisioned low watermark in the UTOPIA

interface.

^IOne-Cycle Delay Mode. This mode follows the UTOPIA Level 2 Standard. The RxPA response occurs one cycle

after the address is polled. RxENB is asserted to activate the selected PHY. RxDATA and RxSOP are output one

cycle after RxENB is sampled active by the PHY device.

^ITwo-Cycle Delay Mode. This mode follows the UTOPIA Level 3 baselined text*. The RxPA response occurs two

cycles after the address is polled. RxENB is asserted to activate the selected PHY. RxDATA and RxSOP are out-

put two cycles after RxENB is sampled active by the PHY device.

^IRxPA[D:A] Assertion. RxPA[D:A] goes high (is asserted) when the amount of data in the receive FIFO has

reached or exceeded the low watermark or there is end of packet (EOP) resident in the FIFO.

^IRxPA[D:A] Deassertion. In ATM mode, the RxPA[D:A] signal goes low (is deasserted) when the FIFO has less

than the low threshold amount of data and there is no EOP inside the FIFO (i.e., part of anATM cell). Once the

last byte of the current cell is transmitted, and if the amount of data within the FIFO is still less than the low

threshold, RxPA[D:A] is deasserted.

In packet mode, the RxPA[D:A] signal goes low (is deasserted) when the FIFO has less than the low threshold

amount of data and there is no EOP inside the FIFO.

Once the data transfer begins (since the amount of data has reached or exceeded the low watermark), and if

there is no EOP below the low threshold (i.e., a long packet), the RxPA signal is deasserted when the FIFO is

drained by the UTOPIA master device. In this case, the master must closely monitor the RxPA[D:A] signals and

use these signals as data valid indicators to ensure that bad data is not read from the TDAT042G5. TDAT042G5

will deassert the RxPA[D:A] signal immediately when the FIFO is drained.

^IData Transfer. A TDAT042G5 ingress channel sends data when it has asserted RxPA[D:A] and the master

device requests data (via RxENB[D:A]). InATM mode, if the master device requests data using RxENB[D:A] and

if the TDAT042G5 has less than the low watermark amount of data to send and there is no end of cell in the FIFO

(RxPA[D:A] is deasserted), then the TDAT042G5 UTOPIA interface will send out data that should be ignored by

the master, i.e., it does not send data from its internal FIFO.

In ATM mode, once an ATM cell transfer starts, the Tx or Rx side must complete the transfer. If the transfer is not

completed, then the cell will be corrupted. The transfer continues until either (1) the end of cell is reached, when

the end of cell exists below the low watermark, or (2) the end of the FIFO is reached. If the end of the FIFO is

reached, no underflow is flagged on the receive side. In ATM mode, the low watermark should be set so that at

least one entire cell is in the FIFO prior to asserting RxPA[D:A].

In packet mode, once the data transfer begins, the RxPA[D:A] signal will remain asserted until the FIFO is

drained if there is no EOP below the low watermark. During the time RxPA[D:A] is asserted, valid data is being

transferred.

RxPA[D:A] is updated on the rising edge of RxCLK[D:A].

In 32-bit mode, only the RxPA[A] pin of port A is used to indicate the packet/cell available status.

^IMPHY Support. When the RxPA signals are used for MPHY direct status, the corresponding

RxCLK[B, C, and/or D] must be provided. This clock will be the same as RxCLK[A].

* ATM Forum Technical Committee, UTOPIA Level 3, STR-PHY-UL3-01.00, July 1999.

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description (continued)

UTOPIA (UT) Interface Block (continued)

UT Receive Input Path (Ingress) (continued)

Figure 23 illustrates the receive-side interface handshaking when operating in point-to-point mode with the RxPA

response provisioned to be a single cycle. In two-cycle mode, the RxSOP, RxDATA, and RxPA signals are

delayed an additional cycle. In the figure, the master device initiates the transfer after observing an asserted

packet available for the channel. The TDAT042G5 samples RxENB low on the first cycle and then asserts

RxSOP/C and RxDATA on the second cycle. RxDATA is sampled on the rising edge of the second cycle by the

master device. Figure 24 illustrates receive-side interface handshaking when operating in two-cycle mode. When

operating in U3+ mode, two-cycle mode must be used.

In this example, the master stops transfer in the middle of the packet. Data with value c is valid on the cycle that

RxENB goes inactive, and when RxENB returns, data is again valid on the first cycle after the slave observes an

active RxENB (data value d).

The packet transfer is complete when the slave asserts the RxEOP signal. If an error occurs in the packet, then the

RxERR signal is asserted simultaneously with the RxEOP. RxERR is ignored if it is not asserted when RxEOP is

active.

RxCLK

RxPA

RxENB

RxSOP/C

RxDATA[15:0]

RxEOP

RxERR

5-7450(F).ar.2

Figure 23. Receive-Side Interface Handshaking in Point-to-Point, Single Cycle Mode

The packet transfer is complete when the slave asserts the RxEOP signal. If an error occurs in the packet, then the

RxERR signal is asserted simultaneously with the RxEOP. RxERR is ignored if it is not asserted when RxEOP is

active.

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Data Sheet

May 2001

Functional Description (continued)

UTOPIA (UT) Interface Block (continued)

UT Receive Input Path (Ingress) (continued)

RxCLK

RxPA

RxENB

RxSOP/C

RxDATA[15:0]

RxEOP

RxERR

5-7450(F)br.1

Figure 24. Receive-Side Interface Handshaking in Point-to-Point, Two-Cycle Mode

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Data Sheet

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Functional Description (continued)

UTOPIA (UT) Interface Block (continued)

UT Transmit Input Path (Egress)

In the transmit direction, data arrives from the various UTOPIA interfaces, and is stored in a 256-byte FIFO, one

per channel. After sufficient data has been stored into the FIFO, it is made available to be sent to the DE.

Like the UTOPIA Rx interface, the UTOPIA Tx interface is designed to accommodate ATM cells as well as packet

traffic. While the traditional UTOPIA interface only transfers ATM cells, this interface has been enhanced to carry

packet traffic. The interfaces supported include the following: UTOPIA Level 2 (U2), enhanced UTOPIA Level 2

(U2+), UTOPIA Level 3 (U3) in 4 x 8-bit mode or 32-bit mode, and enhanced UTOPIA Level 3 (U3+) in 4 x 8-bit

mode or 32-bit mode.

The UTOPIA Tx side can indicate to the ATM side to suspend the transfer, by deasserting TxPA, when necessary.

When the amount of data in the FIFO exceeds its programmable high watermark, it deasserts TxPA. This signal

causes the deassertion of TxPA on the next clock. At this point, the ATM side knows that the UTOPIA Tx block can

only accept a limited number of words, after which it will overflow. In this case, the ATM device must not exceed

writing this limited number of words before suspending the transfer. Transfer is resumed once again when the

FIFO falls below the high watermark. When transferring ATM cells, TxPA must be deasserted four clocks before

the end of cell, or else it must be prepared to accept an entire new cell. When transferring ATM cells, deasserting

TxPA does not immediately suspend the transfer of the current cell because the entire cell can be transmitted with-

out interruption.

Transmit Cell/Packet Available (TxPA). This signal indicates when the TDAT042G5 transmit FIFO can accept

data from the master device. If the FIFO is empty or more than the provisioned space is available in the FIFO,

TxPA[D:A] is set active.

^IOne-Cycle Delay Mode. This mode follows the UTOPIA Level 2 Standard. The TxPA response occurs one cycle

after the address is polled.

^ITwo-Cycle Delay Mode. This mode follows the UTOPIA Level 3 baselined text*. The TxPA response occurs two

cycles after the address is polled.

^ITxPA[D:A] Assertion. The TxPA[D:A] signal behavior relies on the UTOPIA provisionable watermarks. In

packet mode, TxPA[D:A] goes high when the amount of data in the FIFO is less than the high watermark setting.

In ATM mode, TxPA[D:A] goes high when the FIFO has space to receive a complete ATM cell from the master.

(This requires the high threshold to be set appropriately by the user, i.e., set so that an entire cell can be

received once TxPA[D:A] goes active.)

^ITxPA[D:A] Deassertion. In packet mode, TxPA[D:A] goes low when the amount of data in the FIFO reaches or

exceeds the high watermark. In ATM mode, TxPA[D:A] goes low when there is not enough space in the FIFO to

receive an entireATM cell. (This requires the threshold values to be provisioned properly, i.e., set low enough

such that when the high watermark is reached, the transmission of the current cell can be completed without

overflowing the FIFO). In ATM mode, TxPA[D:A] will be deasserted four cycles before the end of the current cell

transfer if the FIFO cannot accept a complete ATM cell on the following transmission.

TxPA[D:A] is updated on the rising edge of TxCLK[D:A].

In 32-bit mode, only the TxPA[A] pin of port A is used to indicate the packet/cell available status.

^IMPHY Support. When the TxPA signals are used for multi-PHY (MPHY) direct status, the corresponding

TxCLK[B, C, and/or D] must be provided. This clock will be the same as TxCLK[A].

* ATM Forum Technical Committee, UTOPIA Level 3, STR-PHY-UL3-01.00, July 1999.

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TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description (continued)

UTOPIA (UT) Interface Block (continued)

UT Transmit Input Path (Egress) (continued)

FIFO. The UTOPIA Tx FIFO is used to create an elastic store that can buffer bursts of data received via the UTO-

PIA Tx, faster than can be transmitted out of the path. After the FIFO exceeds a programmable watermark, it indi-

cates to the UTOPIA Tx master to stop sending data. The master can choose to ignore this request causing the

risk of an overflow. The FIFO block buffers 256 bytes of cell/packet data. The FIFO accommodates four ATM cells

or 256 bytes of packet data. The FIFO is required to manage the asynchronous nature of the UTOPIA interface.

Optionally, in the case of FIFO underflow, a 0x7D207D207D20 . . . will be inserted by the data engine into the mid-

dle of the packet if dry mode is provisioned and the default dry escape sequence is used (0x7D20, where the last

two bytes (the 20 bytes of the default value of 0x7D20) are provisionable). This will be removed at the far end by

the device (provided the link is comprised of two devices and both sides of the link support dry mode).

^IFIFO Watermark Threshold. When carrying ATM cell traffic, this threshold, while measured in words, should be

set at least one cell’s length from end of FIFO. The UTOPIA Tx interface, by definition, must be able to accept an

entire ATM cell after the current ATM cell, unless TxPA is deasserted at least four clock cycles before the end of

the current cell transfer.

When carrying packet traffic, however, the threshold can be set higher, as the UTOPIA Tx interface only needs

to accept a limited number of words after deasserting TxPA. The number of words is a programmable value for

the sender, and should be assumed to be at least 2 words for the purposes of setting the threshold.

FIFO high watermark threshold, EGRESS_WATERMARK_HIGH_[A—D][6:0] (addresses 0x0212, 0x0216,

0x021A, 0x021E), should be set as follows.

Table 29. Egress High Watermark Thresholds

UTOPIA Mode

Maximum Threshold Value

8-bit, U3+

16-bit, U2+

32-bit, U3+

0x3D

0x3B

0x37

Note: The high watermark threshold should be set less than the values in the above table assuming there is no

delay between TxPA deassertion and TxENB deassertion. Then the threshold values may be changed to

optimize UT egress performance and to avoid FIFO overflow.

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155/622/2488 Mbits/s Data Interface

Data Sheet

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Functional Description (continued)

UTOPIA (UT) Interface Block (continued)

UT Transmit Path (Egress) (continued)

Figure 25 illustrates the transmit-side interface handshaking when operating in point-to-point mode with the TxPA

response provisioned to be a single cycle. In two-cycle mode, the TxPA signal is delayed an additional cycle. In the

figure, the master device initiates the transfer after observing an asserted packet available for the channel by

asserting the TxENB signal. The master places data and start of packet on the bus the same cycle as TxENB, and

the TDAT042G5 samples the TxSOP and TxDATA on the following clock cycle (rising edge).

In this example, the master stops transfer in the middle of the packet. Data with value c is valid on the cycle that

TxENB goes inactive, and when TxENB returns, data is again valid on the first cycle (data value d).

The packet transfer is complete when the master asserts the TxEOP signal. If an error occurs in the packet, then

the TxERR signal is asserted simultaneously with the TxEOP. TxERR is ignored if it is not asserted when TxEOP

is active.

TxCLK

TxPA

TxENB

TxSOP/C

TxDATA[15:8]

TxEOP

TxERR

5-7457(F).ar.2

Figure 25. Transmit-Side Interface Handshaking in Point-to-Point, Single Cycle Mode

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Data Sheet

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Functional Description (continued)

UTOPIA (UT) Interface Block (continued)

Multi-PHY Support

In addition to point-to-point UTOPIA mode, the TDAT042G5, as the slave device, can also be configured to support

the polled multi-PHY mode. To operate in multi-PHY mode, channel A must be configured in the polling mode,

since the control signals of channel A are used for all channels. Any combination of B, C, or D can be included in

the polling group, in which case they provide control information to channel A. Channels B, C, and D also can be

configured in any of the UTOPIA modes. In this case, the output is transferred through the channel A interface

(channel A and B interfaces for 32-bit mode). Channels not configured for polling can be operated as point-to-point

connections. If channel A is in 32-bit polling mode, channel B cannot be in point-to- point mode since its interface is

controlled by channel A, while channels C and D may be provisioned as point-to-point connections.

Figure 26 shows a multi-PHY mode when all four channels of the UT are in polling mode.

RxPA[A]/RxDATA[A]

INGRESS CHANNEL A

INGRESS CHANNEL B

INGRESS CHANNEL C

INGRESS CHANNEL D

UTOPIA _PHY_Rx

RxENB[A]/RxADDR

RxPA[B]

UTOPIA _PHY_Rx

RxPA[C]

RxPA[D]

µP

TxPA[A]

EGRESS CHANNEL A

EGRESS CHANNEL B

EGRESS CHANNEL C

EGRESS CHANNEL D

UTOPIA _PHY_Tx

TxENB[A]/TxDATA[A]/TxADDR

TxPA[B]

UTOPIA _PHY_Tx

TxPA[C]

TxPA[D]

5-7349(F)r.2

Figure 26. Multi-PHY Configuration of All Four Channels

Mixed mode polling is also possible. For example, for those channels operated in polling mode, it is legitimate for

some of the channels to be in packet mode while others are in ATM mode. However, if one or more of the channels

are in packet mode, channel A should be configured as packet mode to activate control signals for packet transfer.

Multi-PHY operation can be configured by asserting the polling mode enable bit and Tx/Rx address in the respec-

tive port provisioning registers (see port provisioning registers, pages 158—161). Microprocessor provisionable

registers in each channel include a polling mode enable bit and 5-bit Rx address or 5-bit Tx address. The value for

the Tx and Rx address of an MPHY channel must be identical. Both the Rx and Tx directions have a 5-pin address

input to poll and select the appropriate PHY.

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Data Sheet

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Functional Description (continued)

UTOPIA (UT) Interface Block (continued)

Multi-PHY Support (continued)

In 8-bit or 16-bit multi-PHY mode, only the data bus and the control signals (except the RxPA or TxPA signal) of

channel A are active for the polled group. RxPA[A] indicates the packet/cell availability of the selected or polled

channel. Similarly, TxPA[A] indicates transmit FIFO availability for a selected or polled channel. The remaining

RxPA/TxPA signals for the polled channels are activated and indicate instantaneous or direct status of the particu-

lar channel. In 32-bit multi-PHY mode, the data bus and size control signals of channel B are also active.

TDAT042G5 does not provide a selected packet available (SPA) signal to monitor the status of the current channel

sending/receiving data to or from the master. To prevent the FIFOs from running dry or overflowing in the middle of

a packet transfer, the user must design the UT TDAT042G5 slave-to-master interface with direct status mode

rather than address polling. The direct status of each channel is provided on the associated SPA pin for that chan-

nel. In this mode, the user must guarantee that when channels are switched to receive data from a channel other

than channel A, they immediately reapply the address of channel A to the address bus after the new channel is

selected. The user then gets the direct status SPA signal from channel A. Channels B, C, and D are always directly

sent out of the TDAT042G5. In either receive or transmit, when direct status is used in addition to the direct status

pin for a given interface, its corresponding interface clock pin must be driven by the clock of the A interface.

During the cycle when the selected channel is being changed, the address of the new channel is placed on the

address bus. The user must ignore the RxPA response of the initial channel during the expected response time

(one or two cycles later, depending on the PA response bit when the address of the newly selected channel was

applied).

Figure 27 illustrates the transmit interface timing for the case when the direct status of packet available of channels

A, B, C, and D is present. In this example, channels A and C indicate they can receive data. When the SPA signal

for C is observed, a channel switch is performed by the master by deasserting TxENB and placing the address of

channel C on the address bus. On the following cycle, data is placed on the bus along with the start of packet. In

this example, the TxPA response is configured for two cycles so that the PA response of address 02 results in the

PA of channel C to appear on channel A’s output two clock cycles later. Subsequent data sent to the slave will go

to channel C (i.e., data values I, J, etc.).

When the RxPA signals are used for multi-PHY (MPHY) direct status, the corresponding RxCLK[B, C, and/or D]

must be provided. They may be provided via an external UT master, or they may be sourced from the correspond-

ing TxCLK[D:A] pin by using the UT clock source mode (see UT Clocking, page 88).

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TDAT042G5 SONET/SDH

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Data Sheet

May 2001

Functional Description (continued)

UTOPIA (UT) Interface Block (continued)

Multi-PHY Support (continued)

TXCLK[A]

TXADDR

TXPA[A]

TXPA[B]

TXPA[C]

TXPA[D]

TXENB[A]

HIGH Z

TXSOP/C[A]

TXDATA[A][15:0]

TXDATA[B][15:0]

TXEOP[A]

HIGH Z

TXSIZE[A, B]

5-7933(F).ar.3

Figure 27. TxPA Two-Cycle Responses of a Multi-PHY for All Four Channels

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Data Sheet

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Functional Description (continued)

UTOPIA (UT) Interface Block (continued)

Multi-PHY Support (continued)

The ATM side sends one RxENB (TxENB) signal to channel A for the grouped channels to select a channel which

has ATM cells/packets (or room) available. An MPHY channel is selected using the following procedures.

1.The ATM layer polls the RxPA[D:A] (TxPA[D:A]) status of a channel by placing its address on the RxADDR[4:0]

(TxADDR[4:0]) lines.

2.In the following cycle, the MPHY channel gives its status by driving RxPA[D:A] (TxPA[D:A]) of channel A.

3.The ATM side selects the MPHY channel by placing the desired MPHY address on the address bus

RxADDR[4:0] (TxADDR[4:0]) during this cycle; RxENB[D:A] (TxENB[D:A]) is deasserted.

4.During the next cycle, the ATM side asserts RxENB[D:A] (TxENB[D:A]), and the selection of an MPHY channel is

made.

Only one MPHY channel at a time is selected for a cell/packet transfer when ATM drives RxENB (TxENB) for

channel A from high to low. However, another MPHY channel can be polled for its RxPA (TxPA) status while the

selected channel transfers data.

Figure 28 shows an example of the single-cycleRxPA response of each channel. In this figure, channels A, B, C,

and D have Rx addresses 00, 01, 02, and 03, respectively. RxPA[A] shows the packet availability of all four chan-

nels. Channels A and C have available packets to send, and channels B and D do not have packets to send. By

driving RxENB[A] low at clock edge 1, the ATM side selects channel A, and packet transfer is started at

clock edge 2. The master samples this data at clock edge 3. At clock edge 4, RxPA[C] shows that channel C also

has a packet to send, and this is reflected to RxPA[A] at clock edge 5. RxPA[B] and RxPA[D] show the direct status

of channels B and D, indicating that they do not have packets to send.

RXCLK[A]

RXADDR

RXDATA[A]

P1P2

P3P4

P5P6

P7P8

P9P10 P11P12 P13P14 P15P16 P17P18

HIGH Z

RXSOP/C[A]

RXEOP[A]

HIGH Z

RXSZ[A]

RXENB[A]

HIGH Z

RXPA[A]

RXPA[B]

RXPA[C]

RXPA[D]

5-7348(F)r.2

Figure 28. RxPA Responses of a Multi-PHY for All Four Channels

(PA Response Configured for One Cycle)

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Data Sheet

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Functional Description (continued)

JTAG (Boundary-Scan) Test Block

The JTAG test block provides an IEEE 1149.1 JTAG controller interface for memory BIST, boundary scan, and

32-bit ID register instructions. Details about JTAG (boundary-scan) functionality and interface timing specifications

can be found in MN98-060ASIC-02, HL250C 3.3 Volt 0.25 µm CMOS Standard-Cell Library Manual, page 8-1

through page 8-31.

The instruction register length is 3 bits.

Reset of JTAG Logic

There are two events that will reset the JTAG logic:

^IPulse or pull the TRST pin signal low with no TCK pin signal present. TRST is pulled high on-chip.

^IThe TMS pin signal is driven high for five cycles of TCK. TMS is pulled high on-chip.

TRST can be held high during normal device operation only if TRST is pulled low upon powerup.

Line Interface

LVPECL I/O Termination and Load Specifications

The LVPECL buffers are compatible with the temperature independent ECL 100K levels, but the output levels that

are guaranteed are relaxed 30 mV from the actual 100K levels allowing for noise and variations in the power sup-

ply and process.

All LVPECL output buffers require a terminating resistor. These terminating resistors, which must also be con-

nected to both LVPECLREFHI and LVPECLREFLO, go to a common terminating voltage. All of the terminating

resistors used with a chip must be identical precision (1%) resistors. The value of these terminating resistors is

usually chosen to match the characteristic impedance of the board. To save on power, a terminating voltage equal

to VDDD – 2 V is available in most ECL systems. The minimum value of the terminating resistor that can be used on

these bufers is 50 Ω. This is also the standard termination used in most ECL systems. Larger values of resistance

will save power, but will also slow down the high-to-low transition of the output, since it is RC limited.

if no VDDD – 2 V supply is available, a larger value resistor may be connected directly to GND. It should be chosen

such that the current through it does not exceed the current through a 50 Ω resistor to VDDD – 2 V (21 mA in the

high state). This large resistor will most likely be a poor match to the board impedance. The match can be

improved by the user of a Thevenin equivalent resistor pair. Such a Thevenin equivalent resistor will burn much

more system power (but not on-chip power) than would a single resistor, but it does allow for impedance matching

in the absence of aVDDD – 2 V supply. Termination resistor options are shown in Table 30.

Experienced ECL designers sometimes use the (bipolar) ECL output buffers in a tied-OR configuration. Unfortu-

nately, this cannot be done with these LVPECL buffers.

Table 30. Nominal dc Power for Suggested Terminations

Note: The value is the average of the high and low states inLVPECL output buffer and external terminating resis-

tors, for a single-ended output. The values double for double-ended outputs.

Terminating Resistor and Voltage

Output Transistor (on-chip) Terminating Resistor (off-chip)

Power (mW)

50 Ω to VDDD – 2 V¹

125 Ω to VDDD and 83 Ω to GND²

Standard ECL termination (parallel).

Thevenin equivalent or 50 Ω to VDDD – 2 V.

100

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Data Sheet

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Line Interface (continued)

LVPECL I/O Termination and Load Specifications (continued)

The input common mode range for LVPECL differential buffers is from 1 V to 2.75 V; and the swing needs to be at

least 300 mV. So basically what it means is the lowest voltage on the input should be no lower than (1 V – 0.150 V)

and the highest voltage on the input shouldn’t be more than (2.75 V + 0.150 V). So if the differential swing is

800 mV, then the common mode range would be 2.5 V down to 1.25 V. This is all for 3 V buffers.

Interface Description

Microprocessor Interface

This device is equipped with a generic 16-bit microprocessor interface that allows operation with most commer-

cially available microprocessors. Input MPMODE is used to configure this interface into one of two possible modes

(synchronous or asynchronous). In synchronous mode, the microprocessor interface can operate at speeds from

1 MHz up to 66 MHz.* In asynchronous mode, the internal 78 MHz system clock is used to operate this interface.

Table 31. MPU Modes

MPMODE

Mode

Microprocessor Interface Signals

Async

Sync

CS, INT, D[15:0], A[15:0], ADS, R/W, DS, DT

MPCLK, CS, INT, D[15:0], A[15:0], ADS, R/W, DT

The host interface is designed to connect directly to a commonly used asynchronous or synchronous host bus.

The interface to this block includes a separate clock, MPCLK, which is used in the synchronous interface mode.

The interface is only a slave on the host bus. There is no posting of writes in the host interface; all registers are

directly accessible. The microprocessor interface pins use 3.3 V (5V, TTL-tolerant) CMOS I/O levels. The micro-

processor interface timing specifications are given in the Interface Timing Specifications section (see Table 163—

Table 166, pages 257—263).

* All status counters must be read within the 1-second time window of the PMRST. If this is not the case, counter values will be l ost.

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Interface Description (continued)

General-Purpose I/O Bus (GPIO)

GPIO[3:0] are bidirectional pins. They can be configured individually as input or output by writing to the GPIO mode

and GPIO output configuration registers (addresses 0x0013, 0x0014, 0015; see register descriptions, page 152).

The value to be output is written into the GPIO output register (address 0x000F; see register descriptions,

page 150). To use the GPIO pins as outputs, set the GPIO output configuration bits (bits 8 and 0) to 1, and set the

GPIO mode bits GPIO[3:0]_DIRECTION_ I/O (address 0x0013, bits [3:0]) to 1.

The input value is read from the GPIO input register (address 0x000A; see register description, page148). GPIO

pins can also be used to generate an interrupt upon a change in value. An interrupt can be generated on either the

input level or edge, depending on the GPIO mode register. Figure 29 shows how the GPIO functions.

CORE REGISTERS

INTERRUPTS

GPIO INPUTS

3 2 1 0

0000

0001

0002

0003

0004

0005

DEVICE VERSION

DEVICE NAME =

TDAT042G5

GPIO OUTPUTS

0008 COMPOSITE INTERRUPTS

000A GPIO INPUTS

000C BLOCK INTERRUPT MASKS

POS.

EDGE

DET.

ACTIVE

DIRECTION

3 2 1 0 3 2 1 0

000E

000F

0010

0011

0012

0013

CORE RESETS

GPIO OUTPUTS

GPIO MODE

LEVEL EDGE

LINE PROVISIONING

CHANNEL CONTROL

LOOPBACK CONTROL

GPIO MODE

001F

SCRATCH

GPIO[3:0]

5-7058(F)r.6

Figure 29. GPIO Functionality

If a GPIO pin is an input, the logic value on the pin can be read from a software register. The GPIO pin can also be

programmed to generate a level-sensitive interrupt or a positive edge-triggered interrupt contributing to the external

interrupt pin.

If a GPIO pin is an output, the value provisioned will appear on the device pin immediately.

102

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Interface Description (continued)

Interrupts

Interrupt requests can be read from the composite interrupts register (0x0008; see register description, page 148).

There is also a corresponding block interrupt masks register (0x000C; see register description, page 149). Any

unmasked request will cause the INT pin to go low. GPIO interrupt functionality is shown in Figure 30.

CORE REGISTERS

0000

0001

0002

0003

0004

0005

DEVICE VERSION

DEVICE NAME =

TDAT042G5

PM INTERRUPT

(GPIO)

0008 COMPOSITE INTERRUPTS

000A GPIO INPUTS

000C BLOCK INTERRUPT MASKS

INTERRUPTS

UT DE

PT OH

000E

000F

0010

0011

0012

0013

CORE RESETS

GPIO OUTPUTS

LINE PROVISIONING

CHANNEL CONTROL

LOOPBACK CONTROL

GPIO MODE

BLOCK INTERRUPT MASKS

001F

SCRATCH

INT

5-7059(F)r.5

Figure 30. Interrupt Functionality

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Interface Description (continued)

Reset

If the reset pin RST (C7) is forced low, the software registers will be placed in their default powerup state. The

device will lose its previous state, and data path continuity will be lost. An internal 100 kΩ pull-up and a Schmitt-

trigger input is provided for this pin. Reset can be generated from software by writing 0x0005 to the core resets reg-

ister (0x000E; see register description on page 149 and timing on page 263).

Performance Monitor Reset (PMRST)

A 1 Hz clock (PMRST) is provided to all internal macrocells. This clock is used to control the 1-second binning of

coding violations (CVs) and alarms. The source of this clock is selectable from one of the three following sources:

^IThe PMRST pin (D7)

^IA software controllable register (0x000E; see register description on page 149)

^IAn internal 1-second counter (sourced from the 77.76 MHz transmit clock).

This is configured by the line provisioning register (address 0x0010). When under software control, writing 0x0080

to core resets register (address 0x000E) will generate a PMRSTX pulse.

POS.

EDGE

DET.

CORE REGISTERS

INTERRUPTS

0000

0001

0002

0003

0004

0005

DEVICE VERSION

CORE RESETS

R R R

DEVICE NAME =

TDAT042G5

1 SEC.

COUNT

0008 COMPOSITE INTERRUPTS

000A GPIO INPUTS

000C BLOCK INTERRUPT MASKS

000E

000F

0010

0011

0012

0013

CORE RESETS

GPIO OUTPUTS

LINE PROVISIONING

LINE EQ./UNEQ.

P M S

48 12 12 12 12

6 5 4 3 2 1 0

LINE PROVISIONING

CHANNEL CONTROL

LOOPBACK CONTROL

GPIO MODE

15 14 13 12 11 10 9

LOOPBACKS L B LB

8 7 6 5 4 3 2 1 0

001F

SCRATCH

PMRST I/O CONTROL

DELTA

RST

PMRST

5-7060(F)r.4

Figure 31. Miscellaneous Functionality

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Interface Description (continued)

Performance Monitor Reset (PMRST) (continued)

Address 0x0010, bits 8 and 9 of the core register set defines the mode of operation for PMRST. Address 0x000E,

bit 7 provides the software-controllable reset function (see Register Maps section, page 112). When this bit is set

to 1, the PMRST signal goes high. The register will automatically be reset to 0, and the PMRST signal will go low

after 500 ms.

Table 32. PMRST Provisioning

Core Register

Description

ADDR 0x0010, Bits 9, 8

PMRST comes from external pin (1 Hz, 50% duty cycle signal).

PMRST comes from internal 1-second counter (1 Hz, 50% duty cycle signal).

Writing a logic 1 to the PMRST bit (core register 0x000E, bit 7) in this mode will

reset the counter so that a 0→1 transition occurs on the PMRST within 10 clock

cycles of the 77.76 MHz clock.

PMRST is software controlled. Writing a logic 1 to the PMRST bit (core register

0x000E, bit 7) will cause a 0→1 transition on the internal PMRST signal. This

pulse will be high for 100 cycles of the 77.76 MHz clock and low for 100 cycles of

the 77.76 MHz clock. Writing the PMRST bit to a logic 1 during this 200 clock

cycle interval will have no effect (2.57 µs). The PMRST rising edge must occur

within 10 clock cycles of writing the PMRST bit.

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Interface Description (continued)

Loopback Operation

Figure 32 illustrates the different types of loopback provided in the device. Loopback is controlled by core register

0x0012, loopback control (see register description on page 151).

SINK

FAR

END

FACILITY

TERMINAL

NEAR

END

FACILITY

(OPTICS)

CONT

TERMINAL B

TERMINAL A

5-7061(F)r.4

Figure 32. Loopback Operation

In the following description, only the data path from Terminal A to B is discussed, but the same terms apply to the

reverse direction.

Near-End Loopback

The packet/cell payload is looped back to the data source (Layer 2 device) as soon as it crosses the Layer 1 to

Layer 2 boundary (UTOPIA block).

Far-End Loopback

The packet/cell payload is looped back to the facility (optical) data source as soon as it enters the UTOPIA block of

Terminal B. The data does not enter the Layer 2 device. The total delay from receive data input to transmit data

output in far-end loopback (FELB) mode is approximately 2 µs.

Terminal Loopback

The SONET/SDH signal is looped back at the terminal (line interface) block, and is returned to the Layer 2 device.

For terminal loopback of UTOPIA ports B, C, or D to function, UTOPIA port A must be provisioned for terminal loop-

back. This is because only the Tx clock from port A is used in terminal loopback mode.

Facility Loopback

The facility (optical) data signal is looped back to the facility as soon as it enters the Terminal B line interface block.

SONET facility loopback is only available in STS-3/STM-1 and STS-12/STM-4 modes.

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Interface Description (continued)

System Interfaces

ATM Interfaces

TxCLK[A]

TxENB[A]

TxPA[A]

TxCLK

TxENB

TxCLAV

TxSZ[A]

TxDATA[15:0][A]

TxPRTY[A]

TxSOP/C[A]

TxEOP[A]

TxDATA[15:0]

TxPRTY

TxSOC

TxERR[A]

ATM DEVICE

RxCLK[A]*

RxENB[A]

RxPA[A]

RxCLK

RxENB

RxCLAV

TDAT042G5

RxSZ[A]

RxDATA[15:0][A]

RxPRTY[A]

RxSOP/C[A]

RxEOP[A]

RxDATA[15:0]

RxPRTY

RxSOC

RxERR[A]

†

[B]

DEVICE #2

DEVICE #3

†

[B]

†

[C]

†

[C]

†

[D]

†

DEVICE #4

[D]

5-6750(F)r.3

* RxCLK may be either sunk or sourced, depending upon the application.

†The transmit and receive signals for channels B, C, and D of the TDAT042G5 device are mapped to the remaining three ATM devices as

shown above.

Figure 33. Quad ATM UTOPIA 2

For the quadATM UTOPIA 3 eight-bit interface mode, where theATM device has only an 8-bit interface, the

RxDATA[15:0] and TxDATA[15:0] words are replaced with RxDATA[15:8] and TxDATA[15:8] in each channel of the

TDAT042G5. This is shown in the following table.

Table 33. Quad ATM UTOPIA 3 Interface

TDAT042G5 Channel

ATM Device

TxDATA[15:8][A]

RxDATA[15:8][A]

TxDATA[7:0]

RxDATA[7:0]

Same signals for channel [B]

Same signals for channel [C]

Same signals for channel [D]

Same signals for device #2

Same signals for device #3

Same signals for device #4

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Interface Description (continued)

System Interfaces (continued)

ATM Interfaces (continued)

TX CLOCK

TxCLK[A]

TxENB[A]

TxPA[A]

TxCLK

TxENB

TxCLAV

TxSZ[A:B]

TxDATA[15:0][A:B]

TxPRTY[A]

TxDATA[31:0]

TxPRTY

TxSOP/C[A]

TxEOP[A]

TxSOC

RX CLOCK

TxERR[A]

TDAT042G5

ATM DEVICE

RxCLK[A]*

RxENB[A]

RxPA[A]

RxCLK

RxENB

RxCLAV

RxSZ[A]

RxDATA[15:0][A:B]

RxPRTY[A]

RxDATA[31:0]

RxPRTY

RxSOP/C[A]

RxSOC

RxEOP[A]

RxERR[A]

5-6740(F)r.5

* RxCLK may be either sunk or sourced, depending upon the application.

Figure 34. Single ATM UTOPIA 3

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Interface Description (continued)

System Interfaces (continued)

POS Interfaces

TxCLK[A]

TFCLK

TxENB[A]

TxPA[A]

TxSZ[A]

TENB

TPA

TMOD

TDAT[15:0]

TPRTY

TSOP

TxDATA[15:0][A]

TxPRTY[A]

TxSOP/C[A]

TxEOP[A]

TEOP

TERR

TxERR[A]

POS DEVICE

RxCLK[A]*

RxENB[A]

RxPA[A]

RFCLK

RENB

RPA

TDAT042G5

RxSZ[A]

RMOD

RDAT[15:0]

RPRTY

RSOP

RxDATA[15:0][A]

RxPRTY[A]

RxSOP/C[A]

RxEOP[A]

REOP

RxERR[A]

RERR

†

[B]

DEVICE #2

†

[C]

†

DEVICE #3

DEVICE #4

[C]

†

[D]

†

[D]

5-6741(F)r.7

* RxCLK may be either sunk or sourced, depending upon the application.

†The transmit and receive signals for channels B, C, and D of the TDAT042G5 device are mapped to the remaining three POS devices as

shown above.

Figure 35. Quad POS UTOPIA 2

For the quad POS UTOPIA 3 eight-bit interface mode, where the POS device has only an 8-bit interface, the

RxDATA and TxDATA words are replaced with RxDATA[15:8] and TxDATA[15:8] in each channel of the

TDAT042G5. This is shown in the following table.

Table 34. Quad POS UTOPIA 3 Interface

TDAT042G5 Channel

POS Device

TxDATA[15:8][A]

RxDATA[15:8][A]

TxDATA[7:0]

RxDATA[7:0]

Same signals for channel [B]

Same signals for channel [C]

Same signals for channel [D]

Same signals for device #2

Same signals for device #3

Same signals for device #4

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Interface Description (continued)

System Interfaces (continued)

POS Interfaces (continued)

TX CLOCK

TxCLK[A]

TxENB[A]

TFCLK

TENB

TxPA[A]

TPA

TxSZ[A:B]

TxDATA[15:0][A:B]

TxPRTY[A]

TMOD[1:0]

TDAT[31:0]

TPRTY

TSOP

TxSOP/C[A]

TxEOP[A]

TEOP

TERR

TxERR[A]

RX CLOCK

TDAT042G5

POS DEVICE

RxCLK[A/B]*

RxENB[A]

RFCLK

RENB

RPA

RxPA[A]

RxSZ[A]

RMOD[1:0]

RDAT[31:0]

RPRTY

RSOP

RxDATA[15:0][A:B]

RxPRTY[A]

RxSOP/C[A]

RxEOP[A]

REOP

RxERR[A]

RERR

5-6743(F)r.7

* RxCLK may be either sunk or sourced, depending upon the application.

Figure 36. Single POS UTOPIA 3

TX CLOCK

TxCLK[A]

TxENB[A]

CLK

ENB

TxPA[A]

TxSZ[A:B]

TxDATA[15:0][A:B]

TxPRTY[A]

TxSOP/C[A]

TxEOP[A]

CLAV[0]

MOD[1:0]

DAT[31:0]

PRTY

SOP

EOP

ERR

TxERR[A]

TxADDR[4:0]

TxPA[B:D]

TxADDR[12:0]

TxCLAV[3:1]

RX CLOCK

TDAT042G5

LAYER DEVICE

RxCLK[A:B]*

RxENB[A]

CLK

ENB

CLAV[0]

RxPA[A]

RxSZ[A]

MOD[1:0]

DAT[31:0]

XPRTY

RxDATA[15:0][A:B]

RxPRTY[A]

RxSOP/C[A]

RxEOP[A]

SOP

EOP

RxERR[A]

RxADDR[4:0]

RxPA[B:D]

^XERR

ADDR[12:0]

CLAV[3:1]

5-6743(F).br.2

* RxCLK may be either sunk or sourced, depending upon the application.

Figure 37. 32-bit MPHY UTOPIA 3

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through 13 must be 0. Bits 12 through 9 map to the major functional blocks as shown in Table 35. The usable

address space is also shown in Table 35.

Table 35. Register Address Space

Functional Block

Address Range (Hex)

Core

0x0000—0x001F

0x0200—0x0226

0x0400—0x05C2

0x0800—0x0AF8

0x1000—0x1607

OHP

Table 36—Table 40 are the register maps. Details of the register functions are given in the following register

description tables. Note that the usable register address space is not contiguous. Register addresses not specifi-

cally identified in the following tables are reserved and must not be addressed, i.e., written or read. Registers and

bits that are reserved must not be written or must be written to the indicated default value. In Table 36—Table 40,

the registers may be read only (RO), read/write (R/W), write only (WO), or clear-on-read or clear-on-write

(COR/W).

The core registers must be written prior to provisioning any other registers (1) to establish the internal clock rates

for the device, and (2) because writing to certain core registers resets the remainder of the device. Certain clocks

must be present to read/write registers prior to provisioning the device.

One of the following clocks must be present prior to provisioning to enable register access.

^ITxCKP and TxCKN

^IMPU clock (microprocessor interface synchronous mode only)

Provisioning must be implemented in the following sequence.

^ICore register 0x0010 (mode) must be provisioned first

^ICore register 0x0011 (channel [A—D] control) second

^IRemainder of the core registers must then be provisioned (order does not matter)

It is recommended, but not required, that the remainder of the device be provisioned in the following order.

^IOHP, PT, and DE blocks (order does not matter)

^IUT block to turn on the data source to the master and slave

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Core Registers

This section gives a brief description of each register bit and its functionality. All algorithms are described in the

main text of the document. The abbreviations after each register indicate if the register is read only (RO), read/

write (R/W), write only (WO), or clear-on-read or clear-on-write (COR/W).

Required Provisioning Sequence and Clocks

0x indicates a hexadecimal value in the Reset Default column. Otherwise, the entry is binary. This is true for every

Table 41. Register 0x0000: Device Version (RO)

Reset default of register = 0x0100.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0000

15—8 DEVICE_VERSION[7:0] Device Version Number. Device version register will

0x01¹

change each time the device is changed.

7—0

—

Reserved.

0x00

1. 0x02 for version 1A.

Table 42. Registers 0x0001—0x0005: Device Name (RO)

Reset default of each register is shown below.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0001

0002

0003

0004

0005

15—0

ASCII_NAME_TD

ASCII_NAME_AT

ASCII_NAME_04

ASCII_NAME_2G

ASCII_NAME_5CR

Device ASCII Name. Value = T, D.

Device ASCII Name. Value = A, T.

Device ASCII Name. Value = 0, 4.

Device ASCII Name. Value = 2, G.

Device ASCII Name. Value = 5, CR.

0x5444

0x4154

0x3034

0x3247

0x350D

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Core Registers (continued)

Table 43. Register 0x0008: Composite Interrupts (RO or COR/W)

Reset default of register = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0008

PMRSTI

Performance Monitor Reset Interrupt. Active-high

signal indicating a 1 second event has occurred.

This bit is COR/W.

14—12

11—8

—

Reserved. These bits must be written to their reset

default value (000).

000

0x0

GPIO[3:0]I

General-Purpose Interrupt. Signal indicating the

associated input is active. When the GPIO are out-

puts, this signal will be forced low. These interrupts

are COR/W when the interrupt is programmed to

the positive edge mode; otherwise, this is a read-

only (RO) location.

UTI

DEI

UTOPIA Composite Interrupt. Active-high signal

indicating an unmasked delta or event is active in

the UTOPIA block. This bit is RO.

Data Engine Composite Interrupt. Active-high

signal indicating an unmasked delta or event is

active in the data engine block. This bit is RO.

5—2

—

Reserved. These bits must be written to their reset

default value (0000).

0000

PTI

Path Terminator Composite Interrupt. Active-high

signal indicating an unmasked delta or event is

active in the path terminator block. This bit is RO.

OHPI

Overhead Processor Composite Interrupt.

Active-high signal indicating an unmasked delta or

event is active in the overhead processor block.

This bit is RO.

Table 44. Register 0x000A: GPIO Input (RO)

Reset default of register = 0x000x (x not determined).

Address

(Hex)

Bit #

Name

Function

Reset

Default

000A

15—4

3—0

—

Reserved. These bits must be written to their reset 0x000

default value (0x000).

GPIO[3:0]_INPUT_VALUE General-Purpose Input Value. These are the logi-

cal values of the GPIO[3:0] I/O pins.

Value

148

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Core Registers (continued)

Table 45. Register 0x000C: Block Interrupt Masks (R/W)

Reset default of register = 0xFFFF.

Address

(Hex)

Bit #

Name

Function

Reset

Default

000C

PMRSTM

Performance Monitor Reset Mask. When set to 1,

the associated composite interrupt bit will be inhib-

ited (masked) from contributing to the interrupt pin

(INT).

14—12

11—8

—

Reserved. These bits must be written to their reset

default value (111).

General-Purpose Interrupt Mask. When set to 1,

the associated composite interrupt bits will be inhib-

ited (masked) from contributing to the interrupt pin

(INT).

111

0xF

GPIO[3:0]IM

UTIM

DEIM

UTOPIA Composite Interrupt Mask. When set to

1, the associated composite interrupt bit will be

inhibited (masked) from contributing to the interrupt

pin (INT).

Data Engine Composite Interrupt Mask. When

set to 1, the associated composite interrupt bit will

be inhibited (masked) from contributing to the inter-

rupt pin (INT).

5—2

—

Reserved. These bits must be written to their reset

default value (1111).

Path Terminator Composite Interrupt Mask.

When set to 1, the associated composite interrupt

bit will be inhibited (masked) from contributing to

the interrupt pin (INT).

1111

PTIM

OHPIM

Overhead Processor Composite Interrupt Mask.

When set to 1, the associated composite interrupt

bit will be inhibited (masked) from contributing to

the interrupt pin (INT).

Table 46. Register 0x000E: Core Resets (WO)

Address

(Hex)

Bit #

Name

Function

Reset

Default

000E

15—8

—

PMRST

Reserved.

Performance Monitor Reset. When this bit is set

to 1, the PMRST signal goes high. The register will

automatically be reset to 0, and the PMRST signal

will go low after 500 ms.

6—3

2—0

—

SWRST

Reserved.

Software Reset. When a binary value of 101 is

written to this register, it will create a software reset

of the device. This reset has the same effect as the

hardware reset. All microprocessor registers are

reset to their default states, and all internal data

path state machines are reset.

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Core Registers (continued)

Table 47. Register 0x000F: GPIO Output (R/W)

Reset default of register = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

000F

15—4

3—0

—

Reserved. These bits must be written to their reset

default value (0x000).

0x000

GPIO[3:0]_OUTPUT_VALUE

General-Purpose Output Values. The value writ-

0x0

ten into these bits will appear on the GPIO[3:0] pins.

Provisioning Registers

Table 48. Register 0x0010: Line Provisioning/Mode (R/W)

Reset default of register = 0x1070.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0010

15—13

—

Reserved. These bits must be written to their reset

000

default value (000).

POF_POS

Packet/ATM Over Fiber/SONET. 0 = packet or ATM

over fiber (POF); 1 = packet or ATM over SONET

(POS).

11—10

9—8

—

Reserved. These bits must be written to their reset

default value (00).

PMMODE[1:0]

Performance Monitoring Mode.

00 or 10 = PMRST comes from external pin.

01 = PMRST comes from internal 1-second counter.

11 = PMRST is software controlled.

SDH/SONET

COR/W

SDH or SONET Mode. 1 = SDH; 0 = SONET.

Clear-on-Read or Clear-on-Write Control. This bit

sets the functionality of the COR/W registers.

1 = COR. Clear on read; read register to clear.

0 = COW. Clear on write; write 1 to clear.

COW mode will clear bits to which a 1 is written. Bits

written to 0 are not cleared.

PLL_MODE

PLL Mode. Control for STS-48/STM-16 mode only.

This bit controls the transmit line clock PLL. For

STS-48/STM-16 contra-clocking mode, this PLL

must be active, i.e., the bit = 0.

1 = PLL off (inactive)

0 = PLL on (active)

STS48

STS-48/STM-16 Control. 1 = STS-48/STM-16

mode; 0 = STS-3/STS-12 (STM-1/STM-4) mode.

3—0

STS12[A—D]

STS-12/STS-3 (STM-4/STM-1) Mode Control.

The only values permitted are the following:

1111 = STS-12/STM-4

0x0

0000 = STS-3/STM-1

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Core Registers (continued)

Provisioning Registers (continued)

Table 49. Register 0x0011: Channel (A—D) Control (R/W)

Reset default of register = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0011

EQ_CH_A

Equip Channel A. 1 = enable; 0 = disable, i.e., turns off

clock in Rx direction, except in the STS-48/STM-16

mode. This function is valid only for STS-12/STM-4 and

STS-3/STM-1 modes (no effect in Tx direction).

14—12

—

Reserved. These bits must be written to their reset

default value (000).

000

EQ_CH_B

Equip Channel B. 1 = enable; 0 = disable, i.e., turns off

clock in Rx direction, except in the STS-48/STM-16

mode. This function is valid only for STS-12/STM-4 and

STS-3/STM-1 modes (no effect in Tx direction).

10—8

—

Reserved. These bits must be written to their reset

default value (000).

000

EQ_CH_C

Equip Channel C. 1 = enable; 0 = disable, i.e., turns off

clock in Rx direction, except in the STS-48/STM-16

mode. This function is valid only for STS-12/STM-4 and

STS-3/STM-1 modes (no effect in Tx direction).

6—4

—

Reserved. These bits must be written to their reset

default value (000).

000

EQ_CH_D

Equip Channel D. 1 = enable; 0 = disable, i.e., turns off

clock in Rx direction, except in the STS-48/STM-16

mode. This function is valid only for STS-12/STM-4 and

OSTS-3/STM-1 modes (no effect in Tx direction).

2—0

—

Reserved. These bits must be written to their reset

000

default value (000).

Table 50. Register 0x0012: Loopback Control (R/W)

Reset default of register = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0012

15—12

11—8

7—4

LOOPBACK[3:0]_

CH_A

Loopback Control. Only the following combinations

are valid:

0x0

LOOPBACK[3:0]_

CH_B

0000 = no loopbacks

0001 = SONET facility loopback

0010 = SONET terminal loopback

0100 = UTOPIA far-end loopback

1000 = UTOPIA near-end loopback

LOOPBACK[3:0]_

CH_C

3—0

LOOPBACK[3:0]_

CH_D

SONET facility loopback is only available in STS-3/

STM-1 and STS-12/STM-4 modes.

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Core Registers (continued)

Provisioning Registers (continued)

Table 51. Register 0x0013: GPIO Mode (R/W)

Reset default of register = 0x0000.

Address Bit #

(Hex)

Name

Function

Reset

Default

0013

PMRST_I/O_CTRL

PMRST I/O Control. This bit is set to 1 to make

PMRST an output.

14—12

—

Reserved. These bits must be written to their reset

default value (000).

000

0x0

11—8 GPIO[3:0]_INTERRUPT_ GPIO Interrupt Active State.

ACTIVE_H/L 0 = report received value unchanged (level = input pin

value, positive edge = 1 when signal rises).

1 = invert received value (level = invert input pin value,

positive edge = 0 when detected).

7—4 GPIO[3:0]_INTERRUPT_ GPIO Interrupt Type. 0 = positive edge; 1 = level.

0x0

LEVEL/EDGE

3—0

GPIO[3:0]_DIRECTION_ GPIO Direction Control. 0 = input; 1 = output.

I/O

Table 52. Registers 0x0014, 0x0015: GPIO Output Configuration

Reset default of registers = 0x0000.

Address Bit #

(Hex)

Name

Function

Reset

Default

0014

—

GPIO[1:0]_OC

GPIO[1:0] Output Configuration.

0x0000

15—9

—

Reserved. These bits must be written to their reset

default value (0000000).

0000

000

7—1

GPIO[1]_OC

—

GPIO[1] Output Configuration. Set this bit to 1 to

activate the output of the corresponding GPIO pin.

Reserved. These bits must be written to their reset

default value (0000000).

0000

000

GPIO[0]_OC

GPIO[0] Output Configuration. Set this bit to 1 to

activate the output of the corresponding GPIO pin.

0015

—

GPIO[3:2]_OC

GPIO[3:2] Output Configuration.

0x0000

15—9

—

Reserved. These bits must be written to their reset

default value (0000000).

0000

000

7—1

GPIO[3]_OC

—

GPIO[3] Output Configuration. Set this bit to 1 to

activate the output of the corresponding GPIO pin.

Reserved. These bits must be written to their reset

default value (0000000).

0000

000

GPIO[2]_OC

GPIO[2] Output Configuration. Set this bit to 1 to

activate the output of the corresponding GPIO pin.

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Core Registers (continued)

Provisioning Registers (continued)

Table 53. Register 0x001F: Scratch (R/W)

Reset default of register = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

001F

15—0 CORE_SCRATCH[15:0] Core Scratch Register. A read/write register used to

verify functionality of the microprocessor interface. No

internal action will occur when written data is written to

this location.

0x0000

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UT Registers

This section gives a brief description of each register bit and its functionality. All algorithms are described in the

main text of the document. The abbreviations after each register indicate if the register is read only (RO), read/write

(R/W), write only (WO), or clear-on-read or clear-on-write (COR/W).

0x indicates a hexadecimal value in the Reset Default column. Otherwise, the entry is binary. This is true for every

Version Control

Table 54. Register 0x0200: UT Macrocell Version Number (RO)

Reset default of register = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0200

15—8

7—0

—

Reserved. These bits must be written to their

reset default value (0x00).

0x00

UT_VERSION[7:0]

UT Macrocell Version Number. The version of

the macrocell will increment each time a

change occurs to the macrocell functionality.

0x00

Interrupt

Table 55. Register 0x0201: UT Interrupt (RO)

Reset default of register = 0x0000.

Note: These registers are cleared by accessing registers 0x0202, 0x0203, 0x0204, 0x0205.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0201

15—4

—

Reserved. These bits must be written to their

0x000

reset default value (0x000).

UT_INT[D]

UT Interrupt for Channel D. If this bit is set to

1, it indicates one of the interrupt conditions for

channel D occurred.

0x0

UT_INT[C]

UT_INT[B]

UT_INT[A]

UT Interrupt for Channel C. If this bit is set to

1, it indicates one of the interrupt conditions for

channel C occurred.

UT Interrupt for Channel B. If this bit is set to

1, it indicates one of the interrupt conditions for

channel B occurred.

UT Interrupt for Channel A. If this bit is set to

1, it indicates one of the interrupt conditions for

channel A occurred.

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UT Registers (continued)

Delta and Event Parameters (COR)

Table 56. Registers 0x0202, 0x0203, 0x0204, 0x0205: Channel [A—D] (COR)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0202, 0203, 15—4

—

Reserved. These bits must be written to their

0x000

0204, 0205

reset default value (0x000).

FIFO_OVERFLOW_

FIFO OverflowTransmit Channel [A—D]. If

set, indicates that an overflow occurred in the

Tx FIFO of channel [A—D].

0x0

Tx[A—D]

FIFO_UNDERFLOW_

FIFO Underflow Transmit Channel [A—D]. If

set, indicates that an underflow occurred in the

Tx FIFO of channel [A—D].

Tx[A—D]

FIFO_OVERFLOW_

FIFO Overflow Receive Channel [A—D]. If

set, indicates that an overflow occurred in the

Rx FIFO of channel [A—D].

Rx[A—D]

PARITY_ERROR_

Parity Error Transmit Channel [A—D]. If set,

indicates that a parity error was detected on the

Tx channel of channel [A—D].

Tx[A—D]

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UT Registers (continued)

Interrupt Mask Parameters (R/W)

Table 57. Register 0x0206: Interrupt Mask (R/W)

Reset default of register = 0x000F.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0206

15—4

—

Reserved. These bits must be written to their

0x000

reset default value (0x000).

INTM[D]

INTM[C]

INTM[B]

INTM[A]

Interrupt Mask D. If set to 1, masks any inter-

rupts from channel D.

0xF

Interrupt Mask C. If set to 1, masks any inter-

rupts from channel C.

Interrupt Mask B. If set to 1, masks any inter-

rupts from channel B.

Interrupt Mask A. If set to 1, masks any inter-

rupts from channel A.

Table 58. Registers 0x0207, 0x0208, 0x0209, 0x020A: Interrupt Mask—Channel [A—D] (R/W)

Reset default of registers = 0x000F.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0207, 0208, 15—4

—

Reserved. These bits must be written to their

0x000

0209, 020A

reset default value (0x000).

FIFO_OVERFLOW_Tx_

FIFO Overflow Transmit Mask [A—D]. If set,

masks this interrupt from setting Int[A—D].

0xF

MASK[A—D]

FIFO_UNDERFLOW_Tx_

FIFO Underflow Transmit Mask [A—D]. If set,

masks this interrupt from setting Int[A—D].

MASK[A—D]

FIFO_OVERFLOW_Rx_

FIFO Overflow Receive Mask [A—D]. If set,

masks this interrupt from setting Int[A—D].

MASK[A—D]

PARITY_ERROR_Tx_

Parity Error Transmit Mask [A—D]. If set,

masks this interrupt from setting Int[A—D].

MASK[A—D]

Error Counters in PMRST Mode (RO)

Table 59. Register 0x020B: Channel [A—D] Error Count in PMRST Mode (RO)

Reset default of register = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

020B—020E 15—0

PMRST_PECTx[A—D] PMRST Parity Error Count Transmit

Channel [A—D]. Counts the number of parity

errors that occur for Tx channel [A—D], based

upon the PMRST interval.

0x0000

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UT Registers (continued)

UT Provisioning Registers (R/W)

The fields of the UT provisioning registers in Table 61—Table 64 are summarized in Table 60. Following the table

are the provisioning registers for the four channels.

Note:The default value depends on the channel. Defaults are as follows:

Channel A = 00000

Channel B = 00001

Channel C = 00010

Channel D = 00011

Table 60. Fields of the Provisioning Registers

Field Name

Function

Bit Value

Default

POLLING_ENB_Rx

POLLING_ENB_Tx

Enabled

Disabled

Bit 15 = 1

Bit 15 = 0

Bits [12:8]

RxADDR_[4:0]

TxADDR_[4:0]

MPHY AddressValue

See note above.

CLOCK_MODE_Rx

Source

Sink

Bit 6 = 1

Bit 6 =0

PARITY_Rx

PARITY_Tx

Odd

Bit 5 = 1

Even

Bit 5 = 0

ATM_SIZE_Rx

ATM_SIZE_Tx

52 Bytes

53 Bytes

ATM Cells

Packets

Disabled (Idle)*

Bit 4 = 1

Bit 4 = 0

TRAFFIC_TYPE_Rx

TRAFFIC_TYPE_Tx

Bit 3 = 1

Bit 3 = 0

UTOPIA_MODE_Rx

UTOPIA_MODE_Tx

Bits[2:0] = 000

Bits[2:0] = 001

Bits[2:0] = 010

Bits[2:0] = 011

Bits[2:0] = 100

Bits[2:0] = 101

Bits[2:0] = 110

Bits[2:0] = 111

000

U2+

U3, 8-bit

U3, 32-bit

U3+, 8-bit

U3+, 32-bit

Invalid

*The value 000 for UTOPIA_MODE_Rx bits places the corresponding UTOPIA outputs in the high-impedance state.

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UT Registers (continued)

UT Provisioning Registers (R/W) (continued)

Table 61. Registers 0x020F, 0x0213, 0x0217, 0x021B: Channel [A—D] Receive Provisioning Register (R/W)

Reset default of register 0x020F = 0x0020.

Reset default of register 0x0213 = 0x0120.

Reset default of register 0x0217 = 0x0220.

Reset default of register 0x021B = 0x0320.

Address

(Hex)

Bit #

Name

Function

Reset

Default

020F, 0213,

0217, 021B

POLLING_ENB_Rx

Polling Enable Receive Channel [A—D]. If

set to 1, receive polling mode is enabled.

[A—D]

14—13

12—8

—

Reserved. These bits must be written to their

reset default value (00).

RxADDR_A[4:0]

RxADDR_B[4:0]

RxADDR_C[4:0]

RxADDR_D[4:0]

—

Polling Receive Address Channel [A—D].

Receive polling address.

00000

00001

00010

00011

Reserved. This bit must be written to its reset

default value (0).

CLOCK_MODE_Rx

Clock Mode Receive Channel [A—D].

Defines if the RxCLK[A—D] is sourced or sunk.

If this bit = 1, the clock is sourced, and then

(1) the corresponding Tx clock is used as

RxCLK[A—D], and (2) this clock is also sent out

of the device via RxCLK[A—D].

[A—D]

If this bit = 0, CLOCK_MODE_Rx[A—D] is

sunk, and then RxCLK[A—D] acts as an input.

Default is sink.

PARITY_Rx[A—D]

Parity Receive Channel [A—D]. Defines if odd

(bit = 1) or even (bit = 0) parity is generated for

the data transmitted across the UTOPIA PHY

Rx interface. Default is odd.

ATM_SIZE_Rx[A—D]

ATM Packet Size Receive Channel [A—D].

Defines how many bytes are received per ATM

cell. Default is 53 bytes. Valid only when traffic

type is ATM cells.

Page 86 and page 87 give details of the func-

tion of this bit.

0 = standard 53-byte (also 54-byte and 56-byte)

ATM cell modes.

1 = 52-byte ATM cell mode (HEC omitted).

TRAFFIC_TYPE_Rx

Traffic Type Receive Channel [A—D]. Config-

ures channel to receive either ATM cells or

packets.

[A—D]

Bit Value Traffic Type

packets (default)

ATM cells

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Data Sheet

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UT Registers (continued)

UT Provisioning Registers (R/W) (continued)

Table 61. Registers 0x020F, 0x0213, 0x0217, 0x021B: Channel [A—D] Receive Provisioning Register (R/W)

(continued)

Reset default of register 0x020F = 0x0020.

Reset default of register 0x0213 = 0x0120.

Reset default of register 0x0217 = 0x0220.

Reset default of register 0x021B = 0x0320.

Address

(Hex)

Bit #

Name

Function

Reset

Default

020F, 0213, 2—0

0217, 021B

UTOPIA_MODE_Rx

UTOPIA Mode Receive Channel [A—D]. Con-

figures the Rx channel mode.

000

[A—D][2:0]

Mode

Bit Value

disabled (idle)* bits[2:0] = 000

U2+

U3, 8-bit

U3, 32-bit

U3+, 8-bit

U3+, 32-bit

invalid

bits[2:0] = 001

bits[2:0] = 010

bits[2:0] = 011

bits[2:0] = 100

bits[2:0] = 101

bits[2:0] = 110

bits[2:0] = 111

U3 configuration also requires the appropriate

setting of register 0x0225 (PA response) to be

set for a two-cycle response.

*The value 000 for these bits places the corresponding UTOPIA outputs in the high-impedance state.

Table 62. Registers 0x0210, 0x0214, 0x0218, 0x021C: Channel [A—D]Transmit Provisioning Register (R/W)

Reset default of register 0x0210 = 0x0000.

Reset default of register 0x0214 = 0x0120.

Reset default of register 0x0218 = 0x0220.

Reset default of register 0x021C = 0x0320.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0210, 0214,

0218, 021C

POLLING_ENB_Tx

Polling Enable Transmit Channel [A—D]. If

set, transmit polling mode is enabled.

[A—D]

14—13

12—8

—

Reserved. These bits must be written to their

reset default value (00).

TxADDR_A[4:0]

TxADDR_B[4:0]

TxADDR_C[4:0]

TxADDR_D[4:0]

—

Polling Transmit Address Channel [A—D].

Transmit polling address.

00000

00001

00010

00011

7—6

Reserved. These bits must be written to their

reset default value (00).

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May 2001

UT Registers (continued)

UT Provisioning Registers (R/W) (continued)

Table 62. Registers 0x0210, 0x0214, 0x0218, 0x021C: Channel [A—D] Transmit Provisioning Register (R/W)

(continued)

Reset default of register 0x0210 = 0x0000.

Reset default of register 0x0214 = 0x0120.

Reset default of register 0x0218 = 0x0220.

Reset default of register 0x021C = 0x0320.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0210, 0214,

0218, 021C

PARITY_Tx[A]

Parity Transmit Channel [A—D]. Defines if

odd (bit = 1) or even (bit = 0) parity is generated

for the data transmitted across the UTOPIA

PHY Tx interface. Default is even for channel A

and odd for channels B, C, and D.

PARITY_Tx[B—D]

ATM_SIZE_Tx[A—D]

ATM Packet Size Transmit Channel [A—D].

Defines how many bytes are transmitted per

ATM cell. Default is 53 bytes. Valid only when

traffic type is ATM cells.

Page 86 and page 87 give details of the func-

tion of this bit.

0 = standard 53-byte (also 54-byte and 56-byte)

ATM cell modes.

1 = 52-byte ATM cell mode (HEC omitted).

TRAFFIC_TYPE_Tx

Traffic Type Transmit Channel [A—D]. Con-

figures channel to transmit either ATM cells or

packets.

[A—D]

Bit Value Traffic Type

packets (default)

ATM cells

2—0

UTOPIA_MODE_Tx

UTOPIA Mode Transmit Channel [A—D].

000

[A—D][2:0]

Configures the Tx channel mode.

Mode

Bit Value

disabled (idle) bits[2:0] = 000

U2+

bits[2:0] = 001

bits[2:0] = 010

bits[2:0] = 011

bits[2:0] = 100

bits[2:0] = 101

bits[2:0] = 110

bits[2:0] = 111

U3, 8-bit

U3, 32-bit

U3+, 8-bit

U3+, 32-bit

invalid

U3 configuration also requires appropriate set-

ting of register 0x0225 (PA response) to be set

for a two-cycle response.

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UT Registers (continued)

UT Provisioning Registers (R/W) (continued)

Table 63. Registers 0x0211, 0x0215, 0x0219, 0x021D: Channel [A—D] Ingress Provisioning Register (R/W)

Reset default of registers = 0x361F.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0211, 0215, 15—14

—

Reserved. These bits must be written to their

reset default value (00).

0219, 021D

13—8 INGRESS_WATERMARK Ingress Watermark High for Channel

110110

_HIGH_[A—D][6:0]

[A—D]. Defines threshold before which over-

flow is detected causing a head of FIFO dis-

card; data in the receive FIFO will be discarded

down to the next start of packet/cell.

7—6

—

Reserved. These bits must be written to their

reset default value (00).

5—0 INGRESS_WATERMARK Ingress Watermark Low for Channel [A—D].

011111

_LOW_[A—D][6:0]

Defines how many words must be stored in the

ingress FIFO before transmission out of the

UTOPIA port, if an end of packet is not

received.

Table 64. Registers 0x0212, 0x0216, 0x021A, 0x021E: Channel [A—D] Egress Provisioning Register (R/W)

Reset default of registers = 0x361F.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0212, 0216, 15—14

—

Reserved. These bits must be written to their

021A, 021E

reset default value (00).

13—8 EGRESS_WATERMARK_ Egress Watermark High for Channel [A—D].

110110

HIGH_[A—D][6:0]

Defines how many words can be stored into the

egress FIFO before backpressure is applied to

the UTOPIA PHY Tx port to stop acceptance of

more traffic. Default value is set for packet

transfer. For ATM transfer, the value should be

configured as 0x29. For packet mode, this value

depends upon the specific user-interface char-

acteristics. The default value (110110) will work

for packet mode.

7—6

—

Reserved. These bits must be written to their

reset default value (00).

5—0 EGRESS_WATERMARK_ Egress Watermark Low for Channel [A—D].

011111

LOW_[A—D][6:0]

Defines how many words must be stored in the

egress FIFO before transmission to the data

engine, if an end of packet is not received.

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UT Registers (continued)

Reset Register (R/W)

Table 65. Register 0x021F: Reset Register (R/W)

Reset default of register = 0x00FF.

Address

(Hex)

Bit #

Name

Function

Reset

Default

021F

—

UT_ARST

UTOPIA Asynchronous Reset. Active-high

signal. This must be the last signal written to

the UTOPIA interface during configuration and

must be written to the value 0x00 to enable the

particular channels.

0x00FF

15—8

—

Reserved. These bits must be written to their

0x00

reset default value (0x00).

UT_TxARST_D

UT_TxARST_C

UT_TxARST_B

UT_TxARST_A

UT_RxARST_D

UT_RxARST_C

UT_RxARST_B

UT_RxARST_A

Transmit ARST for Transmit Channel D.

Transmit ARST for Transmit Channel C.

Transmit ARST for Transmit Channel B.

Transmit ARST for Transmit Channel A.

Receive ARST for Receive Channel D.

Receive ARST for Receive Channel C.

Receive ARST for Receive Channel B.

Receive ARST for Receive Channel A.

Error Count Registers (RO)

Table 66. Register 0x0220: Channel [A—D] Error Count (RO)

Reset default of register = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0220—0223 15—0

PECTx[A—D]

Parity Error Count Transmit Channel [A—D].

Counts the instantaneous (real-time) number of

parity errors that occur for Tx channel [A—D].

0x0000

Scratch Register (R/W)

Table 67. Register 0x0224: UT_Scratch Register (R/W)

Reset default of register = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0224

15—0

UT_SCRATCH

UT Scratch Register. Read/write register with

0x0000

no other internal UT connections.

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UT Registers (continued)

PA Response Register (R/W)

Table 68. Register 0x0225: PA Response Register (R/W)

Reset default of register = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0225

—

PA/DATA

Packet Available (PA). In MPHY mode, when

this bit is 0, the PA response follows placement

of a valid address on the address bus by the

ATM master device by one UTOPIA interface

clock period. The RxDATA response follows the

RxENB assertion.

0x0000

If this bit is 1, then the PA response and

RxDATA response follow the address by two

clock periods. Two-cycle response is provided

for U3-compatible operation.

15—8

—

Reserved. These bits must be written to their

0x00

reset default value (0x00).

TxPAD

TxPAC

TxPAB

TxPAA

TxPA Response forTransmit Channel D.

TxPA Response forTransmit Channel C.

TxPA Response forTransmit Channel B.

TxPA Response forTransmit Channel A.

RxPAD/RxDATAD/RxSOP/ RxPA Response for Receive Channel D.

RxPAC/RxDATAC/RxSOP/ RxPA Response for Receive Channel C.

RxPAB/RxDATAB/RxSOP/ RxPA Response for Receive Channel B.

RxPAA/RxDATAA/RxSOP/ RxPA Response for Receive Channel A.

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UT Registers (continued)

Size Mode Register (R/W)

Table 69. Register 0x0226: Size Mode Register (R/W)

Reset default of register = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0226

—

Size Mode. Size mode for each channel. These

bits define the size mode for the TxSZ[D—A]

and RxSZ[D—A] pins (see Table 5, page 32

and page 38).

0x0000

If this mode bit = 0 (default mode):

^ITxSIZE_[D—A] (or RxSIZE_[D—A]) set to 0

means the most significant byte is the last

byte of the current packet, and

^ITxSIZE_[D—A] (or RxSIZE_[D—A]) set to 1

means the least significant byte is the last

byte.

If this mode bit = 1:

^ITxSIZE_[D—A] (or RxSIZE_[D—A]) set to 1

means the most significant byte is the last

byte of the current packet, and

^ITxSIZE_[D—A] (or RxSIZE_[D—A]) set to 0

means the least significant byte is the last

byte.

15—8

—

Reserved. These bits must be written to their

reset default value (0x00).

0x00

TxSIZE_D

TxSIZE_C

TxSIZE_B

TxSIZE_A

RxSIZE_D

RxSIZE_C

RxSIZE_B

RxSIZE_A

TxSIZE_MODE for Transmit Channel D.

TxSIZE_MODE for Transmit Channel C.

TxSIZE_MODE for Transmit Channel B.

TxSIZE_MODE for Transmit Channel A.

RxSIZE_MODE for Receive Channel D.

RxSIZE_MODE for Receive Channel C.

RxSIZE_MODE for Receive Channel B.

RxSIZE_MODE for Receive Channel A.

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OHP Registers

This section gives a brief description of each register bit and its functionality. All algorithms are described in the

main text of the document. The abbreviations after each register indicate if the register is read only (RO), read/

write (R/W), write only (WO), or clear-on-read or clear-on-write (COR/W).

0x indicates a hexadecimal value in the Reset Default column. Otherwise, the entry is binary. This is true for every

Table 70. Register 0x0400: OHP Macrocell Version Number (RO)

Reset default of register = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0400

15—0

OHP_VERSION[15:0]

OHP Macrocell Version Number. The version

of the macrocell will increment each time a

change occurs to the macrocell functionality.

0x0000

Table 71. Register 0x0401: OHP Interrupt (RO)

Reset default of register = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0401

15—4

—

Reserved. These bits must be written to their

0x000

reset default value (0x000).

OHP_INT[D]

OHP_INT[C]

OHP_INT[B]

OHP_INT[A]

OHP Interrupt. Active-high interrupt bits for

channels D to A. Each bit is the ORing of all

event and delta bits of that channel. In STS-48/

STM-16 mode, INT[A] is valid.

0x0

Table 72. Registers 0x0402—0x0409: Delta/Event (COR/W)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0402, 0404,

0406, 0408

LRDIMOND[A—D]

Line/Multiplex RDI Delta. Delta bits indicate a

change of state for the line/multiplex RDI state

bits (LRDIMON[A—D]). Their mask bits are

LRDIMONM[A—D]. Only LRDIMOND[A] is

valid for STS-48/STM-16.

LAISMOND[A—D]

Line/Multiplex AIS Delta. Delta bits indicate a

change of state for the line/multiplex AIS state

bits (LAISMON[A—D]). Their mask bits are

LAISMONM[A—D]. Only LAISMOND[A] is valid

for STS-48/STM-16.

RAPSBABLEE[A—D]

APS Babble Event. Each bit is active-high to

indicate the inconsistence in K1 byte of that

channel. Their mask bits are

RAPSBABLEM[A—D]. Only RAPSBABLEE[A]

is valid for STS-48/STM-16.

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OHP Registers (continued)

Table 72. Registers 0x0402—0x0409: Delta/Event (COR/W) (continued)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0402, 0404,

0406, 0408

S1DMON4D[A—D]

Delta Register for S1DMON[3:0] When

S1MON8or4CTL = 1. Each delta bit indicates a

change of state for S1DMON[3:0] in its channel.

Their mask bits are S1DMON4M[A—D]. In

STS-48/STM-16 mode, S1DMON4D[A] is valid.

S1DMON8D[A—D]

Delta Register for S1DMON[7:4] When

S1MON8or4CTL = 1 or S1DMON[7:0] When

S1MON8or4CTL = 0. Each delta bit indicates a

change of state for S1DMON[7:4]/

S1DMON[7:0] in its channel. Their mask bits

are S1DMON8M[A—D]. In STS-48/STM-16

mode, S1DMON8D[A] is valid.

K2DMOND[A—D]

K2[2:0] Data Monitor Delta. Each bit is active-

high to indicate a change in K2DMON[A—D]

for that channel. Their mask bits are

K2DMONM[A—D]. Only K2DMOND[A] is valid

for STS-48/STM-16.

K1K2DMOND[A—D]

K1K2 Data Monitor Delta. Each bit is active-

high to indicate a change in (K1[7:0] and

K2[7:3]) or (K1[7:0] and K2[7:0]) for that chan-

nel depending on K1K2_2_OR_1. Their mask

bits are K1K2DMONM[A—D]. Only

K1K2DMOND[A] is valid for STS-48/STM-16.

F1DMOND[A—D]

TTOAC_PERRE[A—D]

S1BABBLEE[A—D]

F1 Data Monitor Delta. Their mask bits are

F1DMONM[A—D]. Only F1DMOND[A] is valid

for STS-48/STM-16.

Transmit TOAC Parity Error Event. Event bit

indicates a parity error was detected on the

incoming TOAC.

Receive S1 Byte Babbling Event. Event bit

will be set if CNTDS1FRAME[A—D][3:0] con-

secutive frames pass without a validated S1

byte.

SFD[A—D]

Signal Fail BER Algorithm Delta. Delta bits

indicate a change of state for the signal fail BER

algorithm state bits (SF[A—D]). Their mask bits

are SFM[A—D]. Only SFD[A] is valid for STS-

48/STM-16.

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OHP Registers (continued)

Table 72. Registers 0x0402—0x0409: Delta/Event (COR/W) (continued)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0402, 0404,

0406, 0408

SDD[A—D]

Signal Degrade BER Algorithm Delta. Delta

bit indicates a change of state for the signal

degrade BER algorithm state bits (SD[A—D]).

Their mask bits are SDM[A—D]. Only SDD[A] is

valid for STS-48/STM-16.

OOFD[A—D]

LOFD[A—D]

LOSD[A—D]

LOCD[A—D]

Receive Out-of-Frame Delta. Delta bit indi-

cates a change of state for the out-of-frame

(OOF[A—D]). Their mask bits are

OOFM[A—D]. In STS-48/STM-16 mode, only

OOFD[A] is valid.

Receive Loss-of-Frame Delta. Delta bit indi-

cates a change of state for the loss-of-frame

(LOF[A—D]) . Their mask bits are LOFM[A—D].

In STS-48/STM-16 mode, only LOFD[A] is

valid.

Receive Loss-of-Signal Delta. Delta bit indi-

cates a change of state for the loss-of-signal

(LOS[A—D]). Their mask bits are LOSM[A—D].

In STS-48/STM-16 mode, only LOSD[A] is

valid.

Receive Loss-of-Clock Delta. Delta bit indi-

cates a change of state for the loss-of-clock

(LOC[A—D]). Their mask bits are LOCM[A—D].

In STS-48/STM-16 mode, only LOCD[A] is

valid.

0403, 0405, 15—1

0407, 0409

—

Reserved. These bits must be written to their

reset default value (000000000000000).

000

0000

J0MISE[A—D]

J0 Mismatch Event. Their mask bits are

J0MISM[A—D]. In STS-48/STM-16 mode, only

J0MISE[A] is valid for J0 byte while J0MISE[B—

D] are used for Z0 bytes.

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OHP Registers (continued)

Table 73. Registers 0x040A—0x040D: Receive/Transmit State (RO)

Reset default of registers = 0x000C.

Address

(Hex)

Bit #

Name

Function

Reset

Default

040A—040D

LRDIMON[A—D]

LAISMON[A—D]

—

Line/Multiplex RDI State. In STS-48/

STM-16 mode, only LRDIMON[A] is valid.

Line/Multiplex AIS State. In STS-48/

STM-16 mode, only LAISMON[A] is valid.

13—7

Reserved. These bits must be written to their

reset default value (0000000).

000

0000

TLRDIINT[A—D]

Transmit Line RDI Insert State. State bits for

inserting line RDI value into the K2[2:0] bits. In

STS-48/STM-16 mode, only TLRDIINT[A] is

valid.

SF[A—D]

SD[A—D]

OOF[A—D]

Signal Fail State. In STS-48/STM-16 mode,

only SF[A] is valid.

Signal Degrade State. In STS-48/STM-16

mode, only SD[A] is valid.

Out-of-Frame. Active-high out-of-frame state

bits. In STS-48/STM-16 mode, only OOF[A] is

valid.

LOF[A—D]

LOS[A—D]

LOC[A—D]

Loss-of-Frame. Active-high loss-of-frame state

bits. In STS-48/STM-16 mode, only LOF[A] is

valid.

Loss-of-Signal. Active-high loss-of-signal state

bits. In STS-48/STM-16 mode, only LOS[A] is

valid.

Loss-of-Clock. Active-high loss-of-clock state

bits. In STS-48/STM-16 mode, only LOC[A] is

valid.

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OHP Registers (continued)

Table 74. Registers 0x040E, 0x0410, 0x0412, 0x0414: Mask Bits (R/W)

Reset default of registers = 0xFFFF.

Address

(Hex)

Bit #

Name

Function

Reset

Default

040E, 0410,

0412, 0414

LRDIMONM[A—D]

Line/Multiplex RDI Mask. A 1 masks the cor-

responding occurrence of the alarm to the inter-

rupt. In STS-48/STM-16 mode, only

LRDIMONM[A] is valid.

LAISMONM[A—D]

RAPSBABLEM[A—D]

S1DMON4M[A—D]

Line/Multiplex AIS Mask. A 1 masks the corre-

sponding occurrence of the alarm to the inter-

rupt. In STS-48/STM-16 mode, only

LAISMONM[A] is valid.

APS Babble Mask. A 1 masks the correspond-

ing occurrence of the alarm to the interrupt. In

STS-48/STM-16 mode, only

RAPSBABLEM[A] is valid.

Mask Bits for S1DMON4D When S1MON8

or 4CTL = 1. A 1 masks the corresponding

occurrence of the alarm to the interrupt. In

STS-48/STM-16 mode, only

S1DMON4LSNM[A] is valid.

S1DMON8M[A—D]

K2DMONM[A—D]

K1K2DMONM[A—D]

F1DMONM[A—D]

Mask Bits for S1DMON8D. A 1 masks the cor-

responding occurrence of the alarm to the inter-

rupt. In STS-48/STM-16 mode, only

S1DMON8M[A] is valid.

K2[2:0] Data Monitor Mask. A 1 masks the

corresponding occurrence of the alarm to the

interrupt. In STS-48/STM-16 mode, only

K2DMONM[A] is valid.

K1K2 Data Monitor Mask. A 1 masks the cor-

responding occurrence of the alarm to the inter-

rupt. In STS-48/STM-16 mode, only

K1K2DMONM[A] is valid.

F1 Data Monitor Mask. A 1 masks the corre-

sponding occurrence of the alarm to the inter-

rupt. In STS-48/STM-16 mode, only

F1DMONM[A] is valid.

TTOAC_PERRM[A—D] Transmit TOAC Parity Error Mask. A 1 masks

the corresponding occurrence of the alarm to

the interrupt. All 4 bits are valid in every mode.

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OHP Registers (continued)

Table 74. Registers 0x040E, 0x0410, 0x0412, 0x0414: Mask Bits (R/W) (continued)

Reset default of registers = 0xFFFF.

Address

(Hex)

Bit #

Name

Function

Reset

Default

040E, 0410,

0412, 0414

S1BABBLEM[A—D]

S1 Babbling Mask. A 1 masks the correspond-

ing occurrence of the alarm to the interrupt. In

STS-48/STM-16 mode, only S1BABBLEM[A] is

valid.

SFM[A—D]

SDM[A—D]

Signal Fail Mask. A 1 masks the correspond-

ing occurrence of the alarm to the interrupt. In

STS-48/STM-16 mode, only SFM[A] is valid.

Signal Degrade Mask. A 1 masks the corre-

sponding occurrence of the alarm to the inter-

rupt. In STS-48/STM-16 mode, only SDM[A] is

valid.

OOFM[A—D]

LOFM[A—D]

LOSM[A—D]

LOCM[A—D]

Out-of-Frame Mask. A 1 masks the corre-

sponding occurrence of the alarm to the inter-

rupt. In STS-48/STM-16 mode, only OOFM[A]

is valid.

Loss-of-Frame Mask. A 1 masks the corre-

sponding occurrence of the alarm to the inter-

rupt. In STS-48/STM-16 mode, only LOFM[A] is

valid.

Loss-of-Signal Mask. A 1 masks the corre-

sponding occurrence of the alarm to the inter-

rupt. In STS-48/STM-16 mode, only LOSM[A] is

valid.

Loss-of-Clock Mask. A 1 masks the corre-

sponding occurrence of the alarm to the inter-

rupt. In STS-48/STM-16 mode, only LOCM[A] is

valid.

Table 75. Registers 0x040F, 0x0411, 0x0413, 0x0415: Mask Bits (R/W)

Reset default of registers = 0x8001.

Address

(Hex)

Bit #

Name

Function

Reset

Default

040F, 0411,

0413, 0415

INTM[A—D]

Interrupt Mask. The corresponding occurrence

of a 1 masks the alarm to the interrupt.

14—1

—

Reserved. These bits must be written to their

reset default value (00000000000000).

0000

J0MISM[A—D]

J0 Mismatch Mask. The corresponding occur-

rence of a 1 masks the alarm to the interrupt.

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OHP Registers (continued)

Table 76. Registers 0x0416—0x0419:Toggles (R/W)

Reset default of registers = 0x0000.

Note: These registers are one-shot type registers. They are enabled by writing a 0-to-1 transition to a bit. After

being enabled, the registers must be cleared by writing all bits to 0 following access.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0416—0419 15—5

—

Reserved. These bits must be written to their

reset default value (00000000000).

000

0000

TA1A2ERREN[A—D]

Transmit A1/A2 Error Enable. Enable signal to

start the insertion of A2 errors in the outgoing

frame. The number of consecutive errors is

controlled by TA1A2ERRINS[4:0].

TA1A2ERREN[A] is valid in STS-48/STM-16

mode.

SFCLEAR[A—D]

SFSET[A—D]

Signal Fail Clear. Allows the signal fail algo-

rithm to be forced into the normal state.

Signal Fail Set. Allows the signal fail algorithm

to be forced into the failed state.

Signal Degrade Clear. Allows the signal

degrade algorithm to be forced into the normal

state.

SDCLEAR[A—D]

SDSET[A—D]

Signal Degrade Set. Allows the signal degrade

algorithm to be forced into the degraded state.

Table 77. Registers 0x041A, 0x041C, 0x041E, 0x0420: Continuous N Times Detect (CNTD) Values (R/W)

Reset default of registers = 0x3333.

Address

(Hex)

Bit #

Name

Function

Reset

Default

041A,041C, 15—12

041E, 0420

CNTDK2[A—D][3:0]

Continuous N Times Detect for K2[2:0] Byte.

The valid range for these bits is 0x2—0xF.

Invalid values will be mapped to a value of 0x1.

In STS-48/STM-16 mode, CNTDK2[A] is valid.

Continuous N Times Detect for APS (K1,

K2[7:3]) Byte. The valid range for these bits is

0x2—0xF. Invalid values will be mapped to a

value of 0x1. In STS-48/STM-16 mode,

CNTDK1K2[A] is valid.

0x3

11—8

CNTDK1K2[A—D][3:0]

0x3

7—4

3—0

CNTDF1[A—D][3:0]

Continuous N Times Detect for F1 Byte. The

valid range for these bits is 0x2—0xF. Invalid

values will be mapped to a value of 0x1. In

STS-48/STM-16 mode, CNTDF1[A] is valid.

Continuous N Times Detect for J0Z0 Bytes.

The valid range for these bits is 0x2—0xF.

Invalid values will be mapped to a value of 0x1.

In STS-48/STM-16 mode, CNTDJ0Z0[A] is

valid.

0x3

CNTDJ0Z0[A—D][3:0]

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OHP Registers (continued)

Table 78. Registers 0x041B, 0x041D, 0x041F, 0x0421: Continuous N Times Detect (CNTD)Values (R/W)

Reset default of registers = 0x053C.

Address

(Hex)

Bit #

Name

Function

Reset

Default

041B, 041D, 15—12

—

Reserved. These bits must be written to their reset

0x0

041F, 0421

default value (0x0).

11—8

CNTDS1FRAME

Continuous N Times Detect for S1 Byte Bab-

bling. The valid range for these bits is 0x2—0xF.

Invalid values will be mapped to a value of 0x1. In

STS-48/STM-16 mode, CNTDS1FRAME[A] is

valid.

0x5

[A—D][3:0]

7—4

3—0

CNTDS1[A—D][3:0] Continuous N Times Detect for S1 Byte. The

valid range for these bits is 0x2—0xF. Invalid val-

ues will be mapped to a value of 0x1. In

0x3

STS-48/STM-16 mode, CNTDS1[A] is valid.

CNTDK1K2FRAME Continuous N Times Detect for APS Frame. The

0xC

[A—D][3:0]

valid range for these bits is 0x2—0xF. Invalid val-

ues will be mapped to a value of 0x1. In STS-48/

STM-16 mode, CNTDK1K2FRAME[A] is valid.

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OHP Registers (continued)

Table 79. Registers 0x0422—0x042D: Receive Control (R/W)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0422, 0424, 15—14 J0MONMODE[A—D][1:0] J0 Monitoring Mode. The four modes are,

0426, 0428

00 = The OHP will latch the value of the J0 byte

every frame for a total of 16 bytes. The OHP will

compare the incoming J0 byte with the next

expected value (the expected value is obtained

by cycling through the previously stored 16

received bytes in round-robin fashion) and set

the event bit if different.

01 = This is the SONET framing mode. The

hardware looks for 0x0D followed by 0x0A to

indicate that the next byte is the first byte of the

path trace message. The J0 byte is continu-

ously written into J0DMON with the first byte

residing at the first address. If any received byte

does not match the previously received byte for

its location, then the event bit is set.

10 = This is the SDH framing mode. The hard-

ware looks for the byte with the MSB set to 1,

which indicates that the next byte is the second

byte of the message. The rest of the operation

is the same as the SONET framing mode.

11 = A new J0 byte J0DMON[0][7:0] will be

detected after CNTDJ0Z0[3:0] consecutive con-

sistent occurrences of a new pattern in the J0

overhead byte. Any changes to this byte are

reported to J0MISE and J0MISM. These event

bits will act as delta bits indicating a change of

state for the J0DMON[0][7:0].

M1B7IGNORE[A—D]

Bit 7 of M1 Byte Ignore. Bit 7 of M1 byte will

be ignored if M1B7IGNORE is set to 1 for that

channel. Only M1B7IGNORE[A] is valid for

STS-48/STM-16.

LAISINS[A—D]

LOF_AISINH[A—D]

OOF_AISINH[A—D]

AIS Software Insertion. Active-high for AIS

insertion. In STS-48/STM-16 mode, only LAI-

SINS[A] is valid.

Loss-of-Frame AIS Inhibit. When set to logic

1, the AIS insertion will be inhibited in case of

loss-of-frame.

Out-of-Frame AIS Inhibit. When set to logic 1,

the AIS insertion will be inhibited in case of out-

of-frame.

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OHP Registers (continued)

Table 79. Registers 0x0422—0x042D: Receive Control (R/W) (continued)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0422, 0424,

0426, 0428

LOS_AISINH[A—D]

Loss-of-Signal AIS Inhibit. When set to logic

1, the line AIS insertion will be inhibited in case

of loss-of-signal.

SFB1B2SEL[A—D]

SDB1B2SEL[A—D]

CNTDB1SEL[A—D]

Signal Fail B1/B2 Error Count Select. When

set to logic 0, the B1 errors will be used by the

signal fail error rate algorithm; otherwise, B2

errors are used.

Signal Degrade B1/B2 Error Count Select.

When set to logic 0, the B1 errors will be used

by the signal degrade error rate algorithm; oth-

erwise, B2 errors are used.

Reset CNTD Counters on B1 Error. Active-

high control bits to reset continuous N time

detect counters upon received B1 errors. Only

CNTDB1SEL[0] is valid for STS-48/STM-16.

S1MON8_OR_4CTL[A—D] S1 Byte or Nibble. When set to logic 1, the S1

byte will be monitored as two nibbles. Other-

wise, it is treated as a byte. Only

S1MON8or4CTL[A] is valid for STS-48/STM-

16.

K1K2_2_OR_1[A—D]

K1 and K2 Treated as 2 Registers or 1. When

a bit is set to 1, the K1 and K2 bytes will be

treated as one 16-bit register. Otherwise, they

will be treated as two registers of size 13

(K1[7:0] and K2[7:3]) and 3 (K2[2:0]).

K1K2_2_OR_1[A] is valid for STS-48/STM-16.

B2BITBLKCNT[A—D]

DSCRINH[A—D]

B2 Error Count in Bit or Block. When set to 0,

B2 check logic will count bit errors; otherwise, it

counts block errors. Only B2BITBLKCNT[A] is

valid for STS-48/STM-16.

Descramble Inhibit Control. When a bit is set

to 1, the descrambler for that is disabled. In

STS-48/STM-16 mode, all 4 bits need to be set

to same value.

B1BITBLKCNT[A—D]

ROH_BYPASS[A—D]

B1 Error Count in Bit or Block. When set to 0,

B1 check logic will count bit errors; otherwise, it

counts block errors. Only B1BITBLKCNT[A] is

valid for STS-48/STM-16.

Receive Overhead Bypass. Control bit, when

set to 1, causes the received data to pass

through the block retimed. In STS-48/STM-16

mode, all 4 bits need to be set to same value.

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May 2001

OHP Registers (continued)

Table 79. Registers 0x0422—0x042D: Receive Control (R/W) (continued)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0423, 0425,

0427, 0429

M1BITBLKCNT[A—D]

M1 Error Count in Bit or Block. When set to

0, M1 check logic will count bit errors. When set

to 1, block errors are counted. Only

M1BITBLKCNT[C] is valid for STS-48/STM-16.

14—13

—

Reserved. These bits must be written to their

reset default value (00).

12—0 LOSDETCNT[A—D][12:0] Loss-of-Signal Detection Count. Set the

number of consecutive all-zeros/-ones pattern

detected to declare receive LOS state for each

channel. The time scale is in steps of 8 (for

STS-3/STM-1 and STS-12/STM-4) or 32

(STS-48/STM-16) bits at a time. Only

0000

LOSDETCNT[A][12:0] is valid for STS-48/

STM-16.

042A

15—14

RREFSEL[1:0]

RREF_EN

Receive Reference Sync Select. Select refer-

ence output from channel A (00), B (01), C (10),

and D (11).

Receive Reference Sync Enable. When set to

0, the receive 8 kHz (50% duty cycle) sync out-

put, RxREF (pin AK3), is placed in the high-

impedance state.

12—4

—

Reserved. These bits must be written to their

0000

reset default value (000000000).

00000

RTOACSINH[A]

Receive TOAC Frame (Sync) Inhibit Channel

A. When set to 1, the TOAC sync output,

RxTOHF (pin AK4), is placed in the high-imped-

ance state.

RTOACCINH[A]

Receive TOAC Clock Inhibit Channel A.

When set to 1, the TOAC clock output,

RxTOHCK (pin AK5), is placed in the high-

impedance state.

RTOACDINH[A]

Receive TOAC Data Inhibit Channel A. When

set to 1, the TOAC data output, RxTOHD (pin

AL2), is placed in the high-impedance state.

RTOAC_OEPINS[A]

Receive TOAC Odd or Even Parity Insert

Channel A. When set to 1, the output TOAC

parity bit is even. When set to 0, the parity is

odd.

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Data Sheet

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OHP Registers (continued)

Table 79. Registers 0x0422—0x042D: Receive Control (R/W) (continued)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

042B—042D 15—4

—

Reserved. These bits must be written to their

0x000

reset default value (0x000).

RTOACSINH[B—D]

Receive TOAC Frame (Sync) Inhibit Channel

[B—D]. When set to 1, the TOAC sync output,

RxTOHF (pins AL3, AN5, AP6), is placed in the

high-impedance state.

RTOACCINH[B—D]

RTOACDINH[B—D]

Receive TOAC Clock Inhibit Channel [B—D].

When set to 1, the TOAC clock output,

RxTOHCK (pins AL4, AL6, AL7), is placed in

the high-impedance state.

Receive TOAC Data Inhibit Channel [B—D].

When set to 1, the TOAC data output, RxTOHD

(pins AM5, AM6, AN7), is placed in the high-

impedance state.

RTOAC_OEPINS[B—D] Receive TOAC Odd or Even Parity Insert

Channel [B—D]. When set to 1, the output

TOAC parity bit is even. When set to 0, the par-

ity is odd.

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Data Sheet

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OHP Registers (continued)

Table 80. Registers 0x042E:Transmit Control Port A (R/W)

Reset default of registers = 0x0003.

Address

(Hex)

Bit #

Name

Function

Reset

Default

042E

TTOACINH

Transmit TOAC Clock and Sync Inhibit Chan-

nel A. When set to 1, the transmit TOAC clock

and sync are placed in the high-impedance

state.

TJ0INS[A]

Transmit J0 Insert Control Channel A. Con-

trol bit, when set to a logic 1, inserts the value in

TJ0DINS[A—D][16:1][7:0] into the outgoing J0

bytes; otherwise, the insert value depends on

TTOAC_J0[A—D] registers. TJ0INS[A] is valid

in STS-48/STM-16 mode.*

TTOAC_J0[A]

Transmit TOAC J0 Byte Control Channel A.

Control bit, when set to logic 0, causes the

default value 00000000 for SONET or

11111111 for SDH to be inserted into the J0

byte in the transmit frame. Setting this bit to

logic 1 causes the TTOAC value to be inserted

into the J0 byte. TTOAC_J0[A] is valid for STS-

48/STM-16 mode.*

TTOAC_OEPMON[A]

TTOAC_INS[A]

Transmit TOAC Odd or Even Parity Monitor

Channel A. When set to 1, even parity is

checked for transmit TOAC channels; other-

wise, odd parity is checked.

Transmit TOAC Byte Control Channel A.

Control bit, when set to logic 0, causes the

default value 00000000 for SONET or

11111111 for SDH to be inserted into those

overhead bytes within the transmit frame that

do not have all specific insert control bits. Set-

ting these bits to logic 1 causes the TTOAC

value to be inserted into those overhead bytes

not having specific insert control bits.

TTOAC_INS[A] is valid for STS-48/STM-16

mode.

TTOAC_E2[A]

Transmit TOAC E2 Byte Control Channel A.

Control bit, when set to logic 0, causes the

default value to be inserted into the E2 byte in

the transmit frame. Setting these bits to logic 1

causes the TTOAC value to be inserted into the

E2 byte. TTOAC_E2[A] is valid for STS-48/

STM-16 mode.

* TJ0INS = 1 always sets J0 to the TJ0DINS values regardless of the value of TTOAC_J0.

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OHP Registers (continued)

Table 80. Registers 0x042E: Transmit Control Port A (R/W) (continued)

Reset default of registers = 0x0003.

Address

(Hex)

Bit #

Name

Function

Reset

Default

042E

TTOAC_S1[A]

Transmit TOAC S1 Byte Control Channel A.

Control bit, when set to logic 0, causes the

default value to be inserted into the S1 byte in

the transmit frame. Setting these bits to logic 1

causes the TTOAC value to be inserted into the

S1 byte. TTOAC_S1[A] is valid for STS-48/

STM-16 mode.

TTOAC_D4TO12[A]

TTOAC_D1TO3[A]

Transmit TOAC D4 to D12 Byte Control

Channel A. Control bit, when set to logic 0,

causes the default value to be inserted into the

D4 to D12 bytes in the transmit frame. Setting

these bits to logic 1 causes the TTOAC value to

be inserted into the D4 to D12 bytes.

TTOAC_D4TO12[A] is valid for STS-48/

STM-16 mode.

Transmit TOAC D1 to D3 Byte Control Chan-

nel A. Control bit, when set to logic 0, causes

the default value to be inserted into the D1 to

D3 bytes in the transmit frame. Setting these

bits to logic 1 causes the TTOAC value to be

inserted into the D1 to D3 bytes.

TTOAC_D1TO3[A] is valid for STS-48/STM-16

mode.

TTOAC_F1[A]

TTOAC_E1[A]

Transmit TOAC F1 Byte Control Channel A.

Control bit, when set to logic 0, causes the

default value to be inserted into the F1 byte in

the transmit frame. Setting these bits to logic 1

causes the TTOAC value to be inserted into the

F1 byte. TTOAC_F1[A] is valid for STS-48/

STM-16 mode.

Transmit TOAC E1 Byte Control Channel A.

Control bit, when set to logic 0, causes the

default value to be inserted into the E1 byte in

the transmit frame. Setting this bit to logic 1

causes the TTOAC value to be inserted into the

E1 byte. TTOAC_E1[A] is valid for STS-48/

STM-16 mode.

TAPSBABBLEINS[A]

Transmit APS Babble Insert Channel A. Con-

trol bit, when set to 1, causes an inconsistent

APS byte (K1[7:0], K2[7:3]) to be inserted into

the outgoing STS-M frame until this register is

reset to 0.

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Data Sheet

May 2001

OHP Registers (continued)

Table 80. Registers 0x042E: Transmit Control Port A (R/W) (continued)

Reset default of registers = 0x0003.

Address

(Hex)

Bit #

Name

Function

Reset

Default

042E

TM1_ERR_INS[A]

Transmit M1 Error Insert Channel A. Once

this register is set to 1, an error will be inserted

continuously into the outgoing M1 byte until this

only TM1_ERR_INS is valid.

TM1_REIL_INH[A]

TF1INS[A]

Transmit M1 REI-L Inhibit Channel A. Active-

high to inhibit automatic insertion of REI-L

(MS-REI). In STS-48/STM-16 mode, only

TM1_REIL_INH is valid.

Transmit F1 Insert Control Channel A. Con-

trol bit, when set to a logic 1, inserts the value in

TF1DINS[7:0] into the outgoing F1 byte in the

STS-M frame; otherwise, the insert value

depends on TTOAC_F1 register. TF1INS[A] is

valid in STS-48/STM-16 mode.

TS1INS[A]

Transmit S1 Insert Control Channel A. Con-

trol bit, when set to a logic 1, inserts the value in

TS1DINS[7:0] into the outgoing S1 byte in the

STS-M frame; otherwise, the insert value

depends on TTOAC_S1 register. TS1INS[A] is

valid in STS-48/STM-16 mode.

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Data Sheet

May 2001

OHP Registers (continued)

Table 81. Registers 0x042F, 0x0431, 0x0433, 0x0435: Transmit Control (R/W)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

042F, 0431, 15—11 TA1A2ERRINS[A—D][4:0] Number of Consecutive Frames with A2

0x00

0433, 0435

Error Insertion. These bits specify the number

of consecutive frames to be inserted with a

frame error of the first A2 byte.

TOH_BYPASS[A—D]

Transmit Overhead Bypass. Control bit, when

set to 1, causes the frame from PT pass

through untouched. In STS-48/STM-16 mode,

all 4 bits need to be set to same value.

SCRINH[A—D]

TB1ERRINS[A—D]

TB2ERRINS[A—D]

Scramble Inhibit. When set to high, the scram-

bling is inhibited. In STS-48/STM-16 mode, all

4 bits need to be set to same value.

Transmit B1 Error Insertion. When set to

high, the B1 output will be inverted. For

STS-48/STM-16, only TB1ERRINS[A] is valid.

Transmit B2 Error Insertion. When set to

high, all B2 bytes in that channel will be

inverted. All 4 bits are valid in STS-48/STM-16

mode.

TIMER_LRDIINH[A—D] Transmit 20-Frame Line RDI Inhibit. Control

bit, when set to logic high, inhibits the require-

ment of minimum 20 frame RDI insertion.

TSF_LRDIINH[A—D]

Transmit Signal Fail Line RDI Inhibit. Active-

high.

TLAISMON_LRDIINH

Transmit Line-AIS-Monitored Line RDI

Inhibit. Active-high.

[A—D]

TLOF_LRDIINH[A—D]

TOOF_LRDIINH[A—D]

TLOS_LRDIINH[A—D]

TLOC_LRDIINH[A—D]

Transmit Loss-of-Frame Line RDI Inhibit.

Active-high.

Transmit Out-of-Frame Line RDI Inhibit.

Active-high.

Transmit Loss-of-Signal Line RDI Inhibit.

Active-high.

Transmit Loss-of-Clock Line RDI Inhibit.

Control bit, when set to a logic 1, causes the

associated failure not to contribute to the auto-

matic insertion of RDI-L; otherwise, the associ-

ated alarm contributes to the generation of

RDI-L.

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Data Sheet

May 2001

OHP Registers (continued)

Table 82. Registers 0x0430, 0x0432, 0x0434: Transmit Control Port [B—D] (R/W)

Reset default of registers = 0x0003.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0430, 0432,

0434

—

Reserved. This bit must be written to its reset

default value (0).

TJ0INS[B—D]

Transmit J0 Insert Control Channel [B—D].

Control bit, when set to a logic 1, insert the

value in TJ0DINS[A—D][16:1][7:0] into the out-

going J0 bytes; otherwise, the insert value

depends on TTOAC_J0[A—D] registers.

TJ0INS[A] is valid in STS-48/STM-16 mode.*

TTOAC_J0[B—D]

Transmit TOAC J0 Byte Control Channel

[B—D]. Control bit, when set to logic 0, causes

the default value 00000000 for SONET or

11111111 for SDH to be inserted into the J0

byte in the transmit frame. Setting this bit to

logic 1 causes the TTOAC value to be inserted

into the J0 byte. TTOAC_J0[A] is valid for STS-

48/

STM-16 mode.*

TTOAC_OEPMON[B—D] Transmit TOAC Odd or Even Parity Monitor

Channel [B—D]. When set to 1, even parity is

checked for transmit TOAC channels; other-

wise, odd parity is checked.

TTOAC_INS[B—D]

Transmit TOAC Byte Control Channel

[B—D]. Control bit, when set to logic 0, causes

the default value 00000000 for SONET or

11111111 for SDH to be inserted into those

overhead bytes within the transmit frame that

do not have all specific insert control bits. Set-

ting this bit to logic 1 causes the TTOAC value

to be inserted into those overhead bytes not

having specific insert control bits.

TTOAC_INS[A] is valid for STS-48/STM-16

mode.

TTOAC_E2[B—D]

Transmit TOAC E2 Byte Control Channel

[B—D]. Control bit, when set to logic 0, causes

the default value to be inserted into the E2 byte

in the transmit frame. Setting this bit to logic 1

causes the TTOAC value to be inserted into the

E2 byte. TTOAC_E2[A] is valid for STS-48/

STM-16 mode.

* TJ0INS = 1 always sets J0 to the TJ0DINS values regardless of the value of TTOAC_J0.

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Data Sheet

May 2001

OHP Registers (continued)

Table 82. Registers 0x0430, 0x0432, 0x0434: Transmit Control Port [B—D] (R/W) (continued)

Reset default of registers = 0x0003.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0430, 0432,

0434

TTOAC_S1[B—D]

Transmit TOAC S1 Byte Control Channel

[B—D]. Control bit, when set to logic 0, causes

the default value to be inserted into the S1 byte

in the transmit frame. Setting this bit to logic 1

causes the TTOAC value to be inserted into the

S1 byte. TTOAC_S1[A] is valid for STS-48/

STM-16 mode.

TTOAC_D4TO12[B—D]

TTOAC_D1TO3[B—D]

Transmit TOAC D4 to D12 Byte Control

Channel [B—D]. Control bit, when set to logic

0, causes the default value to be inserted into

the D4 to D12 bytes in the transmit frame. Set-

ting this bit to logic 1 causes the TTOAC value

to be inserted into the D4 to D12 bytes.

TTOAC_D4TO12[A] is valid for STS-48/STM-16

mode.

Transmit TOAC D1 to D3 Byte Control Chan-

nel [B—D]. Control bit, when set to logic 0,

causes the default value to be inserted into the

D1 to D3 bytes in the transmit frame. Setting

this bit to logic 1 causes the TTOAC value to be

inserted into the D1 to D3 bytes.

TTOAC_D1TO3[A] is valid for STS-48/STM-16

mode.

TTOAC_F1[B—D]

TTOAC_E1[B—D]

Transmit TOAC F1 Byte Control Channel

[B—D]. Control bit, when set to logic 0, causes

the default value to be inserted into the F1 byte

in the transmit frame. Setting this bit to logic 1

causes the TTOAC value to be inserted into the

F1 byte. TTOAC_F1[A] is valid for STS-48/

STM-16 mode.

Transmit TOAC E1 Byte Control Channel

[B—D]. Control bit, when set to logic 0, causes

the default value to be inserted into the E1 byte

in the transmit frame. Setting this bit to logic 1

causes the TTOAC value to be inserted into the

E1 byte. TTOAC_E1[A] is valid for STS-48/

STM-16 mode.

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Data Sheet

May 2001

OHP Registers (continued)

Table 82. Registers 0x0430, 0x0432, 0x0434: Transmit Control Port [B—D] (R/W) (continued)

Reset default of registers = 0x0003.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0430, 0432,

0434

TAPSBABBLEINS[B—D] Transmit APS Babble Insert Channel

[B—D]. Control bit, when set to 1, causes an

inconsistent APS byte (K1[7:0], K2[7:3]) to be

inserted into the outgoing STS-M frame until

this register is reset to 0.

TM1_ERR_INS[B—D]

Transmit M1 Error Insert [B—D]. Once this

tinuously into the outgoing M1 byte until this

only TM1_ERR_INS is valid.

TM1_REIL_INH[B—D]

TF1INS[B—D]

Transmit M1 REI-L Inhibit Channel [B—D].

Active-high to inhibit automatic insertion of

REI-L (MS-REI). In STS-48/STM-16 mode, only

TM1_REIL_INH is valid.

Transmit F1 Insert Control Channel [B—D].

Control bit, when set to a logic 1, inserts the

value in TF1DINS[7:0] into the outgoing F1 byte

in the STS-M frame; otherwise, the insert value

depends on TTOAC_F1 register. TF1INS[A] is

valid in STS-48/STM-16 mode.

TS1INS[B—D]

Transmit S1 Insert Control Channel [B—D].

Control bit, when set to a logic 1, inserts the

value in TS1DINS[7:0] into the outgoing S1 byte

in the STS-M frame; otherwise, the insert value

depends on TTOAC_S1 register. TS1INS[A] is

valid in STS-48/STM-16 mode.

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Data Sheet

May 2001

OHP Registers (continued)

Table 83. Registers 0x0436—0x0439: Transmit Control (R/W)

Reset default of registers = 0xC000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0436—0439

TAPSINS[A—D]

Transmit APS Software Insert. When set to 1,

the value in registers TK1DINS[7:0] and

TK2DINS[7:3] will be inserted into K1[7:0] and

K2[7:3] in the transmit frame. When set to 0, a

value of all zeros will be inserted.

TK2SINS[A—D]

Transmit K2 Software Insert. When set to

logic 1, the value in registers TK2DINS[2:0] will

be inserted into K2[2:0] in the transmit frame;

otherwise, hardware insert is enabled for RDI-L

(110) insertion.

13—12

11—0

—

Reserved. These bits must be written to their

reset default value (00).

TAISLINS[A—D][11:0]

Force Line AIS in the Selected Output Time

Slot. Active-high. For STS-3/STM-1, the index

[0:2] corresponds to time slot 1-2-3; for STS-12/

STM-4, the index[0:11] corresponds to time slot

1-4-7-10-2-5-8-11-3-6-9-12; and for STS-48/

STM-16, the index [A][0:11] is for time slot 1-13-

25-37-2-14-26-38-3-15-27-39, [B][0:11] for 4-

16-28-40-5-17-29-41-6-18-30-42, [C][0:11] for

7-19-31-43-8-20-32-44-9-21-33-45, and

[D][0:11] for 10-22-34-46-11-23-35-47-12-24-

36-48.

0x000

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Data Sheet

May 2001

OHP Registers (continued)

Table 84. Registers 0x043A—0x0451: OHP Signal Degrade BER Algorithm Parameters (R/W)

Reset default of registers = 0x0000.

Notes: OHP_SDNSSET[A—D][2:0] are located in registers 0x043B, 0x043D, 0x043F, and 0x0441, respectively.

OHP_SDNSCLEAR[A—D][2:0] are located in registers 0x0447, 0x0449, 0x044B, and 0x044D, respec-

tively.

Address

(Hex)

Bit #

Name

Function

Reset

Default

043A, 043C, 15—0

043E, 0440

OHP_SDNSSET

[A—D][18:3]

Signal Degrade Ns Set [18:3]. Number of

frames in a monitoring block for SD.

0x0000

043B, 043D,

043F, 0441

—

Reserved. This bit must be written to its reset

default value (0).

14—7 OHP_SDMSET[A—D][7:0] Signal Degrade M Set. Threshold of the num-

ber of bad monitoring blocks in an observation

0000

interval. If the number of bad blocks is above

this threshold, then signal degrade (SD) is set.

6—3 OHP_SDLSET[A—D][3:0] Signal Degrade L Set. Error threshold for

0x0

000

determining if a monitoring block is bad.

2—0 OHP_SDNSSET[A—D][2:0] Signal Degrade Ns Set [2:0]. Number of

frames in a monitoring block for SD.

0442—0445 15—0 OHP_SDBSET[A—D][15:0] Signal Degrade B Set. Number of monitoring

0x0000

blocks.

0446, 0448, 15—0

OHP_SDNSCLEAR

Signal Degrade Ns Clear [18:3]. Number of

044A, 044C

[A—D][18:3]

frames in a monitoring block for SD.

0447, 0449,

044B, 044D

—

Reserved. This bit must be written to its reset

default value (0).

14—7

OHP_SDMCLEAR

Signal Degrade M Clear. Threshold of the

number of bad monitoring blocks in an observa-

tion interval. If the number of bad blocks is

below this threshold, then SD (signal degrade)

is cleared.

0000

[A—D][7:0]

6—3

2—0

OHP_SDLCLEAR

Signal Degrade L Clear. Error threshold for

determining if a monitoring block is bad.

0x0

000

[A—D][3:0]

OHP_SDNSCLEAR

Signal Degrade Ns Clear[2:0]. Number of

[A—D][2:0]

frames in a monitoring block for SD.

044E—0451 15—0

OHP_SDBCLEAR

Signal Degrade B Clear. Number of monitoring

0x0000

[A—D][15:0]

blocks.

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Data Sheet

May 2001

OHP Registers (continued)

Table 85. Registers 0x0452—0x0469: OHP Signal Fail BER Algorithm Parameters (R/W)

Reset default of registers = 0x0000.

Notes: OHP_SFNSSET[A—D][2:0] are located in registers 0x0453, 0x0455, 0x0457, and 0x0459, respectively.

OHP_SDNSCLEAR[A—D][2:0] are located in registers 0x045F, 0x0461, 0x0463, 0x0465, respectively.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0452, 0454, 15—0

OHP_SFNSSET

Signal Fail Ns Set [18:3]. Number of frames in

0x0000

0456, 0458

[A—D][18:3]

a monitoring block for SF.

0453, 0455,

0457, 0459

—

Reserved. This bit must be written to its reset

default value (0).

14—7 OHP_SFMSET[A—D][7:0] Signal Fail M Set. Threshold of the number of

bad monitoring blocks in an observation inter-

val. If the number of bad blocks is above this

threshold, then SF (signal fail) is set. (See Table

86, page 187, for register settings in terms of

corresponding BER.)

0000

6—3

OHP_SFLSET[A—D][3:0] Signal Fail L Set. Error threshold for determin-

ing if a monitoring block is bad. (See Table 86,

page 187, for register settings in terms of corre-

sponding BER.)

0x0

000

2—0 OHP_SFNSSET[A—D][2:0] Signal Fail Ns Set [2:0]. Number of frames in a

monitoring block for SF. (See Table 86, page

187, for register settings in terms of corre-

sponding BER.)

045A—045D 15—0 OHP_SFBSET[A—D][15:0] Signal Fail B Set. Number of monitoring

blocks. (See Table 86, page 187, for register

0x0000

settings in terms of corresponding BER.)

045E, 0460, 15—0

0462, 0464

OHP_SFNSCLEAR

Signal Fail Ns Clear [18:3]. Number of frames

in a monitoring block for SF.

0x0000

[A—D][18:3]

045F, 0461,

0463, 0465

—

Reserved. This bit must be written to its reset

default value (0).

14—7

OHP_SFMCLEAR

Signal Fail M Clear. Threshold of the number

of bad monitoring blocks in an observation

interval. If the number of bad blocks is below

this threshold, then SF (signal fail) is cleared.

0x00

[A—D][7:0]

6—3

2—0

OHP_SFLCLEAR

Signal Fail L Clear. Error threshold for deter-

mining if a monitoring block is bad.

0x0

000

[A—D][3:0]

OHP_SFNSCLEAR

Signal Fail Ns Clear [2:0]. Number of frames

in a monitoring block for SF.

[A—D][2:0]

0466—0469 15—0

OHP_SFBCLEAR

Signal Fail B Clear. Number of monitoring

blocks.

0x0000

[A—D][15:0]

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Data Sheet

May 2001

OHP Registers (continued)

Table 86 and Table 87 show values of Ns, L, M, and B for STS-3/STM-1, STS-12/STM-4, and STS-48/STM-16 to

set and clear the BER indicator. SF registers are 0x0452—0x0469, and SD registers are 0x043A—0x0451.

All SF/SD set and clear values are hexadecimal.

Table 86. Ns, L, M, and B Values to Set the BER Indicator

Mode

BER

SF/SD Set Values

Actual

Number of

Frames

Probability of

Detecting L

Errors (%)

Probability of

Declaring

SF/SD (%)

Integra-

tion

Time

(s)

Max-

imum

Number

of Frames

Ns*

@BER @BER/2 @BER @BER/2

STS-3/

STM-1

1.00E-03

1.00E-04

1.00E-05

1.00E-06

1.00E-07

1.00E-08

1.00E-09

1.00E-10

99.96

72.70

71.34

69.74

68.07

56.90

—

85.13

7.28

10.08

10.09

9.44

8.82

11.25

—

97.68

96.06

95.19

95.07

98.47

96.52

—

0.00

0.16

0.52

0.13

0.82

0.60

—

0.008

0.013

0.1

104

384

800

1E0

1275

B5A4

3F7A0

—

3840

47250

465000

4160000

—

8000

80000

664000

5336000

—

667

—

†

STS-12/ 1.00E-03

STM-4

—

100.00

84.92

67.93

66.19

65.75

—

88.43

9.64

7.17

6.66

6.53

—

100.00

98.38

96.48

95.46

95.16

—

0.04

0.00

0.25

0.19

0.18

—

0.008

0.025

0.25

2.5

1.00E-04

1.00E-05

1.00E-06

1.00E-07

1.00E-08

1.00E-09

1.00E-10

117

200

1152

11475

114750

1147500

—

2000

20000

168000

1336000

—

4FB

31CE

1F20C

—

167

—

†

STS-48/ 1.00E-03

STM-16

—

100.00

99.95

90.60

77.55

75.80

74.58

82.92

—

100.00

58.97

16.25

13.09

12.15

11.54

19.71

—

100.00

96.89

96.47

96.69

95.17

98.09

97.29

—

100.00

0.00

0.01

0.18

—

0.008

0.0625

0.625

5.2

1.00E-04

1.00E-05

1.00E-06

1.00E-07

1.00E-08

1.00E-09

1.00E-10

320

480

500

13A

C1C

765C

—

4710

46500

333300

—

5000

41600

336000

—

* These are the numbers to be provisioned in TDAT042G5. The actual values of the BER algorithm are 1 greater than the actual values shown.

†These BER values cannot be provisioned because the maximum value of L is 0xF (i.e., L is a 4-bit register).

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Data Sheet

May 2001

OHP Registers (continued)

Table 87. Ns, L, M, and B Values to Clear the BER Indicator

Mode

BER

SF/SD Set Values

Actual

Number of

Frames

Probability of

Detecting L

Errors (%)

Probability of

Clearing

SF/SD (%)

Integra-

Max-

imum

Number

of Frames

tion

Time

(s)

Ns*

@BER*5 @BER @BER*5 @BER

STS-3/

STM-1

1.00E-03

1.00E-04

1.00E-05

1.00E-06

1.00E-07

1.00E-08

1.00E-09

1.00E-10

—

0.013

0.1

—

104

85.13

93.01

84.42

83.66

82.86

46.31

0.39

11.33

6.84

6.59

6.35

1.48

0.27

0.01

0.34

0.22

0.03

0.50

100.00

99.21

99.88

99.98

99.75

99.84

800

384

8000

1E05

1275

B5A4

3F7A0

3840

47250

465000

4160000

80000

664000

5336000

53360000

667

6670

†

STS-12/ 1.00E-03

STM-4

—

0.008

0.025

0.25

2.5

—

1.00E-04

1.00E-05

1.00E-06

1.00E-07

1.00E-08

1.00E-09

1.00E-10

100.00

98.36

87.99

87.34

87.17

51.54

20.51

8.23

7.94

7.87

0.00

0.07

0.02

0.03

99.03

100.00

99.59

99.64

99.65

200

117

2000

1152

11475

114750

1147500

20000

168000

1336000

13360000

4FB

31CE

1F20C

167

1670

†

STS-48/ 1.00E-03

STM-16

—

†

—

†

—

†

—

†

—

0.008

0.0625

0.625

5.2

—

1.00E-04

100.00

95.07

87.34

86.52

85.95

84.89

45.99

60.11

7.28

7.94

7.61

7.38

7.00

0.00

0.03

99.42

99.47

99.98

99.94

99.95

99.96

99.95

1.00E-05

1.00E-06

1.00E-07

1.00E-08

1.00E-09

1.00E-10

320

500

640

5000

41600

336000

3360000

13A

C1C

765C

6280

62000

333300

420

* These are the numbers to be provisioned inTDAT042G5. The actual values of the BER algorithm are 1 greater than the actual values shown.

†These BER values cannot be provisioned because the maximum value of L is 0xF (i.e., L is a 4-bit register).

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Data Sheet

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OHP Registers (continued)

Table 88. Registers 0x046A—0x047D: B1, B2, M1 Error Count (RO)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

046A—046D 15—0

B1ECNT[A—D][15:0]

B1 Error Count. The value of the internal run-

ning counter is transferred into this holding reg-

ister at the 0-to-1 transition of PMRST signal.

The counter is then reset to 0.

0x0000

046E, 0470, 15—6

—

Reserved. These bits must be written to their

0472, 0474

reset default value (0000000000).

0000

5—0

B2ECNT[A—D][21:16]

B2 Error Count [21:16]. The value of the inter- 000000

nal running counter is transferred into this hold-

ing register at the 0-to-1 transition of PMRST

signal. The counter is then reset to 0.

046F, 0471, 15—0

B2ECNT[A—D][15:0]

B2 Error Count [15:0]. Same description as

0x0000

0473, 0475

above.

0476, 0478, 15—5

047A, 047C

—

Reserved. These bits must be written to their

reset default value (00000000000).

000

0000

4—0

M1ECNT[A—D][20:16]

M1ECNT[A—D][15:0]

M1 Error Count [20:16]. The value of the inter-

nal running counter is transferred into this hold-

ing register at the 0-to-1 transition of PMRST

signal. The counter is then reset to 0.

00000

0477, 0479, 15—0

M1 Error Count [15:0]. Same description as

0x0000

047B, 047D

above.

Table 89. Registers 0x047E—0x0485:Transmit F1, S1, K2, K1 OH InsertValue (R/W)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

047E, 0480, 15—8

0482, 0484

TF1DINS[A—D][7:0]

TS1DINS[A—D][7:0]

TK2DINS[A—D][7:0]

TK1DINS[A—D][7:0]

Transmit F1 Byte Value. Register value is

inserted into the transmit F1 byte.

0x00

7—0

Transmit S1 Byte Value. Register value is

inserted into the transmit S1 byte.

047F, 0481, 15—8

0483, 0485

Transmit K2 Byte Value. Register value is

inserted into the transmit K2 byte.

7—0

Transmit K1 Byte Value. Register value is

inserted into the transmit K1 byte.

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Data Sheet

May 2001

OHP Registers (continued)

Table 90. Registers 0x0486—0x0491: Receive F1, S1, K2, K1 Monitor Value (RO)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0486, 0489, 15—8

048C, 048F

0487, 048A, 15—8

048D, 0490

F1DMON1[A—D][7:0]

F1DMON0[A—D][7:0]

K2DMON[A—D[7:0]

K1DMON[A—D][7:0]

—

Receive F1 Previous Monitor Value.

Receive F1 Current Monitor Value.

Receive K2 Monitor Value.

0x00

7—0

Receive K1 Monitor Value.

0488, 048B, 15—8

Reserved. These bits must be written to their

048E, 0491

reset default value (0x00).

7—0

S1DMON[A—D][7:0]

Receive S1 Monitor Value.

0x00

Table 91. Registers 0x0492—0x04F9: Receive J0 MonitorValue (RO)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0492—0499 15—0 RJ0DMON[A][1—16][7:0] Receive J0 MonitorValue. Registers capture

0x0000

a 16-byte sequence from the J0 byte of each

channel. In STS-48/STM-16 mode,

J0DMON[A][1—16][7:0] is valid for J0 bytes

while J0DMON[B—D][1][7:0] are used for

Z0DMON[B—D][1][7:0].

04B2—04B9 15—0 RJ0DMON[B][1—16][7:0]

04D2—04D9 15—0 RJ0DMON[C][1—16][7:0

04F2—04F9 15—0 RJ0DMON[D][1—16][7:0]

Table 92. Registers 0x0512—0x0579: Transmit J0 Insert Value (R/W)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0512—0519 15—0

0532—0539 15—0

0552—0559 15—0

0572—0579 15—0

TJ0DINS[A][1—16][7:0]

TJ0DINS[B][1—16][7:0]

TJ0DINS[C][1—16][7:0]

TJ0DINS[D][1—16][7:0]

Transmit J0 Insert Value. Registers allow a

16-byte sequence to be inserted into the J0

byte of each channel. In STS-48/STM-16 mode,

TJ0DINS[A][1—16][7:0] is valid for J0 bytes

while TJ0DINS[B—D][1][7:0] are used for

TZ0DINS[B—D][1][7:0].

0x0000

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Data Sheet

May 2001

OHP Registers (continued)

Table 93. Registers 0x05AA—0x05C1:Transmit Z0 InsertValue (R/W)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

05AA—

0x05C1

—

TZ0DINS[A—D][2—12][7:0] Transmit Z0 Insert Value. Register values are

inserted into the transmit Z0 bytes. In STS-3/

STM-1 mode, TZ0DINS[A—D][2—3] are valid; in

STS-12/STM-4 mode, TZ0DINS[A—D][2—12]

are valid; and in STS-48/STM-16 mode, all 44

TZ0DINS bytes plus TJ0DINS[B—D][1][7:0] are

used for 47 Z0 byte values.

0x0000

05AA

15—8

7—0

TZ0DINS[A][2][7:0]

Transmit Z0 Insert A2 Value.

0x00

—

Reserved. These bits must be written to their

reset default value (0x00).

05AB—05AF 15—0

TZ0DINS[A][3—12][7:0]

TZ0DINS[B][2][7:0]

—

Transmit Z0 Insert [A][3—12]Value.

0x0000

0x00

05B0

15—8

7—0

Transmit Z0 Insert B2 Value.

Reserved. These bits must be written to their

0x00

reset default value (0x00).

05B1—05B5 15—0

TZ0DINS[B][3—12][7:0]

TZ0DINS[C][2][7:0]

—

Transmit Z0 Insert [B][3—12]Value.

0x0000

0x00

05B6

15—8

7—0

Transmit Z0 Insert C2 Value.

Reserved. These bits must be written to their

0x00

reset default value (0x00).

05B7—05BB 15—0

TZ0DINS[C][3—12][7:0] Transmit Z0 Insert [C][3—12]Value.

0x0000

0x00

05BC

15—8

7—0

TZ0DINS[D][2][7:0]

Transmit Z0 Insert D2 Value.

—

Reserved. These bits must be written to their

0x00

reset default value (0x00).

05BD—05C1 15—0

TZ0DINS[D][3—12][7:0] Transmit Z0 Insert [D][3—12]Value.

0x0000

Table 94. Register 0x05C2: Scratch Register (R/W)

Reset default of register = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

05C2

15—0

OHP_SCRATCH[15:0]

Scratch Register. Allows the control system to 0x0000

verify read and write operations to the device

without affecting device operation.

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Data Sheet

May 2001

PT Registers

This section gives a brief description of each register bit and its functionality. All algorithms are described in the

main text of the document. The abbreviations after each register indicate if the register is read only (RO), read/write

(R/W), write only (WO), or clear-on-read or clear-on-write (COR/W).

0x indicates a hexadecimal value in the Reset Default column. Otherwise, the entry is binary. This is true for every

Table 95. Register 0x0800: PT Macrocell Version Number (RO)

Reset default of register = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0800

15—8

7—0

—

Reserved. These bits must be written to their

reset default value (0x00).

0x00

PT_VERSION[7:0]

Macrocell Version Number. The version of the

macrocell will increment each time a change

occurs to the macrocell functionality.

0x00

Table 96. Register 0x0801: PT Interrupt (RO)

Reset default of register = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0801

15—4

—

Reserved. These bits must be written to their

0x000

reset default value (0x000).

PT_INT[D]

PT_INT[C]

PT_INT[B]

PT_INT[A]

Interrupt. Active-high interrupt bit on a per-port

basis. These bits are the ORing of all event and

delta bits associated with a particular port. An

event or delta bit contribution can be inhibited

from contributing to the interrupt by setting the

appropriate mask bit.

0x0

Table 97. Registers 0x0802, 0x080F, 0x081C, 0x0829 and 0x0803, 0x0810, 0x081D, 0x082A: PT Delta/Event

Parameters (COR/W)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0802, 080F,

081C, 0829

RJ1DMONMIS[A—D]E

Receive J1 Data Monitor Mismatch. Event bit

indicates a mismatch has occurred between the

expected J1 value and the received value.

14—12

11—0

—

Reserved. These bits must be written to their

reset default value (000).

000

RPIHD[A—D][1—12]

Receive Pointer Interpretation Hardware

Delta. Delta bits indicate a change of the

associated state bit.

0x000

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Data Sheet

May 2001

PT Registers (continued)

Table 97. Registers 0x0802, 0x080F, 0x081C, 0x0829 and 0x0803, 0x0810, 0x081D, 0x082A: PT Delta/Event

Parameters (COR/W) (continued)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0803, 0810,

081D, 082A

TRDIPD[A—D]

—

Transmit RDI-P Delta. Delta bit indicates a

change of the associated state byte.

14—11

Reserved. These bits must be written to their

0000

reset default value (0000).

RZ5DMOND[A—D]

RZ4DMOND[A—D]

RZ3DMOND[A—D]

RH4DMOND[A—D]

RF2DMOND[A—D]

RRDIPDMOND[A—D]

RC2DMOND[A—D]

RUC2D[A—D]

Receive Z5 Data Monitor Delta. Delta bit

indicates a change of the associated state byte.

Receive Z4 Data Monitor Delta. Delta bit

indicates a change of the associated state byte.

Receive Z3 Data Monitor Delta. Delta bit

indicates a change of the associated state byte.

Receive H4 Data Monitor Delta. Delta bit

indicates a change of the associated state byte.

Receive F2 Data Monitor Delta. Delta bit

indicates a change of the associated state byte.

Receive RDI-P Data Monitor Delta. Delta bit

indicates a change of the associated state bit.

Receive C2 Data Monitor Delta. Delta bit

indicates a change of the associated state byte.

Receive Unequipped C2 Values Delta. Delta

bit indicates a change of the associated state

bit.

RPPLMD[A—D]

Receive Path Payload Label Mismatch Delta.

Delta bit indicates a change of the associated

state bit.

RSDD[A—D]

RSFD[A—D]

Receive Signal Degrade Delta. Delta bit

indicates a change of the associated state bit.

Receive Signal Fail Delta. Delta bit indicates a

change of the associated state bit.

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Data Sheet

May 2001

PT Registers (continued)

Table 98. Registers 0x0836—0x083B, 0x0868—0x0887, 0x0888—0x088D, 0x08BA—0x08D9,

0x08DA—0x08DF, 0x090C—0x092B, 0x092C—0x0931, 0x095E—0x097D:

PT State Registers (RO)

Reset default of registers 0x0836, 0x0837, 0x0888, 0x0889, 0x08DA, 0x08DB, 0x092C, 0x092D = 0x0AAA.

Reset default of all other registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0836,

0888,

08DA,

092C

15—14

13—12

11—0

RSSDRP[A—D][1:0]

Receive SS Drop Values. SS bit values from

the four selected ports.

—

Reserved. These bits must be written to their

reset default value (00).

RPIH_STATE[A—D]

[1—6][1:0]

Receive Pointer Interpretation Hardware

State[Bits 1—6]. Software access to the 48

STS-1 PI state values. 00 = Normal;

01 = Concat; 10 = LOP; 11 = AIS.

0xAAA

0837,

0889,

08DB,

092D

15—12

11—0

—

Reserved. These bits must be written to their

reset default value (0x0).

0x0

RPIH_STATE[A—D]

[7—12][1:0]

Receive Pointer Interpretation Hardware

State[Bits 7—12]. Software access to the 48

STS-1 PI state values. 00 = Normal;

01 = Concat; 10 = LOP; 11 = AIS.

0xAAA

0838,

088A,

08DC,

092E

15—13

12—7

6—4

TRDIPINT[A—D][2:0]

Transmit RDI-P State. State bits indicating the

value of the inserted RDI-P value.

000

000000

000

—

Reserved. These bits must be written to their

reset default value (000000).

RRDIPDMON[A—D][2:0] Receive RDI-P Data Monitor State. State bits

indicating the value of the G1[3:1] bits.

RUC2VS[A—D]

RPPLMS[A—D]

RSDS[A—D]

Receive Unequipped C2 Value State. State

bit indicating an unequipped value (0x00) has

been detected in the C2 byte.

Receive Path Payload Label Mismatch State.

State bit indicating a mismatch occurred

(logic 1).

Receive Signal Degrade State Bit. State bit

indicating the state of the BER algorithm.

0 = within BER programmed, 1 = exceed BER

threshold programmed.

RSF[A—D]

Receive Signal Fail State Bit. State bit

indicating the state of the BER algorithm.

0 = within BER programmed, 1 = exceed BER

threshold programmed.

0839,

088B,

08DD,

092F

15—8

7—0

RF2DMON[A—D][7:0]

RC2DMON[A—D][7:0]

Receive F2 Byte Data Monitor. State byte

indicating the value of the validated F2 byte.

0x00

Receive C2 Data Monitor. State byte holding

the accepted value for the monitored C2 byte.

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Data Sheet

May 2001

PT Registers (continued)

Table 98. Registers 0x0836—0x083B, 0x0868—0x0887, 0x0888—0x088D, 0x08BA—0x08D9, 0x08DA—

0x08DF, 0x090C—0x092B, 0x092C—0x0931, 0x095E—0x097D: PT State Registers (RO)

(continued)

Reset default of registers 0x0836, 0x0837, 0x0888, 0x0889, 0x08DA, 0x08DB, 0x092C, 0x092D = 0x0AAA.

Reset default of all other registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

083A,

088C,

08DE,

0930

15—8

7—0

RZ3DMON[A—D][7:0]

RH4DMON[A—D][7:0]

RZ5DMON[A—D][7:0]

RZ4DMON[A—D][7:0]

Receive Z3 Byte Data Monitor. State byte

indicating the value of the validated Z3 byte.

0x00

Receive H4 Byte Data Monitor. State byte

indicating the value of the validated H4 byte.

0x00

083B,

088D,

08DF,

0931

15—8

7—0

Receive Z5 Byte Data Monitor. State byte

indicating the value of the validated Z5 byte.

0x00

Receive Z4 Byte Data Monitor. State byte

indicating the value of the validated Z4 byte.

0x00

0868—0887 15—0

08BA—08D9 15—0

RJ1DMON[A][1—64][7:0] Receive J1 Data Monitor Values. Status

registers for J1 storage.

0x0000

RJ1DMON[B][1—64][7:0]

090C—092B 15—0 RJ1DMON[C][1—64][7:0]

095E—097D 15—0 RJ1DMON[D][1—64][7:0]

Table 99. Register 0x097E: PT Interrupt Mask Control (R/W)

Reset default of register = 0x000F.

Address

(Hex)

Bit #

Name

Function

Reset

Default

097E

15—14

PT_FUNCMODE

Path Terminator Functional Mode. These bits

set the functional mode of the path terminator.

Only the values below are valid.

Bit 15 Bit 14 PT Function

normal mode

pass-through mode (ATM/SDL

over fiber)

13—4

—

Reserved. These bits must be written to their

reset default value (0000000000).

0000

PTINTM[D]

PTINTM[C]

PTINTM[B]

PTINTM[A]

Interrupt Masks. Mask bits to inhibit the

associated composite delta/event bits for each

port from contributing to the interrupt signal

from the PT macro. Setting these bits to 1

masks the interrupts.

0xF

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Data Sheet

May 2001

PT Registers (continued)

Table 100. Registers 0x097F—0x0980, 0x098C—0x098D, 0x0999—0x099A, 0x09A6—0x09A7: PT Interrupt

Mask Control (R/W)

Reset default of registers 0x097F, 0x098C, 0x0999, 0x09A6 = 0x8FFF.

Reset default of registers 0x0980, 0x098D, 0x099A, 0x09A7 = 0xFFFF.

Address

(Hex)

Bit #

Name

Function (All Mask Bits Are Active-High)

Reset

Default

097F, 098C,

0999, 09A6

RJ1DMONMISM[A—D]

Receive J1 Data Monitor Mismatch Mask.

Mask bit to inhibit the associated event bit from

contributing to the interrupt pin (INT).

14—12

11—0

—

Reserved. These bits must be written to their

reset default value (000).

000

RPIH_STATEM[A—D]

[1—12]

Receive Pointer Interpretation Hardware

Mask. Mask bits to inhibit the associated delta

bits from contributing to the interrupt pin (INT).

0xFFF

196

Agere Systems Inc.

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

PT Registers (continued)

Table 100. Registers 0x097F—0x0980, 0x098C—0x098D, 0x0999—0x099A, 0x09A6—0x09A7: PT Interrupt

Mask Control (R/W) (continued)

Reset default of registers 0x097F, 0x098C, 0x0999, 0x09A6 = 0x8FFF.

Reset default of registers 0x0980, 0x098D, 0x099A, 0x09A7 = 0xFFFF.

Address

(Hex)

Bit #

Name

Function (All Mask Bits Are Active-High)

Reset

Default

0980, 098D,

099A, 09A7

TRDIPINTM[A—D]

Transmit RDI-P Mask. Mask bit to inhibit the

associated delta bit from contributing to the

interrupt pin (INT).

14—11

—

Reserved. These bits must be written to their

reset default value (1111).

1111

RZ5DMONM[A—D]

Receive Z5 Data Monitor Mask. Mask bit to

inhibit the associated delta bit from contributing

to the interrupt pin (INT).

RZ4DMONM[A—D]

RZ3DMONM[A—D]

RH4DMONM[A—D]

RF2DMONM[A—D]

RRDIPDMONM[A—D]

RC2DMONM[A—D]

RUC2VM[A—D]

Receive Z4 Data Monitor Mask. Mask bit to

inhibit the associated delta bit from contributing

to the interrupt pin (INT).

Receive Z3 Data Monitor Mask. Mask bit to

inhibit the associated delta bit from contributing

to the interrupt pin (INT).

Receive H4 Data Monitor Mask. Mask bit to

inhibit the associated delta bit from contributing

to the interrupt pin (INT).

Receive F2 Data Monitor Mask. Mask bit to

inhibit the associated delta bit from contributing

to the interrupt pin (INT).

Receive RDI-P Data Monitor Mask. Mask bit

to inhibit the associated delta bit from

contributing to the interrupt pin (INT).

Receive C2 Value Mask. Mask bit to inhibit the

associated delta bit from contributing to the

interrupt pin (INT).

Receive Unequipped C2 Values Mask. Mask

bit to inhibit the associated delta bit from

contributing to the interrupt pin (INT).

RPPLMM[A—D]

Receive Path Payload Label Mismatch Mask.

Mask bit to inhibit the associated delta bit from

contributing to the interrupt pin (INT).

RSDM[A—D]

Receive Signal Degrade Mask. Mask bit to

inhibit the associated delta bit from contributing

to the interrupt pin (INT).

RSFM[A—D]

Receive Signal Fail Mask. Mask bit to inhibit

the associated delta bit from contributing to the

interrupt pin (INT).

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Data Sheet

May 2001

PT Registers (continued)

Table 101. Registers (0x09B3, 0x09BF, 0x09CB, 0x09D7, 0x09E3), (0x09EF, 0x09FB, 0x0A07, 0x0A14,

0x0A20), (0x0A2C, 0x0A38, 0x0A44, 0x0A50, 0x0A5C), (0x0A68, 0x0A74, 0x0A80, 0x0A8C,

0x0A98): Error Counters (RO)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

09B3, 09EF, 15—11

—

Reserved. These bits must be written to their

00000

reset default value (00000).

0A2C, 0A68

10—0

RPI_INC[A—D][10:0]

Receive Pointer Interpreter Increment

Counter. Counter that counts the number of

increments that occurred on the selected time

slot.

000

0000

09BF, 09FB, 15—11

0A38, 0A74

—

Reserved. These bits must be written to their

reset default value (00000).

00000

10—0

RPI_DEC[A—D][10:0]

Receive Pointer Interpreter Decrements

Counter. Counter that counts the number of

decrements that occurred on the selected time

slot.

000

0000

09CB, 0A07, 15—13

—

Reserved. These bits must be written to their

000

reset default value (000).

0A44, 0A80

12—0

RNDFCNT[A—D][12:0]

Receive Pointer Interpreter NDF Counter.

Counter that counts the number of set NDF

(1001) values received on the selected time

slot.

0000

09D7, 0A14, 15—0 RB3ERRCNT[A—D][15:0] B3 Error Count. Number of B3 errors detected 0x0000

on the monitored STS-1 time slots.

0A50, 0A8C

09E3, 0A20, 15—0

0A5C, 0A98

RREIPERRCNT

[A—D][15:0]

Receive Remote Error Indication—Path

Error Count. Count of the number of B3 errors

detected in the G1[7:4] nibble.

0x0000

Table 102. Register 0x0AA4: PT One-Shot Control Parameters (WO)

Address

(Hex)

Bit #

Name

Function

Reset

Default

0AA4

15—12

11—8

7—4

SDCLEAR[A—D]

SDSET[A—D]

Signal Degrade Clear. One-shot clear control.

Signal Degrade Set. One-shot set control.

Signal Fail Clear. One-shot clear control.

Signal Fail Set. One-shot set control.

—

SFCLEAR[A—D]

SFSET[A—D]

3—0

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Data Sheet

May 2001

PT Registers (continued)

Table 103. Registers 0x0AA6—0x0AAD, 0x0AAE, 0x0AB5, 0x0AB6—0x0ABD, 0x0ABE—0x0AC5: PT Control

Parameters (R/W)

Reset default of registers 0x0AA6, 0x0AAE, 0x0AB6, 0x0ABE = 0x1200.

Reset default of registers 0x0AA7, 0x0AAF, 0x0AB7, 0x0ABF = 0x0000.

Reset default of registers 0x0AA8, 0x0AB0, 0x0AB8, 0x0AC0 = 0x0FFF.

Reset default of registers 0x0AA9, 0x0AB1, 0x0AB9, 0x0AC1 = 0x0000.

Reset default of registers 0x0AAA, 0x0AB2, 0x0ABA, 0x0AC2 = 0x0000.

Reset default of registers 0x0AAB, 0x0AB3, 0x0ABB, 0x0AC3 = 0x1AAA.

Reset default of registers 0x0AAC, 0x0AB4, 0x0ABC, 0x0AC4 = 0x3AAA.

Reset default of registers 0x0AAD, 0x0AB5, 0x0ABD, 0x0AC5 = 0x3333.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0AA6, 0AAE, 15—12

0AB6, 0ABE

RPOHMONSEL

Receive POH Monitor Select. Control bit selects which

of the 12 time-slot POH bytes are monitored in the

associated data stream. A total of four

0001

[A—D][3:0]

STS-Nc streams can be monitored at any one time.

Only values from 0001 (time slot 1) to 1100

(time slot 12) are valid. For quad OC-3 and quad OC-12

mode, use the default value 0001.

11—10

—

Reserved. These bits must be written to their reset

default value (00).

RCONC_ALLOR

FIRST[A—D]

Receive Concatenation State: Use All STS-1 Time

Slots or Just the First One. If set to 1, all STS-1 time

slots are used. If set to 0, a higher level state machine

(CONC) is used to process the individual states from

the associated time slots. The higher-order state

machine is defined as follows.

CONC State Equations (ETSI and G.783 (SDH)):

States

Concatenation States (bold states are reported)

AISX

AIS#1 AND AISC#2 AND . . . AISC#X

NORMX NORM#1 AND CONC#2 AND . . . CONC#N

INCX*

DECX*

NDFX*

LOPX

INC#1 AND CONC#2 AND . . . CONC#N

DEC#1 AND CONC#2 AND . . . CONC#N

NDF#1 AND CONC#2 AND . . . CONC#N

(Any other): NOT AISX

AND NOT NORMX

AND NOT INCX

AND NOT DECX

AND NOT NDFX

* States INCX, DECX, and NDFX are considered the same as

NORMX state in terms of reporting.

8—7

RJ1FRAMEA

[A—D][1:0]

Receive J1 Frame Algorithm. Control bits, when set to

00 or 11 = no framing; 01 = SONET framing; 10 = SDH

framing.

* These bits maintain the validated J1 byte, place 0x0000 into all other POH bytes, and invalidate the received payload so that no data is passed

through the DE. These bits do not affect the transmit path and do not affect the transmitted G1 byte.

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Data Sheet

May 2001

PT Registers (continued)

Table 103. Registers 0x0AA6—0x0AAD, 0x0AAE, 0x0AB5, 0x0AB6—0x0ABD, 0x0ABE—0x0AC5: PT Con-

trol Parameters (R/W) (continued)

Reset default of registers 0x0AA6, 0x0AAE, 0x0AB6, 0x0ABE = 0xF200.

Reset default of registers 0x0AA7, 0x0AAF, 0x0AB7, 0x0ABF = 0x0000.

Reset default of registers 0x0AA8, 0x0AB0, 0x0AB8, 0x0AC0 = 0x0FFF.

Reset default of registers 0x0AA9, 0x0AB1, 0x0AB9, 0x0AC1 = 0x0000.

Reset default of registers 0x0AAA, 0x0AB2, 0x0ABA, 0x0AC2 = 0x0000.

Reset default of registers 0x0AAB, 0x0AB3, 0x0ABB, 0x0AC3 = 0x1AAA.

Reset default of registers 0x0AAC, 0x0AB4, 0x0ABC, 0x0AC4 = 0x3AAA.

Reset default of registers 0x0AAD, 0x0AB5, 0x0ABD, 0x0AC5 = 0x3333

Address

(Hex)

Bit #

Name

Function

Reset

Default

0AA6,0AAE,

0AB6, 0ABE

RJ1DMPC[A—D]

Receive J1 Dump Control. Control bit, when set

to a logic 1, causes the device to store the J1 byte

of the selected STS-1 time slot.

—

Reserved. This bit must be written to its reset

default value (0).*

RB3BITBLKCNT[A—D] Receive B3 Bit/Block Count. Control bit, when

set to a logic 0, causes the B3 error counter to

count bit errors; otherwise, block errors are

counted.

RINCDEC_6OR8MAJ

Receive Increment/Decrement 6-or-8 Majority

Voting. If programmed to a logic 0, uses 6 of 10

majority voting to determine a valid increment or

decrement; otherwise, uses 8 of 10 majority voting.

[A—D]

2—1

—

Reserved. These bits must be written to their reset

default value (00).

RDIPMON_ENH_OR1B Remote Defect Indication Enhanced or 1-Bit

Monitoring. Control bit, when set to a logic 1,

causes the RDI-P to detect G1[3:1] bits for an

enhanced failure code; otherwise, monitors G1[3]

for a 1-bit code.

[A—D]

0AA7, 0AAF, 15—12

0AB7, 0ABF

RFORCE_LOP[A—D]

[1—4]

Receive FORCE_LOP. Control bits, when set to a

logic 1, force the associated time slot into the LOP

state; otherwise, does nothing.^†

0x0

11—0

CONCATI_EXPECTED Concatenation Indication Expected. Control bits, 0x000

when set to 0 = do not expect associated time slot

to be in CONC mode; otherwise, expect CONC

mode.

[A—D][1—12]

* SS pointer interpretation algorithm is not implemented.

†These bits maintain the validated J1 byte, place 0x0000 into all other POH bytes, and invalidate the received payload so that no data is passed