USS344S-DB [AGERE]
USS-344 QuadraBus Four-Host PCI-to-USB OpenHCL Host Controller; USS -344 QuadraBus四台主机的PCI到USB OpenHCL主机控制器
| 型号： | USS344S-DB |
| 厂家： | 
AGERE SYSTEMS |
| 描述： | USS-344 QuadraBus Four-Host PCI-to-USB OpenHCL Host Controller |
| 文件： | 总54页 (文件大小：798K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Advance Data Sheet, Rev. 9
June 2001
USS-344 QuadraBus™
Four-Host PCI-to-USB OpenHCI Host Controller
Features
Description
I 32-bit, 33 MHz PCI interface compliant with PCI Local
The Agere Systems Inc. USS-344 QuadraBus provides
a single-chip four-host PCI-to-Universal Serial Bus
(USB) solution. The USS-344 interfaces directly to any
32-bit, 33 MHz PCI bus and is ideal for either onboard
applications or add-in card applications. It can easily be
configured to communicate in either a 3 V PCI environ-
ment or 5 V PCI environment simply by selecting the
appropriate communications voltage level on the VIO
input pin.
The USS-344 provides four downstream USB ports for
connectivity with any USB compliant device or hub. Full-
speed or low-speed peripherals are supported along
with all of the USB transfer types: control, interrupt,
bulk, or isochronous. The USS-344’s OpenHCI compli-
ance offers significant USB performance benefits and
reduced CPU overhead compared to other USB UHCI
host controllers.
In addition, the USS-344 offers a significant perfor-
mance advantage over all other USB host controllers
(both UHCI and OHCI) by providing full USB bandwidth
to each port rather than sharing the USB bandwidth
over all ports. This results in an increase in the number
of devices which can feasibly be connected to a
computer system as well as ensuring high-bandwidth
devices, such as video cameras and audio devices, are
always provided with the high bandwidth they need
while other USB devices are in use.
The USS-344 is a multifunction PCI device with one
single-port USB host controller per PCI function. There
are four PCI functions in the USS-344 for a total of four
single-port USB host controllers. Each single-port host
controller provides the full USB bandwidth (12 Mbits/s)
for devices connected downstream of its port.
Bus Specification Revision 2.2
I Four downstream USB ports
I Each USB port dedicated to providing full USB band-
width to the attached device
I Full compliance with Universal Serial Bus Specifica-
tion Revision 1.1
I OpenHCI Open Host Controller Interface Specifica-
tion for USB Release 1.0a compatible
I Fully compatible with Microsoft Windows 98/95/Win-
dows NT *standard OpenHCI drivers
I Fully compatible with Mac† OS 8.5 and 8.6
I Integrated dual-speed USB transceivers
I 3 V or 5 V switchable PCI signaling
I Low-power mode and wake-up compatible with PCI
Power Management Interface Specification Revision
1.1
I Supports up to 127 devices per port
I Supports peripheral hot swap and wake-up
I Support for legacy keyboard and mouse
I 128-pin TQFP package
I Full 12 Mbits/s bandwidth per port
I Evaluation kit:
— PCI card
— Data sheet
I 0.25 µm technology
Applications
I Seamless integration with 3 V or 5 V PCI-based com-
puter products
I Supports all USB compliant devices and hubs
The USS-344 is fully compatible with the Microsoft
Windows standard OpenHCI drivers. The USS-344
pinout is compatible with the future release of the Agere
USB 2.0 host controller.The USS-344 is a 3.3 V device
fabricated in 0.25 µm technology. Integrated dual-speed
USB transceivers enable a single-chip PCI-to-USB
solution. The USS-344 provides full support for legacy
PC peripherals as defined in the OpenHCI Open Host
Controller Interface Specification for USB Release 1.0a.
I Simultaneous operation of multiple high-performance
devices
* Microsoft, Windows, and Windows NT are registered trademarks
of Microsoft Corporation.
†Mac is a registered trademark of Apple Computer, Inc.
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
Table of Contents
Contents
Page
Features .................................................................................................................................................................. 1
Applications ............................................................................................................................................................. 1
Description ............................................................................................................................................................... 1
Applicable Documents and Specifications ............................................................................................................... 4
Pin Information ........................................................................................................................................................ 4
Register Overview ................................................................................................................................................... 8
PCI Registers ........................................................................................................................................................ 12
PCI Function 0—Single-Port USB Host Controller 0 .......................................................................................12
PCI Function 1—Single-Port USB Host Controller 1 .......................................................................................16
PCI Function 2—Single-Port USB Host Controller 2 .......................................................................................20
PCI Function 3—Single-Port USB Host Controller 3 .......................................................................................24
USB Registers ....................................................................................................................................................... 28
Legacy Support Registers ..................................................................................................................................... 35
HceInput Register............................................................................................................................................35
HceOutput Register.........................................................................................................................................36
HceStatus Register..........................................................................................................................................36
HceControl Register ........................................................................................................................................37
Connection Instructions ......................................................................................................................................... 37
PCI Connection Instructions............................................................................................................................37
USB Connection Instructions...........................................................................................................................38
Test Mode Connection Instructions .................................................................................................................38
Legacy Configuration ............................................................................................................................................. 40
Power Connection Recommendations .................................................................................................................. 41
Power Management Interface ............................................................................................................................... 42
Configuration Space Offset 50h.......................................................................................................................43
Configuration Space Offset 51h.......................................................................................................................43
Configuration Space Offset 52h.......................................................................................................................44
Configuration Space Offset 54h.......................................................................................................................44
Configuration Space Offset 56h.......................................................................................................................45
Configuration Space Offset 57h.......................................................................................................................45
Power Consumption/Dissipation Reporting .....................................................................................................45
NAND Tree Mode .................................................................................................................................................. 46
Absolute Maximum Ratings ................................................................................................................................... 48
Electrical Characteristics ....................................................................................................................................... 49
PCI Electrical Characteristics ..........................................................................................................................49
USB Electrical Characteristics.........................................................................................................................52
Physical Markings .................................................................................................................................................. 53
Outline Diagram ..................................................................................................................................................... 53
128-Pin TQFP..................................................................................................................................................53
Ordering Information .............................................................................................................................................. 54
2
Agere Systems Inc.
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
Description (continued)
USS-344 PCI-TO-USB OpenHCI HOST CONTROLLER
ADDRESS
DATA
USB
ROOT
HUB
AND
HOST
SIE
STATE
HCI
TX
RX
OHCI
ROOT
HUB
CONTROL
SLAVE
BLOCK
CONTROL
PORT
1
LIST
PROCESSOR
BLOCK
DATA
HSIE
S/M
HCI
ADDRESS/
DATA
MASTER
BLOCK
FIFO
DPLL
CONTROL
MIRQ121
KIRQ1I
A20I
LEGACY
IRQ1
SUPPORT
IRQ12
A20MN
SMIN
POWER
MNGMNT
LOGIC
CLK48STOP
PMEN
LEGACY
LOGIC
USB HOST CONTROLLER
POWER
MNGMNT
USB
USB
USB
USB
PCI CORE 0
CORE 0
LEGACY
LOGIC
USB HOST CONTROLLER
POWER
MNGMNT
AD[31:0]
CBE[3:0]
REQN
PCI
PCI CORE 1
CORE 1
ARBITER
GNTN
IDSEL
FRAMEN
IRDYN
LEGACY
LOGIC
USB HOST CONTROLLER
POWER
TRDYN
DEVSELN
STOPN
PERRN
SERRN
PAR
MNGMNT
PCI CORE 2
CORE 2
LEGACY
LOGIC
USB HOST CONTROLLER
POWER
MNGMNT
INTA
INTB
INTC
INTD
PCI CORE 3
CORE 3
5-7828.r1
Figure 1. USS-344 Interconnection Diagram
Agere Systems Inc.
3
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
Applicable Documents and Specifications
I PCI Local Bus Specification Revision 2.1s., June 1, 1995. PCI Special Interest Group.
I Universal Serial Bus Specification Revision 1.1., September 23, 1998. Compaq/Digital Equipment Corporation/
IBM PC Company/Intel/Microsoft/NEC/Northern Telecom.
I OpenHCI Open Host Controller Interface Specification for USB Release 1.0a., July 31, 1997. Compaq/Microsoft/
National Semiconductor.
I PCI Bus Power Management Interface Specification Revision 1.1., December 18, 1998. PCI Special Interest
Group.
Pin Information
VDD
VSS
1
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
PWRFLT2N
PRTPWR2
VSST
2
AD24
C/BEN3
IDSEL
AD23
AD22
VSS
3
VDDT
4
DMNS3
DPLS3
DMNS2
DPLS2
VSST
5
6
7
8
VDD
9
AD21
AD20
AD19
AD18
VSS
VDDT
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
DMNS1
DPLS1
DMNS0
DPLS0
VSST
VDD
AD17
AD16
C/BEN2
FRAMEN
VDD
VDDT
RREF
VDDA
XHI
USS-344
XLO/CLK48
VSSA
VSS
IRDYN
TRDYN
DEVSELN
STOPN
PERRN
VSS
CLK48STOP
VDD
PWRFLT1N
PRTPWR1
PWRFLT0N
PRTPWR0
SMIN
VDD
SERRN
PAR
VSS
VDD
C/BEN1
AD15
VDD
IRQ12
IRQ1
A20MN
A20I
VSS
AD14
AD13
AD12
AD11
KIRQ1I
MIRQ12I
VSS
VDD
5-7830
Figure 2. USS-344 Pin Diagram
4
Agere Systems Inc.
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
Pin Information (continued)
Table 1. Numeric Pin Cross Reference
Pin
Symbol*
Pin
Symbol*
Pin
Symbol*
Pin
Symbol*
1
VDD
VSS
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
VDD
VSS
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
VDD
VSS
MIRQ12I
KIRQ1I
A20I
A20MN
IRQ1
IRQ12
97
DPLS3
DMNS3
VDDT
2
98
3
AD24
C/BEN3
IDSEL
AD23
AD22
VSS
AD14
AD13
AD12
AD11
VDD
99
4
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
VSST
5
PRTPWR2
PWRFLT2N
PRTPWR3
PWRFLT3N
INTAN
VDD
6
7
8
VSS
9
VDD
AD10
AD9
VDD
VSS
SMIN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AD21
AD20
AD19
AD18
VSS
AD8
VSS
C/BEN0
VSS
PRTPWR0
PWRFLT0N
PRTPWR1
PWRFLT1N
VDD
CLK48STOP
VSSA
INTBN
INTCN
INTDN
RSTN
VDD
VDD
VDD
AD7
AD17
AD16
C/BEN2
FRAMEN
VDD
AD6
AD5
CLK
VSS
GNTN
REQN
VSS
VDD
PMEN
AD31
AD30
AD29
AD4
VSS
XLO/CLK48
XHI
VDD
VSS
AD3
VDDA
RREF
IRDYN
TRDYN
DEVSELN
STOPN
PERRN
VSS
AD2
AD1
VDDT
VSST
DPLS0
DMNS0
DPLS1
DMNS1
VDDT
VSST
DPLS2
DMNS2
AD0
VSS
VIO
VDD
VSS
VSS
VDD
VDD
SERRN
PAR
C/BEN1
AD15
TEST0
TEST1
TEST2
TEST3
AD28
AD27
AD26
AD25
* Pins identified as NC are unused and should be left unconnected. Active-low signals within this document are indicated by an N following the
symbol names.
Agere Systems Inc.
5
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
Pin Information (continued)
Table 2. PCI Signals
Pin
Symbol*
Type
Input
Input
Description
PCI Reset (Active-Low).
PCI System Clock (33 MHz).
111
113
116
115
RSTN
CLK
REQN
GNTN
Output/3-State PCI Request (Active-Low).
Input
Bidir
PCI Grant (Active-Low).
PCI Address and Data.
120, 121, 122, 125, 126, 127, 128, AD[31:0]
3, 6, 7, 10, 11, 12, 13, 16, 17, 32,
35, 36, 37, 38, 41, 42, 43, 47, 48,
49, 50, 53, 54, 55, 56
30
PAR
C/BEN[3:0]
FRAMEN
IRDYN
TRDYN
STOPN
IDSEL
DEVSELN
PERRN
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Input
Bidir
Bidir
PCI Parity.
4, 18, 31, 44
PCI Bus Command and Byte Enables.
PCI Cycle Frame (Active-Low).
PCI Initiator Ready (Active-Low).
PCI Target Ready (Active-Low).
PCI Stop (Active-Low).
PCI Initialization Device Select.
PCI Device Select (Active-Low).
PCI Parity Error (Active-Low).
19
22
23
25
5
24
26
29
SERRN Output/Open Drain PCI System Error (Active-Low).
INTAN Output/Open Drain PCI Interrupt A (Active-Low).
INTBN Output/Open Drain PCI Interrupt B (Active-Low).
INTCN Output/Open Drain PCI Interrupt C (Active-Low).
INTDN Output/Open Drain PCI Interrupt D (Active-Low).
PMEN
VDD
105
108
109
110
119
Output/Open Drain Power Management Event (Active-Low).
1, 9, 15, 20, 28, 33, 39, 46, 52, 59,
65, 73, 80, 106, 112, 118, 124
2, 8, 14, 21, 27, 34, 40, 45, 51, 57,
60, 66, 74, 107, 114, 117, 123
58
Power
Power
Power
3.3 V VDD.
VSS
VIO
VSS.
PCI Environment Selection (3.3 V or 5 V).
* An N following the symbol names indicates active-low for the USS-344.
Table 3. USB Port Signals
Pin
Symbol*
Type
Description
89
DPLS0
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
USB Port 0 DPLUS.
90
DMNS0
USB Port 0 DMINUS.
91
DPLS1
USB Port 1 DPLUS.
92
DMNS1
USB Port 1 DMINUS.
95
DPLS2
USB Port 2 DPLUS.
96
DMNS2
USB Port 2 DMINUS.
97
DPLS3
USB Port 3 DPLUS.
98
DMNS3
USB Port 3 DMINUS.
76
PRTPWR0
PRTPWR1
PRTPWR2
PRTPWR3
USB Port 0 Power Enable (Active-Low).
USB Port 1 Power Enable (Active-Low).
USB Port 2 Power Enable (Active-Low).
USB Port 3 Power Enable (Active-Low).
78
101
103
* An N following the symbol names indicates active-low for the USS-344.
6
Agere Systems Inc.
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
Pin Information (continued)
Table 3. USB Port Signals (continued)
Pin
77
79
102
104
81
Symbol*
Type
Description
PWRFLT0N
PWRFLT1N
PWRFLT2N
PWRFLT3N
CLK48STOP
Input
Input
Input
Input
Bidir
USB Port 0 Overcurrent (Active-Low).
USB Port 1 Overcurrent (Active-Low).
USB Port 2 Overcurrent (Active-Low).
USB Port 3 Overcurrent (Active-Low).
USB Clock Stop (Optional). Used to stop external
48 MHz clock in PCI power management state D3.
USB Transceiver VDD (3.3 V).
87, 93, 99
88, 94, 100
86
VDDT
VSST
RREF
Power
Power
Input
USB Transceiver VSS.
USB 2.0 1 kΩ Precision Resistor Connection. Hi-Z if
implementation does not expect upgrade to USB 2.0.
USB 2.0 Analog Power. Connect to VDD if implementa-
tion does not expect upgrade to USB 2.0.
USB 2.0 Analog Power. Connect to VSS if implementa-
tion does not expect upgrade to USB 2.0.
USB 2.0 Crystal Oscillator XHI Connection. Hi-Z if
implementation does not expect upgrade to USB 2.0.
USB 2.0 Crystal Oscillator XHI Connection/USB 1.X
CLK 48 MHz Input.
85
82
84
83
VDDA
VSSA
Power
Power
XHI
Power
XLO/CLK48
Power/Input
* An N following the symbol names indicates active-low for the USS-344.
Table 4. Legacy Support Signals
Pin
68
Symbol*
KIRQ1I
Type
Input
Description
Legacy Keyboard Controller Interrupt (IRQ1 Input from
Keyboard Controller).
67
MIRQ12I
Input
Legacy Mouse Controller Interrupt (IRQ12 Input from
Mouse Controller).
69
70
71
72
75
A20I
A20MN
IRQ1
IRQ12
SMIN
Input
Legacy Gate A20 Input.
Output/Open Drain Legacy Gate A20 Output (to Memory Controller).
Output/Open Drain System Keyboard Interrupt (Active-High).
Output/Open Drain System Mouse Interrupt (Active-High).
Output/Open Drain System Management Interrupt (Active-Low).
* An N following the symbol names indicates active-low for the USS-344.
Table 5. Chip Test Signals
Pin
61
Symbol*
TEST0
Type
Input
Description
Chip Test Signal. Refer to Test Mode Connection
Instructions section for usage information.
Chip Test Signal. Refer to Test Mode Connection
Instructions section for usage information.
Chip Test Signal. Refer to Test Mode Connection
Instructions section for usage information.
Chip Test Signal. Refer to section Test Mode Connection
Instructions for usage information.
62
63
64
TEST1
TEST2
TEST3
Input
Input
Input
* An N following the symbol names indicates active-low for the USS-344.
Agere Systems Inc.
7
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
Register Overview
Table 6. PCI Bus Configuration Memory Summary (Function 0)
Refer to Tables 10—31 for more details on each of these registers.
Configuration Space Offset
Register Name
Read/Write
Default Value (Reset)
11C1h
5803h
0000h
TEST1 = 0b: 0210h
TEST1 = 1b: 0200h
10h
00h—01h
02h—03h
04h—05h
06h—07h
Vendor ID
Device ID
Command
Status
R
R
R/W
R/W
08h
Revision ID*
Class Code
Cache Line Size
Latency Timer
Header Type
BIST
R
R
R
R/W
R
R
09h—0Bh
0Ch
0C0310h
00h
0Dh
00h
0Eh
80h
0Fh
00h
10h—13h
14h—17h
18h—1Bh
1Ch—1Fh
20h—23h
24h—27h
28h—2Bh
2Ch—2Dh
2Eh—2Fh
30h—33h
34h
BAR 0
R/W
R
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
11C1h
BAR 1
BAR 2
R
BAR 3
R
BAR 4
R
BAR 5
R
CardBus CIS Pointer
Subsystem Vendor ID
Subsystem ID
Expansion ROM Base Address
Capabilities Pointer
R
R/W†
R/W†
R
5803h
00000000h
R
TEST1 = 0b: 50h
TEST1 = 1b: 00h
3Ch
3Dh
3Eh
3Fh
4Ch
Interrupt Line
Interrupt Pin
R/W
R
R
R
R/W
00h
01h
Min_Gnt
Max_Lat
03h
56h
Special—Subsystem Write Capability
00000000h
* The revision can be identified electronically using the standard PCI Revision ID register described in this table. The revision can also be iden-
tified by physical markings using the last letter of the USS-344 identifier code printed on the device. The USS-344 identifier code will be
printed using the format USS344XY, where X will identify the package type (T) and Y will identify the revision.
†This register is normally read only. Write capability of this register is available to system BIOS only.
8
Agere Systems Inc.
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
Register Overview (continued)
Table 7. PCI Bus Configuration Memory Summary (Function 1)
Refer to Tables 32—53 for more details on each of these registers.
Configuration Space Offset
Register Name
Read/Write
Default Value (Reset)
00h—01h
02h—03h
04h—05h
06h—07h
Vendor ID
Device ID
Command
Status
R
11C1h
R
5803h
R/W
R/W
0000h
TEST1 = 0b: 0210h
TEST1 = 1b: 0200h
08h
Revision ID*
Class Code
R
R
R
R/W
R
R
10h
09h—0Bh
0Ch
0C0310h
00h
Cache Line Size
Latency Timer
Header Type
BIST
0Dh
00h
0Eh
80h
0Fh
00h
10h—13h
14h—17h
18h—1Bh
1Ch—1Fh
20h—23h
24h—27h
28h—2Bh
2Ch—2Dh
2Eh—2Fh
30h—33h
34h
BAR 0
R/W
R
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
11C1h
BAR 1
BAR 2
R
BAR 3
R
BAR 4
R
BAR 5
R
CardBus CIS Pointer
Subsystem Vendor ID
Subsystem ID
Expansion ROM Base Address
Capabilities Pointer
R
R/W†
R/W†
R
5803h
00000000h
TEST1 = 0b: 50h
TEST1 = 1b: 00h
00h
TEST0 = 0b: 01h
TEST0 = 1b: 02h
03h
56h
00000000h
R
3Ch
3Dh
Interrupt Line
Interrupt Pin
R/W
R
3Eh
3Fh
4Ch
Min_Gnt
Max_Lat
R
R
R/W
Special—Subsystem Write Capability
* The revision can be identified electronically using the standard PCI Revision ID register described in this table. The revision can also be iden-
tified by physical markings using the last letter of the USS-344 identifier code printed on the device. The USS-344 identifier code will be
printed using the format USS344XY, where X will identify the package type (T) and Y will identify the revision.
†This register is normally read only. Write capability of this register is available to system BIOS only.
Agere Systems Inc.
9
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
Register Overview (continued)
Table 8. PCI Bus Configuration Memory Summary (Function 2)
Refer to Tables 54—75 for more details on each of these registers.
Configuration Space Offset
Register Name
Read/Write
Default Value (Reset)
11C1h
5803h
0000h
TEST1 = 0b: 0210h
TEST1 = 1b: 0200h
10h
00h—01h
02h—03h
04h—05h
06h—07h
Vendor ID
Device ID
Command
Status
R
R
R/W
R/W
08h
Revision ID*
Class Code
Cache Line Size
Latency Timer
Header Type
BIST
R
R
R
R/W
R
R
09h—0Bh
0Ch
0C0310h
00h
0Dh
00h
0Eh
80h
0Fh
00h
10h—13h
14h—17h
18h—1Bh
1Ch—1Fh
20h—23h
24h—27h
28h—2Bh
2Ch—2Dh
2Eh—2Fh
30h—33h
34h
BAR 0
R/W
R
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
11C1h
BAR 1
BAR 2
R
BAR 3
R
BAR 4
R
BAR 5
R
CardBus CIS Pointer
Subsystem Vendor ID
Subsystem ID
Expansion ROM Base Address
Capabilities Pointer
R
R/W†
R/W†
R
5803h
00000000h
R
TEST1 = 0b: 50h
TEST1 = 1b: 00h
3Ch
3Dh
Interrupt Line
Interrupt Pin
R/W
R
00h
TEST0 = 0b: 01h
TEST0 = 1b: 03h
3Eh
3Fh
4Ch
Min_Gnt
Max_Lat
R
R
R/W
03h
56h
Special—Subsystem Write Capability
00000000h
* The revision can be identified electronically using the standard PCI Revision ID register described in this table. The revision can also be iden-
tified by physical markings using the last letter of the USS-344 identifier code printed on the device. The USS-344 identifier code will be
printed using the format USS344XY, where X will identify the package type (T) and Y will identify the revision.
†This register is normally read only. Write capability of this register is available to system BIOS only.
10
Agere Systems Inc.
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
Register Overview (continued)
Table 9. PCI Bus Configuration Memory Summary (Function 3)
Refer to Tables 76—97 for more details on each of these registers.
Configuration Space Offset
Register Name
Read/Write
Default Value (Reset)
00h—01h
02h—03h
04h—05h
06h—07h
Vendor ID
Device ID
Command
Status
R
11C1h
R
5803h
R/W
R/W
0000h
TEST1 = 0b: 0210h
TEST1 = 1b: 0200h
08h
Revision ID*
Class Code
R
R
R
R/W
R
R
10h
09h—0Bh
0Ch
0C0310h
00h
Cache Line Size
Latency Timer
Header Type
BIST
0Dh
00h
0Eh
80h
0Fh
00h
10h—13h
14h—17h
18h—1Bh
1Ch—1Fh
20h—23h
24h—27h
28h—2Bh
2Ch—2Dh
2Eh—2Fh
30h—33h
34h
BAR 0
R/W
R
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
11C1h
BAR 1
BAR 2
R
BAR 3
R
BAR 4
R
BAR 5
R
CardBus CIS Pointer
Subsystem Vendor ID
Subsystem ID
Expansion ROM Base Address
Capabilities Pointer
R
R/W†
R/W†
R
5803h
00000000h
TEST1 = 0b: 50h
TEST1 = 1b: 00h
00h
TEST0 = 0b: 01h
TEST0 = 1b: 04h
03h
56h
00000000h
R
3Ch
3Dh
Interrupt Line
Interrupt Pin
R/W
R
3Eh
3Fh
4Ch
Min_Gnt
Max_Lat
R
R
R/W
Special—Subsystem Write Capability
* The revision of the USS-344 can be identified either electronically or by physical markings. The revision can be identified electronically using
the standard PCI Revision ID register described in this table. The revision can also be identified by physical markings using the last letter of
the USS-344 identifier code printed on the device. The USS-344 identifier code will be printed using the format USS344XY, where X will iden-
tify the package type (T) and Y will identify the revision.
†This register is normally read only. Write capability of this register is available to system BIOS only.
Agere Systems Inc.
11
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
PCI Registers
PCI Function 0—Single-Port USB Host Controller 0
Table 10. Vendor ID Register (00h—01h)
This register is fixed as the Agere Systems vendor ID assigned by the PCI SIG.
Bits
Field
Vendor ID
Read/Write
Reset/Description
Assigned 11C1h
15:0
R
Table 11. Device ID Register (02h—03h)
This register is fixed as the Agere Systems product USS-344.
Bits Field Read/Write
Device ID
Reset/Description
Assigned 5803h
15:0
R
Table 12. Command Register (04h—05h)
All read-only bits represent nonconfigurable features of the USS-344.
Bits Field Read/Write
Reset/Description
0
1
2
3
4
IO Space
R/W
R/W
R/W
R
0
0
0
0
0
Memory Space
Bus Master
Special Cycles
Memory Write and
Invalidate Enable
VGA Palette Snoop
R/W
5
6
7
8
9
R
0
0
0
0
0
Parity Error Response R/W
Wait Cycle Control
SERRN Enable
Fast Back-to-back
Enable
R
R/W
R/W
15:10
Reserved
R
000000b
Table 13. Status Register (06h—07h)
All read-only bits represent nonconfigurable features of the USS-344.
Bits Field Read/Write
Reset/Description
3:0
Reserved
R
0000b
4
Capabilities
R
TEST1 = 0b: 1
TEST1 = 1b: 0
5
6
7
66 MHz Capable
UDF Support
Fast Back-to-back
Capable
R
R
R
0
0
0
8
Data Parity Error
Detected
R/W
0
10:9
11
DEVSEL Timing
R
01
0
Signaled Target Abort R/W
Received Target Abort R/W
Received Master Abort R/W
Signaled System Error R/W
12
0
13
0
14
0
15
Detected Parity Error
R/W
0
12
Agere Systems Inc.
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
PCI Registers (continued)
Table 14. Revision ID Register (08h)
Represents the current revision of the USS-344.
Bits
Field
Revision ID*
Read/Write
Reset/Description
7:0
R
10h
* The revision of the USS-344 can be identified either electronically or by physical markings. The revision can be identified
electronically using the standard PCI Revision ID register described in this table. The revision can also be identified by phys-
ical markings using the last letter of the USS-344 identifier code printed on the device. The USS-344 identifier code will be
printed using the format USS344XY, where X will identify the package type (M or T) and Y will identify the revision.
Table 15. Class Code Register (09h—0Bh)
The PCI class code for all OpenHCI host controllers is defined in the OpenHCI specification.
Bits
Field
Read/Write
Reset/Description
7:0
15:8
23:16
Programming Interface R
10h = OpenHCI Host Controller
03h = Universal Serial Bus
0Ch = Serial Bus Controller
Subclass
R
R
Base Class
Table 16. Cache Line Size Register (0Ch)
No cache line is supported by the USS-344.
Bits
Field
Read/Write
Reset/Description
7:0
Cache Line Size
R
00h
Table 17. Latency Timer Register (0Dh)
Controls the number of clock cycles the USS-344 may remain on the PCI bus after becoming bus master.
Bits
Field
Read/Write
Reset/Description
7:0
Latency Timer
R/W
Upper 5 bits are read/write. Lower
3 bits are read only.
Table 18. Header Type Register (0Eh)
The USS-344 supports PCI header type 0 only.
Bits
Field
Header Type
Read/Write
Read/Write
Reset/Description
80h = Multifunction PCI Device
7:0
R
R
Table 19. BIST Register (0Fh)
BIST is not supported by the USS-344.
Bits Field
Reset/Description
7:0
BIST
00h
Agere Systems Inc.
13
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
PCI Registers (continued)
Table 20. Base Address Register 0 (10h—13h)
The Base Address register is used to specify to the PCI operating system the memory size of the USS-344 device.
As recommended by the OpenHCI specification, the lower 12 bits are read only (fixed to logic 0) to indicate 4K
(212) memory size.
Bits
Field
Read/Write
Reset/Description
31:0
BAR 0
R/W
Lower 12 bits are read only. Upper
20 bits are read/write.
Table 21. Base Address Register 1, 2, 3, 4, 5 (14h—17h), (18h—1Bh), (1Ch—1Fh), (20h—23h), (24h—27h)
These Base Address registers are unused by the USS-344 device.
Bits
Field
BAR 1—5
Read/Write
Reset/Description
00000000h
31:0
R
Table 22. Cardbus CIS Pointer Register (28h—2Bh)
Cardbus CIS pointer not required for the USS-344.
Bits
Field
CardBus CIS Pointer
Read/Write
Reset/Description
00000000h
31:0
R
Table 23. Subsystem Vendor ID Register (2Ch—2Dh)
The subsystem vendor ID is R/W for compliance with Microsoft PC98 specifications. On reset, this register is read
only. System BIOS may write a 1 to Special—Subsystem Write Capability register (4Ch) bit 0 to enable write capa-
bility of this register. After configuring this register, the system BIOS must write a 0 to Special—Subsystem Write
Capability register (4Ch) bit 0 to disable write capability of this register.
Bits
Field
Read/Write
Reset/Description
15:0
Subsystem Vendor ID R/W
11C1h
Table 24. Subsystem ID Register (2Eh—2Fh)
The subsystem vendor ID is R/W for compliance with Microsoft PC98 specifications. On reset, this register is read
only. System BIOS may write a 1 to Special—Subsystem Write Capability register (4Ch) bit 0 to enable write capa-
bility of this register. After configuring this register, the system BIOS must write a 0 to Special—Subsystem Write
Capability register (4Ch) bit 0 to disable write capability of this register.
Bits
Field
Read/Write
Reset/Description
15:0
Subsystem ID
R/W
5803h
Table 25. Expansion ROM Base Address Register (30h—33h)
Expansion ROM not supported by the USS-344.
Bits
Field
Read/Write
Reset/Description
31:0
Expansion ROM Base
R
00000000h
Address
14
Agere Systems Inc.
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
PCI Registers (continued)
Table 26. Capabilities Pointer Register (34h)
Bits
Field
Read/Write
Read/Write
Reset/Description
TEST1 = 0b: 50h
TEST1 = 1b: 00h
7:0
Cap_Ptr
R
Table 27. Interrupt Line Register (3Ch)
Bits
Field
Reset/Description
7:0
Interrupt Line
R/W
00h
01h
Table 28. Interrupt Pin Register (3Dh)
Interrupt A used as the PCI interrupt for this core.
Bits
Field
Interrupt Pin
Read/Write
Reset/Description
7:0
R
Table 29. Min_Gnt Register (3Eh)
The USS-344 can support a four DWORD master burst read or write which requires less than 500 ns.
Bits
Field
Read/Write
Reset/Description
Reset/Description
7:0
Min_Gnt
R
03h
Table 30. Max_Lat Register (3Fh)
The USS-344 requires service at a minimum interval of 21.3 µs.
Bits Field Read/Write
7:0
Max_Lat
R
56h
Table 31. Special—Subsystem Write Capability (4Ch)
This is a special register implemented for compliance with Microsoft PC98 Specification, Chapter 9, Item 11. Bit 0
is read/write to allow the system BIOS to enable write capability of the Subsystem Vendor ID and Subsystem ID
registers (refer to Tables 23 and 24).
Bits
Field
Reserved
Subsystem Write
Read/Write
Reset/Description
00000000h
31:1
0
R
R/W
0b
0 = Subsystem write disabled
1 = Subsystem write enabled
Agere Systems Inc.
15
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
PCI Registers (continued)
PCI Function 1—Single-Port USB Host Controller 1
Table 32. Vendor ID Register (00h—01h)
This register is fixed as the Agere Systems vendor ID assigned by the PCI SIG.
Bits
Field
Read/Write
Reset/Description
Assigned 11C1h
15:0
Table 33. Device ID Register (02h—03h)
This register is fixed as the Agere Systems product USS-344.
Bits Field
Vendor ID
R
Read/Write
Reset/Description
15:0
Table 34. Command Register (04h—05h)
All read-only bits represent nonconfigurable features of the USS-344.
Bits Field Read/Write
Device ID
R
Assigned 5803h
Reset/Description
0
1
2
3
4
IO Space
R/W
R/W
R/W
R
0
0
0
0
0
Memory Space
Bus Master
Special Cycles
Memory Write and Invalidate R/W
Enable
VGA Palette Snoop
Parity Error Response
Wait Cycle Control
SERRN Enable
Fast Back-to-back Enable
Reserved
5
R
R/W
R
R/W
R/W
R
0
6
0
7
0
8
0
9
0
15:10
000000b
Table 35. Status Register (06h—07h)
All read-only bits represent nonconfigurable features of the USS-344.
Bits Field Read/Write
Reset/Description
3:0
4
Reserved
Capabilities
R
R
0000b
TEST1 = 0b: 1
TEST1 = 1b: 0
5
66 MHz Capable
R
0
0
6
UDF Support
R
7
8
Fast Back-to-back Capable
Data Parity Error Detected
DEVSEL Timing
Signaled Target Abort
Received Target Abort
Received Master Abort
Signaled System Error
Detected Parity Error
R
R/W
R
R/W
R/W
R/W
R/W
R/W
0
0
10:9
11
12
13
14
15
01
0
0
0
0
0
16
Agere Systems Inc.
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
PCI Registers (continued)
Table 36. Revision ID Register (08h)
Represents the current revision of the USS-344.
Bits
Field
Revision ID*
Read/Write
Reset/Description
7:0
R
10h
* The revision of the USS-344 can be identified either electronically or by physical markings. The revision can be identified
electronically using the standard PCI Revision ID register described in this table. The revision can also be identified by phys-
ical markings using the last letter of the USS-344 identifier code printed on the device. The USS-344 identifier code will be
printed using the format USS344XY, where X will identify the package type (M or T) and Y will identify the revision.
Table 37. Class Code Register (09h—0Bh)
The PCI class code for all OpenHCI host controllers is defined in the OpenHCI specification.
Bits
Field
Read/Write
Reset/Description
7:0
15:8
23:16
Programming Interface R
10h = OpenHCI Host Controller
03h = Universal Serial Bus
0Ch = Serial Bus Controller
Subclass
R
R
Base Class
Table 38. Cache Line Size Register (0Ch)
No cache line is supported by the USS-344.
Bits
Field
Read/Write
Reset/Description
7:0
Cache Line Size
R
00h
Table 39. Latency Timer Register (0Dh)
Controls the number of clock cycles the USS-344 may remain on the PCI bus after becoming bus master.
Bits
Field
Read/Write
Reset/Description
7:0
Latency Timer
R/W
Upper 5 bits are read/write. Lower
3 bits are read only.
Table 40. Header Type Register (0Eh)
The USS-344 supports PCI header type 0 only.
Bits
Field
Header Type
Read/Write
Reset/Description
80h = Multifunction PCI Device
7:0
R
Agere Systems Inc.
17
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
PCI Registers (continued)
Table 41. BIST Register (0Fh)
BIST is not supported by the USS-344.
Bits
Field
Read/Write
Reset/Description
7:0
BIST
R
00h
Table 42. Base Address Register 0 (10h—13h)
The Base Address register is used to specify to the PCI operating system the memory size of the USS-344 device.
As recommended by the OpenHCI specification, the lower 12 bits are read only (fixed to logic 0) to indicate 4K
(212) memory size.
Bits
Field
Read/Write
Reset/Description
31:0
BAR 0
R/W
Lower 12 bits are read only. Upper
20 bits are read/write.
Table 43. Base Address Register 1, 2, 3, 4, 5 (14h—17h), (18h—1Bh), (1Ch—1Fh), (20h—23h), (24h—27h)
These Base Address registers are unused by the USS-344 device.
Bits
Field
BAR 1—5
Read/Write
Reset/Description
00000000h
31:0
R
Table 44. Cardbus CIS Pointer Register (28h—2Bh)
Cardbus CIS pointer not required for the USS-344.
Bits
Field
CardBus CIS Pointer
Read/Write
Reset/Description
00000000h
31:0
R
Table 45. Subsystem Vendor ID Register (2Ch—2Dh)
The subsystem vendor ID is R/W for compliance with Microsoft PC98 specifications. On reset, this register is read
only. System BIOS may write a 1 to Special—Subsystem Write Capability register (4Ch) bit 0 to enable write capa-
bility of this register. After configuring this register, the system BIOS must write a 0 to Special—Subsystem Write
Capability register (4Ch) bit 0 to disable write capability of this register.
Bits
Field
Read/Write
Reset/Description
15:0
Subsystem Vendor ID R/W
11C1h
Table 46. Subsystem ID Register (2Eh—2Fh)
The subsystem vendor ID is R/W for compliance with Microsoft PC98 specifications. On reset, this register is read
only. System BIOS may write a 1 to Special—Subsystem Write Capability register (4Ch) bit 0 to enable write capa-
bility of this register. After configuring this register, the system BIOS must write a 0 to Special—Subsystem Write
Capability register (4Ch) bit 0 to disable write capability of this register.
Bits
Field
Read/Write
Reset/Description
15:0
Subsystem ID
R/W
5803h
18
Agere Systems Inc.
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
PCI Registers (continued)
Table 47. Expansion ROM Base Address Register (30h—33h)
Expansion ROM not supported by the USS-344.
Bits
Field
Read/Write
Read/Write
Read/Write
Reset/Description
00000000h
31:0
Expansion ROM Base
R
Address
Table 48. Capabilities Pointer Register (34h)
Bits Field
Reset/Description
TEST1 = 0b: 50h
TEST1 = 1b: 00h
7:0
Cap_Ptr
R
Table 49. Interrupt Line Register (3Ch)
Bits Field
Interrupt Line
Reset/Description
7:0
R/W
00h
Table 50. Interrupt Pin Register (3Dh)
If TEST0 = 0b, interrupt A is used as the PCI interrupt for this core.
If TEST0 = 1b, interrupt B is used as the PCI interrupt for this core.
Bits
Field
Interrupt Pin
Read/Write
Reset/Description
7:0
R
TEST0 = 0b: 01h
TEST0 = 1b: 02h
Table 51. Min_Gnt Register (3Eh)
The USS-344 can support a four DWORD master burst read or write which requires less than 500 ns.
Bits
Field
Read/Write
Reset/Description
7:0
Min_Gnt
R
03h
Table 52. Max_Lat Register (3Fh)
The USS-344 requires service at a minimum interval of 21.3 µs.
Bits Field Read/Write
Reset/Description
7:0
Max_Lat
R
56h
Table 53. Special—Subsystem Write Capability (4Ch)
This is a special register implemented for compliance with Microsoft PC98 Specification, Chapter 9, Item 11. Bit 0
is read/write to allow the system BIOS to enable write capability of the Subsystem Vendor ID and Subsystem ID
registers (refer to Tables 23 and 24).
Bits
Field
Reserved
Subsystem Write
Read/Write
Reset/Description
00000000h
31:1
0
R
R/W
0b
0 = Subsystem write disabled
1 = Subsystem write enabled
Agere Systems Inc.
19
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
PCI Registers (continued)
PCI Function 2—Single-Port USB Host Controller 2
Table 54. Vendor ID Register (00h—01h)
This register is fixed as the Agere Systems vendor ID assigned by the PCI SIG.
Bits
Field
Read/Write
Reset/Description
Assigned 11C1h
15:0
Table 55. Device ID Register (02h—03h)
This register is fixed as the Agere Systems product USS-344.
Bits Field
Vendor ID
R
Read/Write
Reset/Description
15:0
Table 56. Command Register (04h—05h)
All read-only bits represent nonconfigurable features of the USS-344.
Bits Field
Device ID
R
Assigned 5803h
Read/Write
Reset/Description
0
IO Space
R/W
R/W
R/W
R
0
0
0
0
0
0
0
0
0
0
1
Memory Space
Bus Master
2
3
Special Cycles
Memory Write and Invalidate Enable R/W
4
5
VGA Palette Snoop
Parity Error Response
Wait Cycle Control
SERRN Enable
Fast Back-to-back Enable
Reserved
R
R/W
R
R/W
R/W
R
6
7
8
9
15:10
000000b
Table 57. Status Register (06h—07h)
All read-only bits represent nonconfigurable features of the USS-344.
Bits Field
Read/Write
Reset/Description
3:0
4
Reserved
Capabilities
R
R
0000b
TEST1 = 0b: 1
TEST1 = 1b: 0
5
66 MHz Capable
R
0
6
UDF Support
R
0
7
8
Fast Back-to-back Capable
Data Parity Error Detected
DEVSEL Timing
Signaled Target Abort
Received Target Abort
Received Master Abort
Signaled System Error
Detected Parity Error
R
R/W
R
R/W
R/W
R/W
R/W
R/W
0
0
10:9
11
12
13
14
15
01
0
0
0
0
0
20
Agere Systems Inc.
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
PCI Registers (continued)
Table 58. Revision ID Register (08h)
Represents the current revision of the USS-344.
Bits
Field
Revision ID*
Read/Write
Reset/Description
7:0
R
10h
* The revision of the USS-344 can be identified either electronically or by physical markings. The revision can be identified
electronically using the standard PCI Revision ID register described in this table. The revision can also be identified by phys-
ical markings using the last letter of the USS-344 identifier code printed on the device. The USS-344 identifier code will be
printed using the format USS344XY, where X will identify the package type (M or T) and Y will identify the revision.
Table 59. Class Code Register (09h—0Bh)
The PCI class code for all OpenHCI host controllers is defined in the OpenHCI specification.
Bits
Field
Read/Write
Reset/Description
7:0
15:8
23:16
Programming Interface R
10h = OpenHCI Host Controller
03h = Universal Serial Bus
0Ch = Serial Bus Controller
Subclass
R
R
Base Class
Table 60. Cache Line Size Register (0Ch)
No cache line is supported by the USS-344.
Bits
Field
Read/Write
Reset/Description
7:0
Cache Line Size
R
00h
Table 61. Latency Timer Register (0Dh)
Controls the number of clock cycles the USS-344 may remain on the PCI bus after becoming bus master.
Bits
Field
Read/Write
Reset/Description
7:0
Latency Timer
R/W
Upper 5 bits are read/write. Lower
3 bits are read only.
Table 62. Header Type Register (0Eh)
The USS-344 supports PCI header type 0 only.
Bits
Field
Header Type
Read/Write
Reset/Description
80h = Multifunction PCI Device
7:0
R
Agere Systems Inc.
21
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
PCI Registers (continued)
Table 63. BIST Register (0Fh)
BIST is not supported by the USS-344.
Bits
Field
Read/Write
Reset/Description
7:0
BIST
R
00h
Table 64. Base Address Register 0 (10h—13h)
The Base Address register is used to specify to the PCI operating system the memory size of the USS-344 device.
As recommended by the OpenHCI specification, the lower 12 bits are read only (fixed to logic 0) to indicate 4K
(212) memory size.
Bits
Field
Read/Write
Reset/Description
31:0
BAR 0
R/W
Lower 12 bits are read only. Upper
20 bits are read/write.
Table 65. Base Address Register 1, 2, 3, 4, 5 (14h—17h), (18h—1Bh), (1Ch—1Fh), (20h—23h), (24h—27h)
These Base Address registers are unused by the USS-344 device.
Bits
Field
BAR 1—5
Read/Write
Reset/Description
00000000h
31:0
R
Table 66. Cardbus CIS Pointer Register (28h—2Bh)
Cardbus CIS pointer not required for the USS-344.
Bits
Field
CardBus CIS Pointer
Read/Write
Reset/Description
00000000h
31:0
R
Table 67. Subsystem Vendor ID Register (2Ch—2Dh)
The subsystem vendor ID is R/W for compliance with Microsoft PC98 specifications. On reset, this register is read
only. System BIOS may write a 1 to Special—Subsystem Write Capability register (4Ch) bit 0 to enable write capa-
bility of this register. After configuring this register, the system BIOS must write a 0 to Special—Subsystem Write
Capability register (4Ch) bit 0 to disable write capability of this register.
Bits
Field
Read/Write
Reset/Description
15:0
Subsystem Vendor ID R/W
11C1h
Table 68. Subsystem ID Register (2Eh—2Fh)
The subsystem vendor ID is R/W for compliance with Microsoft PC98 specifications. On reset, this register is read
only. System BIOS may write a 1 to Special—Subsystem Write Capability register (4Ch) bit 0 to enable write capa-
bility of this register. After configuring this register, the system BIOS must write a 0 to Special—Subsystem Write
Capability register (4Ch) bit 0 to disable write capability of this register.
Bits
Field
Read/Write
Reset/Description
15:0
Subsystem ID
R/W
5803h
22
Agere Systems Inc.
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
PCI Registers (continued)
Table 69. Expansion ROM Base Address Register (30h—33h)
Expansion ROM not supported by the USS-344.
Bits
Field
Read/Write
Read/Write
Read/Write
Reset/Description
00000000h
31:0
Expansion ROM Base
R
Address
Table 70. Capabilities Pointer Register (34h)
Bits Field
Reset/Description
TEST1 = 0b: 50h
TEST1 = 1b: 00h
7:0
Cap_Ptr
R
Table 71. Interrupt Line Register (3Ch)
Bits
Field
Reset/Description
7:0
Interrupt Line
R/W
00h
Table 72. Interrupt Pin Register (3Dh)
If TEST0 = 0b, interrupt A is used as the PCI interrupt for this core.
If TEST0 = 1b, interrupt C is used as the PCI interrupt for this core.
Bits
Field
Interrupt Pin
Read/Write
Reset/Description
7:0
R
TEST0 = 0b: 01h
TEST0 = 1b: 03h
Table 73. Min_Gnt Register (3Eh)
The USS-344 can support a four DWORD master burst read or write which requires less than 500 ns.
Bits
Field
Read/Write
Reset/Description
7:0
Min_Gnt
R
03h
Table 74. Max_Lat Register (3Fh)
The USS-344 requires service at a minimum interval of 21.3 µs.
Bits Field Read/Write
Reset/Description
7:0
Max_Lat
R
56h
Table 75. Special—Subsystem Write Capability (4Ch)
This is a special register implemented for compliance with Microsoft PC98 Specification, Chapter 9, Item 11. Bit 0
is read/write to allow the system BIOS to enable write capability of the Subsystem Vendor ID and Subsystem ID
registers (refer to Tables 23 and 24).
Bits
Field
Reserved
Subsystem Write
Read/Write
Reset/Description
00000000h
31:1
0
R
R/W
0b
0 = Subsystem write disabled
1 = Subsystem write enabled
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USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
PCI Registers (continued)
PCI Function 3—Single-Port USB Host Controller 3
Table 76. Vendor ID Register (00h—01h)
This register is fixed as the Agere Systems vendor ID assigned by the PCI SIG.
Bits
Field
Vendor ID
Read/Write
Reset/Description
Assigned 11C1h
15:0
R
Table 77. Device ID Register (02h—03h)
This register is fixed as the Agere Systems product USS-344.
Bits Field Read/Write
Device ID
Reset/Description
Assigned 5803h
15:0
R
Table 78. Command Register (04h—05h)
All read-only bits represent nonconfigurable features of the USS-344.
Bits Field Read/Write
Reset/Description
0
1
2
3
4
IO Space
R/W
R/W
R/W
R
0
0
0
0
0
Memory Space
Bus Master
Special Cycles
Memory Write and
Invalidate Enable
VGA Palette Snoop
R/W
5
6
7
8
9
R
0
0
0
0
0
Parity Error Response R/W
Wait Cycle Control
SERRN Enable
Fast Back-to-back
Enable
R
R/W
R/W
15:10
Reserved
R
000000b
Table 79. Status Register (06h—07h)
All read-only bits represent nonconfigurable features of the USS-344.
Bits Field Read/Write
Reset/Description
3:0
Reserved
R
0000b
4
Capabilities
R
TEST1 = 0b: 1
TEST1 = 1b: 0
5
6
7
66 MHz Capable
UDF Support
Fast Back-to-back
Capable
R
R
R
0
0
0
8
Data Parity Error
Detected
R/W
R
0
10:9
11
DEVSEL Timing
01
0
Signaled Target Abort R/W
Received Target Abort R/W
Received Master Abort R/W
Signaled System Error R/W
12
0
13
0
14
0
15
Detected Parity Error
R/W
0
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USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
PCI Registers (continued)
Table 80. Revision ID Register (08h)
Represents the current revision of the USS-344.
Bits
Field
Revision ID*
Read/Write
Reset/Description
7:0
R
10h
* The revision of the USS-344 can be identified either electronically or by physical markings. The revision can be identified
electronically using the standard PCI Revision ID register described in this table. The revision can also be identified by phys-
ical markings using the last letter of the USS-344 identifier code printed on the device. The USS-344 identifier code will be
printed using the format USS344XY, where X will identify the package type (M or T) and Y will identify the revision.
Table 81. Class Code Register (09h—0Bh)
The PCI class code for all OpenHCI host controllers is defined in the OpenHCI specification.
Bits
Field
Read/Write
Reset/Description
7:0
15:8
23:16
Programming Interface R
10h = OpenHCI Host Controller
03h = Universal Serial Bus
0Ch = Serial Bus Controller
Subclass
R
R
Base Class
Table 82. Cache Line Size Register (0Ch)
No cache line is supported by the USS-344.
Bits
Field
Read/Write
Reset/Description
7:0
Cache Line Size
R
00h
Table 83. Latency Timer Register (0Dh)
Controls the number of clock cycles the USS-344 may remain on the PCI bus after becoming bus master.
Bits
Field
Read/Write
Reset/Description
7:0
Latency Timer
R/W
Upper 5 bits are read/write. Lower
3 bits are read only.
Table 84. Header Type Register (0Eh)
The USS-344 supports PCI header type 0 only.
Bits
Field
Header Type
Read/Write
Reset/Description
80h = Multifunction PCI Device
7:0
R
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Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
PCI Registers (continued)
Table 85. BIST Register (0Fh)
BIST is not supported by the USS-344.
Bits
Field
Read/Write
Reset/Description
7:0
BIST
R
00h
Table 86. Base Address Register 0 (10h—13h)
The Base Address register is used to specify to the PCI operating system the memory size of the USS-344 device.
As recommended by the OpenHCI specification, the lower 12 bits are read only (fixed to logic 0) to indicate 4K
(212) memory size.
Bits
Field
Read/Write
Reset/Description
31:0
BAR 0
R/W
Lower 12 bits are read only. Upper
20 bits are read/write.
Table 87. Base Address Register 1, 2, 3, 4, 5 (14h—17h), (18h—1Bh), (1Ch—1Fh), (20h—23h), (24h—27h)
These base address registers are unused by the USS-344 device.
Bits
Field
BAR 1—5
Read/Write
Reset/Description
00000000h
31:0
R
Table 88. Cardbus CIS Pointer Register (28h—2Bh)
Cardbus CIS pointer not required for the USS-344.
Bits
Field
CardBus CIS Pointer
Read/Write
Reset/Description
00000000h
31:0
R
Table 89. Subsystem Vendor ID Register (2Ch—2Dh)
The subsystem vendor ID is R/W for compliance with Microsoft PC98 specifications. On reset, this register is read
only. System BIOS may write a 1 to Special—Subsystem Write Capability register (4Ch) bit 0 to enable write capa-
bility of this register. After configuring this register, the system BIOS must write a 0 to Special—Subsystem Write
Capability register (4Ch) bit 0 to disable write capability of this register.
Bits
Field
Read/Write
Reset/Description
15:0
Subsystem Vendor ID R/W
11C1h
Table 90. Subsystem ID Register (2Eh—2Fh)
The subsystem vendor ID is R/W for compliance with Microsoft PC98 specifications. On reset, this register is read
only. System BIOS may write a 1 to Special—Subsystem Write Capability register (4Ch) bit 0 to enable write capa-
bility of this register. After configuring this register, the system BIOS must write a 0 to Special—Subsystem Write
Capability register (4Ch) bit 0 to disable write capability of this register.
Bits
Field
Read/Write
Reset/Description
15:0
Subsystem ID
R/W
5803h
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Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
PCI Registers (continued)
Table 91. Expansion ROM Base Address Register (30h—33h)
Expansion ROM not supported by the USS-344.
Bits
Field
Read/Write
Read/Write
Read/Write
Reset/Description
00000000h
31:0
Expansion ROM Base
R
Address
Table 92. Capabilities Pointer Register (34h)
Bits Field
Reset/Description
TEST1 = 0b: 50h
TEST1 = 1b: 00h
7:0
Cap_Ptr
R
Table 93. Interrupt Line Register (3Ch)
Bits
Field
Reset/Description
7:0
Interrupt Line
R/W
00h
Table 94. Interrupt Pin Register (3Dh)
If TEST0 = 0b, interrupt A is used as the PCI interrupt for this core.
If TEST0 = 1b, interrupt D is used as the PCI interrupt for this core.
Bits
Field
Interrupt Pin
Read/Write
Reset/Description
7:0
R
TEST0 = 0b: 01h
TEST0 = 1b: 04h
Table 95. Min_Gnt Register (3Eh)
The USS-344 can support a four DWORD master burst read or write which requires less than 500 ns.
Bits
Field
Read/Write
Reset/Description
7:0
Min_Gnt
R
03h
Table 96. Max_Lat Register (3Fh)
The USS-344 requires service at a minimum interval of 21.3 µs.
Bits Field Read/Write
Reset/Description
7:0
Max_Lat
R
56h
Table 97. Special—Subsystem Write Capability (4Ch)
This is a special register implemented for compliance with Microsoft PC98 Specification, Chapter 9, Item 11. Bit 0
is read/write to allow the system BIOS to enable write capability of the Subsystem Vendor ID and Subsystem ID
registers (refer to Tables 23 and 24).
Bits
Field
Reserved
Subsystem Write
Read/Write
Reset/Description
00000000h
31:1
0
R
R/W
0b
0 = Subsystem write disabled
1 = Subsystem write enabled
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Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
USB Registers
Table 98. USB Operational Registers Summary
Each PCI Function has one set of USB operational registers available through the memory mapped Base Address
register 0. Each set of USB operational registers represents one single-port USB host controller. Refer to Tables
99—120 for more details on each of these registers.
Offset
Register Name
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
44h
48h
4Ch
50h
54h
100h
104h
108h
10Ch
HcRevision
HcControl
HcCommandStatus
HcInterruptStatus
HcInterruptEnable
HcInterruptDisable
HcHCCA
HcPeriodCurrentED
HcControlHeadED
HcControlCurrentED
HcBulkHeadED
HcBulkCurrentED
HcDoneHead
HcFmInterval
HcFmRemaining
HcFmNumber
HcPeriodicStart
HcLSThreshold
HcRhDescriptorA
HcRhDescriptorB
HcRhStatus
HcRhPortStatus1
HceControl
HceInput
HceOutput
HceStatus
Table 99. HcRevision Register (00h)
Bits Field
Reset
HCD
HC
(Host Controller Driver) (Host Controller)
7:0 Revision (REV)
Legacy (L)
10h
1b
R
R
R
R
8
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USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
USB Registers (continued)
Table 100. HcControl Register (04h)
Bits
Field
Reset
HCD
HC
(Host Controller Driver) (Host Controller)
1:0
2
Control Bulk Service Ratio (CBSR)
Periodic List Enable (PLE)
Isochronous Enable (IE)
Control List Enable (CLE)
Bulk List Enable (BLE)
00b
0b
R/W
R/W
R/W
R/W
R/W
R/W
R
R
3
0b
R
4
5
7:6
0b
0b
00b
R
R
R/W
Host Controller Functional State (HCFS)
00b: UsbReset
01b: UsbResume
10b: UsbOperational
11b: UsbSuspend
8
9
10
Interrupt Routing (IR)
Remote Wakeup Connected (WC)
Remote Wakeup Enable (RWE)
0b
0b
0b
R/W
R/W
R/W
R
R/W
R
Table 101. HcCommandStatus Register (08h)
Bits
Field
Reset
HCD
HC
0
1
2
3
Host Controller Reset (HCR)
Control List Filled (CLF)
0b
0b
0b
0b
0b
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
Bulk List Filled (BLF)
Ownership Change Request (OCR)
17:16 Scheduling Overrun Count (SOC)
Table 102. HcInterruptStatus Register (0Ch)
Bits
Field
Reset
HCD
HC
0
1
Scheduling Overrun (SO)
Writeback Done Head (WDH)
Start of Frame (SF)
0b
0b
0b
0b
0b
0b
0b
0b
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2
3
Resume Detected (RD)
4
Unrecoverable Error (UE)
Frame Number Overflow (FNO)
Root Hub Status Change (RHSC)
Ownership Change (OC)
5
6
30
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Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
USB Registers (continued)
Table 103. HcInterruptEnable Register (10h)
Bits
Field
Reset
HCD
HC
(Host Controller Driver) (Host Controller)
0
Scheduling Overrun (SO)
0b
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
0—Ignore
1—Enable interrupt
1
2
Writeback Done Head (WDH)
0b
0b
0b
0b
0b
0b
0b
0b
0—Ignore
1—Enable interrupt
Start of Frame (SF)
0—Ignore
1—Enable interrupt
3
Resume Detected (RD)
0—Ignore
1—Enable interrupt
4
Unrecoverable Error (UE)
0—Ignore
1—Enable interrupt
5
Frame Number Overflow (FNO)
0—Ignore
1—Enable interrupt
6
Root Hub Status Change (RHSC)
0—Ignore
1—Enable interrupt
30
31
Ownership Change (OC)
0—Ignore
1—Enable interrupt
Master Interrupt Enable (MIE)
0—Ignored by HC
1—Enables interrupt generation due to events
specified in the other bits of this register
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Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
USB Registers (continued)
Table 104. HcInterruptDisable Register (14h)
Bits
Field
Reset
HCD
HC
(Host Controller Driver) (Host Controller)
0
Scheduling Overrun (SO)
0b
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
0—Ignore
1—Disable interrupt generation
1
2
Writeback Done Head (WDH)
0b
0b
0b
0b
0b
0b
0b
0b
0—Ignore
1—Disable interrupt
Start of Frame (SF)
0—Ignore
1—Disable interrupt
3
Resume Detected (RD)
0—Ignore
1—Disable interrupt
4
Unrecoverable Error (UE)
0—Ignore
1—Disable interrupt
5
Frame Number Overflow (FNO)
0—Ignore
1—Disable interrupt
6
Root Hub Status Change (RHSC)
0—Ignore
1—Disable interrupt
30
31
Ownership Change (OC)
0—Ignore
1—Disable interrupt
Master Interrupt Enable (MIE)
0—Ignored by HC
1—Disables interrupt generation due to events
specified in the other bits of this register
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Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
USB Registers (continued)
Table 105. HcHCCA Register (18h)
Bits
Field
Reset
HCD
HC
(Host Controller Driver) (Host Controller)
31:8
Host Controller Communications Area (HCCA)
Base Address
0h
R/W
R
Bits 7:0 will always return a 0.
Table 106. HcPeriodCurrentED Register (1Ch)
Bits
Field
Reset
HCD
HC
31:4
Period Current ED (PCED) Base Address
0h
R/W
R
Bits 3:0 will always return a 0.
Table 107. HcControlHeadED Register (20h)
Bits
Field
Reset
HCD
HC
31:4
Control Head ED (CHED) Base Address
0h
R/W
R
Bits 3:0 will always return a 0.
Table 108. HcControlCurrentED Register (24h)
Bits
Field
Reset
HCD
HC
31:4
Control Current ED (CCED) Base Address
0h
R/W
R/W
Bits 3:0 will always return a 0.
Table 109. HcBulkHeadED Register (28h)
Bits
Field
Reset
HCD
HC
31:4
Bulk Head ED (BHED) Base Address
0h
R/W
R
Bits 3:0 will always return a 0.
Table 110. HcBulkCurrentED Register (2Ch)
Bits
Field
Reset
HCD
HC
31:4
Bulk Current ED (BCED) Base Address
0h
R/W
R/W
Bits 3:0 will always return a 0.
Table 111. HcDoneHead Register (30h)
Bits
Field
Reset
HCD
HC
31:4
Done Head ED (DH) Base Address
0h
R
R/W
Bits 3:0 will always return a 0.
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Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
USB Registers (continued)
Table 112. HcFmInterval Register (34h)
Bits
Field
Reset
HCD
HC
(Host Controller Driver) (Host Controller)
13:0
Frame Interval (FI)
2EDFh
0h
0b
R/W
R/W
R/W
R
R
R
30:16 FS Largest Data Packet (FSMPS)
31
Frame Interval Toggle (FIT)
Table 113. HcFmRemaining Register (38h)
Bits
13:0
31
Field
Frame Remaining (FR)
Frame Remaining Toggle (FRT)
Reset
0h
0b
HCD
R
R
HC
R/W
R/W
Table 114. HcFmNumber Register (3Ch)
Bits
15:0
Field
Frame Number (FN)
Reset
0h
HCD
R
HC
R/W
Table 115. HcPeriodicStart Register (40h)
Bits
Field
Reset
HCD
HC
13:0
Periodic Start (PS)
0h
R/W
R
Table 116. HcLSThreshold (44h)
Bits
Field
Reset
HCD
HC
11:0
LS Threshold
628h
R/W
R
Table 117. HcRhDescriptorA Register (48h)
Bits
Field
Reset
HCD
HC
7:0
Number Downstream Ports
01h
R
R
(NDP)
8
9
10
11
Power Switching Mode (PSM)
No Power Switching (NPS)
Device Type (DT)
1b
0b
0b
1b
R/W
R/W
R
R
R
R
R
Overcurrent Protection Mode
R/W
(OCPM)
No Overcurrent Protection
(NOCP)
12
0b
R/W
R/W
R
R
24:31 Power On to Power Good Time 10h
(POTPGT)
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Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
USB Registers (continued)
Table 118. HcRhDescriptorB Register (4Ch)
Bits
Field
Reset
HCD
HC
(Host Controller Driver) (Host Controller)
15:0
Device Removable (DR)
0000h
0002h
R/W
R/W
R
R
17:16 Port Power Control Mask (PPCM)
Table 119. HcRhStatus Register (50h)
Bits
Field
Reset
HCD
HC
0
Local Power Status (LPS)
0b
0b
0b
0b
0b
0b
R/W
R
R/W
R/W
R/W
W
R
R/W
R
1
Overcurrent Indicator (OCI)
15
16
17
31
Device Remote Wakeup Enable (DRWE)
Local Power Status Change (LPSC)
Overcurrent Indicator Change (OCIC)
Clear Remote Wakeup Enable (CRWE)
R
R/W
R
Table 120. HcRhPortStatus1 Register (54h)
Bits
Field
Reset
HCD
HC
0
1
Current Connect Status (CCS)
Port Enable Status (PES)
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2
Port Suspend Status (PSS)
3
Port Overcurrent Indicator (POCI)
Port Reset Status (PRS)
Port Power Status (PPS)
Low-speed Device Attached (LSDA)
Connect Status Change (CSC)
Port Enable Status Change (PESC)
Port Suspend Status Change (PSSC)
Port Overcurrent Indicator Change (OCIC)
Port Reset Status Change (PRSC)
4
8
9
16
17
18
19
20
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USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
Legacy Support Registers
The legacy support function and all registers described in this section are available on all four embedded USB host
controllers. Four operational registers are used to provide the legacy support. Each of these registers is located on
a 32-bit boundary. The offset of these registers is relative to the base address of the respective host controller core
operational registers with HceControl located at offset 100h.
Table 121. Legacy Support Registers
Offset
100h
Register
HceControl
Description
Used to enable and control the emulation hardware and report various status
information.
Emulation side of the Legacy Input Buffer register.
104h
108h
HceInput
HceOutput
Emulation side of the Legacy Output Buffer register where keyboard and
mouse data is to be written by software.
Emulation side of the Legacy Status register.
10Ch
HceStatus
Three of the operational registers (HceStatus, HceInput, HceOutput) are accessible at I/O address 60h and 64h
when emulation is enabled. Reads and writes to the registers using I/O addresses have side effects as outlined in
the Table 122.
Table 122. Emulated Registers
I/O
Cycle
Type
IN
Register Contents
Accessed/Modified
Side
Effects
Address
IN from port 60h will set OutputFull in HceStatus to 0.
60h
60h
HceOutput
HceInput
OUT to port 60h will set InputFull to 1 and CmdData to 0 in
OUT
HceStatus.
IN from port 64h returns current value of HceStatus with no
other side effect.
64h
64h
IN
HceStatus
HceInput
OUT to port 64h will set InputFull to 0 and CmdData in
OUT
HceStatus to 1.
HceInput Register
Table 123. HceInput Register (104h)
Bit
7:0
31:8
Field
InputData
Reserved
R/W
R/W
—
Description
This register holds data that is written to I/O ports 60h and 64h.
—
I/O data that is written to ports 60h and 64h is captured in this register when emulation is enabled. This register
may be read or written directly by accessing it with its memory address in the host controller’s operational register
space. When accessed directly with a memory cycle, reads and writes of this register have no side effects.
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Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
Legacy Support Registers (continued)
HceOutput Register
Table 124. HceOutput Register (108h)
Bit
7:0
Field
OutputData
R/W
R/W
Description
This register hosts data that is returned when an I/O read of port 60h is per-
formed by application software.
—
31:8
Reserved
—
The data placed in this register by the emulation software is returned when I/O port 60h is read and emulation is
enabled. On a read of this location, the OutputFull bit in HceStatus is set to 0.
HceStatus Register
Table 125. HceStatus Register (10Ch)
Bit
0
Field
OutputFull
R/W
R/W
Description
The HC sets this bit to 0 on a read of I/O port 60h. If IRQEn is set and Aux-
OutputFull is set to 0, then an IRQ1 is generated as long as this bit is set to 1.
If IRQEn is set and AuxOutputFull is set to 1, then an IRQ12 is generated as
long as this bit is set to 1. While this bit is 0 and CharacterPending in Hce-
Control is set to 1, an emulation interrupt condition exists.
Except for the case of a Gate A20 sequence, this bit is set to 1 on an I/O write
to address 60h or 64h. While this bit is set to 1 and emulation is enabled, an
emulation interrupt condition exists.
1
InputFull
R/W
Nominally used as a system flag by software to indicate a warm or cold boot.
2
3
Flag
CmdData
R/W
R/W
The HC sets this bit to 0 on an I/O write to port 60h and to 1 on an I/O write to
port 64h.
This bit reflects the state of the keyboard inhibit switch and is set if the key-
4
5
Inhibit Switch
AuxOutputFull
R/W
R/W
board is not inhibited.
IRQ12 is asserted whenever this bit is set to 1 and OutputFull is set to 1 and
the IRQEn bit is set.
Used to indicate a time-out.
6
7
31:8
Time-out
Parity
Reserved
R/W
R/W
—
Indicates parity error on keyboard/mouse data.
—
The contents of the HceStatus register are returned on an I/O Read of port 64h when emulation is enabled. Reads
and writes of port 60h and writes to port 64h can cause changes in this register. Emulation software can directly
access this register through its memory address in the host controller’s operational register space. Accessing this
register through its memory address produces no side effects.
36
Agere Systems Inc.
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Con-
Legacy Support Registers (continued)
HceControl Register
Table 126. HceControl Register (100h)
Bit
Field
Reset
R/W
Description
When set to 1, the HC is enabled for legacy emulation. The
HC decodes accesses to I/O registers 60h and 64h and gen-
erates IRQ1 and/or IRQ12 when appropriate. Additionally,
the HC generates an emulation interrupt at appropriate times
to invoke the emulation software.
0
EmulationEnable
0b
R/W
This bit is a static decode of the emulation interrupt condi-
1
2
3
EmulationInterrupt
CharacterPending
IRQEn
—
0b
0b
R
tion.
When set, an emulation interrupt is generated when the Out-
putFull bit of the HceStatus register is set to 0.
When set, the HC generates IRQ1 or IRQ12 as long as the
OutputFull bit in HceStatus is set to 1. If the AuxOutputFull
bit of HceStatus is 0, then IRQ1 is generated; if it is 1, then
an IRQ12 is generated.
R/W
R/W
When set to 1, IRQ1 and IRQ12 from the keyboard controller
causes an emulation interrupt. The function controlled by this
bit is independent of the setting of the EmulationEnable bit in
this register.
4
ExternalIRQEn
0b
R/W
Set by HC when a data value of D1h is written to I/O port
64h. Cleared by HC on write to I/O port 64h of any value
other than D1h.
Indicates that a positive transition on IRQ1 from keyboard
controller has occurred. SW may write a 1 to this bit to clear
it (set it to 0). SW write of a 0 to this bit has no effect.
5
6
GateA20Sequence
IRQ1Active
IRQ12Active
A20State
0b
0b
0b
0b
—
R/W
R/W
R/W
R/W
—
Indicates that a positive transition on IRQ12 from keyboard
controller has occurred. SW may write a 1 to this bit to clear
it (set it to 0). SW write of a 0 to this bit has no effect.
Indicates current state of gate A20 on keyboard controller.
Used to compare against value written to 60h when
GateA20Sequence is active.
7
8
Must read as 0s.
31:9
Reserved
connecting the VIO signal to the signaling voltage on
the motherboard or VIO pin on the card edge of the
expansion card. The VIO pin will select the PCI
signaling level as indicated in Table 127. A 5 V refer-
ence voltage is not required for the USS-344 to be 5 V
compatible.
Connection Instructions
Figure 6 shows a typical connection of the USS-344 to
provide four USB ports and full legacy support to a
PCI-based system. For each of the following sections,
refer to Figure 6 for guidance.
Table 127. PCI Signaling Levels
PCI Connection Instructions
VIO Pin Input
Voltage
USS-344 PCI Signaling
Level (All PCI Signals)
The USS-344 interfaces directly with any 32-bit,
33 MHz PCI bus simply by connecting all PCI related
signals directly to the signals on the host motherboard
or card edge of an expansion card. The PCI signaling
level for all PCI signals of the USS-344 is selected by
4.75 V—5.25 V
3.0 V—3.6 V
5 V signaling
3.3 V signaling
Agere Systems Inc.
37
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
Test Mode Connection Instructions
Connection Instructions (continued)
TEST[3:0] input pins present various options and test
modes for the USS-344. These pins can be connected
directly to VDD or ground as needed. One test mode
(NAND tree mode) is available for a system designer to
implement. For a system designer who wishes to
implement NAND tree mode, it is recommended that a
pull-down resistor be used on TEST2 input. This will
allow an in-circuit tester to drive TEST2 high and acti-
vate NAND tree mode (see NAND Tree Mode section).
TEST3, TEST1, and TEST0 can be grounded without a
resistor.
USB Connection Instructions
The USS-344 is a port-powered OHCI host controller
(refer to OHCI specification) requiring an external
switchable power regulator to supply downstream USB
port power controlled by the USS-344. The power
regulator interface has been designed to interface
directly with commonly used USB power regulators
with very little additional circuitry. The PRTPWR[0, 1, 2,
3] output signal is used as the switch for the power
regulator. The PRTPWR[0, 1, 2, 3] signal must be boot-
strapped with a pull-up or pull-down resistor to select
the appropriate power switch polarity. Bootstrapping
with a pull-up resistor will select an active-low power
switch while bootstrapping with a pull-down will select
an active-high power switch. Figure 3 depicts a typical
board connection for both power regulator enable
polarities.
It is also recommended that all NAND tree pins have a
corresponding PWB trace that can be driven by the in-
circuit tester during NAND tree mode.
Table 128. Test Mode Decodes
TEST[3:0]
Description
00X0
Share Interrupt A. All four controllers
return a 01h in the Interrupt Pin register
(3Dh) and use the PCI interrupt A pin.
Individual Interrupt. Controller 0 returns
01h in the Interrupt Pin register (3Dh)
and uses the PCI interrupt A pin.
The PWRFLT[0, 1, 2, 3]N can be connected directly to
an active-low power fault regulator output to inform the
USS-344 of a USB port overcurrent condition.
00X1
DPLS[0, 1, 2, 3] and DMNS[0, 1, 2, 3] are related to the
integrated USB transceiver and are connected directly
to the USB port connector through a 28 Ω—32 Ω series
resistor for each signal. Figure 5 shows complete detail
of the USS-344 connection to USB.
Controller 1 returns 02h in the interrupt
pin register (3Dh) and uses the PCI inter-
rupt B pin.
CLK48 must be connected to a 48 MHz oscillator to
provide a suitable USB clock to the USS-344. If
CLK48STOP signal is used to disable the external
oscillator during D3 Power Management state,
CLK48STOP must be bootstrapped with a pull-up or
pull-down resistor to select the appropriate disable
polarity. Bootstrapping with a pull-up resistor will select
an active-low disable while bootstrapping with a pull-
down will select an active-high disable. Figure 4
depicts a typical board connection for both oscillator
enable polarities. CLK48STOP must be pulled to a
stable logic value with a resistor if CLK48STOP is not
used. Figure 4 also shows the typical board connection
when CLK48STOP is not used.
Controller 2 returns 03h in the Interrupt
Pin register (3Dh) and uses the PCI inter-
rupt C pin.
Controller 3 returns 04h in the Interrupt
Pin register (3Dh) and uses the PCI inter-
rupt D pin.
Power Management Interface
Enabled. Power management interface
enabled in all four controllers.
Power Management Interface
Disabled. Power management interface
disabled in all four controllers.
000X
001X
01XX
NAND Test.
38
Agere Systems Inc.
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
Connection Instructions (continued)
5 Vdc-5 Vdc
SWITCHED
REGULATOR
5 Vdc-5 Vdc
SWITCHED
REGULATOR
2 kΩ
PRTPWRX
USS-344
EN
USS-344
EN
PRTPWRX
2 kΩ
ACTIVE-
HIGH
ACTIVE-
LOW
ENABLE
ENABLE
5-8738.r1
Figure 3. Typical Board Connection for Both Power Regulator Enable Polarities
48 MHz
48 MHz
OSCILLATOR
OSCILLATOR
2 kΩ
CLK48STOP
2 kΩ
USS-344
EN
USS-344
EN
CLK48STOP
ACTIVE-
LOW
ACTIVE-
HIGH
ENABLE
ENABLE
CLK48STOP
USS-344
2 kΩ
5-8739
Figure 4. Typical Board Connection for Both Oscillator Enable Polarities or Without Oscillator
USB
CONNECTOR
DPLS
28 Ω—32 Ω
INTEGRATED
USB
15 kΩ
5%
TRANSCEIVER
DOWNSTREAM
PORT
DMNS
28 Ω—32 Ω
INTEGRATED
USB
15 kΩ
5%
TRANSCEIVER
5-9289
Figure 5. USB Transceiver Connection
Agere Systems Inc.
39
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
Legacy Configuration
Also included in the USS-344 is the legacy PS/2 mouse and keyboard interface as defined in the OpenHCI Open
Host Controller Interface Specification for USB Release 1.0a. This legacy interface along with standard USB BIOS
drivers allows USB mice and keyboards to operate in MS-DOS* mode. Legacy support need not be implemented
by the system designer if not desired. If not implemented, A20I, MIRQ12I, and KIRQ12I must be connected to a
stable logic level. Figure 6 shows the typical legacy support connection to the USS-344. Figure 7 shows the typical
connection of the unused legacy support signals when legacy support is not desired.
3.3 Vdc
5 Vdc
CLK48
5 Vdc-5 Vdc
SWITCHED
REGULATOR
VBUS = 5 Vdc
DPLS0/DMNS0
48 MHz
OSC
PRTPWR0
PWRFLT0N
CLK48STOP
USB
CONNECTOR
5 Vdc-5 Vdc
SWITCHED
REGULATOR
VBUS = 5 Vdc
DPLS1/DMNS1
PRTPWR1
PWRFLT1N
USB
CONNECTOR
PCI VIO
AGERE USS-344
PCI-TO-USB
OHCI HOST
CONTROLLER
5 Vdc-5 Vdc
SWITCHED
REGULATOR
VBUS = 5 Vdc
DPLS2/DMNS2
PRTPWR2
PWRFLT2N
PCI SIGNALS
32-bit, 33 MHz
CPU
USB
CONNECTOR
PMEN
5 Vdc-5 Vdc
SWITCHED
REGULATOR
VBUS = 5 Vdc
DPLS3/DMNS3
PRTPWR3
PWRFLT3N
USB
CONNECTOR
SMI
A20MN
KIRQ1I
MIRQ12I
A2OI
PS/2 MOUSE
8042
IRQ1
IRQ12
8259
LEGACY
DEVICE
INTERRUPT
CONTROLLER
CONTROLLER
PS/2 KEYBOARD
OPTIONAL LEGACY SUPPORT
5-7829
Figure 6. Typical Legacy Support Connection
* MS-DOS is a registered trademark of Microsoft Corporation.
40
Agere Systems Inc.
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
Legacy Configuration (continued)
3.3 Vdc
5 Vdc
CLK48
CLK48STOP
48 MHz
5 Vdc-5 Vdc
SWITCHED
REGULATOR
VBUS = 5 Vdc
PRTPWR0
PWRFLT0N
OSC
USB
CONNECTOR
DPLS0/DMNS0
VBUS = 5 Vdc
5 Vdc-5 Vdc
SWITCHED
REGULATOR
PRTPWR1
PWRFLT1N
USB
CONNECTOR
PCI VIO
DPLS1/DMNS1
VBUS = 5 Vdc
AGERE USS-344
PCI-TO-USB
OHCI HOST CONTROLLER
5 Vdc-5 Vdc
SWITCHED
REGULATOR
PRTPWR2
PWRFLT2N
USB
PCI SIGNALS
32-bit, 33 MHz
CONNECTOR
CPU
DPLS2/DMNS2
VBUS = 5 Vdc
PMEN
5 Vdc-5 Vdc
SWITCHED
REGULATOR
PRTPWR3
PWRFLT3N
USB
CONNECTOR
DPLS3/DMNS3
5-8740
Figure 7. Typical Connection When Not Using Legacy Support
Power Connection Recommendations
The USS-344 is a 3.3 V device. Therefore, all VDD inputs must be connected to an appropriate 3.3 V source. VDDT
provides all transceiver power and must be connected to a 3.3 V source. It is recommended that the system
designer undertake special board routing and filtering of VDDT and VSST to isolate these power inputs from noise
induced by other components.
Agere Systems Inc.
41
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
Power Management Interface
An advanced power management capabilities interface compliant with PCI Bus Power Management Interface
Specification Revision 1.1 has been incorporated into each of the USS-344 controllers. This interface allows the
USS-344 to be placed in various power management states offering a variety of power savings for a host system.
Table 129 highlights the USS-344 support for power management states and features supported for each of the
power management states. The USS-344 has the ability to internally gate-off the CLK48 input, disable the USB
transceivers, and assert USB resume signaling asynchronously (without active CLK48) in response to upstream
USB resume being detected. The USS-344 will assert PMEN and retain chip context in accordance with the rules
defined in the PCI Bus Power Management Interface Specification Revision 1.1.
Table 129. USS-344 Support for Power Management States
Power
State
Clk48
CLK48
STOP
Active
USB
Async
PMEN
Chip
Comments
Management Required/
Active
Trans- Resume Assert Context
State
Optional Internally
ciever
Logic
Enabled
Main-
Active
Active
tained
D0
Required
Optional
X
X
X
X
—
—
X
Fully awake backwards com-
patible state. All logic in full-
power mode.
Fully awake state with PCI
bus master capabilities turned
off by host. All logic in full-
power mode because of low
latency returning to D0 State.
D1
—
X
X
D2
Optional
Required
—
—
—
—
X*
X*
X
X
X
USB sleep state with PCI bus
master capabilities turned off
by host. PCI clocks may be
turned off by the system.
Deep USB sleep state with
PCI bus master capabilities
turned off by host. PCI clocks
may be turned off by the sys-
tem.
D3hot
X
—
D3cold
Required
—
—
—
—
—
Fully asleep backwards com-
patible state. All power turned
off. Reset required to recover
to D0 state. All downstream
devices disconnected
because of power loss.
* Asynchronous resume logic active only when PME_Enable register bit is active.
A wakeup event (power management event) detected by a USB host controller is considered either an upstream
resume detected or a connect status change (device disconnecting/connecting) detected. Any of these events
detected by the USS-344 while the power management event is enabled will cause PMEN to be issued.
This power management feature is considered an extension of the PCI Specification and is only present when
enabled by the TEST1 input pin. While the TEST1 input pin is logic 0 (or ground), the power management function
is enabled, the Power Management registers and Capabilities Pointer register are accessible, and the PCI Config-
uration Space Status register, bit 4, will read as logic 1 (capabilities list present). While the TEST1 input pin is
logic 1, the power management function is disabled, the Power Management registers and Capabilities Pointer
register are inaccessible and read as 0h, and the PCI Configuration Space Status register, bit 4, will read as logic 0
(no capabilities list).
42
Agere Systems Inc.
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
Power Management Interface (continued)
The CLK48STOP output pin is active if all four PCI cores in the USS-344 multifunction PCI device have been
placed into the D3hot state. This will allow the external 48 MHz oscillator to be disabled and in a low-power mode
while in this state. CLK48STOP is only active in D3hot state since this is the only low-power state with sufficient
state-change latency to allow the external oscillator to be stopped.
PMEN is an open collector output allowing wire-OR of several PMEN signals.
The following Power Management register definitions present the specific implementation of the PCI Bus Power
Management Interface Specification for the USS-344. All the following registers are located in the PCI configura-
tion memory space of each controller in the USS-344. All further information concerning the register functions and
the system implementation of this interface should be referenced from the PCI Bus Power Management Interface
Specification Revision 1.1 available from the PCI Special Interest Group.
Configuration Space Offset 50h
Table 130. Capabilities Identifier (Cap_ID) Register
Bits
Default
Value
Read/Write
Description
7:0
01h
R
This capability is for the PCI power management data structure.
Configuration Space Offset 51h
Table 131. Next Item Pointer Register
Bits
Default
Value
Read/Write
Description
7:0
00h
R
No other PCI capabilities are implemented.
Agere Systems Inc.
43
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
Power Management Interface (continued)
Configuration Space Offset 52h
Table 132. Power Management Capabilities Register
Bits
Default
Value
Read/
Write
Name/Description
15:11
01110b
R
PME_Support. Specifies the states in which the PME signal can be asserted.
XXXX0b—PME cannot be asserted in D0 state.
XXX1Xb—PME can be asserted in D1 state.
XX1XXb—PME can be asserted in D2 state.
X1XXXb—PME can be asserted in D3hot state.
0XXXXb—PME cannot be asserted in D3cold state.
10
9
1b
1b
R
R
R
D2_Support. This device supports the D2 power management state.
D1_Support. This device supports the D1 power management state.
8:6
000b
Aux_Current. PMEN generation is not supported by this function. Therefore,
this register is not applicable and returns 000b.
5
0b
R
DSI. No device specific initialization sequence is required before using this
device.
Reserved.
4
3
2:0
0b
0b
010b
R
R
R
PME Clock. No clocks are required for this device to issue PMEN.
Version. PCI Power Management Interface Specification Revision 1.1 compli-
ant.
Configuration Space Offset 54h
Table 133. Power Management Control/Status Register
Bits
Default
Value
Read/
Write
Name/Description
15
0b
Read/
Write-
Clear
PME_Status. This bit is set when the function would normally assert the
PMEN signal independent of the state of the PME_En bit.
Writing a 1b to this bit will clear the PME_Status bit and force the function to
stop asserting PMEN.
14:13
12:9
See
R
Data Scale. Variable based upon data select. See Table 136.
Table 136
0000b
R/W
Data_Select. The system uses this register to select the appropriate data for
reporting in the Data Scale register and Data register.
8
7:2
1:0
0b
000000b
00b
R/W
R
R/W
PME_En. When active (1b), the function is enabled to assert PMEN.
Reserved.
Power_State. Represents the current power state of the function.
44
Agere Systems Inc.
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
Power Management Interface (continued)
Configuration Space Offset 56h
Table 134. Power Management Bridge Support Extensions
Bits
Default
Value
Read/
Write
Name/Description
7
0b
R
BPCC_En (Bus Power/Clock Control Enable). This is not a PCI bridge func-
tion.
6
5:0
0b
000000b
R
R
B2_B3# (B2/B3 Support for D3hot). This is not a PCI bridge function.
Reserved.
Configuration Space Offset 57h
Table 135. Data Register
Bits
Default
Value
Read/
Write
Description
7:0
See
R
Represents the amount of power dissipated or consumed in various power
management states. Variable based upon data select. See Table 136.
Table 136
Power Consumption/Dissipation Reporting
Table 136. Power Consumption/Dissipation Reporting
Value In Data
Select
Data Reported
Data
Data Scale
Units (Interpreting Data
Scale)
0000b
D0 Power Consumed
D1 Power Consumed
D2 Power Consumed
D3 Power Consumed
D0 Power Dissipated
D1 Power Dissipated
D2 Power Dissipated
D3 Power Dissipated
Reserved (single-function
PCI device configuration)
1Fh
38h
01b
10b
11b
11b
10b
10b
11b
11b
00b
mW * 100
mW * 100
mW
0001b
0010b
66h
0011b
07h
mW
0100b
37h
mW * 10
mW * 10
mW
0101b
37h
0110b
64h
0111b
03h
mW
NA
1000b—1111b
00000000b
Agere Systems Inc.
45
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
NAND Tree Mode
The USS-344 can be placed in a NAND tree mode of operation for board-level production testing. The NAND tree
is designed to allow board-level contact testing of inputs and bidirectional pins of the USS-344.
To activate the NAND tree in the USS-344, force pin 63 (TEST2) to a logic high and force pin 64 (TEST3) to a logic
low. Pins 62 and 61 (TEST1 and TEST0) may be high or low. No clocks are required. When this is performed, the
NAND tree will be active and follow the order of the map presented in Table 137. Figure 8 shows the NAND tree
logic structure. The test mode connection instructions should be followed to place the USS-344 in NAND tree
mode.
Table 137. NAND Tree
Order
Pin
Pin
Order
Pin
Pin
Assignment
Number
Name
Assignment
Number
Name
1 (Start)
81
CLK48STOP
XLO/CLK48
SMIN
41
10
11
12
13
16
17
18
19
22
23
24
25
26
29
30
31
32
35
36
37
38
41
42
43
44
47
48
49
50
53
54
55
56
67
68
69
70
71
72
AD21
AD20
AD19
AD18
AD17
AD16
C/BEN2
FRAMEN
IRDYN
TRDYN
DEVSELN
STOPN
PERRN
SERRN
PAR
C/BEN1
AD15
AD14
AD13
AD12
AD11
2
83
42
3
75
43
4
76
PRTPWR0
PWRFLT0N
PRTPWR1
PWRFLT1N
DPLS0
DMNS0
DPLS1
DMNS1
DPLS2
DMNS2
DPLS3
DMNS3
PRTPWR2
PWRFLT2N
PRTPWR3
PWRFLT3N
INTAN
44
5
77
45
6
78
46
7
79
47
8
89
48
9
90
49
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
91
50
92
51
95
52
96
53
97
54
98
55
101
102
103
104
105
108
109
110
111
113
115
116
119
120
121
122
125
126
127
128
3
56
57
58
59
60
INTBN
61
INTCN
62
AD10
AD9
AD8
INTDN
63
RSTN
64
CLK
65
C/BEN0
AD7
GNTN
66
REQN
67
AD6
PMEN
68
AD5
AD31
69
AD4
AD30
70
AD3
AD29
71
AD2
AD28
72
AD1
AD27
73
AD0
AD26
74
MIRQ12I
KIRQ1I
A20I
AD25
75
AD24
76
4
C/BEN3
IDSEL
77
A20MN
IRQ1
IRQ12
5
78
6
AD23
AD22
Output Pin
7
46
Agere Systems Inc.
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
NAND Tree Mode (continued)
CLK48STOP
VDD
CLK48
SMIN
PRTPWR0
PWRFLT0N
A20MN
IRQ1
IRQ12
5-7276a
Figure 8. NAND Tree Logic Structure
Agere Systems Inc.
47
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
Absolute Maximum Ratings
Table 138. Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Unit
Ambient Operating Temperature Range
Storage Temperature
Voltage on Any Pin with Respect to Ground
VDD
TA
Tstg
—
0
−40
VSS − 0.3
3.0
70
125
5.5
°C
°C
V
—
3.6
V
VDDT
VIO (3.3 V operation)
VIO (5 V operation)
—
—
—
3.135
3.0
4.75
3.465
3.6
5.25
V
V
V
48
Agere Systems Inc.
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
Electrical Characteristics
Table 139. Power Dissipation
Parameter
Symbol
Min
Typ
Max
Unit
Power Dissipation
PD
283
345
410
mW
PCI Electrical Characteristics
PCI Timing Specifications
The clock waveform must be delivered to each PCI component in the system. In the case of expansion boards,
compliance with the clock specification is measured at the expansion board component, not at the connector slot.
Figure 9 shows the clock waveform and required measurement points for both 5 V and 3.3 V signaling environ-
ments. Table 140 summarizes the clock specifications.
5 V CLOCK
2.4 V
2.0 V
1.5 V
2 Vp-p
(MINIMUM)
0.5 V
0.4 V
tCYC
tHIGH
0.6VCC
3.3 V CLOCK
0.5VCC
0.4VCC
0.3VCC
tLOW
0.4VCC Vp-p
(MINIMUM)
0.2VCC
5-6474
Figure 9. Clock Waveforms
Agere Systems Inc.
49
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
Electrical Characteristics (continued)
PCI Timing Parameters
Table 140. Clock and Reset Specifications
Symbol
Parameter
CLK Cycle Time1
CLK High Time
CLK Low Time
CLK Slew Rate2
RSTN Slew Rate3
Min
Max
Unit
tCYC
tHIGH
tLOW
—
30
11
11
1
∞
—
—
4
ns
ns
ns
V/ns
mV/ns
—
50
—
1. In general, all PCI components must work with any clock frequency between nominal dc and 33 MHz. Device operational parameters at
frequencies under 16 MHz may be guaranteed by design rather than by testing. The clock frequency may be changed at any time during the
operation of the system, as long as the clock edges remain clean (monotonic), and the minimum cycle and high and low times are not
violated. The clock may only be stopped in a low state. A variance on this specification is allowed for components designed for use on the
system motherboard only. These components may operate at any single fixed frequency up to 33 MHz and may enforce a policy of no
frequency changes.
2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak
portion of the clock waveform, as shown in Figure 9.
3. The minimum RSTN slew rate applies only to the rising (deassertion) edge of the reset signal and ensures that system noise cannot render
an otherwise monotonic signal to appear to bounce in the switching range.
50
Agere Systems Inc.
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
Electrical Characteristics (continued)
Table 141. 5 V and 3.3 V PCI Timing Parameters
Symbol
Parameter
Min
Max
Unit
tVAL
tVAL(ptp)
tON
tOFF
tSU
tSU(ptp)
tH
tRST
tRST-CLK
tRST-OFF
tRRSU
tRRH
CLK to Signal Valid Delay—Bused Signals1, 2, 3
CLK to Signal Valid Delay—Point to Point1, 2, 3
Float to Active Delay1, 7
2
11
12
—
28
—
—
—
—
—
40
—
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
2
Active to Float Delay1, 7
—
Input Setup Time to CLK—Bused Signals3, 4
Input Setup Time to CLK—Point to Point3, 4
Input Hold Time from CLK4
7
10, 12
0
Reset Active Time After Power Stable5
Reset Active Time After CLK Stable5
Reset Active to Output Float Delay5, 6, 7
REQN to RSTN Setup Time
1
100
—
10 × tCYC
0
RSTN to REQN Hold Time
1. See the timing measurement conditions in Figure 4-8 of PCI Specification Revision 2.1.
2. For parts compliant to the 5 V signaling environment:
Minimum times are evaluated with 0 pF equivalent load; maximum times are evaluated with 50 pF equivalent load. Actual test capacitance
may vary, but results should be correlated to these specifications. Note that faster buffers may exhibit some ring back when attached to a
50 pF lump load, which should be of no consequence as long as the output buffers are in full compliance with slew rate and V/I curve spec-
ifications.
For parts compliant to the 3.3 V signaling environment:
Minimum times are evaluated with same load used for slew rate measurement (see PCI Specification, Rev. 2.1s); maximum times are eval-
uated with the following load circuits, for high-going and low-going edges, respectively.
TVAL(MAX) RISING EDGE
TVAL(MAX) FALLING EDGE
PIN
1/2 IN. MAX.
1/2 IN. MAX.
OUTPUT
BUFFER
VCC
25 Ω
10 pF
10 pF
25 Ω
3. REQN and GNTN are point-to-point signals and have different output valid delay and input setup times than bused signals. GNTN has a
setup time of 10 ns; REQN has a setup time of 12 ns. All other signals are bused.
4. See the timing measurement conditions in Figure 4-8 of PCI Specification Revision 2.1.
5. RSTN is asserted and deasserted asynchronously with respect to CLK.
6. All output drivers must be asynchronously floated when RSTN is active.
7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the compo-
nent pin is less than or equal to the leakage current specification.
Agere Systems Inc.
51
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
Electrical Characteristics (continued)
USB Electrical Characteristics
Table 142. Full-Speed Source USB Electrical Characteristics
Parameter
Symbol
Conditions1, 2, 3
Min
Max
Unit
Driver Characteristics
Transition Time4, 5
Rise Time
:
tR
tF
CL = 50 pF
CL = 50 pF
4
4
20
20
ns
ns
Fall Time
Rise/Fall Time Matching
Output Signal Crossover Voltage
Driver Output Resistance
Data Source Timings
tRFM
VCRS
ZDRV
(TR/TF)
—
90
1.3
28
110
2.0
43
%
V
Steady-State Drive
Ω
Full-speed Data Rate
tDRATE
tFRAME
Average Bit Rate
11.97
12.03
Mbits/s
ms
(12 Mbits/s 0.25%)
Frame Interval
1.0 ms 0.05%
0.9995
1.0005
1. All voltages measured from the local ground potential, unless otherwise specified.
2. All timings use a capacitive load (CL) to ground of 50 pF, unless otherwise specified.
3. Full-speed timings have a 1.5 kΩ pull-up to 2.8 V on the D+ data line.
4. Measured from 10% to 90% of the data signal.
5. The rising and falling edges should be smoothly transitioning (monotonic).
Table 143. Low-Speed Source USB Electrical Characteristics
Parameter
Symbol
Conditions
Min
Max
Unit
Driver Characteristics
Transition Time1, 2
Rise Time
:
tR
tF
CL = 50 pF
CL = 350 pF
CL = 50 pF
CL = 350 pF
75
—
75
—
—
300
—
ns
ns
ns
ns
%
V
Fall Time
300
Rise/Fall Time Matching
Output Signal Crossover Voltage
Data Source Timings
tRFM
VCRS
(TR/TF)
—
80
120
2.0
1.3
Low-speed Data Rate
tDRATE
Average Bit Rate
1.4775
1.5225
Mbits/s
(1.5 Mbits/s 1.5%)
1. Measured from 10% to 90% of the data signal.
2. The rising and falling edges should be smoothly transitioning (monotonic).
Table 144. CLK48 Clock Specification
Parameter
CLK Cycle Time
CLK High Time
CLK Low Time
Symbol
Min
Max
Unit
tCYC
tHIGH
tLOW
20.8 − 0.01%
8.32
20.8 + 0.01%
12.48
ns
ns
ns
8.32
12.48
52
Agere Systems Inc.
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
Physical Markings
Each USS-344 will be physically marked as follows:
USS344
X
Y
REVISION IDENTIFICATION.
i.e., B IS USS-344 REVISION B
PACKAGE TYPE. T: 128-PIN TQFP
USS-344 DEVICE
5-8116a
Outline Diagram
128-Pin TQFP
Dimensions are in millimeters.
16.00 0.20
14.00 0.20
PIN #1 IDENTIFIER ZONE
103
1.00 REF
128
0.25
1
102
GAGE PLANE
SEATING PLANE
0.45/0.75
DETAIL A
20.00
0.20
22.00
0.20
0.106/0.200
0.19/0.27
M
38
65
0.08
DETAIL B
39
64
DETAIL A
DETAIL B
1.40 0.05
1.60 MAX
SEATING PLANE
0.08
0.50 TYP
0.05/0.15
5-4427
Agere Systems Inc.
53
USS-344 QuadraBus
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
Ordering Information
Device Code
Package
Comcode
USS344S-DB
128-Pin TQFP
108556937
For additional information, contact your Agere Systems Account Manager or the following:
INTERNET:
E-MAIL:
http://www.agere.com
docmaster@micro.lucent.com
N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)
ASIA PACIFIC: Agere Systems Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256
Tel. (65) 778 8833, FAX (65) 777 7495
CHINA:
Agere Systems (Shanghai) Co., Ltd., 33/F Jin Mao Tower, 88 Century Boulevard Pudong, Shanghai 200121 PRC
Tel. (86) 21 50471212, FAX (86) 21 50472266
JAPAN:
Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan
Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700
EUROPE:
Data Requests: DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148
Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot),
FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki),
ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
QuadraBus is a trademark of Agere Systems Inc.
Copyright © 2001 Agere Systems Inc.
All Rights Reserved
Printed in U.S.A.
June 2001
DS99-330CMPR-9 (Replaces DS99-330CMPR-8)
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