8102805PC [AGILENT]
Logic IC Output Optocoupler, 2-Element, 2500V Isolation, 10MBps, HERMETIC SEALED, CERAMIC, DIP-8;
| 型号： | 8102805PC |
| 厂家： | 
AGILENT TECHNOLOGIES, LTD. |
| 描述： | Logic IC Output Optocoupler, 2-Element, 2500V Isolation, 10MBps, HERMETIC SEALED, CERAMIC, DIP-8 输出元件 光电 |
| 文件： | 总12页 (文件大小：262K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Hermetically Sealed, High Speed,
High CMR, Logic Gate
Optocouplers
6N134*
81028
5962-98001
HCPL-268K
HCPL-563X HCPL-665X
HCPL-663X 5962-90855
HCPL-565X HCPL-560X
*See matrix for available extensions.
Technical Data
Features
• Line Receiver
Truth Table
(Positive Logic)
Multichannel Devices
• Dual Marked with Device
Part Number and DSCC
Drawing Number
• Manufactured and Tested on
a MIL-PRF-38534 Certified
Line
• QML-38534, Class H and K
• Five Hermetically Sealed
Package Configurations
• Performance Guaranteed
over -55°C to +125°C
• High Speed: 10 M Bit/s
• CMR: > 10,000 V/µs Typical
• 1500 Vdc Withstand Test
Voltage
• 2500 Vdc Withstand Test
Voltage for HCPL-565X
• High Radiation Immunity
• 6N137, HCPL-2601, HCPL-
2630/-31 Function
Compatibility
• Reliability Data
• TTL Circuit Compatibility
• Voltage Level Shifting
• Isolated Input Line Receiver
• Isolated Output Line Driver
• Logic Ground Isolation
• Harsh Industrial
Environments
• Isolation for Computer,
Communication, and Test
Equipment Systems
Input
On (H)
Off (L)
Output
L
H
Single Channel DIP
Input
Enable
Output
On (H)
Off (L)
On (H)
Off (L)
H
H
L
L
Description
H
H
H
These units are single, dual and
quad channel, hermetically sealed
optocouplers. The products are
capable of operation and storage
over the full military temperature
range and can be purchased as
either standard product or with
full MIL-PRF-38534 Class Level H
or K testing or from the appropri-
ate DSCC Drawing. All devices are
manufactured and tested on a
MIL-PRF-38534 certified line and
are included in the DSCC Quali-
fied Manufacturers List QML-
38534 for Hybrid Microcircuits.
Quad channel devices are
L
Functional Diagram
Multiple Channel Devices
Available
V
CC
V
E
V
OUT
Applications
• Military and Space
• High Reliability Systems
• Transportation, Medical, and
Life Critical Systems
GND
available by special order in the
16 pin DIP through hole
packages.
The connection of a 0.1 µF bypass capacitor between VCC and GND is recommended.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.
2
Each channel contains a GaAsP
light emitting diode which is
optically coupled to an integrated
high speed photon detector. The
output of the detector is an open
collector Schottky clamped
transistor. Internal shields
provide a guaranteed common
mode transient immunity
specification of 1000 V/µs. For
Isolation Voltage applications
requiring up to 2500 Vdc, the
HCPL-5650 family is also
E respectively), and 16 pin
surface mount DIP flat pack
(case outline F), leadless ceramic
chip carrier (case outline 2).
Devices may be purchased with a
variety of lead bend and plating
options. See Selection Guide
Table for details. Standard
Microcircuit Drawing (SMD)
parts are available for each
package and lead style.
maximum ratings, recommended
operating conditions, electrical
specifications, and performance
characteristics shown in the figures
are identical for all parts.
Occasional exceptions exist due to
package variations and limitations,
and are as noted. Additionally, the
same package assembly processes
and materials are used in all
devices. These similarities give
justification for the use of data
obtained from one part to
represent other parts’ performance
for reliability and certain limited
radiation test results.
Because the same electrical die
(emitters and detectors) are used
for each channel of each device
listed in this data sheet, absolute
available. Package styles for
these parts are 8 and 16 pin DIP
through hole (case outlines P and
Selection Guide–Package Styles and Lead Configuration Options
Package
Lead Style
16 Pin DIP
8 Pin DIP
8 Pin DIP
8 Pin DIP
16 Pin Flat Pack 20 Pad LCCC
Through Hole Through Hole Through Hole Through Hole Unformed Leads Surface Mount
Channels
2
1
2
2
4
2
Common Channel
Wiring
VCC, GND
None
VCC, GND
VCC, GND
VCC, GND
None
Withstand Test Voltage
Agilent Part # & Options
Commercial
1500 Vdc
1500 Vdc
1500 Vdc
2500 Vdc
1500 Vdc
1500 Vdc
6N134*
HCPL-5600
HCPL-5630
HCPL-5631
HCPL-563K
Gold Plate
HCPL-5650
HCPL-5651
HCPL-6650
HCPL-6651
HCPL-665K
Gold Plate
HCPL-6630
HCPL-6631
HCPL-663K
Solder Pads
MIL-PRF-38534, Class H 6N134/883B HCPL-5601
MIL-PRF-38534, Class K HCPL-268K
HCPL-560K
Gold Plate
Standard Lead Finish
Solder Dipped
Gold Plate
Gold Plate
Option #200 Option #200 Option #200 Option #200
Option #100 Option #100 Option #100
Butt Cut/Gold Plate
Gull Wing/Soldered
Class H SMD Part #
Prescript for all below
Either Gold or Solder
Gold Plate
Option #300 Option #300 Option #300
None
5962-
None
None
None
None
8102801EX 9085501HPX 8102802PX
8102801EC 9085501HPC 8102802PC
8102801EA 9085501HPA 8102802PA
8102801UC 9085501HYC 8102802YC
8102801UA 9085501HYA 8102802YA
8102801TA 9085501HXA 8102802ZA
8102805PX
8102805PC
8102805PA
8102804FX
8102804FC
81028032X
Solder Dipped
81028032A
Butt Cut/Gold Plate
Butt Cut/Soldered
Gull Wing/Soldered
Class K SMD Part #
Prescript for all below
Either Gold or Solder
Gold Plate
5962-
5962-
5962-
5962-
5962-
9800101KEX 9085501KPX 9800102KPX
9800101KEC 9085501KPC 9800102KPC
9800101KEA 9085501KPA 9800102KPA
9800101KUC 9085501KYC 9800102KYC
9800101KUA 9085501KYA 9800102KYA
9800101KTA 9085501KXA 9800102KZA
9800104KFX
9800104KFC
9800103K2X
Solder Dipped
9800103K2A
Butt Cut/Gold Plate
Butt Cut/Soldered
Gull Wing/Soldered
*JEDEC registered part.
3
Functional Diagrams
16 Pin DIP
Through Hole
2 Channels
8 Pin DIP
Through Hole
1 Channel
8 Pin DIP
Through Hole
2 Channels
16 Pin Flat Pack
Unformed Leads
4 Channels
20 Pad LCCC
Surface Mount
2 Channels
15
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
V
CC2
V
1
2
3
4
8
7
6
5
1
V
8
CC
CC
V
V
CC
15
14
13
CC
19
20
13
12
V
O2
V
O1
O2
V
V
V
V
V
E
O1
O2
O3
O1
2
3
4
7
6
5
GND
2
V
V
OUT
V
CC1
2
3
10
V
O1
V
O2 12
11
V
O4
GND
GND
1
GND
GND
GND
10
9
7
8
Note: All DIP and flat pack devices have common VCC and ground. Single channel DIP has an enable pin 7. LCCC (leadless ceramic
chip carrier) package has isolated channels with separate VCC and ground connections. All diagrams are “top view.”
Outline Drawings
16 Pin DIP Through Hole, 2 Channels
20.06 (0.790)
20.83 (0.820)
8.13 (0.320)
MAX.
0.89 (0.035)
1.65 (0.065)
4.45 (0.175)
MAX.
0.51 (0.020)
MIN.
3.81 (0.150)
0.20 (0.008)
0.33 (0.013)
MIN.
7.36 (0.290)
7.87 (0.310)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
Leaded Device Marking
Leadless Device Marking
Agilent DESIGNATOR
A QYYWWZ
XXXXXX
XXXXXXX
XXX XXX
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
Agilent DESIGNATOR
Agilent P/N
PIN ONE/
ESD IDENT
COUNTRY OF MFR.
A QYYWWZ
XXXXXX
• XXXX
XXXXXX
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
DSCC SMD*
DSCC SMD*
Agilent CAGE CODE*
Agilent P/N
DSCC SMD*
DSCC SMD*
PIN ONE/
COUNTRY OF MFR.
Agilent CAGE CODE*
•
50434
XXX 50434
ESD IDENT
* QUALIFIED PARTS ONLY
* QUALIFIED PARTS ONLY
4
Outline Drawings (continued)
8 Pin DIP Through Hole, 1 and 2 Channels
8 Pin DIP Through Hole, 2 Channels
2500 Vdc Withstand Test Voltage
9.40 (0.370)
9.91 (0.390)
8.13 (0.320)
MAX.
9.40 (0.370)
9.91 (0.390)
8.13 (0.320)
MAX.
0.76 (0.030)
1.27 (0.050)
0.76 (0.030)
1.27 (0.050)
7.16 (0.282)
7.57 (0.298)
7.16 (0.282)
7.57 (0.298)
4.32 (0.170)
MAX.
5.08 (0.200)
MAX.
3.81 (0.150)
MIN.
0.51 (0.020)
MIN.
0.20 (0.008)
0.33 (0.013)
0.51 (0.020)
3.81 (0.150)
MIN.
0.20 (0.008)
0.33 (0.013)
MIN.
7.36 (0.290)
7.87 (0.310)
7.36 (0.290)
7.87 (0.310)
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
16 Pin Flat Pack, 4 Channels
20 Terminal LCCC Surface Mount,
2 Channels
7.24 (0.285)
6.99 (0.275)
8.70 (0.342)
9.10 (0.358)
2.29 (0.090)
MAX.
4.95 (0.195)
5.21 (0.205)
1.78 (0.070)
1.02 (0.040) (3 PLCS)
2.03 (0.080)
1.14 (0.045)
1.40 (0.055)
8.70 (0.342)
9.10 (0.358)
4.95 (0.195)
11.13 (0.438)
10.72 (0.422)
TERMINAL 1 IDENTIFIER
2.16 (0.085)
5.21 (0.205)
1.27 (0.050)
REF.
METALLIZED
CASTILLATIONS (20 PLCS)
1.78 (0.070)
2.03 (0.080)
0.64
(0.025)
(20 PLCS)
0.51 (0.020)
0.46 (0.018)
0.36 (0.014)
1.52 (0.060)
2.03 (0.080)
8.13 (0.320)
MAX.
2.85 (0.112)
MAX.
0.31 (0.012)
0.23 (0.009)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
SOLDER THICKNESS 0.127 (0.005) MAX.
0.88 (0.0345)
MIN.
9.02 (0.355)
8.76 (0.345)
5.23
(0.206)
MAX.
0.89 (0.035)
0.69 (0.027)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
5
Hermetic Optocoupler Options
Option
Description
100
Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This
option is available on commercial and hi-rel product in 8 and 16 pin DIP (see drawings below
for details).
4.32 (0.170)
MAX.
0.51 (0.020)
1.14 (0.045)
MIN.
1.40 (0.055)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
4.32 (0.170)
MAX.
0.51 (0.020)
MIN.
1.14 (0.045)
1.40 (0.055)
0.20 (0.008)
0.33 (0.013)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
7.36 (0.290)
7.87 (0.310)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
200
300
Lead finish is solder dipped rather than gold plated. This option is available on commercial
and hi-rel product in 8 and 16 pin DIP. DSCC Drawing part numbers contain provisions for
lead finish. All leadless chip carrier devices are delivered with solder dipped terminals as a
standard feature.
Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This
option is available on commercial and hi-rel product in 8 and 16 pin DIP (see drawings below
for details). This option has solder dipped leads.
4.57 (0.180)
MAX.
0.51 (0.020)
1.40 (0.055)
MIN.
1.65 (0.065)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
4.57 (0.180)
MAX.
4.57 (0.180)
MAX.
0.20 (0.008)
0.33 (0.013)
0.51 (0.020)
MIN.
5° MAX.
1.40 (0.055)
1.65 (0.065)
9.65 (0.380)
9.91 (0.390)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
6
Absolute Maximum Ratings
(No derating required up to +125°C)
Storage Temperature Range, TS ...................................-65°C to +150°C
Operating Temperature, TA ..........................................-55°C to +125°C
Case Temperature, TC ................................................................+170°C
Junction Temperature, T ...........................................................+175°C
J
Lead Solder Temperature ............................................... 260°C for 10 s
Peak Forward Input Current, IF PK, (each channel,
≤ 1 ms duration) ...................................................................... 40 mA
Average Input Forward Current, IF AVG (each channel) ................ 20 mA
Input Power Dissipation (each channel) ..................................... 35 mW
Reverse Input Voltage, VR (each channel) ......................................... 5 V
Supply Voltage, VCC (1 minute maximum) ........................................ 7 V
Output Current, IO (each channel) ............................................... 25 mA
Output Power Dissipation (each channel) .................................. 40 mW
Output Voltage, VO (each channel).................................................. 7 V*
Package Power Dissipation, PD (each channel) ........................ 200 mW
*Selection for higher output voltages up to 20 V is available.
Single Channel Product Only
Emitter Input Voltage, VE ............................................................... 5.5 V
8 Pin Ceramic DIP Single Channel Schematic
Note enable pin 7. An external
0.01 µF to 0.1 µF bypass
capacitor must be connected
between VCC and ground for each
package type.
ESD Classification
(MIL-STD-883, Method 3015)
HCPL-5600/01/0K ............................................................... (∆), Class 1
6N134, 6N134/883B, HCPL-5630/31/3K, HCPL-5650/51,
HCPL-6630/31/3K and HCPL-6650/51/5K....................... (Dot), Class 3
Recommended Operating Conditions
Parameter
Symbol
IFL
Min.
0
10
Max.
250
20
5.5
6
Units
µA
mA
V
Input Current, Low Level, Each Channel
Input Current, High Level, Each Channel*
Supply Voltage, Output
IFH
VCC
N
4.5
Fan Out (TTL Load) Each Channel
*Meets or exceeds DSCC SMD and JEDEC requirements.
7
Recommended Operating Conditions (cont’d.)
Single Channel Product Only[10]
Parameter
High Level Enable Voltage
Low Level Enable Voltage
Symbol
Min.
2.0
0
Max.
VCC
0.8
Units
V
V
VEH
VEL
Electrical Characteristics (TA = -55°C to +125°C, unless otherwise specified)
Limits
Subgroups Min. Typ.** Max. Units Fig. Note
Group A[13]
Parameter
High Level
Output Current
Low Level
Output Voltage
Symbol
IOH*
Test Conditions
VCC = 5.5 V, VO = 5.5 V,
IF = 250 µA
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
20
250
µA
1
1
1, 9
1
VOL* VCC = 5.5 V, IF = 10 mA,
IOL (Sinking) = 10 mA
hF CTR VO = 0.6 V, IF = 10 mA,
VCC = 5.5 V
0.3
0.6
V
2
Current Transfer
Ratio
100
%
Logic
Single
ICCH*
VCC = 5.5 V, IF = 0 mA
9
14
28
42
18
36
50
1.9
mA
mA
mA
mA
mA
mA
1
High
Channel
Supply
Current
Dual
Channel
VCC = 5.5 V,
IF1 = IF2 = 0 mA
VCC = 5.5 V, IF1 = IF2 =
IF3 = IF4 = 0 mA
VCC = 5.5 V,
IF = 20 mA
VCC = 5.5 V,
IF1 = IF2 = 20 mA
VCC = 5.5 V, IF1 = IF2 =
IF3 = IF4 = 20 mA
IF = 20 mA
18
25
13
26
33
1.5
6
Quad
Channel
Logic
Single
ICCL*
1, 2, 3
1
6
Low
Channel
Supply
Current
Dual
Channel
Quad
Channel
Input Forward
Voltage
VF*
1, 2, 3
1, 2
V
V
3
3
1, 15
1, 16
1.55 1.75
1.85
3
Input Reverse
Breakdown
Voltage
BVR* IR = 10 µA
1, 2, 3
5
V
1
Input-Output
Leakage Current
II-O*
RH = 45%
V
I-O = 1500
1
1.0
1.0
µA
2, 8, 17
18
1, 3,
14
Vdc
T = 25°C
A
VI-O = 2500
t = 5 s
f = 1 MHz, TC = 25°C
1
4
µA
pF
Vdc
Capacitance
Between Input/
Output
CI-O
1.0
4.0
*Identified test parameters for JEDEC registered parts.
**All typical values are at VCC = 5 V, TA = 25°C.
8
Electrical Characteristics, (Contd.) TA = -55°C to +125°C unless otherwise specified
Group A[13]
Limits
Test
Conditions
Parameter
Symbol
Subgroups Min. Typ.** Max. Units Fig. Note
Propagation Delay
Time to High
Output Level
VCC = 5 V,
tPLH
*
9
10, 11
9
60
55
100
140
100
120
ns
4, 5, 1, 5
6
RL = 510 Ω,
CL = 50 pF,
IF = 13 mA
Propagation Delay
Time to Low
Output Level
tPHL*
ns
ns
10, 11
Output Rise Time
Output Fall Time
tLH
tHL
RL = 510 Ω,
CL = 50 pF,
IF = 13 mA
9, 10, 11
35
35
90
40
1
Common Mode
Transient
Immunity at
High Output
Level
Common Mode
Transient
|CMH| VCM = 50 V(PEAK), 9, 10, 11
VCC = 5 V,
1000 >10000
V/µs
V/µs
7
7
1, 7,
14
VO (min.) = 2 V,
RL = 510 Ω,
IF = 0 mA
|CML| VCM = 50 V(PEAK), 9, 10, 11
VCC = 5 V,
1000 >10000
1, 7,
14
Immunity at
Low Output
Level
VO (max.) = 0.8 V,
RL = 510 kΩ,
IF = 10 mA
Single Channel Product Only
Low Level
Enable Current
High Level
Enable Voltage
IEL
VEH
VEL
VCC = 5.5 V,
VE = 0.5 V
1, 2, 3
1, 2, 3
1, 2, 3
-1.45
2.0
-2.0 mA
V
10
Low Level
0.8
V
Enable Voltage
*Identified test parameters for JEDEC registered part.
**All typical values are at VCC = 5 V, TA = 25°C.
Typical Characteristics, TA = 25°C, VCC = 5 V
Parameter
Input Capacitance
Input Diode Temperature
Coefficient
Sym.
CIN
∆VF
∆TA
RI-O
Typ.
60
-1.5
Units
pF
mV/°C
Test Conditions
VF = 0 V, f = 1 MHz
IF = 20 mA
Fig.
Note
1
1
Resistance (Input-Output)
1012
Ω
VI-O = 500 V
2
Single Channel Product Only
Propagation Delay Time of
Enable from VEH to VEL
Propagation Delay Time of
Enable from VEL to VEH
tELH
tEHL
35
35
ns
ns
RL = 510 Ω, CL = 50 pF
IF = 13 mA, VEH = 3 V,
VEL = 0 V
8, 9
1, 11
1, 12
Dual and Quad Channel Product Only
Input-Input
II-I
0.5
nA
Relative Humidity = 45%
4
Leakage Current
Resistance (Input-Input)
Capacitance (Input-Input)
V = 500 V, t = 5 s
I-I
RI-I
CI-I
1012
0.55
Ω
V = 500 V
4
4
I-I
pF
f = 1 MHz
9
Notes:
1. Each channel.
2. All devices are considered two-terminal devices; II-O is measured between all input leads or terminals shorted together and all
output leads or terminals shorted together.
3. Measured between each input pair shorted together and all output connections for that channel shorted together.
4. Measured between adjacent input pairs shorted together for each multichannel device.
5. tPHL propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.5 V point on the leading
edge of the output pulse. The tPLH propagation delay is measured from the 50% point on the trailing edge of the input pulse to the
1.5 V point on the trailing edge of the output pulse.
6. The HCPL-6630, HCPL-6631, and HCPL-663K dual channel parts function as two independent single channel units. Use the single
channel parameter limits for each channel.
7. CML is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state
(VO < 0.8 V). CMH is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the
logic high state (VO > 2.0 V).
8. This is a momentary withstand test, not an operating condition.
9. It is essential that a bypass capacitor (0.01 to 0.1 µF, ceramic) be connected from VCC to ground. Total lead length between both
ends of this external capacitor and the isolator connections should not exceed 20 mm.
10. No external pull up is required for a high logic state on the enable input.
11. The tELH enable propagation delay is measured from the 1.5 V point on the trailing edge of the enable input pulse to the 1.5 V
point on the trailing edge of the output pulse.
12. The tEHL enable propagation delay is measured from the 1.5 V point on the leading edge of the enable input pulse to the 1.5 V
point on the leading edge of the output pulse.
13. Standard parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD and 883B parts receive 100% testing at 25, 125, and
-55°C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively).
14. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed
to limits specified for all lots not specifically tested.
15. Not required for 6N134, 6N134/883B, 8102801, HCPL-268K and 5962-9800101 types.
16. Required for 6N134, 6N134/883B, 8102801, HCPL-268K and 5962-9800101 types.
17. Not required for HCPL-5650, HCPL-5651 and 8102805 types.
18. Required for HCPL-5650, HCPL-5651 and 8102805 types only.
Figure 1. High Level Output Current
vs. Temperature.
Figure 2. Input-Output
Characteristics.
Figure 3. Input Diode Forward
Characteristic.
10
D.U.T.
5 V
V
CC
PULSE
GENERATOR
R
L
I
F
V
O
Z
t
= 50 Ω
= 5 ns
O
H
0.01 µF
BYPASS
V
O
C *
L
INPUT
MONITORING
NODE
GND
Rm
* C INCLUDES PROBE AND STRAY WIRING CAPACITANCE.
L
Figure 5. Propagation Delay, t
PLH
and
PHL
t
vs. Pulse Input Current, I
.
FH
Figure 4. Test Circuit for t
and t
.*
PLH
PHL
D.U.T.
+5 V
B
V
CC
510 Ω
I
I
A
OUTPUT V
MONITORING
NODE
O
0.01 µF
BYPASS
GND
–
V
FF
V
CM
+
PULSE GEN.
Figure 6. Propagation Delay vs.
Temperature.
Figure 7. Test Circuit for Common Mode Transient Immunity
and Typical Waveforms.
11
PULSE
GENERATOR
OUTPUT V
MONITORING
NODE
E
Z
= 50 Ω
t = 5 ns
O
r
+5 V
D.U.T.
V
CC
R
L
V
E
I
= 13 mA
F
V
OUT
OUTPUT V
MONITORING
NODE
O
0.01 µF
BYPASS
C *
L
GND
* C INCLUDES PROBE AND
L
STRAY WIRING CAPACITANCE.
Figure 9. Enable Propagation Delay
vs. Temperature.
Figure 8. Test Circuit for t
and t
.
ELH
EHL
V
CC
+5.5 V
V
D.U.T.*
OC
+5.5 V
V
CC
(EACH INPUT)
0.01 µF
+
–
V
200 Ω
200 Ω
(EACH OUTPUT)
IN
5.3 V
(EACH OUTPUT)
GND
CONDITIONS: I = 20 mA
F
I
= 25 mA
O
T
= +125 °C
A
* ALL CHANNELS TESTED SIMULTANEOUSLY.
Figure 10. Operating Circuit for Burn-In and Steady State Life Tests.
MIL-PRF-38534 Class H,
Class K, and DSCC SMD
Test Program
Agilent’s Hi-Rel Optocouplers are
in compliance with MIL-PRF-
38534 Classes H and K. Class H
and Class K devices are also in
compliance with DSCC drawings
81028, 5962-90855 and 5962-
98001.
Testing consists of 100% screen-
ing and quality conformance
inspection to MIL-PRF-38534.
www.semiconductor.agilent.com
Data subject to change.
Copyright © 1999 Agilent Technologies
Obsoletes 5968-4743E
5968-9407E (10/00)
相关型号：
8102805PX
Logic IC Output Optocoupler, 2-Element, 2500V Isolation, 10MBps, HERMETIC SEALED, CERAMIC, DIP-8
AGILENT
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