HCPL-0302-560E [AGILENT]
IC Output Optocoupler;
| 型号： | HCPL-0302-560E |
| 厂家： | 
AGILENT TECHNOLOGIES, LTD. |
| 描述： | IC Output Optocoupler |
| 文件： | 总16页 (文件大小：130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Agilent HCPL-3020/HCPL-0302
0.4 Amp Output Current IGBT
Gate Drive Optocoupler
Data Sheet
Features
• 0.4 A maximum peak output
current
• 0.2 A minimum peak output
current
• High speed response: 0.7 µs
Functional Diagram
Description
maximum propagation delay over
temperature range
The HCPL-3020 and HCPL-
0302 consist of a GaAsP LED
optically coupled to an
integrated circuit with a power
output stage. These
optocouplers are ideally suited
for driving power IGBTs and
MOSFETs used in motor
control inverter applications.
The high operating voltage
range of the output stage
provides the drive voltages
required by gate-controlled
devices. The voltage and
N/C
ANODE
CATHODE
N/C
1
8
V
CC
• Ultra high CMR: minimum 10 kV/
µs at VCM = 1000 V
N/C
2
3
4
7
6
5
• Bootstrappable supply current:
maximum 3 mA
V
V
O
• Wide operating temperature
range: –40°C to 100°C
EE
• Wide VCC operating range: 10 V to
30 V over temperature range
SHIELD
• Available in DIP 8 and SO-8
packages
Truth Table
LED
• Safety approvals: UL approval,
3750 VRMS for 1 minute
current supplied by this
V
O
optocoupler makes it ideally
suited for directly driving
small or medium power
IGBTs. For IGBTs with higher
ratings, the HCPL-0314/3140
(0.6 A), HCPL-3150 (0.6 A) or
HCPL-3120 (2.5 A) gate drive
opto-couplers can be used.
• CSA approval
OFF
LOW
HIGH
• IEC/EN/DIN EN 60747-5-2
approval
ON
VIORM = 630 VPEAK (HCPL-3020),
VIORM = 566 VPEAK (HCPL-0302)
Note:
A 0.1 uF bypass capacitor must be
connected between pins VCC and
VEE.
Applications
• Isolated IGBT/power MOSFET
gate drive
• AC and brushless DC motor drives
• Industrial inverters
• Air conditioner
• Washing machine
• Induction heater for cooker
• Switching power supplies (SPS)
CAUTION: It is advised that normal static precautions be taken in handling and assembly of
this component to prevent damage and /or degradation which may be induced by ESD.
Ordering Information
Specify part number followed by option number (if desired).
Example:
HCPL-3020-XXXX
No option = Standard DIP package, 50 per tube
300 = Gull Wing Surface Mount Option, 50 per tube
500 = Tape and Reel Packaging Option
060 = IEC/EN/DIN EN 60747-5-2, V
XXXE = Lead Free Option
= 630 V
IORM
PEAK
HCPL-0302-XXXX
No option = Standard SO-8 package, 100 per tube
500 = Tape and Reel Packaging Option
060 = IEC/EN/DIN EN 60747-5-2, V
XXXE = Lead Free Option
= 566 V
IORM
PEAK
Package Outline Drawings
HCPL-3020 Standard DIP Package
7.62 0.25
(0.300 0.010)
9.65 0.25
(0.380 0.010)
8
1
7
6
5
6.35 0.25
(0.250 0.010)
TYPE NUMBER
OPTION CODE*
DATE CODE
A XXXXZ
YYWW
2
3
4
1.78 (0.070) MAX.
1.19 (0.047) MAX.
+ 0.076
- 0.051
0.254
5 TYP.
+ 0.003)
- 0.002)
(0.010
3.56 0.13
(0.140 0.005)
4.70 (0.185) MAX.
0.51 (0.020) MIN.
DIMENSIONS IN MILLIMETERS AND (INCHES).
2.92 (0.115) MIN.
* MARKING CODE LETTER FOR OPTION NUMBERS.
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
1.080 0.320
0.65 (0.025) MAX.
(0.043 0.013)
NOTE:
2.54 0.25
FLOATING LEAD PROTUSION IS 0.25 mm (10 mils) MAX.
(0.100 0.010)
2
HCPL-3020 Gull Wing Surface Mount Option 300
Land Pattern Recommendation
1.016 (0.040)
9.65 0.25
(0.380 0.010)
6
7
5
8
1
6.350 0.25
(0.250 0.010)
10.9 (0.430)
3
2
4
2.0 (0.080)
1.27 (0.050)
9.65 0.25
1.780
(0.380 0.010)
(0.070)
MAX.
1.19
(0.047)
MAX.
7.62 0.25
(0.300 0.010)
0.20 (0.008)
0.33 (0.013)
3.56 0.13
(0.140 0.005)
0.635 0.25
(0.025 0.010)
1.080 0.320
(0.043 0.013)
0.635 0.130
(0.025 0.005)
12 NOM.
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
NOTE: FLOATING LEAD PROTUSION IS 0.25 mm (10 mils) MAX.
Land Pattern Recommendation
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
HCPL-0302 Small Outline SO-8 Package
8
7
2
6
5
5.994 0.203
(0.236 0.008)
XXX
YWW
3.937 0.127
TYPE NUMBER
(LAST 3 DIGITS)
(0.155 0.005)
7.49 (0.295)
1.9 (0.075)
DATE CODE
1
3
4
PIN ONE
0.406 0.076
(0.016 0.003)
1.270
(0.050)
BSC
0.64 (0.025)
*
5.080 0.127
(0.200 0.005)
0.432
(0.017)
7
45 X
3.175 0.127
(0.125 0.005)
0 ~ 7
0.228 0.025
(0.009 0.001)
1.524
(0.060)
0.203 0.102
(0.008 0.004)
*
TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
5.207 0.254 (0.205 0.010)
0.305
(0.012)
MIN.
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.
NOTE: FLOATING LEAD PROTUSION IS 0.15 mm (6 mils) MAX.
3
Solder Reflow Temperature Profile
300
PREHEATING RATE 3˚C + 1˚C/–0.5˚C/SEC.
REFLOW HEATING RATE 2.5˚C 0.5˚C/SEC.
PEAK
TEMP.
245˚C
PEAK
TEMP.
240˚C
PEAK
TEMP.
230˚C
200
100
0
2.5˚C 0.5˚C/SEC.
SOLDERING
TIME
200˚C
30
160˚C
150˚C
140˚C
SEC.
30
SEC.
3˚C + 1˚C/–0.5˚C
PREHEATING TIME
150˚C, 90 + 30 SEC.
50 SEC.
TIGHT
TYPICAL
LOOSE
0
50
100
150
200
250
ROOM TEMPERATURE
TIME (SECONDS)
Recommended Solder Reflow Temperature Profile (Lead free)
TIME WITHIN 5 ˚C of ACTUAL
PEAK TEMPERATURE
t
p
20-40 SEC.
260 +0/-5 ˚C
T
p
217 ˚C
T
L
RAMP-UP
3 ˚C/SEC. MAX.
150 - 200 ˚C
RAMP-DOWN
6 ˚C/SEC. MAX.
T
smax
T
smin
t
s
t
L
60 to 150 SEC.
PREHEAT
60 to 180 SEC.
25
t 25 ˚C to PEAK
TIME (SECONDS)
NOTES:
THE TIME FROM 25 ˚C to PEAK TEMPERATURE = 8 MINUTES MAX.
= 200 ˚C, T = 150 ˚C
T
smax
smin
4
Regulatory Information
The HCPL-0302/3020 has been approved by the following organizations:
IEC/EN/DIN EN 60747-5-2
Approved under:
UL
Approval under UL 1577, component recognition
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01.
(Option 060 only)
program up to V
= 3750 V
. File E55361.
ISO
RMS
CSA
Approval under CSA Component Acceptance
Notice #5, File CA 88324.
IEC/EN/DIN EN 60747-5-2 Insulation Characteristics (HCPL-3020 and HCPL-0302 Option 060)
Description
Symbol
HCPL-3020 HCPL-0302 Unit
Installation Classification per DIN VDE 0110/1.89, Table 1
for Rated Mains Voltage - 150 V
for Rated Mains Voltage - 300 V
for Rated Mains Voltage - 600 V
I – IV
I – III
I – II
I – IV
I – III
rms
rms
rms
Climatic Classification
55/100/21 55/100/21
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b
2
2
V
V
630
566
V
V
IORM
PR
peak
peak
[1]
[1]
V
x 1.875 = V , 100% Production Test with t = 1 sec,
IORM
PR
m
Partial Discharge < 5 pC
1181
1050
Input to Output Test Voltage, Method a
V
x 1.5 = V , Type and Sample Test, t = 60 sec,
PR m
IORM
Partial Discharge < 5 pC
V
V
945
840
V
V
PR
peak
peak
Highest Allowable Overvoltage
(Transient Overvoltage t = 10 sec)
6000
4000
ini
IOTM
Safety-Limiting Values – Maximum Values Allowed in the Event of a
Failure.
Case Temperature
T
175
230
600
150
150
600
°C
mA
mW
S
[2]
Input Current
I
S, INPUT
[2]
Output Power
P
S, OUTPUT
9
9
Insulation Resistance at T , V = 500 V
R
>10
>10
Ω
S
IO
S
800
700
600
500
400
300
1. Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog,
under Product Safety Regulations section, (IEC/EN/DIN EN 60747-5-2), for a detailed
description of Method a and Method b partial discharge test profiles.
P
(mW)
S
I
(mA)
S
2. Refer to the following figure for dependence of P and I on ambient temperature.
S
S
200
100
0
0
25 50 75 100 125 150 175 200
– CASE TEMPERATURE – C
T
S
5
Insulation and Safety Related Specifications
Parameter
Symbol HCPL-3020 HCPL-0302 Units Conditions
Minimum External Air Gap
(Clearance)
L(101) 7.1
4.9
mm
mm
mm
Measured from input terminals to output
terminals, shortest distance through air.
Minimum External Tracking
(Creepage)
L(102) 7.4
4.8
Measured from input terminals to output
terminals, shortest distance path along body.
Minimum Internal Plastic Gap
(Internal Clearance)
0.08
0.08
Through insulation distance conductor to
conductor, usually the straight line distance
thickness between the emitter and detector.
Tracking Resistance
(Comparative Tracking
Index)
CTI
>175
IIIa
>175
IIIa
V
DIN IEC 112/VDE 0303 Part 1
Isolation Group
Material Group (DIN VDE 0110, 1/89, Table 1)
Absolute Maximum Ratings
Parameter
Symbol
Min.
–55
Max.
125
100
20
Units
°C
°C
mA
A
Note
Storage Temperature
Operating Temperature
Average Input Current
T
T
S
–40
A
I
I
1
F(AVG)
F(TRAN)
Peak Transient Input Current (<1 µs pulse width, 300 pps)
Reverse Input Voltage
1.0
5
V
R
V
“High” Peak Output Current
“Low” Peak Output Current
Supply Voltage
I
I
0.4
0.4
35
A
2
2
OH(PEAK)
OL(PEAK)
A
V
V
P
– V
–0.5
–0.5
V
CC
EE
Output Voltage
V
CC
V
O(PEAK)
Output Power Dissipation
Input Power Dissipation
250
45
mW
mW
3
4
O
I
P
Lead Solder Temperature
Solder Reflow Temperature Profile
260°C for 10 sec., 1.6 mm below seating plane
See Package Outline Drawings section
Recommended Operating Conditions
Parameter
Symbol
V - V
CC
Min.
10
Max.
30
Units
V
Note
Power Supply
EE
Input Current (ON)
Input Voltage (OFF)
Operating Temperature
I
7
12
mA
V
F(ON)
V
–3.0
–40
0.8
F(OFF)
T
100
°C
A
6
Electrical Specifications (DC)
Over recommended operating conditions unless otherwise specified.
Parameter
Symbol Min.
Typ.
Max. Units Test Conditions Fig.
Note
High Level Output Current
I
0.15
0.2
A
V = V – 4
5
OH
OL
O
CC
0.3
A
V = V – 10
2
2
O
CC
Low Level Output Current
I
0.15
0.2
A
V = V + 2.5
5
O
EE
0.3
A
V = V + 10
4
2
O
EE
High Level Output Voltage
Low Level Output Voltage
V
V
V
– 4
V
– 1.8
V
I = –100 mA
1
6, 7
OH
CC
CC
O
0.4
0.7
1.2
1
3
3
6
V
I = 100 mA
O
3
OL
High Level Supply Current
Low Level Supply Current
I
I
I
mA
mA
mA
V
I = 0 mA
O
5, 6
14
CCH
CCL
FLH
I = 0 mA
O
Threshold Input Current Low to High
Threshold Input Voltage High to Low
Input Forward Voltage
I = 0 mA,
7, 13
14
O
V > 5 V
O
V
V
0.8
1.2
FHL
F
1.5
1.8
V
I = 10 mA
F
Temperature Coefficient of Input
Forward Voltage
DV /DT
–1.6
mV/°C
F
A
Input Reverse Breakdown Voltage
Input Capacitance
BV
5
V
I = 10 µA
R
R
C
60
pF
f = 1 MHz,
IN
V = 0 V
F
Switching Specifications (AC)
Over recommended operating conditions unless otherwise specified.
Parameter
Symbol Min. Typ. Max. Units Test Conditions
Fig.
Note
Propagation Delay Time to High
Output Level
t
t
0.1
0.2 0.7
µs
R =75Ω, C = 1.5 nF,
8, 9
14
PLH
g
g
f = 10 kHz, Duty Cycle = 50%, 10, 11
I = 7 mA, V = 30 V
12, 15
F
CC
Propagation Delay Time to Low
Output Level
0.1
0.2 0.7
0.5
µs
µs
PHL
Propagation Delay Difference
PDD
–0.5
10
Between Any Two Parts or Channels
Rise Time
Fall Time
t
t
50
50
ns
ns
R
F
Output High Level Common Mode
Transient Immunity
|CM | 10
kV/µs T = 25°C, V = 1000 V
16
16
11
12
H
A
CM
Output Low Level Common Mode
Transient Immunity
|CM | 10
kV/µs
L
7
Package Characteristics
Parameter
Symbol
Min.
Typ. Max. Units
Test Conditions
T = 25°C, RH < 50%
Fig. Note
Input-Output Momentary
Withstand Voltage
V
ISO
3750
V
rms
8, 9
A
12
Input-Output Resistance
Input-Output Capacitance
R
C
10
Ω
V
= 500 V
I-O
9
I-O
I-O
0.6
pF
Freq = 1 MHz
Notes:
1. Derate linearly above 70°C free air temperature at a rate of 0.3 mA/°C.
2. Maximum pulse width = 10 µs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with I peak
O
minimum = 0.2 A. See Application section for additional details on limiting I peak.
OL
3. Derate linearly above 85°C, free air temperature at the rate of 4.0 mW/°C.
4. Input power dissipation does not require derating.
5. Maximum pulse width = 50 µs, maximum duty cycle = 0.5%.
6. In this test, V is measured with a DC load current. When driving capacitive load V will approach V as I approaches zero amps.
OH
OH
CC
OH
7. Maximum pulse width = 1 µs, maximum duty cycle = 20%.
8. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage >4500 V for 1 second (leakage detection
rms
current limit I < 5 µA). This test is performed before 100% production test for partial discharge (method B) shown in the IEC/EN/DIN EN 60747-5-2
I-O
Insulation Characteristics Table, if applicable.
9. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together.
10. PDD is the difference between t
and t
between any two parts or channels under the same test conditions.
PLH
PHL
11. Common mode transient immunity in the high state is the maximum tolerable |dV /dt| of the common mode pulse V to assure that the output
CM
CM
will remain in the high state (i.e. V > 6.0 V).
O
12. Common mode transient immunity in a low state is the maximum tolerable |dV /dt| of the common mode pulse, V , to assure that the output will
CM
CM
remain in a low state (i.e. V < 1.0 V).
O
13. This load condition approximates the gate load of a 1200 V/20 A IGBT.
14. The power supply current increases when operating frequency and C of the driven IGBT increases.
g
0
0
0.44
-0.5
0.43
0.42
0.41
0.40
0.39
-1
-1.0
-2
-1.5
-2.0
-3
-2.5
-50 -25
0
25
50
75 100 125
-4
T
– TEMPERATURE – C
0
0.2
0.4
-50 -25
0
25
50
75 100 125
A
I
– OUTPUT HIGH CURRENT – A
T
– TEMPERATURE – C
OH
A
Figure 3. V vs. temperature.
Figure 1. V vs. temperature.
Figure 2. V vs. I
.
OH
OH
OH
OL
8
5
1.4
1.2
1.0
0.8
0.6
0.4
1.2
1.0
4
3
2
1
0
0.8
0.6
0.4
0.2
0
I
I
L
CC
I
I
L
CC
0.2
0
H
CC
H
CC
0
0.1
0.2
0.3
0.4
-50 -25
0
25
– TEMPERATURE – C
A
50
75 100 125
10
15
CC
20
25
30
I
– OUTPUT LOW CURRENT – A
T
V
– SUPPLY VOLTAGE – V
OL
Figure 4. V vs. I
.
Figure 5. I vs. temperature.
Figure 6. I vs. V .
CC
OL
OL
CC
CC
3.5
3.0
2.5
2.0
400
300
200
400
300
200
100
0
100
0
T
T
PLH
PHL
1.5
-50 -25
0
25
50
75 100 125
10
15
CC
20
25
30
6
9
12
I – FORWARD LED CURRENT – mA
F
15
18
T
– TEMPERATURE – C
V
– SUPPLY VOLTAGE – V
A
Figure 7. I vs. temperature.
Figure 8. Propagation delay vs. V
.
Figure 9. Propagation delay vs. I .
FLH
CC
F
500
400
350
300
400
300
200
400
300
200
100
0
T
T
PLH
PHL
250
200
100
0
T
T
PLH
PHL
T
T
PLH
PHL
-50 -25
0
25
50
75 100 125
0
50
100
150
200
0
20
40
60
80
100
T
– TEMPERATURE – C
Rg – SERIES LOAD RESISTANCE – Ω
Cg – LOAD CAPACITANCE – nF
A
Figure 10. Propagation delay vs. temperature.
Figure 11. Propagation delay vs. R .
Figure 12. Propagation delay vs. C
g.
g
9
35
30
25
20
15
10
25
20
15
10
5
5
0
-5
0
1.2
0
1
2
3
4
5
6
1.4
1.6
1.8
I
– FORWARD LED CURRENT – mA
F
V – FORWARD VOLTAGE – V
F
Figure 13. Transfer characteristics.
Figure 14. Input current vs. forward voltage.
1
8
I
0.1 µF
F
I
= 7 to 16 mA
F
V
= 15
CC
+
to 30 V
2
3
4
7
6
5
–
t
t
f
r
500 Ω
+
V
O
–
90%
10 KHz
50% DUTY
CYCLE
75 Ω
1.5 nF
50%
10%
V
OUT
t
t
PHL
PLH
Figure 15. Propagation delay test circuits and waveforms.
V
CM
δV
V
CM
1
2
3
4
8
7
6
5
=
δt
∆t
I
F
0.1 µF
A
B
0 V
∆t
+
+
–
V
O
5 V
–
V
= 30 V
CC
V
V
OH
OL
V
O
SWITCH AT A: I = 10 mA
F
V
O
SWITCH AT B: I = 0 mA
F
+
V
= 1000 V
CM
Figure 16. CMR test circuits and waveforms.
10
Applications Information Eliminating
Negative IGBT Gate Drive
a small PC board directly
above the IGBT) can eliminate
the need for negative IGBT
gate drive in many
applications as shown in
Figure 17. Care should be
taken with such a PC board
design to avoid routing the
IGBT collector or emitter
traces close to the HCPL-3020
or HCPL-0302 input as this
can result in unwanted
coupling of transient signals
into the input of HCPL-3020
or HCPL-0302 and degrade
performance. (If the IGBT
drain must be routed near the
HCPL-3020 or HCPL-0302
input, then the LED should be
reverse biased when in the off
state, to prevent the transient
signals coupled from the IGBT
drain from turning on the
HCPL-3020 or HCPL-0302.
To keep the IGBT firmly off,
the HCPL-3020 and HCPL-
0302 have a very low
maximum V specification of
OL
1.0 V. Minimizing R and the
g
lead inductance from the
HCPL-3020 or HCPL-0302 to
the IGBT gate and emitter
(possibly by mounting the
HCPL-3020 or HCPL-0302 on
HCPL-3020/0302
8
+5 V
1
V
= 15 V
CC
+ HVDC
270 Ω
0.1 µF
7
+
–
2
Rg
Q1
Q2
3-PHASE
AC
CONTROL
3
6
5
INPUT
74XXX
OPEN
4
COLLECTOR
- HVDC
Figure 17. Recommended LED drive and application circuit for HCPL-3020 and HCPL-0302.
11
Selecting the Gate Resistor (Rg) for HCPL-3020
Step 1: Calculate R minimum from the I peak specification. The IGBT and R in Figure 17 can
g
OL
g
be analyzed as a simple RC circuit with a voltage supplied by the HCPL-3020.
R
≤
=
=
V
– V
CC OL
g
I
OLPEAK
24 - 1
0.4
57.5 Ω
The V value of 1 V in the previous equation is the V at the peak current of 0.4 A. (See Figure
OL
OL
4).
Step 2: Check the HCPL-3020 power dissipation and increase R if necessary. The HCPL-3020 total
g
power dissipation (P ) is equal to the sum of the emitter power (P ) and the output power (P ).
T
E
O
P = P + P
T
E
O
E
O
P
P
= I • V • Duty Cycle
F F
= P
+ P
= I • V + E
(R ;Q ) • f
SW g g
O(BIAS)
O(SWITCHING)
CC
CC
= (I
+ K
• Q • f) • V + E
(R ;Q ) • f
SW g g
CCBIAS
ICC
g
CC
where
• Q • f is the increase in I due to switching and K is a constant of 0.001 mA/(nC*kHz).
ICC
K
ICC
g
CC
For the circuit in Figure 17 with I (worst case) = 10 mA, R = 57.5 Ω, Max Duty Cycle = 80%,
F
g
Q = 100 nC, f = 20 kHz and T
g
= 85°C:
AMAX
P = 10 mA • 1.8 V • 0.8 = 14 mW
E
P = [(3 mA + (0.001 mA/nC • kHz) • 20 kHz • 100 nC)] • 24 V + 0.31 • 20 kHz
O
= 126 mW < 250 mW (P
) @ 85°C
O(MAX)
The value of 3 mA for I in the previous equation is the max. I over entire operating
CC
CC
temperature range.
Since P for this case is less than P
, R = 57.5 Ω is alright for the power dissipation.
O
O(MAX)
g
4.0
Qg = 50 nC
3.5
Qg = 100 nC
Qg = 200 nC
Qg = 400 nC
3.0
2.5
2.0
1.5
1.0
0.5
0
0
20
40
60
80
100
Rg – GATE RESISTANCE – Ω
Figure 18. Energy dissipated in the HCPL-3020 and
HCPL-0302 and for each IGBT switching cycle.
12
LED Drive Circuit Considerations for
Ultra High CMR Performance
C
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
LEDO1
Without a detector shield, the
dominant cause of optocoupler
CMR failure is capacitive
coupling from the input side
of the optocoupler, through
the package, to the detector IC
as shown in Figure 19. The
HCPL-3020 and HCPL-0302
improve CMR performance by
using a detector IC with an
optically transparent Faraday
shield, which diverts the
C
C
C
C
LEDP
LEDP
C
LEDO2
LEDN
LEDN
SHIELD
Figure 19. Optocoupler input to output
capacitance model for unshielded
optocouplers.
Figure 20. Optocoupler Input to output
capacitance model for shielded optocouplers.
capacitively coupled current
away from the sensitive IC
circuitry. However, this shield
does not eliminate the
+5 V
1
8
capacitive coupling between
the LED and optocoupler pins
5-8 as shown in Figure 20.
This capacitive coupling causes
perturbations in the LED
current during common mode
transients and becomes the
major source of CMR failures
for a shielded optocoupler.
The main design objective of a
high CMR LED drive circuit
becomes keeping the LED in
the proper state (on or off)
during common mode
0.1
µF
+
–
C
LEDP
V
= 18 V
CC
2
7
6
5
+
I
LEDP
V
SAT
–
3
4
• • •
• • •
C
LEDN
Rg
SHIELD
* THE ARROWS INDICATE THE DIRECTION
OF CURRENT FLOW DURING –dV /dt.
CM
+
V
–
CM
transients. For example, the
recommended application
circuit (Figure 17), can
Figure 21. Equivalent circuit for figure 15 during common mode transient.
achieve 10 kV/µs CMR while
minimizing component
complexity.
Techniques to keep the LED in
the proper state are discussed
in the next two sections.
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
+5 V
+5 V
C
C
C
C
LEDP
LEDP
LEDN
LEDN
Q1
LEDN
I
SHIELD
SHIELD
Figure 22. Not recommended open collector
drive circuit.
Figure 23. Recommended LED drive circuit for
ultra-high CMR IPM dead time and propagation
delayspecifications.
13
CMR with the LED On (CMRH)
Dead Time and Propagation Delay
Specifications
Note that the propagation delays
used to calculate PDD and dead time
are taken at equal temperatures and
test conditions since the optocouplers
under consideration are typically
mounted in close proximity to each
other and are switching identical
IGBTs.
A high CMR LED drive circuit
must keep the LED on during
common mode transients. This
is achieved by overdriving the
LED current beyond the input
threshold so that it is not
pulled below the threshold
during a transient. A minimum
LED current of 7 mA provides
adequate margin over the
The HCPL-3020 and HCPL-
0302 include a Propagation
Delay Difference (PDD)
specification intended to help
designers minimize “dead
time” in their power inverter
designs. Dead time is the time
high and low side power
transistors are off. Any
maximum I
of 6 mA to
overlap in Ql and Q2
FLH
achieve 10 kV/µs CMR.
conduction will result in large
currents flowing through the
power devices from the high
voltage to the low-voltage
motor rails. To minimize dead
time in a given design, the
turn on of LED2 should be
delayed (relative to the turn
off of LED1) so that under
worst-case conditions,
CMR with the LED Off (CMRL)
A high CMR LED drive circuit
must keep the LED off (V
-
F
V
) during common mode
F(OFF)
transients. For example,
during a -dV /dt transient in
CM
Figure 21, the current flowing
through C
also flows
LEDP
transistor Q1 has just turned
off when transistor Q2 turns
on, as shown in Figure 24.
The amount of delay necessary
to achieve this condition is
equal to the maximum value
of the propagation delay
difference specification, PDD
max, which is specified to be
500 ns over the operating
temperature range of –40° to
100°C.
through the R
and V
of
SAT
SAT
the logic gate. As long as the
low state voltage developed
across the logic gate is less
than V
the LED will
F(OFF)
remain off and no common
mode failure will occur.
The open collector drive
circuit, shown in Figure 22,
cannot keep the LED off
during a +dV /dt transient,
CM
since all the current flowing
Delaying the LED signal by the
maximum propagation delay
difference ensures that the
minimum dead time is zero,
but it does not tell a designer
what the maximum dead time
will be. The maximum dead
time is equivalent to the
difference between the
through C
must be
LEDN
supplied by the LED, and it is
not recommended for
applications requiring ultra
high CMR performance. The
1
alternative drive circuit, which
likes the recommended
application circuit (Figure 17),
does achieve ultra high CMR
performance by shunting the
LED in the off state.
maximum and minimum
propagation delay difference
specification as shown in
Figure 25. The maximum dead
time for the HCPL-3020 and
HCPL-0302 is 1 ms (= 0.5 µs
– (–0.5 µs)) over the operating
temperature range of –40°C to
100°C.
14
I
LED1
V
OUT1
Q1 ON
Q1 OFF
Q2 ON
Q2 OFF
V
OUT2
I
LED2
t
PHL MAX
t
PLH MIN
PDD* MAX = (t - t
)
= t
- t
PHL PLH MAX PHL MAX PLH MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
Figure 24. Minimum LED skew for zero dead time.
I
LED1
V
OUT1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
V
OUT2
I
LED2
t
PHL MIN
t
PHL MAX
t
PLH
MIN
t
PLH MAX
(t
t
)
PHL- PLH MAX
PDD* MAX
MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLER)
= (t
- t
) + (t
) – (t
- t )
PLH MAX PLH MIN
PHL MAX PHL MIN
= (t
- t
PHL MAX PLH MIN
- t )
PHL MIN PLH MAX
= PDD* MAX – PDD* MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION
DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
Figure 25. Waveforms for dead time.
15
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Data subject to change.
Copyright © 2005 Agilent Technologies, Inc.
obsolete5989-2160EN
July 13, 2005
5989-2947EN
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