HCPL-0611 [AGILENT]
Small Outline, 5 Lead, High CMR, High Speed, Logic Gate Optocouplers; 小外形， 5铅，高CMR ，高速逻辑门光电耦合器
| 型号： | HCPL-0611 |
| 厂家： | 
AGILENT TECHNOLOGIES, LTD. |
| 描述： | Small Outline, 5 Lead, High CMR, High Speed, Logic Gate Optocouplers |
| 文件： | 总10页 (文件大小：264K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Small Outline, 5 Lead, High
CMR, High Speed, Logic Gate
Optocouplers
Technical Data
HCPL-M600
HCPL-M601
HCPL-M611
Description
Features
ThesesmalloutlinehighCMR,
high speed, logic gate optocoup-
lersaresinglechanneldevicesin
afiveleadminiaturefootprint.
Theyareelectricallyequivalentto
thefollowingAgilent
•SurfaceMountable
•VerySmall,LowProfile
JEDECRegisteredPackage
Outline
•CompatiblewithInfrared
VaporPhaseReflowand
WaveSolderingProcesses
•InternalShieldforHigh
CommonModeRejection
(CMR)
HCPL-M601:10,000V/µsat
VCM = 50 V
optocouplers (except there is no
outputenablefeature):
SO-5 Package
HCPL-M600
HCPL-M601
HCPL-M611
Standard DIP
SO-8 Package
6N137
HCPL-0600
HCPL-0601
HCPL-0611
HCPL-2601
HCPL-2611
HCPL-M611:15,000V/µsat
VCM = 1000 V
•HighSpeed:10Mbd
•LSTTL/TTLCompatible
•LowInputCurrent
Capability:5mA
•Guaranteedacanddc
Performanceover
TheSO-5JEDECregistered(MO-
155) package outline does not
require“throughholes”inaPCB.
Thispackageoccupies
approximatelyonefourththe
footprintareaofthestandard
dual-in-linepackage.Thelead
profile is designed to be com-
patiblewithstandardsurface
mountprocesses.
Schottky-clampedtransistor.The
internalshieldprovidesa
guaranteedcommonmode
transientimmunityspecificationof
5,000V/µsfortheHCPL-M601,
and10,000V/µsfortheHCPL-
M611.
Temperature:-40°Cto85°C
•Recognizedunderthe
ComponentProgramofU.L.
(File No. E55361) for
DielectricWithstandProof
Test Voltageof2500 Vac, 1
Minute
Thisuniquedesignprovides
maximumacanddccircuit
isolationwhileachievingTTL
compatibility.Theoptocouplerac
anddcoperationalparametersare
guaranteedfrom-40°Cto85°C
allowingtroublefreesystem
performance.
TheHCPL-M600/01/11optically
coupledgatescombineaGaAsP
lightemittingdiodeandan
integratedhighgainphoton
detector.Theoutputofthe
detectorI.C.isanOpen-collector
CAUTION: The small device geometries inherent to the design of this bipolar component increase the component's
susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken
in handling and assembly of this component to prevent damage and/or degradation which may be induced by
ESD.
2
TheHCPL-M600/01/11are
suitableforhighspeedlogic
interfacing,input/output
buffering,aslinereceiversin
environmentsthatconventional
linereceiverscannottolerate,and
arerecommendedforusein
extremelyhighgroundorinduced
noiseenvironments.
Applications
•IsolatedLineReceiver
•Simplex/MultiplexData
Transmission
•Computer-Peripheral
Interface
•MicroprocessorSystem
Interface
OutlineDrawing(JEDECMO-155)
•DigitalIsolationforA/D,D/A
Conversion
•SwitchingPowerSupply
•InstrumentInput/Output
Isolation
•GroundLoopElimination
ANODE
1
3
6
5
V
V
CC
MXXX
XXX
7.0 ± 0.2
(0.276 ± 0.008)
4.4 ± 0.1
(0.173 ± 0.004)
OUT
CATHODE
4
GND
•PulseTransformer
Replacement
0.4 ± 0.05
(0.016 ± 0.002)
3.6 ± 0.1*
(0.142 ± 0.004)
0.102 ± 0.102
(0.004 ± 0.004)
0.15 ± 0.025
(0.006 ± 0.001)
2.5 ± 0.1
(0.098 ± 0.004)
7° MAX.
1.27
(0.050)
0.71
BSG
MIN.
(0.028)
MAX. LEAD COPLANARITY
= 0.102 (0.004)
DIMENSIONS IN MILLIMETERS (INCHES)
"Agilent" IS MARKED ON THE
UNDERSIDE OF THE PACKAGE
* MAXIMUM MOLD FLASH ON EACH SIDE IS 0.15 mm (0.006)
PinLocation(forreferenceonly)
Schematic
0.3
(0.01)
I
+
1
I
CC
F
4.4
(0.17)
V
V
CC
O
6
5
I
O
1.3
(0.05)
2.5
(0.10)
–
3
GND
4
HCPL-M601/11 SHIELD
0.9
(0.04)
TRUTH TABLE
(POSITIVE LOGIC)
0.5
(0.02)
USE OF A 0.1 µF BYPASS CAPACITOR
MUST BE CONNECTED BETWEEN PINS
6 AND 4 (SEE NOTE 1).
7.2
(0.28)
LED
ON
OUTPUT
L
OFF
H
3
RecommendedOperatingConditions
Parameter
Symbol
IFL*
Min.
0
Max.
250
15
Units
µA
InputCurrent,LowLevel
InputCurrent,HighLevel
SupplyVoltage,Output
Fan Out (RL = 1 kΩ)
IFH
5
mA
V
V
CC
4.5
5.5
5
N
TTL
Loads
OutputPull-UpResistor
OperatingTemperature
RL
330
-40
4,000
85
Ω
T
A
°C
* The off condition can also be guaranteed by ensuring that VF(off) ≤0.8 volts.
AbsoluteMaximumRatings
(NoDeratingRequiredupto85°C)
StorageTemperature .................................................... -55°C to +125°C
OperatingTemperature .................................................. -40°C to +85°C
ForwardInputCurrent-IF (seeNote2) ....................................... 20mA
ReverseInputVoltage-VR ................................................................. 5 V
SupplyVoltage-VCC (1MinuteMaximum) ........................................ 7 V
OutputCollectorCurrent-IO........................................................ 50mA
OutputCollectorPowerDissipation ............................................ 85 mW
OutputCollectorVoltage-VO ............................................................ 7 V
(Selectionforhigheroutputvoltagesupto20Visavailable)
InfraredandVaporPhaseReflowTemperature ....................... see below
260
240
∆T = 145°C, 1°C/SEC
220
∆T = 115°C, 0.3°C/SEC
200
180
160
140
120
100
80
∆T = 100°C, 1.5°C/SEC
60
40
20
0
0
1
2
3
4
5
6
7
8
9
10
11
12
TIME – MINUTES
Maximum Solder Reflow Thermal Profile.
(Note: Use of Non-Chlorine Activated Fluxes is Recommended.)
4
Insulation Related Specifications
Parameter
Symbol Value Units
Conditions
Min. External Air Gap
(Clearance)
L(IO1)
≥5
mm
mm
mm
V
Measured from input terminals
to output terminals
Min. External Tracking Path
(Creepage)
L(IO2)
≥5
Measured from input terminals
to output terminals
Min. Internal Plastic Gap
(Clearance)
0.08
Through insulation distance
conductor to conductor
Tracking Resistance
CTI
175
IIIa
DIN IEC 112/VDE 0303 Part 1
Material Group DIN VDE 0109
Isolation Group (per DIN VDE 0109)
Electrical Specifications
Over recommended temperature (T = -40°C to 85°C) unless otherwise specified. (See note 1.)
A
Parameter
Symbol Min. Typ.* Max. Units
Test Conditions
Fig. Note
Input Threshold
Current
ITH
IOH
VOL
ICCH
ICCL
VF
2
5.5
0.4
4
5
mA
µA
V
VCC = 5.5 V, IO ≥13 mA,
VO = 0.6 V
13
High Level Output
Current
100
0.6
VCC = 5.5 V, VO = 5.5 V
IF = 250 µA
1
Low Level Output
Voltage
VCC = 5.5 V, IF = 5 mA,
IOL (Sinking) = 13 mA
2, 4,
5, 13
High Level Supply
Current
7.5
mA
VCC = 5.5 V, IF = 0 mA,
Low Level Supply
Current
6
10.5
VCC = 5.5 V, IF = 10 mA,
Input Forward
Voltage
1.4
1.75
1.85
V
T = 25°C
A
3
1.5
1.3
5
IF = 10 mA
Input Reverse
BVR
IR = 10 µA
Breakdown Voltage
Input Capacitance
CIN
60
pF
VF = 0V, f = 1 MHz
Input Diode
Temperature
Coefficient
∆VF/∆TA
-1.6
mV/°C IF = 10 mA
12
Input-Output
Insulation
V
2500
VRMS
Ω
RH ≤ 50%, t = 1 min.
3, 4
3
ISO
Resistance
(Input-Output)
RI-O
CI-O
1012
0.6
VI-O = 500 V
f = 1 MHz
Capacitance
pF
3
(Input-Output)
*All typicals at T = 25°C, VCC = 5 V.
A
5
Switching Specifications
Over recommended temperature (TA = -40°C to 85°C), VCC = 5 V, IF = 7.5 mA unless otherwise specified.
Device
Parameter Symbol HCPL- Min. Typ.* Max. Unit
Test Conditions
Fig. Note
Propagation
Delay Time
to High
tPLH
tPHL
tPSK
20
25
48
50
75
ns TA = 25°C
6, 7
5
6
100
8
Output Level
Propagation
Delay Time
to Low
75
TA = 25°C
6, 7
8
100
RL = 350 Ω
Output Level
Propagation
Delay Skew
40
35
10,
11
Pulse Width |tPHL - tPLH
Distortion
|
3.5
24
CL = 15 pF
9
10
Output Rise
Time
(10%-90%)
trise
10
10
Output Fall
Time
tfall
10
(10%-90%)
Common
Mode
Transient
Immunity at
High Output
Level
|CMH|
M600
10,000
V/µs VCM = 10 V VO(min) = 2 V
11 7, 9
RL = 350 Ω
IF = 0 mA
M601 5,000 10,000
M611 10,000 15,000
VCM = 50 V
VCM =1000V TA = 25°C
Common
Mode
Transient
Immunity at
Low Output
Level
|CMH|
M600
10,000
VCM = 10 V VO(max) = 0.8 V 11 8, 9
RL = 350 Ω
IF = 7.5 mA
M601 5,000 10,000
M611 10,000 15,000
VCM = 50 V
VCM = 1000V
TA = 25°C
*All typicals at TA = 25°C, VCC = 5 V.
Notes:
1. Bypassing of the power supply line is required with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler. The total lead
length between both ends of the capacitor and the isolator pins should not exceed 10 mm.
2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current
does not exceed 20 mA.
3. Device considered a two terminal device: pins 1 and 3 shorted together, and pins 4, 5 and 6 shorted together.
4. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 3000 VRMS for 1 second
(Leakage detection current limit, II-O ≤ 5 µA).
5. The tPLH propagation delay is measured from 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the
rising edge of the output pulse.
6. The tPHL propagation delay is measured from 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the
falling edge of the output pulse.
7. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic
state (i.e., VOUT > 2.0 V).
8. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic
state (i.e., VOUT > 0.8 V).
9. For sinusoidal voltages, (|dVCM|/dt)max = πfCMVCM(p-p)
.
10. See application section; “Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew” for more information.
11. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within
the worst case operating condition range.
6
15
10
0.5
0.4
100
V
= 5.5 V
= 5.0 mA
T = 25°C
A
CC
V
V
I
= 5.5 V
CC
= 5.5 V
I
F
O
10
= 250 µA
I
F
F
+
V
–
I
= 12.8 mA
O
1.0
F
I
= 16 mA
= 6.4 mA
O
0.3
0.2
0.1
0.1
5
0
I
O
0.01
I
= 9.6 mA
O
0.001
-60 -40 -20
0
20 40 60 80 100
1.10 1.20
1.30 1.40
1.50
1.60
-60 -40 -20
0
20 40 60 80 100
T
– TEMPERATURE – °C
A
T
– TEMPERATURE – °C
V
– FORWARD VOLTAGE – VOLTS
A
F
Figure 1. High Level Output
Current vs. Temperature.
Figure 2. Low Level Output Voltage
vs. Temperature.
Figure 3. Input Diode Forward
Characteristic.
6
V
= 5 V
CC
= 25 °C
T
A
5
4
3
2
R
= 350 Ω
L
PULSE GEN.
R
= 1 KΩ
L
Z = 50 Ω
O
+5 V
t = t = 5 ns
f
r
R
= 4 KΩ
L
I
F
V
1
3
6
5
4
CC
1
0
R
L
0.1µF
BYPASS
OUTPUT V
O
MONITORING
NODE
0
1
2
3
4
6
5
*C
L
INPUT
MONITORING
NODE
I
– FORWARD INPUT CURRENT – mA
F
GND
R
M
Figure 4. Output Voltage vs.
Forward Input current.
*C IS APPROXIMATELY 15 pF WHICH INCLUDES
L
PROBE AND STRAY WIRING CAPACITANCE.
80
V
V
= 5.0 V
= 0.6 V
CC
OL
I
I
= 7.5 mA
F
F
INPUT
= 3.75 mA
I
60
40
F
I
I
= 10 mA, 15 mA
= 5.0 mA
F
F
t
t
PLH
PHL
OUTPUT
V
O
1.5 V
20
0
Figure 6. Test Circuit for tPHL and tPLH
.
-60 -40 -20
0
20 40 60 80 100
T
– TEMPERATURE – °C
A
Figure 5. Low Level Output Current
vs. Temperature.
7
100
80
105
90
40
30
20
10
V
I
= 5.0 V
V
T
= 5.0 V
CC
= 7.5 mA
CC
= 25°C
R
= 4 kΩ
L
F
A
t
, R = 4 KΩ
L
t
, R = 4 KΩ
L
PLH
PLH
V
= 5.0 V
CC
= 7.5 mA
t
, R = 350 Ω
L
PHL
I
F
1 KΩ
4 KΩ
60
40
75
60
t
PLH
, R = 350 Ω
L
R
= 350 kΩ
L
t
, R = 1 KΩ
L
PLH
t
, R = 1 KΩ
L
PLH
t
, R = 350 Ω
L
PLH
45
30
0
20
0
t
, R = 350 Ω
PHL
L
R
= 1 kΩ
L
1 KΩ
4 KΩ
-10
-60 -40 -20
0
20 40
80 100
5
7
9
11
13
15
-60 -40 -20
0
20 40
80 100
60
60
I
– PULSE INPUT CURRENT – mA
T
– TEMPERATURE – °C
T
– TEMPERATURE – °C
F
A
A
Figure 7. Propagation Delay vs.
Temperature.
Figure 8. Propagation Delay vs.
Pulse Input Current.
Figure 9. Pulse Width Distortion vs.
Temperature.
V
= 5.0 V
t
t
CC
= 7.5 mA
RISE
FALL
I
F
I
F
+5 V
B
A
R
= 4 kΩ
= 1 kΩ
V
300
290
60
L
1
3
CC
6
350 Ω
OUTPUT V
0.1 µF
BYPASS
O
5
4
MONITORING
NODE
V
R
FF
L
40
GND
R
R
= 350 Ω
L
20
0
= 350 Ω, 1 kΩ, 4 kΩ
L
0
_
+
-60 -40 -20
20 40 60 80 100
PULSE
GENERATOR
= 50 Ω
T
– TEMPERATURE – °C
A
Z
O
Figure 10. Rise and Fall Time vs.
Temperature.
V
(PEAK)
CM
V
CM
0 V
5 V
SWITCH AT A: I = 0 mA
F
CM
H
V
V
O
V
(MIN.)
O
SWITCH AT B: I = 7.5 mA
F
-2.4
-2.2
V
(MAX.)
O
O
CM
0.5 V
L
-2.0
-1.8
-1.6
Figure 11. Test Circuit for Common
Mode Transient Immunity and
Typical Waveforms.
-1.4
-1.2
0.1
1
10
100
I
– PULSE INPUT CURRENT – mA
F
Figure 12. Temperature Coefficient
for Forward Voltage vs. Input
Current.
8
PropagationDelay,Pulse- beingsentthroughagroupof
only one edge were used, the
clock signal would need to be
twiceasfast.
WidthDistortionand
optocouplers,differencesin
propagationdelayswillcausethe
datatoarriveattheoutputsofthe
optocouplersatdifferenttimes.If
thisdifferenceinpropagation
delaysislargeenough,itwill
determinethemaximumrateat
whichparalleldatacanbesent
throughtheoptocouplers.
PropagationDelaySkew
Propagationdelayisafigureof
meritwhichdescribeshow
quicklyalogicsignalpropagates
throughasystem.Thepropaga-
Propagationdelayskew
representstheuncertaintyof
whereanedgemightbeafter
beingsentthroughan
tiondelayfromlowtohigh(tPLH
istheamountoftimerequiredfor
aninputsignaltopropagateto
theoutput,causingtheoutputto
change from low to high.
)
optocoupler. Figure16shows
thattherewillbeuncertaintyin
boththedataandtheclocklines.
Itisimportantthatthesetwo
areasofuncertaintynotoverlap,
otherwisetheclocksignalmight
arrivebeforeallofthedata
outputshavesettled,orsomeof
thedataoutputsmaystartto
changebeforetheclocksignal
hasarrived.Fromthese
considerations,theabsolute
minimumpulsewidththatcanbe
sentthroughoptocouplersina
parallelapplicationistwicetPSK.A
cautiousdesignshouldusea
slightlylongerpulsewidthto
ensurethatanyadditional
Propagationdelayskewisdefined
asthedifferencebetweenthe
minimumandmaximum
propagationdelays,eithertPLH or
tPHL, for any given group of
optocouplerswhichareoperating
underthesameconditions(i.e.,
thesamedrivecurrent,supply
voltage,outputload,and
Similarly,thepropagationdelay
from high to low (tPHL) is the
amountoftimerequiredforthe
inputsignaltopropagatetothe
output,causingtheoutputto
change from high to low (see
Figure7).
operatingtemperature).As
Pulse-widthdistortion(PWD)
resultswhentPLHandtPHLdifferin
value.PWDisdefinedasthe
differencebetweentPLH andtPHL
andoftendeterminesthemaxi-
mumdataratecapabilityofa
transmissionsystem.PWD can
be expressed in percent by
dividingthePWD(inns)bythe
minimumpulsewidth(inns)
beingtransmitted.Typically,PWD
on the order of 20-30% of the
minimumpulsewidthistolerable;
theexactfiguredependsonthe
particularapplication(RS232,
RS422, T-1, etc.).
illustratedinFigure15,ifthe
inputs of a group of optocouplers
areswitchedeitherONorOFFat
thesametime,tPSK isthe
differencebetweentheshortest
propagationdelay,eithertPLHor
tPHL,andthelongestpropagation
uncertaintyintherestofthe
circuit does not cause aproblem.
delay,eithertPLH ortPHL
.
ThetPSK specifiedoptocouplers
offertheadvantagesof
Asmentionedearlier,tPSK can
determinethemaximumparallel
datatransmissionrate.Figure11
isthetimingdiagramofatypical
paralleldataapplicationwithboth
theclockandthedatalinesbeing
sentthroughoptocouplers.The
figureshowsdataandclock
signalsattheinputsandoutputs
of the optocouplers. To obtain the
maximumdatatransmissionrate,
both edges of the clock signal are
being used to clock the data; if
guaranteedspecificationsfor
propagationdelays,pulse-width
distortionandpropagationdelay
skewovertherecommended
temperature,andinputcurrent,
andpowersupplyranges.
Propagationdelayskew,tPSK,is
animportantparameterto
considerinparalleldataappli-
cationswheresynchronizationof
signalsonparalleldatalinesisa
concern.Iftheparalleldatais
9
6
5
4
3
2
V
V
= 5.0 V
CC
= 0.6 V
5 V
6
5
5 V
V
1
V
2
CC
CC
O
390 Ω
470
*D1
I
F
1
3
R
= 350 Ω
L
R
R
= 1 kΩ
V
0.1 µF
BYPASS
L
F
4
GND 1
GND 2
SHIELD
1
0
1
2
= 4 kΩ
L
* DIODE D1 (1N916 OR EQUIVALENT) IS NOT REQUIRED
FOR UNITS WITH OPEN COLLECTOR OUTPUT.
-60 -40 -20
0
20 40 60 80 100
T
– TEMPERATURE – °C
A
Figure 13. Input Threshold Current
vs. Temperature.
Figure 14. Recommended TTL/LSTTL to TTL/LSTTL Interface Circuit.
DATA
INPUTS
I
F
50%
50%
CLOCK
1.5 V
V
O
DATA
I
F
OUTPUTS
t
PSK
V
1.5 V
O
CLOCK
t
PSK
t
PSK
Figure 15. Illustration of
Propagation Delay Skew – tPSK
Figure16.ParallelDataTransmissionExample.
.
www.semiconductor.agilent.com
Data subject to change.
Copyright © 1999 Agilent Technologies
Obsoletes 5091-9635E (10/93)
5966-4942E (11/99)
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